Modular converter real-time simulation method and system based on FPGA pipelined norton equivalence

Abstract

This invention discloses a real-time simulation method and system for modular converters based on FPGA-based pipelined Norton equivalent simulation, solving the technical problem of a significant increase in the overall simulation step size caused by existing Norton equivalent simulation methods. The method includes acquiring MMC simulation model parameters, simulation step size, and FPGA master clock frequency; performing FPGA hardware configuration operations accordingly; outputting FPGA initialization configuration data; determining streaming submodule status data packets based on this data; combining the two to perform pipelined Norton equivalent parameter calculation; outputting submodule Norton equivalent parameters, data validity flags, and submodule switching flags; performing tree-based reduction and convergence of bridge arm equivalent parameters based on the above parameters and FPGA initialization configuration data; outputting the total bridge arm Norton equivalent parameters; and solving the bridge arm and system equations simultaneously based on these parameters and FPGA initialization configuration data to output MMC system electrical quantities, performing signal format conversion to obtain user-specified simulation waveform data.

Description

Technical Field

[0001] This invention relates to the field of power simulation technology, and in particular to a real-time simulation method and system for modular converters based on FPGA-pipeline Norton equivalent. Background Technology

[0002] With the accelerated advancement of energy transition, new power transmission technologies, represented by flexible direct current transmission (VSC-HVDC), are widely used in long-distance, high-capacity power transmission, offshore wind power grid integration, and urban power grid interconnection. Modular multilevel converters (MMCs), as the core equipment of flexible direct current transmission systems, typically contain hundreds to thousands of sub-modules in each arm. The development and verification of system control and protection strategies heavily rely on high-precision real-time simulation platforms. Traditional real-time simulators based on CPUs (Central Processing Units) or DSPs (Digital Signal Processors) are limited by their serial computing architecture, making it difficult to perform detailed modeling and simulation of large-scale MMC systems while meeting real-time constraints. Therefore, FPGA-based hardware-accelerated real-time simulation solutions have become a current research hotspot.

[0003] In MMC real-time simulation, the core computational bottleneck lies in the need to perform discrete equivalent calculations on all submodules and aggregate them into bridge arm-level parameters within each simulation time step. The Norton equivalent method is a classic approach to handle the switching dynamics of submodules, but when the number of submodules reaches hundreds or even thousands, traditional sequential iteration or fully parallel deployment schemes face a severe contradiction between hardware resource consumption and timing convergence. How to achieve high-throughput, deterministic-latency Norton equivalent calculations and fast aggregation of a large number of submodules on limited FPGA resources is a key technical challenge restricting the scale and step size of MMC real-time simulation.

[0004] Existing Norton equivalent simulation methods configure independent computing hardware units for each submodule. When the number of submodules expands from dozens to hundreds or even thousands, the required number of DSP multipliers, on-chip memory (BRAM, Block Random Access Memory), and logic units (LUT, Look-Up Table) increases proportionally. Taking a real-world engineering MMC containing thousands of submodules as an example, the required hardware resources may far exceed the capacity limit of a single FPGA, necessitating the use of a multi-FPGA cascaded solution. This introduces inter-chip communication delays and synchronization overhead, resulting in a significant increase in the overall simulation step size. Summary of the Invention

[0005] This invention provides a real-time simulation method and system for modular converters based on FPGA-based pipelined Norton equivalent simulation. It solves the technical problem that existing Norton equivalent simulation methods use a multi-FPGA cascade scheme, which introduces inter-chip communication delay and synchronization overhead, resulting in a significant increase in the overall simulation step size.

[0006] The first aspect of this invention provides a real-time simulation method for a modular converter based on FPGA-pipelined Norton equivalent, comprising: Obtain the MMC simulation model parameters, simulation step size, and FPGA main clock frequency, and perform FPGA hardware configuration operations based on the MMC simulation model parameters, the simulation step size, and the FPGA main clock frequency, and output FPGA initialization configuration data; Based on the FPGA initialization configuration data, determine the streaming submodule status data packet; Based on the streaming submodule status data packet and the FPGA initialization configuration data, perform pipelined Norton equivalent parameter calculation operations, and output the submodule Norton equivalent parameters, data validity flag and submodule switching flag; Based on the Norton equivalent parameters of the submodule, the data validity flag, the submodule switching flag, and the FPGA initialization configuration data, perform tree-shaped reduction and convergence of bridge arm equivalent parameters, and output the total Norton equivalent parameters of the bridge arm; Based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, the simultaneous solution operation of the bridge arm and system equations is performed, and the electrical quantities of the MMC system are output. The electrical quantities of the MMC system are subjected to signal format conversion processing to obtain user-specified simulation waveform data.

[0007] Optionally, the step of performing FPGA hardware configuration operations based on the MMC simulation model parameters, the simulation step size, and the FPGA master clock frequency, and outputting FPGA initialization configuration data, includes: The Norton equivalent conductance constant is calculated for the submodule capacitance value and the simulation step size in the MMC simulation model parameters, and the Norton equivalent conductance constant is output. The Norton equivalent conductivity constant is converted to a fixed-point format and output as a Norton equivalent conductivity constant. The bridge arm inductance, bridge arm resistance and simulation step size in the MMC simulation model parameters are used to construct the bridge arm equation discretization coefficient matrix, and the bridge arm equation discretization coefficient matrix is ​​output. Perform matrix decomposition and fixed-point format conversion on the discretized coefficient matrix of the bridge arm equation, and output the LU decomposition matrix in fixed-point format; The DC-side rated voltage and the number of sub-modules per bridge arm in the MMC simulation model parameters are processed to solve for the initial capacitor voltage of the sub-modules, and an initial state data packet of the sub-modules is generated. Perform tree reduction layer calculation on the number of each bridge arm submodule and output the tree reduction layer. Based on the number of tree reduction layers, the FPGA master clock frequency, and the number of sub-modules in each bridge arm, the FPGA operation configuration parameters are determined. Based on the submodule type in the parameters of the MMC simulation model, the minimum value of the bypass conductance is obtained by solving. The Norton equivalent conductivity constant in fixed-point format, the LU decomposition matrix, the initial state data packet of the submodule, and the discretization coefficient matrix of the bridge arm equation are downloaded to the designated storage area on the FPGA chip to obtain the pre-configured parameter data packet stored on the FPGA chip. The FPGA internal configuration registers are written to using the register writing method according to the FPGA operation configuration parameters to obtain the FPGA register configuration and operation control parameters. The pre-configured parameter data package stored on the FPGA chip, the running control parameters configured in the FPGA registers, and the minimum bypass conductance are integrated to output FPGA initialization configuration data.

[0008] Optionally, the step of performing pipelined Norton equivalent parameter calculation based on the streaming submodule status data packet and the FPGA initialization configuration data, and outputting the submodule Norton equivalent parameters, data validity flag, and submodule switching flag, includes: Perform data field extraction processing on the streaming submodule status data packet and output the extracted submodule status single-field data; Perform switch determination processing on the switch status in the extracted submodule status single field data to generate a submodule switching flag; Based on the fixed-point format Norton equivalent conductivity constant in the FPGA initialization configuration data, fixed-point multiplication is performed on the historical values ​​of capacitor voltage in the extracted submodule status single-field data, and the multiplication result set is output. Perform Norton current source historical item addition and subtraction operations on the multiplication result set and the historical values ​​of capacitor branch current in the extracted submodule status single field data, and output the Norton current source calculated value set. Based on the submodule switching flag and the minimum bypass conductance in the FPGA initialization configuration data, conditional selection processing is performed on the Norton current source calculation value set and the fixed-point format Norton equivalent conductance constant, and the irregular submodule Norton equivalent parameters are output. Perform precision alignment processing on the irregular submodule Norton equivalent parameters and output the submodule Norton equivalent parameters; Perform valid flag generation processing on the Norton equivalent parameters of the submodule and output the data valid flag.

[0009] Optionally, the step of performing tree-structured reduction and convergence of bridge arm equivalent parameters based on the submodule Norton equivalent parameters, the data validity flag, the submodule switching flag, and the FPGA initialization configuration data, and outputting the total Norton equivalent parameters of the bridge arm, includes: Based on the submodule switching flag, the Norton equivalent parameters of the submodule are effectively filtered to determine the valid Norton equivalent parameters of the submodule. Based on the data validity flag, the equivalent current and equivalent conductance in the Norton equivalent parameters of the valid submodule are subjected to a reduction operation of adding each layer in pairs, and the intermediate accumulation results of each layer are output. Perform a final summation on the intermediate accumulation results of each layer and output the total Norton equivalent parameters of each single bridge arm of the six bridge arms; Based on the parallel time-sharing mode selection flag corresponding to the FPGA running configuration parameters in the FPGA initialization configuration data, it is determined whether the total Norton equivalent parameters of each single bridge arm of the six bridge arms are valid. If so, the total Norton equivalent parameters of each individual bridge arm of the six bridge arms are integrated, and the total Norton equivalent parameters of the bridge arms are output.

[0010] Optionally, the step of performing a simultaneous solution operation of the bridge arm and system equations based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, and outputting the electrical quantities of the MMC system, includes: The bridge arm total Norton equivalent parameters and the bridge arm inductance and resistance discretization parameters contained in the bridge arm equation discretization coefficient matrix in the FPGA initialization configuration data are processed by assembling the right-hand vector of the bridge arm equation, and the bridge arm equation right-hand vector is output. Based on the fixed-point LU decomposition matrix in the FPGA initialization configuration data, the right-hand vector of the bridge arm equation is processed sequentially by the previous substitution operation and the back substitution operation to output the six bridge arm currents. The currents of the six bridge arms are substituted into the system-level circuit equations containing the AC-side transformer model and the DC-side line model, respectively, and the system equations are solved to output the AC-side three-phase voltage and current and the DC-side voltage and current. The electrical quantities of the MMC system are output by integrating the current of the six bridge arms, the three-phase voltage and current on the AC side, and the voltage and current on the DC side.

[0011] Optionally, it also includes: Calculate the current of the current step submodule capacitor branch based on the bridge arm current in the electrical quantities of the MMC system. Based on the submodule switching flag, the submodule state parameter update process is performed on the current time step submodule capacitor branch current and the historical values ​​of capacitor voltage and capacitor branch current contained in the submodule initial state data packet in the FPGA initialization configuration data, and the updated historical values ​​of capacitor voltage and capacitor branch current are output. Based on the updated historical values ​​of capacitor voltage and capacitor branch current, the submodule status data packet is determined; The status data packet of the submodule is written through the spare buffer port of the on-chip dual-port BRAM of the FPGA, and the status data writing result is output. Integrate the state data writing results and the submodule state data packet to output the updated streaming submodule state data packet.

[0012] A second aspect of this invention provides a real-time simulation system for a modular converter based on FPGA-pipelined Norton equivalent, comprising: The acquisition module is used to acquire MMC simulation model parameters, simulation step size and FPGA main clock frequency, and perform FPGA hardware configuration operations based on the MMC simulation model parameters, the simulation step size and the FPGA main clock frequency, and output FPGA initialization configuration data; The determination module is used to determine the streaming submodule status data packet based on the FPGA initialization configuration data; The output module is used to perform pipelined Norton equivalent parameter calculation operations based on the streaming submodule status data packet and the FPGA initialization configuration data, and output the submodule Norton equivalent parameters, data validity flag and submodule switching flag; The reduction module is used to perform tree-shaped reduction and convergence of bridge arm equivalent parameters based on the Norton equivalent parameters of the sub-module, the data validity flag, the sub-module switching flag, and the FPGA initialization configuration data, and output the total Norton equivalent parameters of the bridge arm. The solution module is used to perform a simultaneous solution operation of the bridge arm and system equations based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, and output the electrical quantities of the MMC system. The conversion module is used to perform signal format conversion processing on the electrical quantities of the MMC system to obtain user-specified simulation waveform data.

[0013] The third aspect of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described above.

[0014] The fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed, it implements the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described above.

[0015] The fifth aspect of the present invention provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein, when the program instructions are executed by a computer, the computer performs the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described above.

[0016] As can be seen from the above technical solutions, the present invention has the following advantages: The above technical solution of the present invention provides a real-time simulation method for modular converters based on FPGA pipelined Norton equivalents. This method acquires MMC simulation model parameters, simulation step size, and FPGA master clock frequency. Based on these parameters, the method performs FPGA hardware configuration operations and outputs FPGA initialization configuration data. Based on the FPGA initialization configuration data, it determines the streaming submodule status data packet. Based on the streaming submodule status data packet and the FPGA initialization configuration data, it performs pipelined Norton equivalent parameter calculation operations and outputs the submodule Norton equivalent parameters, data validity flags, and submodule switching flags. Based on the submodule Norton equivalent parameters, data validity flags, submodule switching flags, and the FPGA initialization configuration data, it performs tree-structured reduction and convergence bridge arm equivalent parameter operations and outputs the total bridge arm Norton equivalent parameters. Based on the bridge arm... The total Norton equivalent parameters and FPGA initialization configuration data are used to perform the simultaneous solution of bridge arm and system equations, outputting the electrical quantities of the MMC system. Signal format conversion processing is then performed on the MMC system electrical quantities to obtain user-specified simulation waveform data. Based on the above scheme, this invention achieves maximum overlap in the time dimension of multiple stages, including data reading, pipelined computation, tree reduction, and equation solving, through the timing control of a global state machine. The data reading stage corresponds to the acquisition and reading of MMC simulation model parameters and submodule state data; the pipelined computation stage corresponds to the pipelined Norton equivalent parameter calculation operation; the tree reduction stage corresponds to the convergence processing of bridge arm equivalent parameters; and the equation solving stage corresponds to the simultaneous solution of bridge arm and system equations. Each stage can start the subsequent stage without waiting for the previous stage to finish completely, making the actual critical path of the simulation time step much lower than the simple sum of the time consumed by each stage, thereby significantly reducing the simulation time step. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of the steps of a real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent provided in Embodiment 1 of the present invention. Figure 2 This is an overall flowchart of a real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent, provided in Embodiment 1 of the present invention. Figure 3This is a schematic diagram of the submodule state storage and data reading principle provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the pipelined Norton equivalent computation level partitioning principle provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the tree-shaped reduction and convergence principle provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the bridge arm and system equation solving principle provided in Embodiment 1 of the present invention; Figure 7 This is an example flowchart of a real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent, provided in Embodiment 1 of the present invention. Figure 8 This is a flowchart of the overall technical solution of a real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent provided in Embodiment 1 of the present invention. Figure 9 This is a diagram showing the association of key technical features provided in Embodiment 1 of the present invention; Figure 10 This is a structural block diagram of a real-time simulation system for a modular converter based on FPGA pipelined Norton equivalent, provided in Embodiment 2 of the present invention. Detailed Implementation

[0019] This invention provides a real-time simulation method and system for modular converters based on FPGA-based pipelined Norton equivalent simulation. It solves the technical problem that existing Norton equivalent simulation methods use a multi-FPGA cascade scheme, which introduces inter-chip communication delay and synchronization overhead, resulting in a significant increase in the overall simulation step size.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be noted that in the optional embodiments of the present invention, the object information and other related data involved require the permission or consent of the object when the embodiments of the present invention are applied to specific products or technologies, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. That is to say, if the embodiments of the present invention involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations, and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject is required, and the embodiments also need to be implemented with the authorization and consent of the object.

[0021] Terminology Explanation

[0022] MMC (Modular Multilevel Converter): A voltage source converter topology widely used in flexible DC transmission (VSC-HVDC) systems. Each arm of the converter consists of hundreds or even thousands of identical sub-modules (SMs) connected in series. Multilevel stepped wave output is achieved by controlling the switching state of each sub-module. It features low output voltage harmonic content, strong scalability, and high modularity.

[0023] Norton Equivalent Circuit: A fundamental equivalent transformation method in circuit theory, which equates any two-terminal linear network containing a source to a simplified circuit model consisting of an ideal current source and a conductor in parallel. In real-time power electronics simulation, energy storage elements (such as capacitors) in submodules can be discretized into an adjoint model of "Norton current source + equivalent conductor" within each simulation time step. This transforms the switching network into a linear problem within discrete time steps, facilitating the solution of simultaneous equations at the bridge arm / system level.

[0024] FPGA (Field Programmable Gate Array): An integrated circuit chip whose logic functions can be configured by the user through a hardware description language after manufacturing. It has characteristics such as high parallel computing capability, deterministic latency and nanosecond-level clock cycle, making it very suitable for hardware acceleration of a large number of repetitive computing tasks in real-time simulation of power systems. It is a key hardware platform in current real-time simulators that replaces traditional CPUs and DSPs.

[0025] Pipeline technology: A timing optimization method in digital circuit design that decomposes a complex computation process into several sequentially executed sub-stages. Each sub-stage is completed by independent hardware logic, and different data is processed simultaneously in different sub-stages, thereby significantly improving the system's data throughput at the cost of controllable computational latency. Deep pipelining refers to dividing the computation process into a larger number of pipeline stages to achieve higher clock frequencies and throughput.

[0026] Tree-based Reduction Network: A hardware-level parallel data aggregation structure that rapidly reduces multiple input data into a single result by merging them layer by layer. Its number of computation layers is logarithmic to the number of inputs (log2N). It is often used for large-scale parallel addition, maximum value extraction and other operations, and can complete the aggregation calculation of a large amount of data in a very short number of clock cycles.

[0027] Please see Figure 1 , Figure 1 The flowchart illustrates the steps of a real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent, as provided in Embodiment 1 of the present invention.

[0028] This invention provides a real-time simulation method for modular converters based on FPGA-pipelined Norton equivalents, comprising: Step 101: Obtain the MMC simulation model parameters, simulation step size, and FPGA master clock frequency. Based on the MMC simulation model parameters, simulation step size, and FPGA master clock frequency, perform FPGA hardware configuration operations and output FPGA initialization configuration data.

[0029] MMC (Modular Multilevel Converter) simulation model parameters refer to all the basic parameters used to construct the simulation model of the modular multilevel converter.

[0030] The simulation step size refers to the time interval between two adjacent simulation calculations in the real-time simulation of a modular multilevel converter.

[0031] FPGA master clock frequency refers to the reference clock frequency that drives the operation of various hardware modules inside the FPGA.

[0032] It should be noted that the simulation model parameters, simulation calculation step size, and FPGA master clock frequency corresponding to the modular multilevel converter are collected. Based on these three types of basic parameters, the FPGA hardware configuration is completed, and then the initialization configuration data adapted to the operation of the FPGA hardware is output.

[0033] The acquisition methods for MMC simulation model parameters, simulation step size, and FPGA master clock frequency all rely on the configuration interaction mechanism and hardware information reading logic of the FPGA real-time simulation platform. The specific acquisition methods are as follows: MMC simulation model parameters are obtained through three methods: manual input via the user's visual configuration interface, import from engineering design documents, and retrieval from a pre-built parameter template library. These parameters cover core topology and electrical parameters such as the number of converter arms, the number of submodule stages, capacitor values, inductance values, and line impedance, providing complete basic data for simulation model construction. The simulation step size is customized by the user based on the electromagnetic transient simulation accuracy requirements of the power system, the FPGA hardware computing power, and pipeline calculation timing constraints. It can also be adaptively tuned by matching the simulation step size with the FPGA master clock cycle to ensure that the simulation time interval is synchronized with the hardware runtime timing. The FPGA master clock frequency is obtained by reading the hardware configuration information embedded in the FPGA hardware platform and retrieving the timing constraint file parameters generated by the development tools. Alternatively, the user can manually set the reference clock frequency according to the simulation parallel processing efficiency and real-time requirements, providing a clock reference for subsequent FPGA hardware configuration and pipeline timing planning.

[0034] Further, step 101 may include the following sub-steps: S11. Perform Norton equivalent conductance constant calculation on the submodule capacitance value and simulation step size in the MMC simulation model parameters, and output the Norton equivalent conductance constant. S12. Perform format conversion processing on the Norton equivalent conductivity constant and output the Norton equivalent conductivity constant in fixed-point format; S13. Perform the construction of the bridge arm equation discretization coefficient matrix for the bridge arm inductance, bridge arm resistance and simulation step size in the MMC simulation model parameters, and output the bridge arm equation discretization coefficient matrix. S14. Perform matrix decomposition and fixed-point format conversion on the discretized coefficient matrix of the bridge arm equation, and output the LU decomposition matrix in fixed-point format; S15. Perform initial capacitor voltage calculation on the DC side rated voltage and the number of sub-modules per bridge arm in the MMC simulation model parameters to generate the initial state data packet of the sub-module. S16. Perform tree reduction layer calculation on the number of submodules of each bridge arm and output the tree reduction layer. S17. Determine the FPGA operation configuration parameters based on the number of tree reduction layers, FPGA master clock frequency, and the number of sub-modules per bridge arm; S18. Based on the sub-module type in the MMC simulation model parameters, the minimum value of bypass conductance is obtained by solving. S19. Download the Norton equivalent conductance constant, LU decomposition matrix, submodule initial state data package, and bridge arm equation discretization coefficient matrix in fixed-point format to the specified storage area on the FPGA chip to obtain the pre-configuration parameter data package stored on the FPGA chip. S110. Using the register writing method, the internal configuration register of the FPGA is written according to the FPGA operation configuration parameters to obtain the operation control parameters after the FPGA register configuration is completed. S111 integrates the pre-configured parameter data package stored on the FPGA chip, the running control parameters and the minimum bypass conductance value configured in the FPGA registers, and outputs the FPGA initialization configuration data.

[0035] The designated on-chip storage area of ​​an FPGA refers to a dedicated storage area reserved inside the FPGA chip for storing pre-configured simulation parameters, enabling fast reading and retrieval of parameters.

[0036] It should be noted that, as Figure 2 The diagram illustrates the eight core modules and their interconnections within the FPGA of the real-time simulation system of this invention. The switch command receiving module receives switch control commands from the external controller under test and updates them to the sub-module state storage module (effective in the next time step). After simulation starts, the sub-module state storage module reads the state data of each sub-module sequentially and streams it into the pipelined Norton computing engine for equivalent parameter calculation. The calculation results are aggregated into the total equivalent parameters of the bridge arms via a tree-structured reducer adder network and sent to the bridge arm equation solving module and the system equation solving module for simultaneous solution. The solution results are fed back to the state storage module by the state write-back module to complete the state update, and the simulation results are simultaneously output by the data output interface module. The entire system forms a closed-loop computational circuit, advancing one simulation time step with each completed cycle.

[0037] Specifically, the overall framework of this invention consists of the following core modules: a sub-module state storage module, a switch instruction receiving module, a pipelined Norton computation engine, a tree-structured reduce adder network, a bridge arm equation solving module, a system equation solving module, a state write-back module, and a data output interface module. These eight modules work collaboratively within a single FPGA chip to form a complete MMC real-time simulation system.

[0038] The submodule state storage module is implemented using an on-chip dual-port BRAM (Block Random Access Memory) array, responsible for storing the dynamic state information of all submodules. The state information of each submodule includes: capacitor voltage value (V_c) (32-bit fixed-point or floating-point), current switch state (S) (1 bit or 2 bits, depending on the submodule topology), and the capacitor branch current of the previous time step (I_{c,}) (32 bits, used for calculating the historical terms of the discrete adjoint model). To facilitate BRAM organization and alignment, this paper uniformly uses a 96-bit state data packet format to store the state of each submodule: - ([95:64]): (V_c) (32 bits) - ([63:32]): (I_{c,}) (32 bits) - ([31:0]): State field (including switch state code S, submodule type identifier, reserved bits / check bits, etc.)

[0039] For a bridge arm containing N submodules, the state storage module needs to allocate N sets of storage space. The dual-port characteristic of BRAM allows read and write operations to be performed simultaneously without conflict. The storage module internally employs a ping-pong buffer structure: one buffer is used for reading at the current time step, and the other is used for writing back the calculation results at the current time step. The roles of the two buffers are swapped during time step switching. Each storage address corresponds to a complete state data packet of a submodule, which is read sequentially cycle by cycle using an address counter and fed into the subsequent pipeline.

[0040] The switch command receiving module receives switch control commands from the external controller under test in real time via a high-speed digital interface (such as an Aurora or GTH transceiver). This module internally incorporates command decoding logic and timestamp synchronization logic, enabling it to align asynchronously arriving switch commands to the simulation time step boundaries, ensuring that the switching actions of the submodules in the simulation model are consistent with the timing of the external controller's commands. The received switch commands are written to the corresponding submodule's switch state field in the submodule state storage module and take effect at the start of the next simulation time step.

[0041] The pipelined Norton computation engine is the core hardware module of this invention. This engine consists of P-stage pipelined registers and combinational logic, with P typically having 12 stages. Each pipeline stage completes one atomic operation step in the Norton equivalent calculation, including: reading state data, switch determination, multiplication / addition / subtraction operations required for historical item calculation, condition selection, precision alignment, and output. The entire pipeline is driven by the FPGA master clock; when the pipeline is full, it outputs the Norton equivalent result of one submodule every clock cycle. For an MMC containing M bridge arms (typically M=6), the system can be configured with M independent pipelined engines to process each bridge arm in parallel, or a single-engine time-division multiplexing approach can be used to process each bridge arm sequentially. This invention preferably configures 6 parallel engines to maximize throughput and simplify cross-bridge arm scheduling.

[0042] The tree-structured reduction adder network receives Norton equivalent parameters from each submodule output by the pipeline engine and aggregates them level by level into a total bridge arm equivalent parameter. This network consists of log2N layers of cascaded hardware adders, with each layer containing a decreasing number of addition units. Taking 512 submodules as an example, the first layer contains 256 adders, the second layer 128, and so on, decreasing to only one adder in the ninth layer. A total of nine layers are sufficient to accumulate the 512 inputs. Since the pipeline engine outputs results cycle by cycle in a streaming manner rather than all at once, this invention designs a streaming tree-structured reduction structure: this structure uses registers and enable control to perform online merging at each layer. When two adjacent inputs in the same layer arrive, the addition operation is triggered, and the result is passed to the next layer. This design avoids the wasted time of waiting for all submodules to complete their calculations before initiating aggregation. The output of the tree-structured reduction network consists of two bridge arm-level parameters: the total Norton equivalent current (I_{}) and the total equivalent conductance (G_{}) of the bridge arm.

[0043] The bridge arm equation solving module receives the total equivalent parameters of each bridge arm, and combines them with the discretized parameters of the bridge arm inductance (L_{}) and resistance (R_{}) to establish the bridge arm-level circuit equations and solve for the bridge arm currents. The bridge arm equations, after discretization using numerical integration, are expressed as linear algebraic equations. Their coefficient matrix remains unchanged during simulation (because the bridge arm inductance and resistance are fixed parameters with a fixed step size). LU decomposition can be pre-completed before simulation starts, and the decomposition results can be stored in the FPGA's on-chip ROM (Read-Only Memory). The solution process performs forward and backward substitution operations, resulting in low computational complexity and deterministic calculations.

[0044] The system equation solving module, after solving for the bridge arm currents, substitutes the currents and equivalent parameters of the six bridge arms into the system-level circuit equations to solve for the three-phase AC voltage and current and the DC voltage and current. The system equations are also solved efficiently using a pre-decomposed coefficient matrix method.

[0045] The state write-back module substitutes the solved bridge arm currents back into each submodule, updates the capacitor voltage values ​​using the submodule's capacitance equations, and updates the historical values ​​of the capacitor branch currents, providing initial values ​​for the next time step. The updated state data is written to the spare buffer of the submodule's state storage module.

[0046] The data output interface module outputs selected simulation waveform data (such as bridge arm current, submodule capacitor voltage, AC / DC side voltage and current, etc.) to external devices via a high-speed DAC (Digital-to-Analog Converter) or digital interface for waveform monitoring and hardware-in-the-loop testing.

[0047] Based on the above, such as Figure 3 The diagram illustrates the workflow for sequentially reading submodule status data from the BRAM. The address generator increments the address value each clock cycle, reading the corresponding submodule status data packet from the BRAM's port A. The read data packet is then parsed and sent to the input-level registers of the pipelined Norton compute engine. Ping-pong buffer switching control logic ensures physical separation between the read and write-back regions, achieving conflict-free data flow. The entire process is fully controlled by a hardware state machine, ensuring deterministic latency characteristics.

[0048] The working principle of the submodule state storage module is based on the dual-port synchronous read / write characteristics of the FPGA on-chip BRAM. The system independently allocates a continuous BRAM address space for each bridge arm of the MMC. Each address unit stores a 96-bit state data packet of a submodule: (V_c) (32 bits), (I_{c,}) (32 bits), and a 32-bit state field including the switch state S.

[0049] During simulation, the address generator module increments the address counter at the FPGA master clock frequency (typically 200MHz to 500MHz). Each clock cycle, it reads a submodule's status data packet from port A of the BRAM and sends it to the input-level register of the pipelined Norton compute engine. Simultaneously, port B of the BRAM is occupied by the status write-back module, used to write updated data calculated in the current time step to a spare buffer. The switching of the ping-pong buffer is controlled by a global time step counter: when the time step counter is odd, port A reads from buffer 0 and port B writes to buffer 1; when the time step counter is even, the two ports switch roles. This mechanism ensures that read and write operations do not physically interfere with each other, avoiding data conflicts and race conditions.

[0050] The address generator is also responsible for generating bridge arm selection signals. Once all submodule data for the current bridge arm has been read, it automatically switches to the address space of the next bridge arm to continue reading. For a configuration of six parallel pipeline engines, the system is configured with six independent address generators, each driving the data reading of the corresponding BRAM region for each bridge arm, achieving fully parallel processing of the six bridge arms.

[0051] For the submodule capacitance values ​​and simulation step size in the MMC simulation model parameters, numerical calculations are performed using the Norton equivalent principle to obtain the Norton equivalent conductance constant reflecting the capacitance characteristics of the submodule. This Norton equivalent conductance constant is then converted into a fixed-point format that can be directly computed by the FPGA hardware, ensuring data compatibility with the FPGA's computing architecture, and outputting the Norton equivalent conductance constant in fixed-point format. Based on the bridge arm inductance and resistance in the MMC simulation model parameters, and combined with the simulation step size, a discretization algorithm is used to process the bridge arm circuit equations, constructing... The discretized coefficient matrix of the bridge arm equations is used for subsequent equation solving. LU decomposition is performed on this discretized coefficient matrix, breaking it down into lower and upper triangular matrices. Simultaneously, it is converted to a fixed-point number format, and the LU decomposition matrix in fixed-point number format is output to simplify the subsequent solution process. Based on the DC-side rated voltage in the MMC simulation model parameters, and combined with the number of sub-modules in each bridge arm, an average distribution calculation is performed to obtain the initial capacitor voltage of each sub-module, and these are integrated to form the initial state data package of the sub-modules. Based on the number of sub-modules in each bridge arm, a tree-structured reduction operation is obtained through hierarchical reduction logic. The required number of tree reduction layers is determined. Based on the number of tree reduction layers, FPGA master clock frequency, and the number of submodules per bridge arm, the parallel operation mode and timing control parameters of the FPGA are configured to determine the FPGA operation configuration parameters. According to the submodule type in the MMC simulation model parameters, the minimum bypass conductance value to avoid numerical anomalies when a submodule is bypassed is obtained by solving for the submodule's operating characteristics. Through the FPGA's on-chip data transmission channel, the Norton equivalent conductance constant in fixed-point format, the LU decomposition matrix, the submodule initial state data packet, and the discretization coefficient matrix of the bridge arm equation are downloaded to the designated storage area on the FPGA, integrating them to form a pre-configured parameter data packet stored on the FPGA. Using a register write protocol, the internal configuration registers of the FPGA are written according to the FPGA operation configuration parameters to complete the register configuration and obtain the FPGA register-configured operation control parameters. Finally, the pre-configured parameter data packet stored on the FPGA, the FPGA register-configured operation control parameters, and the minimum bypass conductance value are integrated to form complete FPGA initialization configuration data, providing hardware configuration support for the smooth start and efficient operation of subsequent simulation processes.

[0052] Step 102: Based on the FPGA initialization configuration data, determine the streaming submodule status data packet.

[0053] It should be noted that, based on the FPGA initialization configuration data generated in the early stage of integration, the initial state data packet of the submodule is first extracted from this data. At the same time, the parameters related to the number of submodules and timing control in the FPGA running configuration parameters are called. Combined with the FPGA master clock frequency, the extracted initial state data of the submodule is time-adapted and formatted. According to the running sequence of the submodule and the data flow requirements of subsequent pipeline calculations, the initial capacitor voltage and other state information of each submodule are organized into a continuous data stream. Thus, the streaming submodule state data packet that can be directly input into the subsequent pipelined Norton equivalent parameter calculation stage is determined.

[0054] Step 103: Based on the streaming submodule status data packet and FPGA initialization configuration data, perform pipelined Norton equivalent parameter calculation operation, and output the submodule Norton equivalent parameters, data validity flag and submodule switching flag.

[0055] The data validity flag is a signal used to identify whether the calculation results of the Norton equivalent parameters of the submodule are valid for subsequent operations.

[0056] The submodule switching flag is an identification signal used to indicate whether a submodule is in the active or bypass working state.

[0057] It should be noted that, taking the streaming submodule status data packet as input data and combining it with the relevant parameters in the FPGA initialization configuration data, the parallel calculation of Norton equivalent parameters is completed by relying on the FPGA pipeline computing architecture. At the same time, the submodule switching status is determined and the validity of the calculation results is marked, and the submodule Norton equivalent parameters, data validity flag and submodule switching flag are output.

[0058] Furthermore, step 103 may include the following sub-steps: S31. Perform data field extraction processing on the convection submodule status data packet, and output the extracted submodule status single field data; S32. Perform switch determination processing on the switch status in the extracted submodule status single field data to generate a submodule switching flag; S33. Based on the fixed-point format Norton equivalent conductivity constant in the FPGA initialization configuration data, perform fixed-point multiplication on the historical values ​​of capacitor voltage in the extracted submodule status single field data, and output the multiplication result set. S34. Perform Norton current source historical item addition and subtraction operations on the multiplication result set and the historical values ​​of capacitor branch current in the extracted submodule status single field data, and output the Norton current source calculated value set. S35. Based on the submodule switching flag and the minimum bypass conductance in the FPGA initialization configuration data, perform condition selection processing on the Norton current source calculation value set and the fixed-point format Norton equivalent conductance constant, and output the irregular submodule Norton equivalent parameters. S36. Perform precision alignment processing on the irregular Norton equivalent parameters of the submodule and output the Norton equivalent parameters of the submodule. S37. Perform valid flag generation processing on the Norton equivalent parameter of the submodule and output the data valid flag.

[0059] Submodule status single-field data refers to the independent submodule status information obtained after extracting and processing the data fields of the streaming submodule status data packet, including single-type status data such as switch status, capacitor voltage history value, and capacitor branch current history value.

[0060] The multiplication result set refers to the set of multiplication results obtained after performing fixed-point multiplication based on the Norton equivalent conductance constant and the historical value of the capacitor voltage in the fixed-point number format.

[0061] Conditional selection processing refers to the process of selectively adapting the Norton current source calculation value set and the fixed-point format Norton equivalent conductance constant based on the submodule switching flag and the minimum value of the bypass conductance. The adaptation logic corresponds to the submodule switching state.

[0062] Precision alignment processing refers to the process of calibrating the decimal point position and adjusting the numerical range of irregular Norton equivalent parameters of submodules to ensure that the parameter format is uniform and the accuracy meets the standards.

[0063] The valid flag generation process refers to the process of verifying the validity of the Norton equivalent parameter of the submodule and generating a flag to indicate whether the parameter can be used for subsequent tree reduction and other operations.

[0064] It should be noted that, as Figure 4 The diagram illustrates the internal hierarchical structure of the 12-stage deep pipelined Norton equivalent computation engine. Data is input from stage 1 on the left, sequentially passing through steps such as switch determination, multiplication, addition and subtraction, condition selection, and precision alignment, ultimately outputting the complete Norton equivalent current and equivalent conductance from stage 12. Stages are isolated by clock registers, allowing data from multiple different submodules to be processed simultaneously at different stages of the pipeline. This deep pipelined design achieves a throughput approaching "one submodule per clock cycle" with fewer physical computation units, which is key to the efficient resource utilization of this invention.

[0065] Specifically, the core working principle of the pipelined Norton computing engine is to decompose the calculation process of the Norton equivalent circuit parameters of the submodule into multiple sequentially executed atomic operation steps. Each step corresponds to a stage of the pipeline, and each stage is separated by registers triggered by the clock edge, so that data from different submodules can be processed simultaneously in different pipeline stages.

[0066] Taking the half-bridge submodule as an example, when the submodule is in the "engaged" state, the adjoint model obtained by discretizing its capacitor branch using the trapezoidal integral method can be expressed as: - Equivalent conductance: (;G=) - Norton current source (historical term): (;I=-GV) c -I c )

[0067] When a submodule is in a "bypass" state, to avoid numerical singularities, the following values ​​can be used: -(;G=G) (minimum value) -(;I=0)

[0068] Where (C) is the capacitance value of the submodule, (t) is the simulation step size, and (V) is the capacitance value of the submodule. c (I) represents the capacitor voltage at the end of the previous step. c ) represents the current in the capacitor branch at the end of the previous time step (signed according to the agreed direction).

[0069] The pipeline is divided into the following stages: Stage 1 (data receiving stage) latches the submodule status data packets from the input register and extracts (V c (S) and (I) c Three fields. Level 2 (Switch Determination Level) generates a switching flag based on the switch state S. insert When the flag insert =1 indicates that the capacitor is engaged, flag insert =0 indicates capacitor bypass. Stages 3 to 5 (multiplication stages) perform fixed-point multiplication (GV). c Since (G=2C / t) is a constant during simulation (step size and capacitance value are fixed), this constant is pre-calculated and stored in the constant register during simulation initialization. Therefore, the multiplication operation is a constant multiplied by a variable. In the FPGA, this multiplication is performed by the DSP hard core, implemented in three pipeline stages. Stages 6 and 7 (addition and subtraction stages) execute (I_=-(GV)). c -I c Levels 8 and 9 (conditional selection level) are based on the flag. insert The flag bit allows for multiplexing of Norton equivalent current and equivalent conductance: if flag insert =1, output (I) c =I) and (G c =G); if flag insert =0, output (I=0) and (G) c =Gbpass Levels 10 and 11 (precision alignment level) perform fixed-point number format normalization on the selected results, including overflow detection, truncation, or rounding, to ensure that the bit width and decimal point position of the output data are consistent with the input format of the subsequent tree reduction network. Level 12 (output stage) writes the final (I) and (G) values ​​into the output register and generates a valid data flag signal. out .

[0070] Once the pipeline is fully filled, a new Norton equivalent result for a submodule is output each clock cycle, while new submodule status data is continuously input. For a bridge arm containing 512 submodules, completing the calculation for all submodules requires (512+11=523) clock cycles. At a 500MHz master clock, this calculation takes approximately 1.05 microseconds.

[0071] It is worth mentioning that this invention can also schedule multiplier resources through time-division multiplexing by configuring a set of shared multipliers (without configuring a separate arithmetic unit for each submodule). Specifically, effective submodules are first selected based on their switching status, and then the Norton equivalent calculation tasks of each effective submodule are sequentially assigned to the shared multiplier according to a preset scheduling order. After the Norton parameter calculation of each submodule is completed, the bridge arm equivalent parameters are aggregated through a tree reduction method, and finally the total Norton parameters of the bridge arm are output. The advantages of this scheme are simple control logic, low hardware resource consumption, and no need for complex pipeline design; however, it has obvious limitations, namely, it can only process the calculation task of one submodule at a time, resulting in low computational efficiency, and multi-task scheduling is prone to delays, which cannot meet the real-time requirements of large-scale MMC simulation. When the number of submodules is large, the calculation time increases significantly, making it difficult to control the simulation step size within a reasonable range, and it is especially unsuitable for high-concurrency, fast-response simulation scenarios.

[0072] In this embodiment, the streaming submodule status data packet is first processed according to a preset data field division rule (specifically: based on the attributes of the MMC submodule status data, the streaming submodule status data packet is decomposed into three independent fields: switch status, capacitor voltage history value, and capacitor branch current history value; a fixed bit length is set for each field—the switch status field occupies 1 bit, the capacitor voltage history value and capacitor branch current history value fields each occupy 32 bits, and each field is arranged in a fixed order of "switch status - capacitor voltage history value - capacitor branch current history value", with no redundant bits between fields). The switch status, capacitor voltage history value, and capacitor branch current history value are then extracted. The system extracts independent submodule status information and outputs extracted submodule status single-field data. For the switch status in the extracted submodule status single-field data, based on the preset switch status determination logic (specifically: read the 1-bit value of the switch status field; if the value is 1, the submodule is in the engaged state; if the value is 0, the submodule is in the bypass state; if any value other than 0 or 1 appears, the switch status is abnormal), it determines whether the submodule is currently in the engaged or bypass state, and then generates the corresponding submodule switching flag. It then calls the fixed-point format Norton equivalent conductance constant in the FPGA initialization configuration data, and uses the FPGA's internal fixed-point arithmetic unit to process the extracted submodule... The historical capacitor voltage values ​​in the block status single-field data are subjected to fixed-point multiplication to obtain the corresponding multiplication result set. Following the Norton current source historical item calculation formula, the multiplication result set is added or subtracted from the extracted historical capacitor branch current values ​​in the submodule status single-field data to output the Norton current source calculated value set. Combining the submodule switching flag and the bypass conductance minimum value in the FPGA initialization configuration data, conditional selection logic is executed. If the submodule is in bypass state, the bypass conductance minimum value and the corresponding current source parameters are selected; if it is in active state, the Norton current source calculated value set and the fixed-point format Norton equivalent conductance constant are selected, and the result is output. The Norton equivalent parameters of the submodules are standardized. According to the FPGA operation precision standard (specifically: 32-bit fixed-point operation precision, where the integer part occupies 16 bits and the decimal part occupies 16 bits, the effective range of the value is limited to [-2^15, 2^15-1], the decimal point alignment is based on 16 decimal places, and when the value exceeds the effective range, it is calibrated to the range using saturation processing to ensure that the parameters match the hardware operation capability of the FPGA fixed-point operation unit), the Norton equivalent parameters of the unstandardized submodules are subjected to precision alignment processing such as decimal point alignment and value range calibration to ensure that the parameter format is uniform and meets the requirements of subsequent operation, and the Norton equivalent parameters of the submodules are output.Finally, based on the preset parameter validity judgment rules (specifically: verifying whether the values ​​of the Norton equivalent parameters of the submodule are within the preset valid range, whether they conform to the FPGA fixed-point number format specification and are free from format errors, whether the parameter values ​​have abnormal jumps, and whether they contain null values ​​or invalid codes; and verifying the logical consistency between the parameters and the submodule switching flag and data validity flag; if all the above conditions are met, it is judged as valid; if any one condition is not met, it is judged as invalid), the numerical range and format specification of the Norton equivalent parameters of the submodule are verified, and a data validity flag is generated to indicate whether the parameters can be used for subsequent calculations.

[0073] Step 104: Based on the Norton equivalent parameters of the submodule, the data validity flag, the submodule switching flag, and the FPGA initialization configuration data, perform the tree-shaped reduction and convergence of the bridge arm equivalent parameters, and output the total Norton equivalent parameters of the bridge arm.

[0074] The tree-structured reduction and aggregation of bridge arm equivalent parameters refers to the process of using a tree-structured reduction algorithm to summarize and integrate the Norton equivalent parameters of multiple sub-modules, and finally obtain the equivalent parameters of the entire bridge arm.

[0075] It should be noted that, based on the obtained Norton equivalent parameters of the submodule, data validity flags, and submodule switching flags, combined with the FPGA initialization configuration data, and following a preset tree reduction logic (specifically: first, valid Norton equivalent parameters of the submodule are selected based on the data validity flags and submodule switching flags; then, according to the preset tree reduction layer number in the FPGA initialization configuration data, the valid parameters are grouped into pairs and placed in the first layer of the tree reduction; for each group of parameters, the pairwise summation of equivalent conductance and equivalent current is performed, and the intermediate result of the first layer is output; subsequent layers divide the intermediate results of the previous layer into pairs), The process of repeatedly performing the summation of equivalent conductance and equivalent current is repeated until all reduction layers are completed. If the number of parameters in a certain layer is odd, the last ungrouped parameter is directly substituted into the next layer for calculation. Finally, the summation result of the last layer is used as the summation value of a single bridge arm. The summation values ​​of the single bridge arms of the six bridge arms are then integrated to obtain the total Norton equivalent parameters of the bridge arms. The Norton equivalent parameters of each submodule are aggregated and integrated. First, the valid parameter data is filtered out, and then the valid parameters are aggregated and calculated using the tree reduction algorithm. Finally, the total Norton equivalent parameters of the bridge arms are output, completing the tree reduction and aggregation of bridge arm equivalent parameters.

[0076] Furthermore, step 104 may include the following sub-steps: S41. Based on the submodule switching flag, effectively filter the Norton equivalent parameters of the submodule to determine the valid Norton equivalent parameters of the submodule. S42. Based on the data validity flag, perform a reduction operation by adding the equivalent current and equivalent conductance in the Norton equivalent parameters of the valid submodules layer by layer, and output the intermediate accumulation results of each layer. S43. Perform final summation on the intermediate accumulation results of each layer and output the total Norton equivalent parameters of each single bridge arm of the six bridge arms. S44. Based on the parallel time-sharing mode selection flag corresponding to the FPGA running configuration parameters in the FPGA initialization configuration data, determine whether the total Norton equivalent parameters of each single bridge arm of the six bridge arms are valid. S45. If so, integrate the total Norton equivalent parameters of each single bridge arm of the six-bridge arm and output the total Norton equivalent parameters of the bridge arm.

[0077] Reduction operation refers to the process of summarizing and integrating the Norton equivalent parameters of multiple effective sub-modules layer by layer according to the tree structure, in order to achieve centralized summarization of parameters.

[0078] The intermediate summation result refers to the summation result obtained after each layer of reduction is completed during the reduction operation, which is the basis for the final summation.

[0079] The total Norton equivalent parameter of a single bridge arm refers to the overall Norton equivalent parameter of the bridge arm after reduction operation, which reflects the electrical characteristics of the single bridge arm.

[0080] The parallel time-sharing mode selection flag is a flag stored in the FPGA initialization configuration data, used to determine whether the total Norton equivalent parameter of each bridge arm is valid.

[0081] It should be noted that, as Figure 5 The diagram illustrates the layer-by-layer convergence principle of the tree-structured reduce adder network. Submodule equivalent parameters from the pipelined Norton computation engine flow into the first layer. Each pair of adjacent results is summed pairwise by an adder, and the resulting intermediate results are fed into the second layer for further pairwise summation. This process continues layer by layer, decreasing until the total Norton equivalent current and total equivalent conductance of the bridge arms are output at the log₂N layer. This structure reduces the convergence delay from O(N) of a traditional chained adder to O(log₂N). For 512 submodules, under high-frequency conditions, the additional delay can be reduced to the order of 18 clock cycles, significantly shortening the non-computational overhead in the simulation time step.

[0082] Specifically, the working principle of a tree-structured reduction adder network is to reduce N parallel or streaming input values ​​to a single result through a log2N-level pairwise addition operation. This invention, targeting the streaming data characteristics of pipelined outputs, designs an online tree-structured reduction structure, the core principle of which is as follows: The first layer receives the Norton equivalent parameters from the submodules output cycle by cycle in the pipeline. N / 2 register pairs and an adder are set up in the first layer. Each register pair temporarily stores the results of two adjacent submodules. When the result of the first submodule arrives, it is stored in register A; when the result of the second submodule arrives, it is stored in register B. The adder is then triggered to pass the result A+B to the second layer. The second layer similarly sets up N / 4 register pairs, receives the output from the first layer, adds them pairwise, and then passes them to the third layer. This process continues until the last layer contains only one adder, outputting the final bridge arm equivalent parameters.

[0083] Taking N=512 as an example, the tree-structured reduction network has 9 layers. The first layer produces 256 intermediate sums, the second layer produces 128 intermediate sums, and so on, decreasing until the ninth layer outputs a final sum. Without adding internal pipelines to the adders, the entire process can be completed in approximately log₂N (=9) additional clock cycles after the last result is output by the pipeline. To ensure timing convergence of the addition operation at high clock frequencies, this invention allows for a 2-stage pipeline within each adder layer, thus the total reduction delay is approximately (2log₂N) clock cycles (18 cycles for N=512). The tree-structured reduction of Norton's equivalent current and equivalent conductance is processed in parallel using two independent adder networks without adding additional time overhead.

[0084] It is worth mentioning that when a single FPGA chip has limited resources and cannot handle the computational tasks and parameter storage of all sub-modules, this invention can also employ a multi-FPGA cascade approach to distribute sub-module computation, tree reduction, and system equation solving tasks across different FPGA chips. Specifically, some FPGAs handle Norton equivalent parameter calculations for sub-modules, some handle tree reduction and aggregation, and some handle system equation solving. Each FPGA chip transmits data and performs synchronous computation through a high-speed interface. While this solution addresses the issue of insufficient single FPGA resources, it has significant drawbacks: multi-chip cascading generates substantial data transmission delays, and synchronization between chips is challenging, leading to parameter transmission deviations. Furthermore, hardware costs increase significantly, system maintenance complexity rises, and collaborative computation between multiple chips further extends the overall simulation step size, failing to meet the high-efficiency, real-time requirements of MMC simulation.

[0085] In this embodiment, based on the submodule switching flag, the Norton equivalent parameters corresponding to the submodules in the active state are selected, and invalid parameters in the bypass state are eliminated, thereby determining the valid Norton equivalent parameters of the submodules. Then, according to the data validity flag, the selected valid Norton equivalent parameters of the submodules are reduced by adding them layer by layer. After each layer of reduction is completed, the intermediate accumulation result of the corresponding layer is recorded to form the intermediate accumulation result of each layer. After the intermediate accumulation of all layers is completed, the final summation operation is performed on all intermediate accumulation results to obtain the total Norton equivalent parameters of each of the six bridge arms. Then, the running configuration parameters in the FPGA initialization configuration data are called, and the parallel time-sharing mode selection flag is used to verify the total Norton equivalent parameters of each of the six bridge arms one by one to determine whether they meet the operation requirements and whether the data is valid. If the total Norton equivalent parameters of all single bridge arms are valid, the total Norton equivalent parameters of the single bridge arms of the six bridge arms are integrated, and the total Norton equivalent parameters of the bridge arms are finally output. The entire process leverages the parallel computing advantages of FPGAs, eliminating the need for cross-chip data transfer and avoiding the communication delays and synchronization overhead associated with cascading multiple FPGAs, thus effectively shortening computation time. Specifically, if the total Norton equivalent parameters of some single bridge arms are invalid (judged by parameters exceeding the preset range, incorrect format, or abnormal data), they are not included in the aggregation; only valid parameters are reduced and integrated, ultimately outputting the total Norton equivalent parameters of the bridge arms that can be used for subsequent calculations.

[0086] Step 105: Based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, perform the simultaneous solution operation of the bridge arm and system equations, and output the electrical quantities of the MMC system.

[0087] It should be noted that, based on the previously obtained total Norton equivalent parameters of the bridge arms and the FPGA initialization configuration data, combined with the timing control requirements corresponding to the FPGA master clock frequency, the pre-set simultaneous solution logic within the FPGA is invoked (specifically: first, the fixed-point LU decomposition matrix and the discretization coefficient matrix of the bridge arm equations are extracted from the pre-stored fixed-point format in the FPGA initialization configuration data; the total Norton equivalent parameters of the bridge arms are substituted into the pre-constructed discretization equations of the bridge arm circuits; and the right-hand vector of the bridge arm equations is assembled according to the fixed order of "equivalent conductance parameters first, equivalent current parameters second"; then, based on the LU decomposition matrix, the preceding substitution operation (starting from the first row of the lower triangular matrix, the known values ​​are substituted row by row to solve the intermediate variables, completing the layer-by-layer solution of the lower triangular equation system) and the back substitution operation are performed on the right-hand vector). (The six-arm current is solved by substituting the intermediate variables obtained from the previous calculations into the last row of the upper triangular matrix.) Then, the solved six-arm current is substituted into the system-level circuit equations containing the AC-side transformer model and the DC-side line model. According to Kirchhoff's voltage / current law, the numerical solution of the system equations is completed in a fixed order of "first solving the AC-side three-phase voltage and current, then solving the DC-side voltage and current". Finally, the six-arm current, AC-side three-phase voltage and current, and DC-side voltage and current are integrated to obtain the complete electrical quantities of the MMC system. The equivalent parameters of the bridge arms are substituted into the system equations and combined with the circuit characteristics of the MMC system. Through this fixed calculation process, the simultaneous solution of the bridge arm and system equations is completed, and the voltage, current and other related electrical parameters of the MMC system are accurately calculated. Finally, the electrical quantities of the MMC system are output.

[0088] Furthermore, step 105 may include the following sub-steps: S51. Perform bridge arm equation right-end vector assembly processing on the total Norton equivalent parameters of the bridge arm and the bridge arm inductance and bridge arm resistance discretization parameters contained in the bridge arm equation discretization coefficient matrix in the FPGA initialization configuration data, and output the bridge arm equation right-end vector. S52. Based on the fixed-point LU decomposition matrix in the FPGA initialization configuration data, perform the forward substitution and back substitution operations on the right-hand vector of the bridge arm equation in sequence, and output the six bridge arm currents. S53. Substitute the currents of the six bridge arms into the system-level circuit equations containing the AC-side transformer model and the DC-side line model, respectively, and execute the system equation solution to output the AC-side three-phase voltage and current and the DC-side voltage and current. S54 integrates the current of the six bridge arms, the three-phase voltage and current on the AC side, and the voltage and current on the DC side to output the electrical quantities of the MMC system.

[0089] MMC system electrical quantities refer to various electrical parameters generated during the operation of the MMC system, including system voltage, current, power, etc. They are the core data reflecting the operating status of the MMC system and the basis for subsequent signal format conversion and simulation result output.

[0090] The AC-side transformer model equation is a mathematical equation used to characterize the electrical characteristics of the AC-side transformer in an MMC system. It is based on the laws of electromagnetic induction and Kirchhoff's laws and incorporates key parameters such as transformer turns ratio, leakage reactance, and winding resistance. The correlation between AC-side voltage and current can be established through the input bridge arm current, which is the core basis for solving the three-phase voltage and current on the AC side.

[0091] The DC-side line model equations are mathematical equations used to characterize the transmission characteristics of the DC-side line in an MMC system. They are constructed based on transmission line theory and discretization algorithms, and the core incorporates parameters such as the resistance, inductance, and distributed capacitance of the DC line. The DC-side line voltage drop and current loss can be calculated through the input bridge arm current, which is the core basis for solving the DC-side voltage and current.

[0092] It should be noted that, as Figure 6 The diagram illustrates the hardware solution process for the bridge arm equations and the system equations. The Norton equivalent parameters of each bridge arm output by the tree reduction network are used as input, first to assemble the right-hand vector b of the linear equation system. Then, using the LU decomposition matrix pre-stored in on-chip ROM, the preceding and following operations are performed sequentially to obtain the currents of the six bridge arms and the AC / DC side node voltages. Since the coefficient matrix is ​​a constant matrix, the LU decomposition is performed only once during the initialization phase, requiring only low-computation preceding and following operations during runtime, ensuring that this step is completed within a few clock cycles.

[0093] Specifically, after obtaining the total Norton equivalent parameters ((I_{}) and (G_{})) of each bridge arm, it is necessary to establish and solve the bridge arm level and system level circuit equations to obtain the bridge arm current and node voltage.

[0094] The bridge arm level equations can be established using the nodal admittance method or the equivalent port method: the series branch of each bridge arm submodule is equivalent to the "Norton current source and conductance of the bridge arm port" within the discrete time step, which together with the bridge arm inductance (L_{}), resistance (R_{}), and AC / DC side connection relationship to form a linear equation system. After discretizing the bridge arm inductor current equation using the trapezoidal integral method, the unknowns of the six bridge arms (bridge arm current or equivalent nodal voltage / current combination) can be organized into a matrix form: [Ax=b] where (A) is a constant coefficient matrix (which remains unchanged when the simulation step size and bridge arm parameters are fixed), (x) is an unknown vector, and (b) is a known vector composed of (I_{}), (G_{}), DC side voltage, etc.

[0095] Since the coefficient matrix A remains unchanged throughout the simulation, its LU decomposition can be pre-calculated by the host computer during the simulation initialization phase and downloaded to the FPGA's on-chip ROM for storage. Within each simulation time step, the FPGA only needs to perform the preceding substitution operation (solving Ly=b) and the back substitution operation (solving Ux=y), resulting in low computational load and deterministic latency.

[0096] The system-level equations further incorporate the AC-side transformer model (equivalent to inductance and resistance in series) and the DC-side model (equivalent to capacitance and line resistance) to establish a complete MMC system circuit equation. Since the dimension increase of the system-level equations is not significant (usually 12 to 18 order), they can still be solved efficiently using the pre-decomposed LU matrix method.

[0097] In this embodiment, the total Norton equivalent parameters of the bridge arms are extracted. Combined with the discretization coefficient matrix of the bridge arm equations contained in the FPGA initialization configuration data, the discretization parameters of the bridge arm inductance and resistance are extracted. Following a preset vector assembly rule (i.e., first classifying and organizing various parameters, then standardizing the Norton equivalent parameters, bridge arm inductance and resistance parameters in a unified format, clarifying the parameter arrangement order, and storing them according to their corresponding FPGA storage addresses to ensure the data format matches the FPGA computing architecture and subsequent equation solving requirements), the two types of parameters are integrated and sorted to complete the assembly of the right-hand vector of the bridge arm equations, outputting the right-hand vector of the bridge arm equations that meets the subsequent solution requirements. Then, the fixed-point LU decomposition matrix stored in the FPGA initialization configuration data is called. Using this matrix as the solution basis, the preceding subtraction operation is performed on the right-hand vector of the bridge arm equations, gradually substituting parameters to complete intermediate calculations. Finally, the calculation results are corrected through back substitution operations, and the results for each of the six bridge arms are output. The corresponding current data, namely the six-arm current, is then substituted into the preset AC-side transformer model equation and DC-side line model equation. Based on Kirchhoff's Voltage Law (KVL) and Current Law (KCL), the system-level circuit equations are solved. First, the six-arm current is substituted into the AC-side transformer model equation, and the voltage drop of the three-phase AC voltage is calculated by combining the transformer ratio, leakage reactance, and other core parameters. Then, the three-phase AC voltage is solved by combining the grid reference voltage, and the three-phase AC current is derived according to Ohm's law. Next, the six-arm current is substituted into the DC-side line model equation, and the voltage drop of the DC-side line is calculated by combining the resistance and inductance parameters of the DC-side line and the discretization coefficient corresponding to the simulation step size. The DC-side voltage is solved by combining the DC-side bus reference voltage, and the DC-side current is derived by the current conservation principle. Finally, the six-arm current, AC-side and DC-side related electrical parameters are integrated to form the complete MMC system electrical quantities.

[0098] Step 106: Perform signal format conversion processing on the electrical quantities of the MMC system to obtain the user-specified simulation waveform data.

[0099] It should be noted that the electrical quantities of the MMC system obtained in the previous solution (including the current of the six bridge arms, the three-phase voltage and current on the AC side, and the voltage and current on the DC side) undergo signal format conversion processing. First, the original data format of the MMC system electrical quantities is parsed—that is, the fixed-point format used by the FPGA internal calculation. Then, combined with the user-preset simulation waveform data format requirements (such as data type, sampling frequency, and frame structure arrangement), the fixed-point format electrical quantity data is converted into the user-specified floating-point or standard waveform data format using the FPGA's internal format conversion module. At the same time, the data timing is calibrated to ensure that the timing of the converted data is consistent with the simulation step size. Invalid and redundant data generated during the conversion process is removed. The data is then organized according to the user-specified waveform data arrangement rules (such as organizing data in the order of "AC side-DC side-bridge arm") to finally obtain the user-specified simulation waveform data. This process does not require cross-chip format conversion. All operations are completed by the FPGA's on-chip module, avoiding the delay and data loss caused by cross-chip data transmission. At the same time, it simplifies the format conversion process, improves conversion efficiency, reduces the time spent in the simulation result output stage, and further helps to shorten the overall simulation step size.

[0100] Optionally, it also includes: Calculate the current in the current step submodule capacitor branch based on the bridge arm current in the electrical quantities of the MMC system. Based on the submodule switching flag, the submodule state parameter update process is performed on the current submodule capacitor branch current and the historical values ​​of capacitor voltage and capacitor branch current contained in the submodule initial state data packet in the FPGA initialization configuration data, and the updated historical values ​​of capacitor voltage and capacitor branch current are output. Based on the updated historical values ​​of capacitor voltage and capacitor branch current, determine the submodule status data packet; The status data packets of the submodule are written through the spare buffer port of the dual-port BRAM on the FPGA chip, and the status data writing result is output. Integrate the state data writing results and submodule state data packets, and output the updated streaming submodule state data packets.

[0101] It should be noted that, based on the bridge arm current in the electrical quantities of the MMC system and combined with the characteristics of the submodule circuit structure, the actual current of the submodule capacitor branch at the current time step is calculated through current allocation logic. That is, according to the correspondence between the bridge arm current and the number of submodules, the bridge arm current is reasonably allocated to each submodule. Combined with the working state of the submodule (on / bypass), invalid current components are eliminated to finally obtain the current of the submodule capacitor branch at the current time step. Based on the submodule switching flag, it is determined whether the submodule is in the working state. If the submodule is in the on state, the current submodule capacitor branch current at the current time step is replaced and updated with the historical values ​​of capacitor voltage and capacitor branch current contained in the submodule initial state data packet in the FPGA initialization configuration data. The timestamp of the historical data is corrected synchronously to complete the submodule state parameter update processing, and the updated historical values ​​of capacitor voltage and capacitor branch current are output. Based on the updated historical values ​​of capacitor voltage and capacitor branch current, the operating status and historical parameters of the submodule are integrated to determine the submodule status data packet containing complete status data. Then, through the spare buffer port of the FPGA's on-chip dual-port BRAM, the submodule status data packet is written to the spare buffer according to the preset storage address and data format. During the writing process, the integrity of data transmission is verified in real time to avoid data loss or format corruption. After writing is completed, the status data writing result is output. Finally, the status data writing result is integrated with the updated streaming submodule status data packet, redundant and invalid data is removed, and the updated streaming submodule status data packet is output. This updated streaming submodule status data packet can be used as a new submodule status data packet, providing real-time updated status data support for subsequent cyclic Norton equivalent calculations, tree reduction, and other operations.

[0102] For example, such as Figure 7 The diagram illustrates the complete seven-step implementation process of this invention. Step one is a one-time offline initialization process, while steps two through seven constitute a cyclically executed simulation main loop. Each loop advances one simulation time step: starting from submodule data reading, through pipelined Norton equivalent calculation, tree-based reduction and convergence, simultaneous equation solving, state write-back and update, to result output and time step advancement, forming a complete closed-loop calculation process. The data reading in step two and the pipelined calculation in step three highly overlap in time, and the state write-back in step six can also overlap in time with step two of the next time step. This data flow scheduling reduces the overall waiting time, enabling the system to maintain microsecond-level simulation step size and deterministic latency even with a large number of submodules.

[0103] Specifically, before the simulation system starts, the host computer software performs initialization operations based on the user-defined MMC simulation model parameters. The user inputs MMC topology parameters through the graphical interface, including: the number of submodules per bridge arm N (e.g., 512), submodule type (half-bridge or full-bridge), submodule capacitance value C (e.g., 15mF), bridge arm inductance Larm (e.g., 50mH), bridge arm resistance Rarm (e.g., 0.5Ω), DC side rated voltage Vdc (e.g., 640kV), AC side transformer parameters, simulation step size Δt (e.g., 2µs), and FPGA master clock frequency fclk (e.g., 500MHz).

[0104] The host computer software then performs the following pre-calculations: calculates the Norton equivalent conductance constant (G=2C / t) and converts it to the FPGA's internal fixed-point format; calculates the discretization coefficient matrix A of the bridge arm equation based on the bridge arm parameters and simulation step size, performs LU decomposition to obtain the L and U matrices, and converts them to fixed-point format; sets the bypass conductance value (G_=1^{-6}) (or selects a more suitable minimum value according to the numerical scale) to avoid numerical singularities; and generates the submodule initial state data packet, including the initial capacitor voltage (usually set to (Vdc / N)), the initial switching state (set according to control requirements, commonly full bypass or specified start-up state), and the initial capacitor branch current (zero value or start-up estimate).

[0105] All pre-calculated results are downloaded to designated areas of the FPGA's on-chip memory via JTAG or PCIe interface: the constant G is stored in the pipeline engine's constant register, the LU decomposition matrix is ​​stored in the ROM area of ​​the bridge arm equation solving module, the submodule initial state data is stored in BRAM buffer 0, and the bypass conductance value is stored in the constant register of the conditional selection stage. The following operating parameters are written to the FPGA's internal configuration register: number of submodules N, number of pipeline stages P, number of bridge arms M=6, number of tree reduction layers L= log2N Parallel / time-sharing mode selection flag. After configuration, the FPGA hardware logic enters standby mode, waiting for the start signal.

[0106] When the host computer sends the simulation start signal, the global time-step controller inside the FPGA starts working. The time-step controller is a finite state machine (FSM), and its state transition process is as follows: idle state → read / compute state (parallel) → convergence state → solve state → write back state → complete state → read / compute state (loop).

[0107] Upon entering the read / compute state, six address generators (in fully parallel mode) simultaneously and sequentially read submodule status data from their respective BRAM regions. The address generators increment the address value each clock cycle, starting with address 0 for the first submodule's status data packet, address 1 for the second, and so on, incrementing until address N-1 for the last submodule. The status data packet generated by each read operation appears at the BRAM's data output port in the next clock cycle, is then latched into the pipeline input stage register, and enters the pipeline for computation.

[0108] Meanwhile, during the read / compute state, the switch instruction receiving module checks if any new switch instructions have arrived. If so, the new instruction is cached and written to the "next time step switch status" field of the corresponding submodule; the timestamp of the instruction is aligned with the boundary of the current simulation time step to ensure that the instruction takes effect at the start of the next simulation time step, thereby avoiding inconsistencies in the solution caused by changing equivalent parameters in the middle of the current time step.

[0109] In the read / compute state, the pipeline engine continuously receives new submodule data and processes it step by step.

[0110] Taking the half-bridge submodule as an example, for the i-th submodule (i=0,1,…,N-1) entering the pipeline, its calculation process is completed within P=12 clock cycles as follows: Clock cycle k (Level 1): Status data packet of latch submodule i {Vc_prev(i),S(i),Ic_prev(i)}.

[0111] Clock cycle k+1 (level 2): ​​parse the switch state S(i) and generate the switching flag flag_insert(i).

[0112] Clock cycles k+2 to k+4 (levels 3 to 5): Perform multiplication operation temp_mul(i)=G×Vc_prev(i), where (G=2C / t) is a pre-stored constant.

[0113] Clock cycles k+5 to k+6 (levels 6 to 7): Execute historical item calculation (I_(i)=-temp_mul(i)-I_{c,}(i)).

[0114] Clock cycles k+7 to k+8 (levels 8 to 9): Selected based on the execution condition of flag_insert(i). If flag_insert(i)=1, then (I_(i)=I_(i)), (G_(i)=G); if flag_insert(i)=0, then (I_(i)=0), (G_(i)=G_).

[0115] Clock cycles k+9 to k+10 (levels 10 to 11): Perform precision alignment operations on the output, including saturation / truncation / rounding and format normalization.

[0116] Clock cycle k+11 (level 12): Write the final result {INorton_out(i),GNorton_out(i)} to the output register, and at the same time set the valid_out signal to notify the tree reduction network that new data has arrived.

[0117] Once the pipeline is fully filled, the Norton equivalent result of one submodule is output every clock cycle, while new submodule data is continuously input. All calculations for N submodules are completed within (N+P-1) clock cycles.

[0118] The valid_out signal output from the pipeline triggers the tree-based reduction network to start working. For Norton equivalent current and equivalent conductance, two tree-based reduction networks operate in parallel.

[0119] The first layer contains N / 2 reduction units. The j-th reduction unit (j=0,1,…,N / 2-1) is responsible for adding the outputs of the 2j-th and 2j+1-th submodules. When the 2j-th result arrives, it is stored in register A(j), and when the 2j+1-th result arrives, it is stored in register B(j), which then triggers the adder to calculate and output to the second layer. The second layer continues to add the outputs of the first layer pairwise, and so on, until the L-th layer (L= log2N It contains only one reduction unit, outputting the final total Norton equivalent current of the bridge arm: [I_{}={i=0}^{N-1}I{}(i)]. Similarly, it outputs the total equivalent conductance of the bridge arm: [G_{}={i=0}^{N-1}G{}(i)].

[0120] In fully parallel mode, the tree reduction of all six bridge arms is completed simultaneously, and the FSM transitions to the solution state after the reduction results of all bridge arms are valid. In time-division multiplexing mode, the six bridge arms complete the reduction sequentially, and the FSM transitions to the solution state after the reduction of the sixth bridge arm is completed.

[0121] After the FSM enters the solution state, the bridge arm equation solving module assembles the {Iarm_Norton,Garm} parameters of the six bridge arms into a right-hand vector b, and constructs the input terms required for the solution by combining the discretized parameters of the bridge arm inductance / resistance. After assembly, the preceding substitution operation Ly=b and the back substitution operation Ux=y are executed, where the elements of the L and U matrices are read from the on-chip ROM. For solving a 6×6 LU, the number of multiply-accumulate operations is typically on the order of tens to hundreds (depending on whether sparse / structured solving is used), which can be completed in tens of clock cycles using pipelined multiply-accumulate units in an FPGA.

[0122] The six arm currents {Iarm_1,…,Iarm_6} obtained from the solution, as well as the three-phase AC voltage and current and the DC voltage and current derived from the system equations, are stored in the results register.

[0123] After the FSM enters the write-back state, the state write-back module updates the capacitor voltage and capacitor branch current history of each submodule using the solved bridge arm current. For the i-th submodule, if it is in the input state (flag_insert(i)=1), the capacitor voltage is updated according to the capacitor equation: [V_c(i,k)=V_{c,}(i)+(I_c(i,k)+I_{c,}(i))] where (I_c(i,k)) is the capacitor branch current at the current time step, which can be obtained by combining the bridge arm current with the submodule's position and current direction: [I_c(i,k)=I_(k)S_(i)] (S_(i)) is the direction flag (+1 or -1), determined by the upper / lower bridge arm to which the submodule belongs and the current reference direction.

[0124] If the submodule is in a bypass state, then (V_c(i,k)=V_{c,}(i)), and (I_c(i,k)) can be set to zero or kept as an equivalent value consistent with the bypass path according to convention (in implementation, it is usually set to zero to simplify history items).

[0125] The historical current of the capacitor branch required for the next time step is then updated (stored in the (I_{c,}) field of the state packet): [I_{c,}(i)I_c(i,k)] and the updated state data packet {Vc(i,k),S(i),Ic_prev(i)} is written to the spare buffer through the B port of the BRAM. The write-back operation is performed at a rate of writing one submodule per clock cycle, and the write-back of N submodules requires N clock cycles; it can be parallelized and overlapped with the read of the next time step through ping-pong buffering.

[0126] After the write-back state is completed, the FSM enters the completion state. During the completion state, the data output interface module outputs the user-specified simulation variables (such as bridge arm current waveforms, capacitor voltage waveforms of selected submodules, AC three-phase voltage and current waveforms, etc.) as analog signals through a high-speed DAC, or sends them to an external recording device in the form of data frames through a digital interface.

[0127] After the completion state ends, the FSM automatically switches back to the read / compute state, the time step counter increments, the ping-pong buffer role switches, and the next simulation time step begins. The total time of the entire FSM loop is the computation delay of one simulation time step, which must be less than the user-defined simulation step size Δt to ensure real-time performance.

[0128] Based on specific parameters: N=512, P=12, fclk=500MHz. Single-arm state readout takes 512 cycles; pipeline computation takes 523 cycles and highly overlaps with readout. The critical path is determined by the link from "last readout to computation / reduction / solution completion". The tree-based reduction adds approximately 18 cycles, and equation solving takes approximately 50 cycles. Therefore, the critical path magnitude is approximately: [(512+11)+18+50], which is approximately 1.18 microseconds at 500MHz. By combining the overlapping scheduling of write-back and next time-step readout, the system can stably maintain the simulation step size at approximately 1-2 microseconds on an engineering scale.

[0129] For comparison of technical effects, existing technologies can be referenced, such as the FPGA-based parallel decomposition Norton equivalent simulation method. This scheme allocates an independent hardware computing unit to each submodule. Within each simulation time step, each computing unit simultaneously calculates the Norton current source and equivalent conductance. Then, a simple cascaded adder is used to sequentially accumulate the results from each submodule into bridge arm parameters. Its working principle is as follows: based on the submodule switching signals and state variables such as capacitor voltage from the previous time step, the submodule circuit is discretized into a Norton equivalent model using numerical integration. Each computing unit independently performs multiplication and addition operations, and the results are serially aggregated through a chained adder. This scheme is mainly applied to MMC simulations with tens to hundreds of submodules, with simulation step sizes typically between 500 nanoseconds and 1 microsecond. However, this scheme has the following main drawbacks: First, the fully parallel deployment method results in a linear relationship between FPGA resource consumption and the number of sub-modules. When the number of sub-modules exceeds several hundred, the DSP and BRAM resources of a single FPGA are quickly exhausted, making it impossible to further expand the scale. Second, the convergence delay of the chained cascaded adder is linearly related to the number of sub-modules. As the scale increases, the convergence delay increases significantly, which seriously restricts the shortening of the simulation step size and the expansion of the scale.

[0130] Based on the above, the shortcomings of existing technologies can be roughly divided into three parts: Disadvantage 1: The linear increase in hardware resource consumption with scale limits the simulable scale. Existing solutions configure independent computing hardware units for each submodule. When the number of submodules expands from dozens to hundreds or even thousands, the required number of DSP multipliers, on-chip RAM (BRAM), and logic units (LUTs) increases proportionally. Taking a real-world engineering MMC containing thousands of submodules as an example, the required hardware resources may far exceed the capacity limit of a single FPGA, necessitating the use of a multi-FPGA cascaded solution. This introduces inter-chip communication delays and synchronization overhead, significantly increasing the overall simulation step size and system complexity.

[0131] Disadvantage 2: The excessive delay of the chain-like convergence structure restricts the simulation step size and scale expansion. The discrete equivalent calculation results of each submodule need to be accumulated to form the bridge arm equivalent parameters. The existing solution uses a chain-like cascaded adder for step-by-step accumulation, and its convergence delay is proportional to the number of submodules N (O(N)). When N reaches hundreds, the convergence operation requires a large number of clock cycles, making it difficult to maintain the overall simulation time step at the microsecond level in large-scale scenarios.

[0132] Disadvantage 3: The lack of a time-division multiplexing mechanism for computing resources leads to low hardware utilization. In the existing scheme, each computing unit is idle after completing the equivalent calculation of the current time step, and only restarts the calculation when the next simulation time step arrives. Since there is often overlap between equivalent calculation and aggregation in the simulation cycle, a large amount of hardware resources are idle most of the time, resulting in low hardware utilization efficiency and wasting valuable FPGA resources.

[0133] To address the aforementioned issues, this invention provides a real-time simulation method for modular converters based on FPGA-pipelined Norton equivalents. This method aims to solve three core problems in large-scale MMC real-time simulation: excessive hardware resource consumption, long convergence delay, and low hardware utilization in Norton equivalent calculations of submodules. By designing a deeply pipelined Norton equivalent hardware solver unit, efficient time-division multiplexing of a large number of submodules is achieved with a small number of physical computing units. By introducing a hardware-level tree-structured reduction network to replace the chain-cascaded adders, the convergence delay is reduced from O(N) to O(log₂N). Ultimately, a single FPGA can simulate MMC converters containing thousands of submodules in real time, and the simulation step size is stably maintained at approximately 1–2 microseconds on a typical engineering scale (e.g., approximately 512 submodules per bridge arm, 500MHz FPGA master clock). This provides a large-scale, deterministic real-time simulation environment for verifying control and protection strategies of flexible DC transmission systems.

[0134] like Figure 8 The diagram illustrates the five core processing layers and their data flow of the overall technical solution of this invention. The submodule data preprocessing layer reads the submodule state parameters from the on-chip memory and streams them into the pipelined Norton equivalent calculation layer. The calculation layer outputs the Norton equivalent current source and equivalent conductance of each submodule cycle-by-cycle through a deep pipeline structure. These results are rapidly accumulated into the bridge arm level total equivalent parameters via a tree-structured reduction and aggregation layer. The bridge arm and system equation solving layer uses these equivalent parameters to solve for the electrical quantities of the entire MMC system. Finally, the result output and state update layer uses the solution results to update the submodule state and outputs simulation waveform data. All five layers operate in a full data stream mode within the FPGA, with seamless connections between adjacent layers via on-chip registers and FIFOs, ensuring deterministic latency and high throughput in the overall simulation process.

[0135] Specifically, the core idea of ​​this invention is to perform time-series expansion of the Norton equivalent calculation tasks of a large number of sub-modules in MMC through a deep pipeline architecture, then use a hardware-level tree reduction network to quickly aggregate the bridge arm parameters, and finally combine the solution of bridge arm-level circuit equations and system-level simultaneous equations to complete the real-time simulation of the entire MMC system.

[0136] The core architecture of the overall solution comprises five layers: a submodule data preprocessing layer, a pipelined Norton equivalent computation layer, a tree-structured reduction and convergence layer, a bridge arm and system equation solving layer, and a result output and state update layer. These five layers operate within the FPGA in a fully hardware-based data flow manner. Intermediate results are passed between layers via on-chip FIFOs or register cascading, ensuring the continuity of the data flow and deterministic computation latency.

[0137] In the submodule data preprocessing layer, at the start of each simulation time step, the system reads the state parameters of all submodules from the on-chip dual-port BRAM, including capacitor voltage values, switch state signals, and the capacitor branch current from the previous time step (used for historical term calculation of the discrete adjoint model). These parameters are input into subsequent pipelined computation units in the form of streaming data according to the preset submodule numbering order. The preprocessing layer is also responsible for updating the switch states of each submodule according to the switch commands issued by the control system and performing necessary data format conversions (e.g., converting external fixed-point format to internal computation format). The preprocessing layer is designed with a double buffering mechanism, that is, while the calculation of the current time step is in progress, the control commands required for the next time step have been preloaded into the spare buffer, thereby eliminating the waiting delay in the data preparation stage.

[0138] The key innovation of this invention in the pipelined Norton equivalent computation layer lies in the design of a P-level deep pipelined Norton equivalent hardware solver unit. This pipeline operates at a rate of one submodule per clock cycle, outputting the Norton equivalent parameters of the submodule at the current time step: equivalent current source (I_) and equivalent conductance (G_). The pipeline depth P is determined by the total timing requirements of the computation chain (multiplication, addition / subtraction, conditional selection, fixed-point warping, etc.), typically ranging from 8 to 16 stages. Once the pipeline is fully filled, the Norton equivalent result of one submodule is output from the pipeline end each clock cycle. For a bridge arm containing N submodules, completing the computation of all submodules requires only (N+P-1) clock cycles, where (P-1) is the initial pipeline filling delay. Under (NP) conditions, the equivalent throughput is close to one submodule per clock cycle. This design allows for efficient processing of a large number of submodule computation tasks with limited physical computing resources.

[0139] In the tree-structured reduction and convergence layer, the Norton equivalent current sources and equivalent conductances of each submodule output from the pipeline end need to be accumulated to obtain the total equivalent current and total equivalent conductance at the bridge arm level. This invention uses a hardware-level tree-structured reduction network to replace the traditional chained adder. The tree-structured reduction network divides N inputs into N / 2 pairs. The first stage simultaneously performs N / 2 pairwise additions, the second stage adds the N / 2 intermediate results pairwise again to obtain N / 4 results, and so on, obtaining the final convergence result after log2N stages of addition. To adapt to the streaming output characteristics of the pipeline, this invention designs an online tree-structured reduction structure, allowing data to begin converging level by level without waiting for all outputs to complete, reducing waiting latency.

[0140] In the bridge arm and system equation solution layer, after obtaining the Norton equivalent parameters of each bridge arm, the system substitutes the equivalent parameters of the six bridge arms (six bridge arms in total for three-phase upper and lower sections) into the pre-established bridge arm-level and system-level circuit equations for solution. The bridge arm-level equations consider lumped parameters such as bridge arm inductance and resistance, while the system-level equations include AC-side transformer models and DC-side line models. Due to the low dimensionality of the bridge arm-level equations (typically order 6 to 12), they can be efficiently solved in the FPGA using pre-calculated LU decomposition matrices.

[0141] In the results output and state update layer, the solved arm currents and node voltages are substituted back into each submodule to update its capacitor voltage and capacitor branch current, preparing for the next simulation step. Simultaneously, key waveform data is output to an external controller via a high-speed DAC interface or a high-speed digital interface for hardware-in-the-loop testing.

[0142] As can be seen from the above, if Figure 9 The diagram illustrates the logical connections between the key technical features of this invention. The adaptive configuration of the pipeline stages determines the clock frequency and throughput of the computing engine; the streaming processing capability of the online tree-reduction structure matches the streaming output characteristics of the pipeline; and the expansion support of the full-bridge submodule is enhanced through conditional selection logic within the pipeline. The parallel or time-sharing processing strategy for multiple bridge arms comprehensively considers the balance between the number of pipeline engines and the FPGA resource capacity. Fixed-point precision optimization ensures the numerical accuracy of the calculation results within a limited bit width, and the ping-pong buffer mechanism guarantees uninterrupted data flow. These technical features collectively support the invention's ability to achieve large-scale real-time MMC simulation on a single FPGA.

[0143] Specifically, the pipelined Norton computation engine of this invention supports parameterized configuration of the number of pipeline stages. Through generic parameters or generation statements in the FPGA hardware description language, users can adjust the number of pipeline stages P before synthesis based on the clock frequency and timing constraints of the target FPGA device. When the target clock frequency is low (e.g., 200MHz), fewer pipeline stages (e.g., 8 stages) can be configured to reduce pipeline fill latency; when the target clock frequency is high (e.g., 500MHz), the number of pipeline stages can be increased to 16 to ensure that the combinational logic depth of each stage meets timing constraints. This parameterized design allows the same RTL code to be adapted to different FPGA devices, improving the portability and flexibility of the design. Secondly, traditional tree-structured reduction networks often assume that inputs are parallel and ready or require centralized caching of inputs before computation begins. The online tree-structured reduction structure of this invention allows input data to arrive cycle-by-cycle in a streaming manner. Its key technical feature is the setting of register pairs with enable control at each layer, tracking the readiness state of each pair of inputs through data arrival counting: when both inputs arrive, addition is triggered and the result is pushed to the next layer. This design allows for a high degree of temporal overlap between the reduction operation and the pipeline output, reducing wait-related latency. Furthermore, in addition to half-bridge submodules, the pipelined Norton computation engine of this invention also supports Norton equivalent computation for full-bridge submodules. Full-bridge submodules have more switching states, and their equivalent models require more complex conditional decisions regarding capacitor branch current directions and bypass paths. This invention supports full-bridge submodule computation without altering the overall pipeline framework by adding switch state encoding and parsing logic at the pipeline's switch decision stage and extending the multiplexer at the conditional selection stage. This extension only adds a small amount of lookup table resources and has minimal impact on the overall clock frequency. Moreover, for the six arms of a three-phase MMC, this invention provides two parallel processing strategies for users to choose from based on FPGA resource capacity: a fully parallel strategy and a time-division multiplexing strategy. The fully parallel strategy configures each of the six bridge arms with an independent pipeline engine and tree reduction network, allowing computation on all six bridge arms to proceed in complete parallel. This strategy is suitable for high-end FPGA devices (such as the Xilinx UltraScale+ series). The time-sharing strategy uses a single pipeline engine and tree reduction network to process data from all six bridge arms sequentially. Bridge arm switching logic switches to the next bridge arm after completing the previous one, making it suitable for resource-constrained mid-range FPGA devices. The computation time for all six bridge arms under the fully parallel strategy is approximately equal to that of a single bridge arm, while the time-sharing strategy takes approximately six times longer.

[0144] In summary, the core key points and protected aspects of this invention are mainly reflected in five aspects. The core lies in achieving efficient operation of large-scale MMC simulation through innovative design of hardware architecture and computation scheduling. Firstly, the architecture design of the deeply pipelined Norton equivalent hardware solver unit decomposes the calculation process of Norton equivalent parameters for submodules into P-level pipeline stages. This allows the pipeline to output the Norton equivalent result of one submodule per clock cycle once it is full. By using a small number of physical computing units to perform time-division multiplexing on a large number of submodules, the bottleneck of FPGA resources is effectively overcome, enabling efficient simulation of thousands of submodules on a single FPGA. This is a key innovation in overcoming the latency and synchronization problems caused by multi-FPGA cascading. Secondly, the streaming convergence structure of the online tree-shaped reduction network is designed. A tree-shaped reduction adder network matching the pipeline output characteristics is designed, and a hierarchical accumulation method is used to achieve rapid aggregation of submodule parameters, reducing the traditional O(N) level aggregation latency to O(log₂N) level, significantly shortening the parameter aggregation time. Meanwhile, by employing an overlapping scheduling mechanism of pipelined computation and tree reduction, parallel execution of data reading, parameter calculation, result aggregation, and storage writing is achieved, further improving computational efficiency. Furthermore, the parameterized pipeline design supports both half-bridge and full-bridge submodule topologies, allowing the same hardware architecture to adapt to different submodule configurations. Simulation calculations under different topologies can be completed without modifying the hardware structure, enhancing the system's versatility. Finally, the combined use of ping-pong buffers and dual-port BRAM enables conflict-free reading and writing of simulation data, ensuring continuous and efficient pipeline operation and providing core support for achieving microsecond-level simulation steps.

[0145] The protected aspects of this invention focus on the aforementioned key technological innovations, including a deeply pipelined Norton equivalent hardware solver architecture, an online tree-structured reduction and convergence structure, an overlapping scheduling mechanism for pipelines and reductions, a parameterized pipeline topology adaptation design, and a ping-pong buffer and dual-port BRAM data supply mechanism. These innovative designs collectively enable efficient simulation of large-scale MMC on a single FPGA, effectively shortening the simulation step size, improving simulation real-time performance, solving the latency and synchronization problems caused by traditional multi-FPGA cascading, and ensuring the efficient and accurate operation of large-scale MMC simulation.

[0146] Compared with existing Norton equivalent simulation schemes based on parallel deployment of FPGA submodules, this invention achieves a fundamental improvement in three dimensions: hardware resource efficiency, scalability, and simulation step size maintenance capability in large-scale scenarios.

[0147] In terms of hardware resource efficiency, existing solutions configure independent computing units for each submodule. N submodules require N sets of multipliers and adders. When N=512, a large number of DSP hard cores and logic resources are needed, and resource consumption increases linearly with scale. In engineering, when it is extended to thousands of submodules, multiple FPGAs are often forced to be used. In contrast, the pipelined design of this invention can achieve a throughput of "processing one submodule per cycle" with only a small number of DSPs and logics on a single bridge arm. Resource consumption is weakly correlated with the number of submodules (mainly reflected in BRAM capacity and reduction network size), significantly improving the scale of submodules that a single FPGA can support.

[0148] Regarding simulation step size, the convergence delay of existing chain-cascaded adders is O(N). When N is large, convergence becomes a significant bottleneck, making it difficult to maintain the simulation step size in the microsecond range in large-scale scenarios. The tree-structured reduction network of this invention reduces the convergence delay to O(log₂N) (for example, about 18 clock cycles when N=512). Combined with the overlapping scheduling of pipelined computation and reduction, the system can still maintain the simulation step size stably in the range of about 1 to 2 microseconds when expanded to thousands of submodules, thereby achieving better real-time performance and deterministic latency in engineering-scale applications.

[0149] Furthermore, the typical application scenarios of this invention mainly fall into three categories. The first category is hardware-in-the-loop testing of control and protection strategies for flexible DC transmission systems. In ultra-high voltage flexible DC transmission projects, each converter contains 6 arms, each arm has approximately 500 sub-modules, totaling approximately 3,000 sub-modules. Using the real-time simulation method of this invention, microsecond-level simulation of this scale of MMC can be achieved on a single FPGA, meeting the actual application requirements of engineering. The second category is simulation of offshore wind power flexible DC transmission systems. This system includes MMC converters at both ends of the offshore and onshore converter stations, totaling approximately 4,000 to 6,000 sub-modules. Using the pipelined operation method of this invention, real-time simulation at this scale can be achieved, ensuring that the simulation step size is synchronized with actual operation. The third category is rapid prototype verification of MMC converter valve control systems. For functions such as voltage equalization sorting and redundancy switching of hundreds of sub-modules, rapid verification can be achieved through pipelined operation on a single FPGA, significantly improving development efficiency.

[0150] The key features of this invention are mainly reflected in three aspects. First, it adopts a pipelined architecture design, decomposing the submodule computing tasks into multiple parallel processing stages, so that the computing results of one submodule are output in each clock cycle, which greatly improves the computing efficiency. Second, it can complete the parallel computing of large-scale submodules through a single FPGA, without the need for cascading multiple FPGAs, avoiding the latency and synchronization problems of cross-chip data transmission, while reducing hardware costs and system complexity. Third, it uses on-chip dual-port BRAM to realize fast data reading, writing and storage, and combines timing control to realize real-time data updates, ensuring that the simulation step size is maintained at the microsecond level, adapting to the simulation requirements of large-scale MMC, solving the problems of latency and synchronization deviation caused by traditional multi-FPGA cascading, and taking into account computing efficiency, data accuracy and engineering practicality.

[0151] In this embodiment of the invention, a real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent is provided. This method acquires MMC simulation model parameters, simulation step size, and FPGA master clock frequency. Based on these parameters, the method performs FPGA hardware configuration operations and outputs FPGA initialization configuration data. Based on the FPGA initialization configuration data, it determines the streaming submodule status data packet. Based on the streaming submodule status data packet and the FPGA initialization configuration data, it performs pipelined Norton equivalent parameter calculation operations and outputs the submodule Norton equivalent parameters, data validity flags, and submodule switching flags. Based on the submodule Norton equivalent parameters, data validity flags, submodule switching flags, and the FPGA initialization configuration data, it performs tree-structured reduction and convergence bridge arm equivalent parameter operations and outputs the total bridge arm Norton equivalent parameters. Based on the bridge... The system uses Norton's equivalent parameters of the bridge arm and FPGA initialization configuration data to perform a simultaneous solution operation of the bridge arm and system equations, outputting the electrical quantities of the MMC system. Signal format conversion processing is then performed on the MMC system electrical quantities to obtain user-specified simulation waveform data. Based on the above scheme, this invention achieves maximum overlap in the time dimension of multiple stages, such as data reading, pipelined calculation, tree reduction, and equation solving, through the timing control of a global state machine. The data reading stage corresponds to the acquisition and reading of MMC simulation model parameters and submodule state data; the pipelined calculation stage corresponds to the pipelined Norton's equivalent parameter calculation operation; the tree reduction stage corresponds to the convergence processing of bridge arm equivalent parameters; and the equation solving stage corresponds to the simultaneous solution of the bridge arm and system equations. Each stage can start the subsequent stage without waiting for the previous stage to finish completely, making the actual critical path of the simulation time step much lower than the simple sum of the time consumed by each stage, thereby significantly reducing the simulation time step.

[0152] Please see Figure 10 , Figure 10This is a structural block diagram of a real-time simulation system for a modular converter based on FPGA pipelined Norton equivalent, provided in Embodiment 2 of the present invention.

[0153] This invention provides a real-time simulation system for a modular converter based on FPGA-pipelined Norton equivalent, comprising: The acquisition module 1001 is used to acquire the MMC simulation model parameters, simulation step size and FPGA main clock frequency, and perform FPGA hardware configuration operations based on the MMC simulation model parameters, simulation step size and FPGA main clock frequency, and output FPGA initialization configuration data. Module 1002 is used to determine the status data packet of the streaming submodule based on the FPGA initialization configuration data. Output module 1003 is used to perform pipelined Norton equivalent parameter calculation operations based on the streaming submodule status data packet and FPGA initialization configuration data, and output the submodule Norton equivalent parameters, data validity flag and submodule switching flag; The reduction module 1004 is used to perform tree-shaped reduction and convergence of bridge arm equivalent parameters based on the submodule Norton equivalent parameters, data validity flag, submodule switching flag and FPGA initialization configuration data, and output the total Norton equivalent parameters of the bridge arm. Solver module 1005 is used to perform simultaneous solution of bridge arm and system equations based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, and output the electrical quantities of the MMC system. The conversion module 1006 is used to perform signal format conversion processing on the electrical quantities of the MMC system to obtain the simulation waveform data specified by the user.

[0154] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system and modules described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0155] This invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program; when the computer program is executed by the processor, the processor performs the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described in the above embodiments.

[0156] This invention also provides a computer-readable storage medium storing a computer program / instruction thereon, which, when executed by a processor, implements the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described in the above embodiments.

[0157] This invention also provides a computer program product, including a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, wherein when the program instructions are executed by a computer, the computer performs the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described in the above embodiments.

[0158] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0159] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0160] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0161] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0162] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A modular converter real-time simulation method based on FPGA pipelined Norton equivalence, characterized in that, include: Obtain the MMC simulation model parameters, simulation step size, and FPGA main clock frequency, and perform FPGA hardware configuration operations based on the MMC simulation model parameters, the simulation step size, and the FPGA main clock frequency, and output FPGA initialization configuration data; Based on the FPGA initialization configuration data, determine the streaming submodule status data packet; Based on the streaming submodule status data packet and the FPGA initialization configuration data, perform pipelined Norton equivalent parameter calculation operations, and output the submodule Norton equivalent parameters, data validity flag and submodule switching flag; Based on the Norton equivalent parameters of the submodule, the data validity flag, the submodule switching flag, and the FPGA initialization configuration data, perform tree-shaped reduction and convergence of bridge arm equivalent parameters, and output the total Norton equivalent parameters of the bridge arm; Based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, the simultaneous solution operation of the bridge arm and system equations is performed, and the electrical quantities of the MMC system are output. The electrical quantities of the MMC system are subjected to signal format conversion processing to obtain user-specified simulation waveform data.

2. The real-time simulation method for modular converters based on FPGA pipelined Norton equivalents according to claim 1, characterized in that, The step of performing FPGA hardware configuration operations based on the MMC simulation model parameters, the simulation step size, and the FPGA master clock frequency, and outputting FPGA initialization configuration data, includes: The Norton equivalent conductance constant is calculated for the submodule capacitance value and the simulation step size in the MMC simulation model parameters, and the Norton equivalent conductance constant is output. The Norton equivalent conductivity constant is converted to a fixed-point format and output as a Norton equivalent conductivity constant. The bridge arm inductance, bridge arm resistance and simulation step size in the MMC simulation model parameters are used to construct the bridge arm equation discretization coefficient matrix, and the bridge arm equation discretization coefficient matrix is ​​output. Perform matrix decomposition and fixed-point format conversion on the discretized coefficient matrix of the bridge arm equation, and output the LU decomposition matrix in fixed-point format; The DC-side rated voltage and the number of sub-modules per bridge arm in the MMC simulation model parameters are processed to solve for the initial capacitor voltage of the sub-modules, and an initial state data packet of the sub-modules is generated. Perform tree reduction layer calculation on the number of each bridge arm submodule and output the tree reduction layer. Based on the number of tree reduction layers, the FPGA master clock frequency, and the number of sub-modules in each bridge arm, the FPGA operation configuration parameters are determined. Based on the submodule type in the parameters of the MMC simulation model, the minimum value of the bypass conductance is obtained by solving. The Norton equivalent conductivity constant in fixed-point format, the LU decomposition matrix, the initial state data packet of the submodule, and the discretization coefficient matrix of the bridge arm equation are downloaded to the designated storage area on the FPGA chip to obtain the pre-configured parameter data packet stored on the FPGA chip. The FPGA internal configuration registers are written to using the register writing method according to the FPGA operation configuration parameters to obtain the FPGA register configuration and operation control parameters. The pre-configured parameter data package stored on the FPGA chip, the running control parameters configured in the FPGA registers, and the minimum bypass conductance are integrated to output FPGA initialization configuration data.

3. The real-time simulation method for modular converters based on FPGA pipelined Norton equivalents according to claim 1, characterized in that, The step involves performing a pipelined Norton equivalent parameter calculation operation based on the streaming submodule status data packet and the FPGA initialization configuration data, outputting the submodule Norton equivalent parameters, data validity flag, and submodule switching flag, including: Perform data field extraction processing on the streaming submodule status data packet and output the extracted submodule status single-field data; Perform switch determination processing on the switch status in the extracted submodule status single field data to generate a submodule switching flag; Based on the fixed-point format Norton equivalent conductivity constant in the FPGA initialization configuration data, fixed-point multiplication is performed on the historical values ​​of capacitor voltage in the extracted submodule status single-field data, and the multiplication result set is output. Perform Norton current source historical item addition and subtraction operations on the multiplication result set and the historical values ​​of capacitor branch current in the extracted submodule status single field data, and output the Norton current source calculated value set. Based on the submodule switching flag and the minimum bypass conductance in the FPGA initialization configuration data, conditional selection processing is performed on the Norton current source calculation value set and the fixed-point format Norton equivalent conductance constant, and the irregular submodule Norton equivalent parameters are output. Perform precision alignment processing on the irregular submodule Norton equivalent parameters and output the submodule Norton equivalent parameters; Perform valid flag generation processing on the Norton equivalent parameters of the submodule and output the data valid flag.

4. The real-time simulation method for modular converters based on FPGA pipelined Norton equivalents according to claim 1, characterized in that, The step involves performing a tree-based reduction and convergence of bridge arm equivalent parameters based on the Norton equivalent parameters of the submodule, the data validity flag, the submodule switching flag, and the FPGA initialization configuration data, outputting the total Norton equivalent parameters of the bridge arm, including: Based on the submodule switching flag, the Norton equivalent parameters of the submodule are effectively filtered to determine the valid Norton equivalent parameters of the submodule. Based on the data validity flag, the equivalent current and equivalent conductance in the Norton equivalent parameters of the valid submodule are subjected to a reduction operation of adding each layer in pairs, and the intermediate accumulation results of each layer are output. Perform a final summation on the intermediate accumulation results of each layer and output the total Norton equivalent parameters of each single bridge arm of the six bridge arms; Based on the parallel time-sharing mode selection flag corresponding to the FPGA running configuration parameters in the FPGA initialization configuration data, it is determined whether the total Norton equivalent parameters of each single bridge arm of the six bridge arms are valid. If so, the total Norton equivalent parameters of each individual bridge arm of the six bridge arms are integrated, and the total Norton equivalent parameters of the bridge arms are output.

5. The real-time simulation method for modular converters based on FPGA pipelined Norton equivalents according to claim 2, characterized in that, Based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, the simultaneous solution operation of the bridge arm and system equations is performed, and the electrical quantities of the MMC system are output, including: The bridge arm total Norton equivalent parameters and the bridge arm inductance and resistance discretization parameters contained in the bridge arm equation discretization coefficient matrix in the FPGA initialization configuration data are processed by assembling the right-hand vector of the bridge arm equation, and the bridge arm equation right-hand vector is output. Based on the fixed-point LU decomposition matrix in the FPGA initialization configuration data, the right-hand vector of the bridge arm equation is processed sequentially by the previous substitution operation and the back substitution operation to output the six bridge arm currents. The currents of the six bridge arms are substituted into the system-level circuit equations containing the AC-side transformer model and the DC-side line model, respectively, and the system equations are solved to output the AC-side three-phase voltage and current and the DC-side voltage and current. The electrical quantities of the MMC system are output by integrating the current of the six bridge arms, the three-phase voltage and current on the AC side, and the voltage and current on the DC side.

6. The real-time simulation method for modular converters based on FPGA pipelined Norton equivalents according to claim 1, characterized in that, The method further includes: Calculate the current of the current step submodule capacitor branch based on the bridge arm current in the electrical quantities of the MMC system. Based on the submodule switching flag, the submodule state parameter update process is performed on the current time step submodule capacitor branch current and the historical values ​​of capacitor voltage and capacitor branch current contained in the submodule initial state data packet in the FPGA initialization configuration data, and the updated historical values ​​of capacitor voltage and capacitor branch current are output. Based on the updated historical values ​​of capacitor voltage and capacitor branch current, the submodule status data packet is determined; The status data packet of the submodule is written through the spare buffer port of the on-chip dual-port BRAM of the FPGA, and the status data writing result is output. Integrate the state data writing results and the submodule state data packet to output the updated streaming submodule state data packet.

7. A real-time simulation system for a modular converter based on FPGA-pipelined Norton equivalent, characterized in that, include: The acquisition module is used to acquire MMC simulation model parameters, simulation step size and FPGA main clock frequency, and perform FPGA hardware configuration operations based on the MMC simulation model parameters, the simulation step size and the FPGA main clock frequency, and output FPGA initialization configuration data; The determination module is used to determine the streaming submodule status data packet based on the FPGA initialization configuration data; The output module is used to perform pipelined Norton equivalent parameter calculation operations based on the streaming submodule status data packet and the FPGA initialization configuration data, and output the submodule Norton equivalent parameters, data validity flag and submodule switching flag; The reduction module is used to perform tree-shaped reduction and convergence of bridge arm equivalent parameters based on the Norton equivalent parameters of the sub-module, the data validity flag, the sub-module switching flag, and the FPGA initialization configuration data, and output the total Norton equivalent parameters of the bridge arm. The solution module is used to perform a simultaneous solution operation of the bridge arm and system equations based on the total Norton equivalent parameters of the bridge arm and the FPGA initialization configuration data, and output the electrical quantities of the MMC system. The conversion module is used to perform signal format conversion processing on the electrical quantities of the MMC system to obtain user-specified simulation waveform data.

8. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor causes the processor to perform the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the real-time simulation method for modular converters based on FPGA pipelined Norton equivalents as described in any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, wherein when the program instructions are executed by a computer, the computer performs the steps of the real-time simulation method for a modular converter based on FPGA pipelined Norton equivalent as described in any one of claims 1-6.

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