Chip startup running control method and device, equipment and storage medium

Abstract

This application discloses a chip startup and operation control method, apparatus, device, and storage medium, relating to the field of chip technology. The method includes: acquiring adaptive adaptation data area test data and adaptive adaptation data area read data; determining adaptation rate mode information and corresponding adaptation operating frequency information based on the comparison results of the adaptive adaptation data area test data and the adaptive adaptation data area read data; determining adaptation parameter configuration information and corresponding linker script configuration information based on the adaptation rate mode information and the adaptation operating frequency information; configuring the exception vector table of the linker script configuration information and the corresponding flash code segment to a preset access area to obtain directed linker configuration information; and controlling the flash controller to operate normally based on the operation configuration information corresponding to the adaptation parameter configuration information and the directed linker configuration information.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to chip startup and operation control methods, apparatus, devices and storage media. Background Technology

[0002] In SOC chip design, the Flash-based XIP mode has become a key technology for saving SRAM resources, reducing chip area, and lowering power consumption because it allows the CPU to directly fetch instructions from Flash without copying the program to SRAM. However, with the increasing diversification of Flash manufacturers, models, and specifications, practical applications urgently require chips that can flexibly adapt to different Flash and achieve optimal operating performance under a single software version. At the same time, in online operation scenarios such as firmware upgrades or configuration modifications, chips also need to safely and efficiently complete Flash read and write operations without affecting the stable operation of the system.

[0003] Currently, the existing approach requires pre-setting a separate set of XIP configuration parameters for each Flash model to be supported, generating multiple dedicated program versions, each corresponding to a Flash specification. When Flash erase / write operations are needed, only the Flash read / write related code is moved to SRAM for execution, while the system's exception vector table still needs to reside in Flash to maintain XIP mode. However, this existing adaptation method results in high development and maintenance costs. Once a new model or Flash without pre-set parameters is connected, the chip cannot properly enable XIP mode, exhibiting extremely poor adaptation flexibility. It fails to achieve the goal of a single software version being compatible with all Flash types and achieving optimal performance. Furthermore, retaining the exception vector table in Flash means that during the entire Flash erase / write operation process, all system interrupts and exceptions become unresponsive, significantly impacting system efficiency and stability. Therefore, how to adaptively adapt to various Flash types to achieve stable and efficient chip startup and operation control has become an urgent problem to be solved. Summary of the Invention

[0004] The main objective of this application is to provide a chip startup and operation control method, apparatus, device, and storage medium, aiming to solve the technical problem of how to adaptively adapt to various types of flash memory to achieve stable and efficient chip startup and operation control.

[0005] To achieve the above objectives, this application proposes a chip startup and operation control method, the method comprising: Obtain test data and read data from the adaptive adaptation data area; Based on the comparison results of the test data and the read data of the adaptive adaptation data area, the adaptation rate mode information and the corresponding adaptation working frequency information are determined. Based on the adaptation rate mode information and the adaptation working frequency information, determine the adaptation parameter configuration information and the corresponding link script configuration information; The exception vector table of the linking script configuration information and the corresponding flash code segment are configured to be linked to a preset access area to obtain the targeted linking configuration information. The flash memory controller is controlled to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directed link configuration information.

[0006] In one embodiment, the step of determining the adaptation rate mode information and the corresponding adaptation operating frequency information based on the comparison results of the adaptive adaptation data area test data and the adaptive adaptation data area read data includes: The test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area are compared to determine the comparison result; Based on the comparison results, the adaptation rate mode information under the preset peripheral interface mode configuration is determined; Based on the adaptation rate mode information, the working frequency records that are consistent in the comparison results are read sequentially at a preset working frequency to determine the adaptation working frequency information.

[0007] In one embodiment, the step of determining the adaptation rate mode information under the preset peripheral interface mode configuration based on the comparison result includes: When the comparison results are consistent, the adapted rate mode information is the rate mode that supports the preset peripheral interface mode configuration. When the comparison results are inconsistent, the adapted rate mode information is a rate mode that does not support the preset peripheral interface mode configuration and maintains the preset operating frequency configuration. The preset operating frequency configuration includes at least one of 100 MHz, 50 MHz, 20 MHz, 10 MHz, 5 MHz and 1 MHz.

[0008] In one embodiment, the step of configuring the exception vector table of the linker script configuration information and the corresponding flash code segment to be linked to a preset access area to obtain the directed link configuration information includes: The exception vector table and corresponding flash code segment of the linker script configuration information are modified to determine the modification parameter information; Based on the modified parameter information, a directional link is established to a preset access area to obtain directional link area information. The preset access area is a static random access memory area. The corresponding targeted link configuration information is determined based on the targeted link region information.

[0009] In one embodiment, the step of determining the corresponding redirection configuration information based on the redirection region information includes: Get initialization code information; Based on the initialization code information, the exception vector table, flash code segment, and read / write code segment in the directed link area information are moved to the preset access area for configuration, and the first directed link configuration information is determined. Based on the initialization code information, the read-only data segment and other code segments in the directed link area information are configured to determine the second directed link configuration information; The redirected link configuration information is obtained based on the first redirected link configuration information and the second redirected link configuration information.

[0010] In one embodiment, the step of controlling the flash controller to operate normally based on the runtime configuration information corresponding to the adaptation parameter configuration information and the directed link configuration information includes: Get version upgrade information; Based on the version upgrade information, determine the corresponding mode switching information; When the mode switching information indicates switching to online execution mode, the flash controller is controlled to operate normally according to the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

[0011] In one embodiment, the step of obtaining version upgrade information includes: Obtain the boot tag information of the first and second running version partitions; The partition information where the running version is located is determined based on the boot tag information; Based on the partition information of the running version, firmware upgrades are performed on partitions that are not currently running versions to obtain version upgrade information.

[0012] Furthermore, to achieve the above objectives, this application also proposes a chip startup and operation control device, which includes: The acquisition module is used to acquire test data and read data from the adaptive adaptation data area. The processing module is used to determine the adaptation rate mode information and the corresponding adaptation working frequency information based on the comparison results of the test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area. The processing module is also used to determine the adaptation parameter configuration information and the corresponding link script configuration information based on the adaptation rate mode information and the adaptation working frequency information; The execution module is used to redirect the exception vector table of the linked script configuration information and the corresponding flash code segment to a preset access area for configuration, thereby obtaining the redirected link configuration information; The execution module is also used to control the flash controller to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

[0013] In addition, to achieve the above objectives, this application also proposes a chip startup and operation control device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip startup and operation control method described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the chip startup and operation control method described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: This embodiment proposes a chip startup and operation control method, which acquires adaptive adaptation data area test data and adaptive adaptation data area read data; based on the comparison results of the adaptive adaptation data area test data and the adaptive adaptation data area read data, determines the adaptation rate mode information and the corresponding adaptation operating frequency information; based on the adaptation rate mode information and the adaptation operating frequency information, determines the adaptation parameter configuration information and the corresponding linker script configuration information; the exception vector table and the corresponding flash code segment of the linker script configuration information are directionally linked to a preset access area for configuration, obtaining directional link configuration information; and the flash controller is controlled to operate normally based on the operation configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information. This application automatically trains the optimal rate mode and highest operating frequency for the current flash memory by comparing the test data and read data of the flash adaptive adaptation data area, obtaining the adaptation parameter configuration information. Simultaneously, by modifying the linker script to directionally link the exception vector table and flash code segment to a preset access area for configuration, the flash controller is controlled to operate normally, achieving adaptive adaptation of a single software version to various types of flash memory and maximizing performance, while ensuring the stability of interrupt response and the high efficiency of system operation during mode switching. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an embodiment of the chip startup and operation control method of this application. Figure 2 This is a schematic diagram of the storage partition for the chip startup and operation control method of this application; Figure 3 Flowchart for adaptive training of the chip startup and operation control method in this application to select the optimal configuration; Figure 4 This is a schematic diagram of the partition configuration of the chip startup and operation control method code segment in this application; Figure 5 This is a schematic diagram illustrating the mode switching of the chip startup and operation control method in this application; Figure 6 This is a block diagram illustrating the startup and operation of the chip in the chip startup and operation control method of this application; Figure 7 This is a flowchart illustrating Embodiment 2 of the chip startup and operation control method of this application. Figure 8 This is a schematic diagram of the module structure of the chip startup and operation control device according to an embodiment of this application; Figure 9 This is a schematic diagram of the device structure of the hardware operating environment involved in the chip startup and operation control method in this application embodiment.

[0019] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0021] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0022] The main solution of this application embodiment is as follows: Acquire adaptive adaptation data area test data and adaptive adaptation data area read data; based on the comparison results of the adaptive adaptation data area test data and the adaptive adaptation data area read data, determine adaptation rate mode information and corresponding adaptation operating frequency information; based on the adaptation rate mode information and the adaptation operating frequency information, determine adaptation parameter configuration information and corresponding linking script configuration information; configure the exception vector table of the linking script configuration information and the corresponding flash code segment to a preset access area to obtain directed linking configuration information; control the flash controller to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directed linking configuration information.

[0023] In this embodiment, for ease of description, the following description will focus on the identification chip starting and running control device as the execution subject.

[0024] Because the existing technology adaptation methods lead to high development and maintenance costs, once a new model or Flash without preset parameters is connected, the chip cannot properly enable XIP mode, resulting in extremely poor adaptation flexibility. It is impossible to achieve the goal of a single software version being compatible with all Flash and achieving the best performance. Furthermore, keeping the exception vector table in the Flash means that during the entire process of Flash erasing and writing, all system interrupts and exceptions cannot be responded to, which greatly affects the efficiency and stability of system operation.

[0025] This application provides a solution that automatically trains the optimal speed mode and maximum operating frequency for the current flash memory by comparing test data and read data from the flash memory adaptive adaptation data area, thereby obtaining adaptation parameter configuration information. At the same time, by modifying the linker script, the exception vector table and flash code segment are configured to be linked to the preset access area, thereby controlling the normal operation of the flash memory controller. This achieves adaptive adaptation of a single software version to various types of flash memory and maximizes its performance, while ensuring the stability of interrupt response and the high efficiency of system operation during mode switching.

[0026] Based on this, embodiments of this application provide a chip startup and operation control method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip startup and operation control method of this application.

[0027] In this embodiment, the chip startup and operation control method includes steps S10 to S50: Step S10: Obtain test data and read data from the adaptive adaptation data area; It should be noted that the adaptive adaptation data area test data is the original baseline data of known content pre-written into a specific adaptation data area in the flash memory, used to determine whether an error occurs during the data reading process. The adaptive adaptation data area read data is the data actually read from the same adaptation data area after the flash controller is configured to a specific online execution mode, used for consistency comparison with the test data.

[0028] In a specific embodiment, the adaptive data area test data is generated and written by the chip in normal data read / write mode. That is, the chip switches the flash memory controller to normal data read / write mode. In this mode, the processor accesses the flash memory in the same way as accessing a normal data storage partition, and can perform erase and write operations, such as... Figure 2 As shown, Figure 2 This diagram illustrates the storage partitioning of the chip startup and operation control method described in this application. It specifies the starting address, size, and purpose of each region on the Flash memory. For example, the entire Flash memory is divided into several functional partitions, such as a startup marker area, a running version A area, a running version B area, a configuration data area, an XIP optimal configuration storage area, and an adaptive data usage area. At this point, the pre-defined adaptive data area in the flash memory can be erased to ensure that the area is clean. A set of random data, for example, 64 bytes, is generated using a random number generator, and this set of random data with known content is written into the adaptive data area as test data. For example, during a startup process, the system randomly generates 64 bytes of data and writes it to the starting address of the adaptive data area; this set of data becomes the test data for this training.

[0029] The process of acquiring data from the adaptive data area is tightly coupled with the testing process. After writing test data, the chip switches the flash controller back to XIP mode (online execution mode) and sets the initialization parameters for XIP mode. For example, the operating frequency can be initially set to 1MHz, the rate mode to 4-wire mode, QPI (Quad Peripheral Interface) mode can be enabled, and the flash chip can be configured to enter QPI mode. After completing the above initialization configuration, the previously written 64 bytes of data are read from the adaptive data area through the XIP mode bus interface. This read data is the read data. At this point, the system initiates a read operation on the adaptive data area at a preset operating frequency of 1MHz, 4-wire rate mode, and with the 4-wire peripheral interface mode enabled. The 64 bytes of read data are then buffered for comparison.

[0030] Step S20: Based on the comparison results of the test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area, determine the adaptation rate mode information and the corresponding adaptation working frequency information. It should be noted that the adaptation rate mode information refers to the optimal number of data lines that the flash controller and the flash chip can support when transmitting data, such as single-line mode, dual-line mode, or four-line mode, and whether four-line peripheral interface mode is supported in four-line mode. The adaptation operating frequency information refers to the highest clock frequency at which the flash controller can stably read data from the flash chip under the determined optimal rate mode.

[0031] In a specific embodiment, the test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area are compared to determine the comparison result. That is, the flash memory controller is configured to a preset peripheral interface mode, such as enabling the four-wire peripheral interface mode, and the flash memory chip is set to enter the four-wire peripheral interface mode. Data is read from the adaptive adaptation data area at a working frequency of 1 MHz and a four-wire rate mode. The 64 bytes of read data from the adaptive adaptation data area are compared byte by byte with the previously written test data of the adaptive adaptation data area.

[0032] When the comparison results are consistent, the adapted rate mode information is the rate mode that supports the preset peripheral interface mode configuration. That is, when the comparison results are consistent, it indicates that the flash memory chip can support the instruction and data transmission of the four-wire peripheral interface mode under the operating frequency and rate mode. At this time, the adapted rate mode information is recorded as: supports the four-wire peripheral interface mode, and the rate mode is the four-wire mode.

[0033] When the comparison results are inconsistent, the adaptation rate mode information indicates that the speed mode does not support the preset peripheral interface mode configuration and maintains the preset operating frequency configuration. The preset operating frequency configuration includes at least one of 100 MHz, 50 MHz, 20 MHz, 10 MHz, 5 MHz, and 1 MHz. That is, when the comparison results of the read data and the test data are inconsistent, it indicates that the flash memory chip does not support the four-wire peripheral interface mode or cannot work normally in the four-wire peripheral interface mode. At this time, the adaptation rate mode information records that the flash memory does not support the four-wire peripheral interface mode, and turns off the four-wire peripheral interface configuration of the flash memory controller and the four-wire peripheral interface mode of the flash memory chip, keeping the operating frequency unchanged at 1 MHz. It then attempts to reread data from the adaptive adaptation data area in the four-wire, two-wire, and single-wire speed modes with the preset operating frequency configuration, and compares it with the test data respectively. The preset operating frequency configuration includes at least one of 100 MHz, 50 MHz, 20 MHz, 10 MHz, 5 MHz, and 1 MHz.

[0034] Based on the adaptation rate mode information, the matching operating frequency records in the comparison results are read sequentially at a preset operating frequency to determine the adaptation operating frequency information. That is, all matching operating frequencies are recorded, and the highest operating frequency is selected as the adaptation operating frequency information. For example, in dual-line rate mode, if the comparison is inconsistent when reading data at 100 MHz and 50 MHz respectively, but consistent when reading at 20 MHz, then the adaptation operating frequency information is determined to be 20 MHz. This frequency is the highest frequency at which the flash memory chip can stably operate in the current rate mode.

[0035] In a specific embodiment, such as Figure 3 As shown, Figure 3 To establish the optimal configuration selection flowchart for the adaptive training of the chip startup and operation control method in this application, the Flash memory can be switched to normal data read / write mode, the adaptive adaptation data area erased, and 64 bytes of test data randomly written. The Flash memory can then be switched to XIP mode, with initialization parameters set to a working frequency of 1MHz, a rate mode of 4 lines, and QPI mode enabled. The Flash memory is then put into QPI mode. The previously written 64 bytes of data are read through XIP mode and compared with the original data. If they match, it is recorded that the Flash memory supports QPI mode and the rate mode supports 4 lines, and the corresponding configuration is maintained. If they do not match, it is recorded that QPI mode is not supported, QPI configuration is disabled, and the 1MHz working frequency is maintained. Then... The system first attempts to read data in 4-line, 2-line, and 1-line rate modes. By comparing the data, the maximum read rate mode supported by the Flash is determined and recorded. Based on this, while maintaining the recorded QPI support and rate mode, the system reads data from the adaptive data area at operating frequencies of 100MHz, 50MHz, 20MHz, 10MHz, 5MHz, and 1MHz. By comparing the results, the maximum supported operating frequency is determined and recorded. Finally, the Flash is switched back to normal data read / write mode, and the recorded QPI support, rate mode, and maximum operating frequency are written to the XIP optimal configuration storage area. Then, the Flash controller is switched to XIP mode and the running version is started with the optimal configuration.

[0036] It should be understood that by traversing the rate modes and operating frequencies step by step and comparing and verifying them separately, the actual performance boundary of the currently connected flash memory chip can be accurately detected, and the information on the adapted rate mode and the adapted operating frequency can be obtained. This ensures that the subsequent online execution mode runs under the optimal configuration that is both stable and high-speed. If this comparison and training process is skipped and the system runs directly with fixed high-frequency parameters, it may cause data reading errors due to exceeding the actual capabilities of the flash memory chip, leading to system startup failure or abnormal operation.

[0037] In one feasible implementation, step S20 may include steps A11 to A13: Step A11: Compare the test data of the adaptive adaptation data area with the read data of the adaptive adaptation data area to determine the comparison result; It is understood that the comparison result is a conclusion indicating whether the test data and read data in the adaptive data area are completely consistent, obtained by comparing them byte by byte. At a low-speed and safe operating frequency, the chip will compare the newly read data from the adaptive data area with the known original test data previously written in that area, byte by byte. If every byte of the two sets of data is exactly the same, the comparison result is consistent, indicating that the data read path under the current configuration is reliable. Conversely, if there is a difference in any byte of data, the comparison result is inconsistent, indicating that the current configuration caused an error in the data reading process or that the flash memory itself does not support this configuration mode.

[0038] Step A12: Determine the adaptation rate mode information under the preset peripheral interface mode configuration based on the comparison results; It should be noted that the adaptation rate mode information is a key parameter used to describe the optimal data bus width mode currently supported by the flash memory, indicating that the flash memory can perform data communication in single-wire, dual-wire, or quad-wire rate modes.

[0039] Understandably, the default peripheral interface mode configuration is an advanced four-wire peripheral interface mode configuration for flash memory. In this mode, instructions, addresses, and data are all transmitted on four data lines to achieve the highest instruction execution efficiency. The core objective of determining the adaptation rate mode information is to automatically determine whether the currently connected flash memory chip supports and can operate stably under the default peripheral interface mode configuration, thereby maximizing the use of the high-speed, wide-bus mode to improve the chip's post-boot performance while ensuring compatibility.

[0040] In one feasible implementation, step A12 may include steps B11-B12: Step B11: When the comparison results are consistent, the adapted rate mode information is the rate mode that supports the preset peripheral interface mode configuration. Understandably, when the data read and written test data are completely consistent after operating at the preset frequency in four-wire rate mode and with the four-wire peripheral interface mode enabled, it indicates that the flash memory chip fully supports this efficient four-wire communication mode. At this time, the chip will record the four-wire mode as the adaptation rate mode information. This means that during the chip's startup and online execution, the flash memory controller can safely maintain the four-wire peripheral interface mode configuration and use the four-wire rate mode to interact with the flash memory for instructions and data in order to obtain the maximum data throughput bandwidth.

[0041] Step B12: When the comparison result is inconsistent, the adapted rate mode information is a rate mode that does not support the preset peripheral interface mode configuration and maintains the preset operating frequency configuration. The preset operating frequency configuration includes at least one of 100 MHz, 50 MHz, 20 MHz, 10 MHz, 5 MHz and 1 MHz.

[0042] Understandably, when data comparisons are inconsistent, it indicates that the current flash memory cannot support the efficient four-wire peripheral interface mode. At this time, the chip will record the information that the mode is not supported and disable the controller's four-wire peripheral interface configuration, causing the flash memory to return to the standard serial peripheral interface mode. Based on this, the system will try to configure the controller to four-wire, two-wire, and single-wire rate modes sequentially at the current safe operating frequency. Each time, it will reread the data in the adaptive data area using the configured mode and compare it with the test data to find and record the highest data line width mode that the flash memory can actually support as the final adaptation rate mode information, thereby ensuring that reliable baseline communication can be established even on flash memory that does not support advanced features.

[0043] Step A13: Based on the adaptation rate mode information, read the working frequency records that are consistent in the comparison results at a preset working frequency in sequence to determine the adaptation working frequency information.

[0044] Understandably, after determining the highest speed mode that the flash memory can support, it is necessary to find the highest clock frequency at which the flash memory can operate stably in this mode. To do this, the chip will maintain the determined adaptation speed mode configuration and then adjust the operating frequency of the flash memory controller in descending order, for example, from 100 MHz to 1 MHz. At each frequency point, the operation of reading and comparing the adaptive adaptation data area will be re-executed. The highest frequency at which the read data is completely consistent with the original test data will be recorded as the adaptation operating frequency information, ensuring that the set operating frequency can achieve zero-error reliability performance on the current flash memory.

[0045] Step S30: Determine the adaptation parameter configuration information and the corresponding link script configuration information based on the adaptation rate mode information and the adaptation working frequency information; It should be noted that the adaptation parameter configuration information is a set of runtime parameters that can be directly loaded and applied by the flash memory controller. It may include a boot flag, runtime version, configuration data, optimal configuration storage area, and adaptive configuration data usage area, so as to run the online execution mode in the best performance state on the currently connected flash memory chip. The linker script configuration information is configuration information generated during the software compilation stage, which defines the layout rules of each code segment and data segment of the program in the processor address space, and in particular specifies which code segments need to be linked to static random access memory for execution in a specific mode.

[0046] In a specific embodiment, the corresponding configuration parameters can be integrated based on the adaptation rate mode information and adaptation operating frequency information to generate adaptation parameter configuration information. This information can be used in the current boot process and is persistently stored in the XIP optimal configuration storage area of ​​the flash memory. The configuration parameters can include parameters such as QPI mode support, rate mode, and maximum operating frequency. Organizing them in a preset format allows the chip to directly read and load from this area upon restarting, eliminating the need for repeated training and starting the running version in the optimal online execution mode. For example, when the chip powers on again, the initialization code first checks whether there is valid adaptation parameter configuration information in the XIP optimal configuration storage area. If it exists, it reads and loads it directly without repeating the adaptive training process. This allows the optimal parameter configuration of the flash controller to be completed in a very short time, thereby significantly accelerating the chip's boot speed, enabling the system to quickly enter the optimal performance operating state, and significantly improving performance.

[0047] The linker script configuration information can be obtained during the compilation and build phase of the runtime version. This means that specific field modifiers, such as "attribute((section("sram_exec")))", can be used in the source code to annotate code segments related to exception vector tables and flash operations. Simultaneously, the compiler's linker script file is modified to identify these specific field modifiers and add corresponding mapping rules. This instructs the linker to locate the code segments with these modifiers in the static random access memory (SRAM) address space, thus obtaining the linker script configuration information. For example, adding an output segment to the linker script and mapping its starting address to the base address of SRAM will automatically arrange all marked code within this address range.

[0048] It should be understood that if the linker script configuration information is not generated correctly during the compilation phase, it will result in the inability to properly move critical code segments to static random access memory during the initialization process, which may cause system crashes or malfunctions during flash write / erase operations.

[0049] Step S40: The exception vector table of the link script configuration information and the corresponding flash code segment are configured to be linked to a preset access area to obtain the directed link configuration information; It should be noted that the aforementioned targeted link configuration information is the link layout information that, during the compilation phase, modifies the linker script to remap and fix the exception vector table and flash operation-related code segments from the original default flash address space to the static random access memory (SRAM) address space. This information may include the target starting address and length of the code segments in SRAM, and clearly defines which code segments need to be moved from flash memory to SRAM for execution during the initialization phase. This configuration ensures that the processor's exception handling mechanism can still operate normally when the flash controller switches to normal data read / write mode and stops online execution mode instruction fetching.

[0050] In a specific embodiment, the exception vector table and corresponding flash code segments in the linker script configuration information are modified to determine the modification parameter information. Based on the modification parameter information, the linker script links to a preset access area to obtain the directed link area information. The preset access area is the static random access memory area. That is, during the compilation stage of the runtime version, the linker script file is modified to identify the code segments marked by specific field modifiers in the modification parameter information in the source code. For example, the exception vector table and flash operation-related code segments modified by "attribute((section("sram_exec")))". The linker script links these code segments to the address space of static random access memory, instead of the default flash address space. After compilation, the code segment distribution in the firmware file is the directed link configuration information, which specifies the exact location of the exception vector table, flash read / write code segments, etc. in static random access memory.

[0051] Obtain initialization code information; based on the initialization code information, move the exception vector table, flash memory code segment, and read / write code segment in the directed link area information to a preset access area for configuration, and determine the first directed link configuration information; based on the initialization code information, configure the read-only data segment and other code segments in the directed link area information, and determine the second directed link configuration information; based on the first and second directed link configuration information, obtain the directed link configuration information, that is, the initialization code traverses the load address and runtime address mapping table in the directed link area information, calls the memory copy function to move the exception vector table, flash memory operation-related code segments, and read / write code segments to a preset access area for configuration, and determines the first directed link configuration information; based on the first and second directed link configuration information, obtain the directed link configuration information, that is, the initialization code traverses the load address and runtime address mapping table in the directed link area information, calls the memory copy function to move the exception vector table, flash memory operation-related code segments, and read / write code segments to a preset access area for configuration, and determines the second directed link configuration information. The read / write code segments are moved one by one from the load address in flash memory to the corresponding execution address in static random access memory (SRAM). The processor's vector table base address register is then reset to the starting address of the exception vector table in SRAM. This completes the establishment of the first directed link configuration information. After the transfer is complete, for read-only data segments and other code segments marked as having their load domain located in flash memory and also in flash memory, no copy operation is performed. Instead, the online execution mode parameters of the flash controller are configured to ensure that the processor can directly and correctly fetch instructions and read constant data from flash memory. This completes the establishment of the second directed link configuration information, thus obtaining the configuration for different version partitions, such as... Figure 4 As shown, Figure 4 This diagram illustrates the code segment partitioning configuration of the chip startup and operation control method in this application. The distribution of each segment in the Flash version partition includes: an exception vector table, Flash operation-related code segments, other code segments, read-only data segments, and read-write data segments. During version operation, the distribution of each segment in the SRAM area is: an exception vector table, Flash operation-related code segments, read-write data segments, and other related code segments or data segments that still need to run in SRAM. With this configuration, the SOC chip can efficiently fetch instructions directly from the flash memory to execute the main application in online execution mode during normal operation. When firmware upgrades or configuration modifications are required and the flash memory is switched to normal read-write mode, since the exception vector table and flash operation code reside in the static random access memory, all interrupts and exceptions of the system can be responded to normally, realizing an embedded operating environment that balances startup efficiency, operating performance, and system stability.

[0052] In one feasible implementation, step S40 may include steps C11-C13: Step C11: Modify the exception vector table and corresponding flash code segment of the link script configuration information, and determine the modification parameter information; It should be noted that the modification parameter information is used to separate the modified code segment from the read-only code segment so that it can be placed in a read-write memory area for execution.

[0053] Understandably, the exception vector table is a jump table for embedded processors to respond to interrupts and exception events. It contains the entry addresses for handling various exceptions such as system power-on reset, hardware errors, and peripheral interrupts, and can maintain the system's real-time responsiveness. The flash code segment is the operation function code directly related to flash erasure, writing, and controller mode switching. It must be moved out of the flash memory itself during execution to avoid instruction fetch conflicts that could lead to system crashes when the flash memory enters the erase / write state.

[0054] Step C12: Based on the modified parameter information, a directional link is established to a preset access area to obtain directional link area information. The preset access area is a static random access memory area. It should be noted that the directional link area information accurately records the load address, execution address, and space size of the modified code segment and data segment in the preset access area, providing a clear mapping relationship for code movement during the chip startup phase.

[0055] Understandably, the default access area is a high-speed static random access memory area inside the chip, which has the same access latency as the processor and the ability to read and write randomly byte by byte. When processing the target file, once the code segment is identified to carry a specific segment name defined in the modification parameter information, the segment will be relocated from the default flash memory address space to the static random access memory address space according to the default mapping rules in the linker script.

[0056] Step C13: Determine the corresponding directed link configuration information based on the directed link region information.

[0057] Understandably, the directed link configuration information is a runtime configuration state formed during the chip startup phase by the initialization code after actually performing transport and remapping operations based on the directed link region information. It is used to enable the exception vector table and flash memory operation code segment to run in static random access memory, while most of the remaining application code and read-only data remain in flash memory and are accessed through online execution mode. This achieves the key goal of maintaining a low overall memory footprint while ensuring normal response to system interruptions during flash memory erase and write operations.

[0058] In one feasible implementation, step C13 may include steps D11-D14: Step D11: Obtain initialization code information; It should be noted that the initialization code information is a piece of boot code that is executed first after the chip is powered on and before jumping to the main application. It contains a complete set of logic for moving code segments and redirecting the system according to the directed link area information. It is written in assembly language or C language and is executed by the reset vector after the system is reset. It is used to copy specific code segments in flash memory to static random access memory, initialize global readable and writable data segments, and remap the exception vector table.

[0059] Step D12: Based on the initialization code information, the exception vector table, flash code segment, and read / write code segment in the directed link area information are moved to the preset access area for configuration, and the first directed link configuration information is determined. It should be noted that the first directional link configuration information is the running configuration state that is directly related to the processor's real-time response capability and system stability after the transfer and remapping operations are completed. This ensures that when the flash memory enters an unreadable erase / write mode, the system's exception handling mechanism and flash memory operation driver can still be executed correctly.

[0060] Understandably, the exception vector table is the entry address table that the processor jumps to when handling all interrupts and exception events. Its correct operation is a prerequisite for maintaining the system clock tick, peripheral response, and error handling. The flash code segment is the low-level driver function that performs physical erasure and programming of flash memory. It must have independent execution capability when the flash memory is unreadable. The read / write code segment is the control logic code used to manage flash read / write operations and mode switching.

[0061] Step D13: Based on the initialization code information, configure the read-only data segment and other code segments in the directed link area information to determine the second directed link configuration information; It should be noted that the second directional link configuration information is a configuration state established for code segments and data segments that are still stored in flash memory and accessed through online execution mode. This allows the system to access the main logic and constant data of the application normally while ensuring low static access memory resource consumption.

[0062] Understandably, the read-only data segment is a collection of immutable data such as constant data, lookup tables, and string literals defined in the program. Its contents remain unchanged during program execution. Other code segments are the main application code, excluding exception vector tables and flash operation-related code, including business logic functions, algorithm libraries, etc. They do not need to be executed during flash erase and write, so they can be safely left in flash memory for instruction fetching in online execution mode.

[0063] Step D14: Obtain the directed link configuration information based on the first directed link configuration information and the second directed link configuration information.

[0064] Understandably, the directed link configuration information integrates the configuration of critical code segments that need to be moved to static random access memory and the configuration of main code segments that are kept in flash memory for online execution, so that the processor can access the correct code and data in different operating scenarios.

[0065] Step S50: Control the flash controller to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

[0066] It should be noted that the aforementioned runtime configuration information is a set of runtime parameters used to guide the collaborative work of the flash memory controller and processor system. These parameters include, for example, peripheral interface mode, speed mode, operating frequency, the location of the exception vector table in static random access memory, and the execution address of the flash memory operation code segment. This ensures that the system remains in a stable and controllable operating state when the chip switches between online execution mode and normal data read / write mode.

[0067] In a specific embodiment, version upgrade information is obtained, and corresponding mode switching information is determined based on the version upgrade information. When the mode switching information indicates a switch to online execution mode, the flash controller is controlled to operate normally according to the running configuration information corresponding to the adaptation parameter configuration information and the directed link configuration information. That is, when the version upgrade information indicates a version upgrade, if the mode switching information indicates a switch to normal data read / write mode, the boot flag stored in the boot flag area is read to determine whether the currently running version is A or B. An upgrade operation is performed on the partition of the non-currently running version. If the boot flag points to running version A, the partition of running version B is erased and written; if the boot flag points to running version B... Then, the firmware is erased and written to the running version A partition. After the new firmware is written and verified, the system updates the boot flag in the boot flag area to the newly upgraded version partition. It then reads the adaptation parameter configuration information from the XIP optimal configuration storage area again and loads the optimal online execution configuration. At this time, the mode switching information is to switch back to online execution mode, and the processor is guided to jump to the entry address of the new firmware version to continue running. During the entire mode switching process, since the exception vector table always resides in the static random access memory and maintains normal operation, the system's clock interrupt, peripheral response, and exception handling will not be affected. Thus, while ensuring the smooth progress of firmware upgrades and configuration modification operations, the efficiency and stability of the embedded system are maintained.

[0068] It should be understood that, such as Figure 5 As shown, Figure 5This diagram illustrates the mode switching of the chip startup and operation control method in this application. When an upgrade or configuration modification is required during the version operation, the Flash controller is first switched to normal read / write mode. If a version upgrade is performed, the startup flag in the startup flag area is read, the upgrade operation is performed on the non-current running partition, and the startup flag is updated. If configuration data read / write is performed, the corresponding read / write operation is performed directly. After the above operations are completed, data must be read from the XIP optimal configuration storage area and the optimal configuration must be loaded. Then, the Flash controller is switched back to XIP mode to continue running the version.

[0069] This embodiment proposes a chip startup and operation control method, which involves acquiring adaptive adaptation data area test data and adaptive adaptation data area read data; determining adaptation rate mode information and corresponding adaptation operating frequency information based on the comparison results of the adaptive adaptation data area test data and the adaptive adaptation data area read data; determining adaptation parameter configuration information and corresponding linker script configuration information based on the adaptation rate mode information and the adaptation operating frequency information; configuring the exception vector table of the linker script configuration information and the corresponding flash code segment to a preset access area to obtain directed link configuration information; and controlling the flash controller to operate normally based on the operation configuration information corresponding to the adaptation parameter configuration information and the directed link configuration information. This invention solves the technical problem of how to adaptively adapt to various types of flash memory to achieve stable and efficient chip startup and operation control. Compared with existing technologies, this application automatically trains the optimal speed mode and maximum operating frequency for the current flash memory by comparing test data and read data from the flash memory adaptive adaptation data area, and obtains adaptation parameter configuration information. At the same time, by modifying the linker script, the exception vector table and flash code segment are directed to the preset access area for configuration, thereby controlling the normal operation of the flash memory controller. This achieves adaptive adaptation of a single software version to various types of flash memory and maximizes its performance, while ensuring the stability of interrupt response and the high efficiency of system operation during mode switching.

[0070] It should be understood that, such as Figure 6 As shown, Figure 6The diagram below illustrates the startup and operation block diagram of the chip startup and operation control method of this application. After the SOC chip is powered on, it executes the bootrom program to perform adaptive training to select the optimal XIP configuration and writes the optimal configuration into the XIP optimal configuration storage area of ​​Flash. Subsequent restarts can directly read and load from this storage area without repeated training, thereby accelerating the startup process. The startup flag is read and the corresponding running version is selected for startup. During the running version startup process, the readable and writable data segments, Flash operation-related code segments, and exception vector table are moved to SRAM for execution, while other non-Flash operation-related code segments and all read-only data segments remain in Flash and run in XIP mode. When performing version upgrades or configuration data area operations during version operation, the Flash running mode is first switched to normal read and write mode to complete the corresponding operations. After the operations are completed, the data in the XIP optimal configuration storage area is read, and then the Flash running mode is switched back to XIP mode to continue running.

[0071] Based on the first embodiment of this application, in the second embodiment of this application, the same or similar content as the first embodiment can be referred to the above description, and will not be repeated hereafter.

[0072] In this embodiment, refer to Figure 7 , Figure 7 This is a flowchart illustrating Embodiment 2 of the chip startup and operation control method of this application. Step S50 specifically includes steps S51 to S53: Step S51: Obtain version upgrade information; It should be noted that the version upgrade information is a set of information used by the chip to update firmware during operation. This information may include boot flag information and partition information of the running version. The boot flag information is an identifier pre-stored in the Flash boot flag area, such as "VERSION-A" or "VERSION-B". The partition pointed to by the boot flag is the partition where the currently running version is located, and the other partition automatically becomes the upgrade target. The partition information of the running version directly maps to the specific physical partition in the Flash memory where the currently executing firmware program is located, such as running version A partition or running version B partition. By comparing these two types of information, the system can determine its current operating status and lock onto a free and safe backup partition as the target for firmware upgrade.

[0073] In a specific embodiment, boot flag information of the first and second running version partitions is obtained; the partition information of the running version is determined based on the boot flag information; firmware upgrades are performed on partitions not in the current running version based on the partition information of the running version, obtaining version upgrade information. That is, after entering the firmware upgrade process, pre-stored boot flag information is read from the boot flag area of ​​Flash to identify the version partition to be booted when the chip is powered on. For example, a flag value of VERSION-A indicates that the current running version is running version A, and a flag value of VERSION-B indicates that the current running version is running version B. Based on this boot flag information, the partition information of the running version can be determined, that is, the version information of the running version can be clearly defined. The system determines whether the firmware currently being upgraded is running in partition A or partition B. Based on the partition information of the running version, it automatically selects a partition that is not currently running as the target upgrade partition. If the current running version is A, the firmware upgrade operation is performed on partition B; if the current running version is B, the firmware upgrade operation is performed on partition A. The upgrade process includes erasing the original data on the target partition, writing the new firmware to the partition, and completing data verification. After the upgrade operation is completed and the new firmware is confirmed to have been written successfully, the system updates the boot flag in the boot flag area to point to the partition where the new upgrade version is located, thereby obtaining the version upgrade information. The system can record the target partition for the upgrade, the write location of the new firmware, and the updated boot flag.

[0074] In one feasible implementation, step S51 may include steps E11 to E13: Step E11: Obtain the boot tag information of the first and second running version partitions; It should be noted that the boot flag information is a specific identifier stored in the Flash boot flag area, which is used to indicate to the boot program which firmware version should be booted and executed during the chip power-on boot phase. For example, a flag value of VERSION-A indicates that version A should be booted and executed, and a flag value of VERSION-B indicates that version B should be booted and executed.

[0075] Understandably, the first running version partition is an independent physical area in the Flash storage space designated for storing the firmware image of running version A, such as the running version A area. It contains the complete program code, read-only data, and initialization data of that version. The second running version partition is another independent physical area that is parallel to the first running version partition and has the same function, such as the running version B area. It is used to store the firmware image of running version B. The two partitions serve as backup and upgrade target partitions for each other. By reading the boot flag information stored in the boot flag area, the boot pointer relationship of the current version can be determined.

[0076] Step E12: Determine the partition information where the running version is located based on the boot tag information; It should be noted that the partition information of the running version is used to clearly identify the address mapping and status information of the Flash partition where the currently running firmware version is located. For example, when the boot flag information is VERSION-A, the partition information of the running version points to the running version A partition, and when the boot flag information is VERSION-B, the information points to the running version B partition. By parsing the value of the boot flag information, the physical partition location of the currently executing code can be uniquely determined.

[0077] Step E13: Based on the partition information of the running version, perform firmware upgrade on the partition that is not in the current running version to obtain version upgrade information.

[0078] Understandably, firmware upgrades involve writing the new version of the program code into a free partition that is not currently running while the chip is running normally, thus completing the entire firmware update process. Since the currently running partition is never modified, tasks can continue to be executed normally during the upgrade without being affected. At the same time, the exception vector table maintains the continuity of event response because it resides in SRAM. Even if an unexpected power outage occurs during the upgrade process, the chip can still restart from the original partition, effectively preventing risks caused by upgrade failure.

[0079] Step S52: Determine the corresponding mode switching information based on the version upgrade information; It should be noted that the mode switching information is a set of control instructions for the flash memory controller to safely and orderly switch between different operating modes, specifying the conditions under which the flash memory controller should switch from the current mode to the target mode and the state that should be maintained after the switch is completed.

[0080] In a specific embodiment, when the version upgrade information indicates that a firmware upgrade is needed for the free partition, the mode switching information determined accordingly includes the instruction to "switch the flash controller to normal data read / write mode". For example, after the system obtains the version upgrade information that "the current running version is A, and the running version B partition is about to be upgraded", it will immediately generate the corresponding mode switching information. This is used to allow the flash controller to abandon the current efficient online execution instruction fetching mode and enter the normal read / write state that allows sector erasure and data programming. However, when the version upgrade information indicates that the firmware upgrade operation has been completed or the configuration data modification operation has been successfully executed, the mode switching information determined based on this state is completely the opposite. Its content is "switch the flash controller to online execution mode". Therefore, the mode switching information essentially instructs the chip to read the pre-trained and stored adaptation parameters from the XIP optimal configuration storage area and reconfigure the registers of the flash controller to restore it to the high-speed, four-line (or optimal linewidth) online execution state, guiding the processor to jump to the normal execution flow of the new firmware or the original firmware. For example, after the upgrade of version B is completed and verified, the mode switching information will trigger the system to load the optimal XIP configuration and pull the flash controller back from the normal read / write mode to the online execution mode. The whole process realizes closed-loop control of the running mode, improving the overall running efficiency and stability.

[0081] Step S53: When the mode switching information is switched to online execution mode, the flash controller is controlled to operate normally according to the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

[0082] Understandably, controlling the normal operation of the flash memory controller means that it can switch back to high-performance execution state after online operations such as firmware upgrades or configuration modifications are completed, so as to achieve the goal of optimal performance and stable operation for flash memory of different specifications under a single software version.

[0083] In a specific embodiment, after a version upgrade operation or configuration data read / write operation is completed, it is necessary to restore from the current normal data read / write mode to XIP mode to continue normal program execution. At this time, the system reads the adaptation parameter configuration information from the XIP optimal configuration storage area of ​​Flash, including the best QPI mode setting supported by the current Flash, the maximum rate mode (1 line, 2 lines or 4 lines), and the highest operating frequency, and writes them one by one into the corresponding hardware registers of the flash controller to complete the physical layer configuration of the flash controller. At the same time, the system ensures that the processor's exception vector table has been remapped to SRAM and the Flash operation-related code segments reside in SRAM for execution, while the main application code and read-only data segments remain in Flash and are fetched through XIP mode. After completing the corresponding hardware configuration and software layout coordination settings, the runtime configuration information has been fully loaded and taken effect. The flash controller is thus configured to run in XIP mode with the best performance parameters, and the processor continues to fetch instructions directly from Flash to execute the program. The system seamlessly restores to normal operation while maintaining normal response to interrupts and exceptions.

[0084] This embodiment proposes a chip startup and operation control method, which acquires version upgrade information; determines corresponding mode switching information based on the version upgrade information; and controls the flash controller to operate normally according to the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information when the mode switching information indicates switching to online execution mode. This solves the technical problem of how to adaptively adapt to various types of flash memory for stable and efficient chip startup and operation control. Compared with existing technologies, this application automatically identifies the firmware upgrade requirements of the current system by acquiring version upgrade information, determines the flash controller mode switching information to be executed, and when the mode switching information indicates a need to return to online execution mode, loads the adaptation parameter configuration information obtained through adaptive training and the directional link configuration information generated during the compilation stage to obtain the running configuration information to reinitialize the flash controller. This allows for seamless restoration to online execution mode with optimal performance parameters, enabling a seamless switch from normal read / write mode to online execution mode after firmware upgrade, without manual intervention or restart. Simultaneously, it allows the flash to operate at its optimal speed and frequency to fully utilize its performance, ensuring stable and reliable operation and effectively balancing upgrade flexibility, operational efficiency, and system stability.

[0085] This application also provides a chip startup and operation control device, please refer to... Figure 8 The chip startup and operation control device includes: Module 10 is used to acquire test data and read data from the adaptive adaptation data area. Processing module 20 is used to determine the adaptation rate mode information and the corresponding adaptation working frequency information based on the comparison results of the test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area. The processing module 20 is also used to determine the adaptation parameter configuration information and the corresponding link script configuration information based on the adaptation rate mode information and the adaptation working frequency information; Execution module 30 is used to configure the exception vector table of the link script configuration information and the corresponding flash code segment to a preset access area for configuration, so as to obtain the directed link configuration information; The execution module 30 is also used to control the flash controller to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

[0086] The processing module 20 is further configured to compare the test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area to determine the comparison result; Based on the comparison results, the adaptation rate mode information under the preset peripheral interface mode configuration is determined; Based on the adaptation rate mode information, the working frequency records that are consistent in the comparison results are read sequentially at a preset working frequency to determine the adaptation working frequency information.

[0087] The processing module 20 is further configured to, when the comparison result is consistent, adapt the rate mode information to a rate mode that supports the preset peripheral interface mode configuration. When the comparison results are inconsistent, the adapted rate mode information is a rate mode that does not support the preset peripheral interface mode configuration and maintains the preset operating frequency configuration. The preset operating frequency configuration includes at least one of 100 MHz, 50 MHz, 20 MHz, 10 MHz, 5 MHz and 1 MHz.

[0088] The execution module 30 is further configured to modify the exception vector table of the linker script configuration information and the corresponding flash code segment, and determine the modification parameter information; Based on the modified parameter information, a directional link is established to a preset access area to obtain directional link area information. The preset access area is a static random access memory area. The corresponding targeted link configuration information is determined based on the targeted link region information.

[0089] The execution module 30 is also used to obtain initialization code information; Based on the initialization code information, the exception vector table, flash code segment, and read / write code segment in the directed link area information are moved to the preset access area for configuration, and the first directed link configuration information is determined. Based on the initialization code information, the read-only data segment and other code segments in the directed link area information are configured to determine the second directed link configuration information; The redirected link configuration information is obtained based on the first redirected link configuration information and the second redirected link configuration information.

[0090] The execution module 30 is also used to obtain version upgrade information; Based on the version upgrade information, determine the corresponding mode switching information; When the mode switching information indicates switching to online execution mode, the flash controller is controlled to operate normally according to the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

[0091] The execution module 30 is also used to obtain the startup flag information of the first running version partition and the second running version partition; The partition information where the running version is located is determined based on the boot tag information; Based on the partition information of the running version, firmware upgrades are performed on partitions that are not currently running versions to obtain version upgrade information.

[0092] The chip boot and operation control device provided in this application, employing the chip boot and operation control method in the above embodiments, can solve the technical problem of how to adaptively adapt to various types of flash memory to achieve stable and efficient chip boot and operation control. Compared with the prior art, the beneficial effects of the chip boot and operation control device provided in this application are the same as those of the chip boot and operation control method provided in the above embodiments, and other technical features in the chip boot and operation control device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0093] This application provides a chip startup and operation control device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the chip startup and operation control method in the first embodiment described above.

[0094] The following is for reference. Figure 9The diagram illustrates a structural schematic suitable for implementing a chip startup and operation control device according to embodiments of this application. The chip startup and operation control device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 9 The chip startup control device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0095] like Figure 9 As shown, the chip startup and operation control device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in ROM (Read Only Memory) 1002 or a program loaded from storage device 1003 into RAM (Random Access Memory) 1004. RAM 1004 also stores various programs and data required for the operation of the chip startup and operation control device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via bus 1005. Input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touch screens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the chip startup control device to communicate wirelessly or wiredly with other devices to exchange data. While the figure shows chip startup control devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0096] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0097] The chip boot and operation control device provided in this application, employing the chip boot and operation control method in the above embodiments, can solve the technical problem of how to adaptively adapt to various types of flash memory to achieve stable and efficient chip boot and operation control. Compared with the prior art, the beneficial effects of the chip boot and operation control device provided in this application are the same as those of the chip boot and operation control method provided in the above embodiments, and other technical features in this chip boot and operation control device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0098] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0100] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the chip startup and operation control method in the above embodiments.

[0101] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0102] The aforementioned computer-readable storage medium may be included in the chip startup and operation control device; or it may exist independently and not assembled into the chip startup and operation control device.

[0103] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by a chip startup and operation control device, the chip startup and operation control device performs the following actions: acquiring adaptive adaptation data area test data and adaptive adaptation data area read data; determining adaptation rate mode information and corresponding adaptation operating frequency information based on the comparison results of the adaptive adaptation data area test data and the adaptive adaptation data area read data; determining adaptation parameter configuration information and corresponding linker script configuration information based on the adaptation rate mode information and the adaptation operating frequency information; configuring the exception vector table of the linker script configuration information and the corresponding flash memory code segment to a preset access area to obtain directed linker configuration information; and controlling the flash memory controller to operate normally based on the adaptation parameter configuration information and the corresponding operation configuration information of the directed linker configuration information.

[0104] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0106] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0107] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described chip startup and operation control method. This solves the technical problem of how to adaptively adapt to various types of flash memory to achieve stable and efficient chip startup and operation control. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the chip startup and operation control method provided in the above embodiments, and will not be repeated here.

[0108] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A chip startup and operation control method, characterized in that, The method includes: Obtain test data and read data from the adaptive adaptation data area; Based on the comparison results of the test data and the read data of the adaptive adaptation data area, the adaptation rate mode information and the corresponding adaptation working frequency information are determined. Based on the adaptation rate mode information and the adaptation working frequency information, determine the adaptation parameter configuration information and the corresponding link script configuration information; The exception vector table of the linking script configuration information and the corresponding flash code segment are configured to be linked to a preset access area to obtain the targeted linking configuration information. The flash memory controller is controlled to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directed link configuration information.

2. The method as described in claim 1, characterized in that, The step of determining the adaptation rate mode information and the corresponding adaptation operating frequency information based on the comparison results of the test data and the read data of the adaptive adaptation data area includes: The test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area are compared to determine the comparison result; Based on the comparison results, the adaptation rate mode information under the preset peripheral interface mode configuration is determined; Based on the adaptation rate mode information, the working frequency records that are consistent in the comparison results are read sequentially at a preset working frequency to determine the adaptation working frequency information.

3. The method as described in claim 2, characterized in that, The step of determining the adaptation rate mode information under the preset peripheral interface mode configuration based on the comparison result includes: When the comparison results are consistent, the adapted rate mode information is the rate mode that supports the preset peripheral interface mode configuration. When the comparison results are inconsistent, the adapted rate mode information is a rate mode that does not support the preset peripheral interface mode configuration and maintains the preset operating frequency configuration. The preset operating frequency configuration includes at least one of 100 MHz, 50 MHz, 20 MHz, 10 MHz, 5 MHz and 1 MHz.

4. The method as described in claim 1, characterized in that, The step of configuring the exception vector table of the linking script configuration information and the corresponding flash code segment to a preset access area to obtain the targeted linking configuration information includes: The exception vector table and corresponding flash code segment of the linker script configuration information are modified to determine the modification parameter information; Based on the modified parameter information, a directional link is established to a preset access area to obtain directional link area information. The preset access area is a static random access memory area. The corresponding targeted link configuration information is determined based on the targeted link region information.

5. The method as described in claim 4, characterized in that, The step of determining the corresponding redirection configuration information based on the redirection region information includes: Get initialization code information; Based on the initialization code information, the exception vector table, flash code segment, and read / write code segment in the directed link area information are moved to the preset access area for configuration, and the first directed link configuration information is determined. Based on the initialization code information, the read-only data segment and other code segments in the directed link area information are configured to determine the second directed link configuration information; The redirected link configuration information is obtained based on the first redirected link configuration information and the second redirected link configuration information.

6. The method as described in claim 1, characterized in that, The step of controlling the flash controller to operate normally based on the runtime configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information includes: Get version upgrade information; Based on the version upgrade information, determine the corresponding mode switching information; When the mode switching information indicates switching to online execution mode, the flash controller is controlled to operate normally according to the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

7. The method as described in claim 6, characterized in that, The steps for obtaining version upgrade information include: Obtain the boot tag information of the first and second running version partitions; The partition information where the running version is located is determined based on the boot tag information; Based on the partition information of the running version, firmware upgrades are performed on partitions that are not currently running versions to obtain version upgrade information.

8. A chip startup and operation control device, characterized in that, The device includes: The acquisition module is used to acquire test data and read data from the adaptive adaptation data area. The processing module is used to determine the adaptation rate mode information and the corresponding adaptation working frequency information based on the comparison results of the test data of the adaptive adaptation data area and the read data of the adaptive adaptation data area. The processing module is also used to determine the adaptation parameter configuration information and the corresponding link script configuration information based on the adaptation rate mode information and the adaptation working frequency information; The execution module is used to redirect the exception vector table of the linked script configuration information and the corresponding flash code segment to a preset access area for configuration, thereby obtaining the redirected link configuration information; The execution module is also used to control the flash controller to operate normally based on the running configuration information corresponding to the adaptation parameter configuration information and the directional link configuration information.

9. A chip-based startup and operation control device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip startup and operation control method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the chip startup and operation control method as described in any one of claims 1 to 7.

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