Debugging module, debugging system, debugging method and storage medium
By introducing a debugging module into the system-on-a-chip (SoC), and utilizing the synchronous operation of auxiliary and comparison modules and the comparison of data signals, real-time monitoring and rapid location of anomalies in the SoC are achieved, thus solving the problem of debugging and troubleshooting SoCs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2024-12-27
- Publication Date
- 2026-06-30
AI Technical Summary
Vulnerabilities that occur in the operating mode of a system-on-a-chip are difficult to expose in the debug mode, increasing the difficulty of debugging.
A debugging module is adopted, including an auxiliary module and a comparison module. The auxiliary module runs synchronously with the module under test, generates and compares data signals to output abnormal signals, and realizes real-time monitoring and rapid location of abnormalities.
It can quickly and accurately locate the abnormal position of the module under test without putting the system-on-a-chip into debug mode, simplifying the debugging process.
Smart Images
Figure CN122309328A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of testing technology, and in particular to a debugging module, debugging system, debugging method and storage medium. Background Technology
[0002] As System-on-Chips (SoCs) become increasingly larger and their applications more complex, debugging and troubleshooting SoCs play a more significant role in product development. A typical SoC debugging process involves configuring the SoC in debug mode and using a host computer to control the SoC's processor core to execute application instructions to determine if the SoC is functioning correctly. However, some vulnerabilities (bugs) that appear in the operating mode of an SoC are not exposed in debug mode, increasing the difficulty of debugging and troubleshooting SoCs. Summary of the Invention
[0003] Based on this, this disclosure provides a debugging module, debugging system, debugging method, and storage medium, which can simplify the debugging of the module under test and quickly and accurately locate the location of the abnormality in the module under test.
[0004] A debugging module is used to test a module under test (DUT) in a microprocessor. The DUT includes a processor core configured to execute test instructions according to a program under test (SUB) to generate a plurality of first data signals. The debugging module includes:
[0005] An auxiliary module includes a processor core identical to the processor core under test. The processor core is configured to run auxiliary instructions according to an auxiliary program to generate multiple second data signals. The auxiliary program is identical to the program under test, and the auxiliary instructions are identical to the instructions under test. The auxiliary module and the module under test run synchronously, and multiple preset times during the synchronous operation correspond to the multiple first data signals and the multiple second data signals, respectively.
[0006] The comparison module is connected to the module under test and the auxiliary module respectively, and is used to acquire the first data signal and the second data signal at each preset time. When the first data signal and the second data signal are different, the comparison signal representing the occurrence of the target anomaly is output. The target anomaly includes at least one of the anomaly of the program under test and the anomaly of the instruction under test.
[0007] In one embodiment, the microprocessor further includes:
[0008] A data buffer processing module is connected to the module under test and the comparison module respectively, and is used to acquire and store multiple first data signals, as well as the correspondence between the multiple first data signals and the instruction under test and the program under test, and to send the corresponding first data signal to the comparison module according to each preset time.
[0009] In one embodiment, the debugging module is independent of the microprocessor, and the debugging module further includes:
[0010] The data buffer module is connected to the auxiliary module and the comparison module respectively, and is used to acquire and store multiple second data signals, and send the corresponding second data signal to the comparison module according to each preset time.
[0011] In one embodiment, the debugging module further includes:
[0012] The first debugging interface control unit is connected to the comparison module;
[0013] The microprocessor also includes:
[0014] The second debugging interface control unit is connected to the data buffer processing module and the first debugging interface control unit, respectively.
[0015] The data buffer processing module receives a read instruction signal sent by the first debugging interface control unit, and sends the first data signal corresponding to each preset time to the comparison module according to the read instruction signal.
[0016] In one embodiment, the data buffering module includes:
[0017] A first state machine is connected to the module under test and is used to receive and, according to a first clock signal including each preset time, sequentially send a plurality of first data signals, the program under test corresponding to each first data signal, and the instruction under test;
[0018] The first memory is connected to the module under test, the first state machine, and the second debug interface control unit, respectively. It is used to store the first data signal sent by the first state machine, as well as the program under test and the instruction under test corresponding to the first data signal, in the corresponding storage address according to the first clock signal and the corresponding preset time. Multiple first data signals and multiple storage addresses correspond to each other. The first data signal is sent sequentially according to the second clock signal in the read instruction signal.
[0019] The parallel-to-serial conversion unit is connected to the first memory and the second debugging interface control unit respectively. It is used to receive and convert the first data signal of parallel data into the first data signal of serial data, and send the first data signal of serial data to the second debugging interface control unit in sequence according to the second clock signal.
[0020] The comparison module is used to compare the first data signal of the parallel data corresponding to the first data signal of the serial data and the second data signal of the parallel data.
[0021] In one embodiment, the comparison module includes:
[0022] A serial-to-parallel conversion unit, connected to the first debugging interface control unit, is used to receive and convert the first data signal of serial data into the first data signal of parallel data, and to send the first data signal of parallel data sequentially according to the first clock signal.
[0023] The first data comparison circuit is connected to the serial-to-parallel conversion unit and the data buffer module, respectively, and is used to receive and compare the second data signal at a preset time with the first data signal of the parallel data output by the serial-to-parallel conversion unit.
[0024] In one embodiment, the data buffer module includes:
[0025] The second state machine, connected to the auxiliary module, is used to receive and sequentially send multiple second data signals according to a first clock signal including multiple preset times.
[0026] The second memory is connected to the auxiliary module, the second state machine, and the comparison module, respectively. It is used to store the second data signals of the parallel data sent by the second state machine in the corresponding storage addresses according to the first clock signal and at the corresponding preset time. The multiple second data signals and multiple storage addresses correspond to each other. It also sends the second data signals of the parallel data to the comparison module according to the first clock signal.
[0027] In one embodiment, the debugging module is integrated inside the microprocessor, and the data buffer processing module and the comparison module are connected via a bus.
[0028] In one embodiment, the data buffering module includes:
[0029] The third state machine is connected to the module under test and is used to receive and, according to the first clock signal including each preset time, sequentially send a plurality of first data signals, the program under test corresponding to each first data signal and the instruction under test;
[0030] The third memory is connected to the third state machine, the module under test, and the comparison module, respectively. It is used to store the first data signal sent by the third state machine, as well as the program under test and the instruction under test corresponding to the first data signal, in the corresponding storage address according to the first clock signal and the corresponding preset time. Multiple first data signals and multiple storage addresses correspond to each other. It also sends the first data signals of parallel data to the comparison module in sequence according to the first clock signal.
[0031] The auxiliary module sequentially sends the second data signal of the parallel data to the comparison module according to the first clock signal.
[0032] In one embodiment, the comparison module includes:
[0033] The second data comparison circuit is connected to the third memory and the auxiliary module respectively, and is used to receive and compare the first data signal of the parallel data and the second data signal of the parallel data.
[0034] In one embodiment, the comparison module is further configured to output execution information corresponding to the first data signal when the first data signal and the second data signal are different. The execution information includes the instruction to be tested corresponding to the first data signal, the program to be tested corresponding to the first data signal, and the position information of the program to be tested running corresponding to the first data signal.
[0035] In one embodiment, the module under test further includes: a program under test storage module, which is connected to the core of the processor under test and stores the program under test internally;
[0036] The auxiliary module includes:
[0037] An auxiliary program storage module is connected to the processor core and stores the auxiliary program inside.
[0038] A debugging system, comprising:
[0039] Such as the debugging module and the microprocessor described above;
[0040] The host computer, connected to the debugging module, is used to acquire and display a comparison signal and the execution information corresponding to the first data signal when the first data signal and the second data signal are different.
[0041] The execution information includes the instruction to be tested corresponding to the first data signal, the program to be tested corresponding to the first data signal, and the location information of the program to be tested running corresponding to the first data signal.
[0042] A debugging method, comprising:
[0043] Acquire multiple first data signals generated by the processor core under test in the module under test according to the instructions under test executed by the program under test;
[0044] The processor core in the auxiliary module acquires multiple second data signals generated by the auxiliary program running auxiliary instructions; the auxiliary module and the module under test run synchronously, and multiple preset times during the synchronous operation correspond to the multiple first data signals and the multiple second data signals respectively; the auxiliary program and the program under test are the same, and the auxiliary instructions and the instructions under test are the same;
[0045] When the first data signal and the second data signal are different at a preset time, a comparison signal representing the occurrence of a target anomaly is output; the target anomaly includes at least one of the program under test anomaly and the instruction under test anomaly.
[0046] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the debugging method described above.
[0047] In the aforementioned debugging module, the processor core in the auxiliary module and the processor core under test in the module under test are configured to run the same instructions according to the same program, generating multiple first data signals and multiple second data signals respectively. The comparison module acquires the first and second data signals at preset times during the synchronous operation of the auxiliary module and the module under test, and outputs a comparison signal indicating the occurrence of a target anomaly when the first and second data signals are different. This enables real-time monitoring of the processor core under test running the instructions under test according to the program under test, without requiring the microprocessor to be in debug mode. Furthermore, the debugging module's testing process of the module under test in the microprocessor can completely reproduce the application scenario of the processor core under test running the instructions under test according to the program under test. When an anomaly occurs, the corresponding instructions and program under test can be quickly located, thereby accurately pinpointing the location of the anomaly and simplifying the debugging of the module under test in the microprocessor.
[0048] In the aforementioned debugging system, the processor core in the auxiliary module of the debugging module and the processor core under test in the module under test are configured to run the same instructions according to the same program, generating multiple first data signals and multiple second data signals respectively. The comparison module acquires the first and second data signals at preset moments during the synchronous operation of the auxiliary module and the module under test, and outputs a comparison signal indicating the occurrence of a target anomaly when the first and second data signals are different. This enables real-time monitoring of the processor core under test running the instructions under test according to the program under test, without requiring the microprocessor to be in debug mode. Furthermore, the process of testing the module under test in the microprocessor can completely reproduce the application scenario of the processor core under test running the instructions under test according to the program under test. When an anomaly occurs, the corresponding instructions and program under test can be quickly located, thereby accurately locating the location of the anomaly and simplifying the debugging of the module under test in the microprocessor.
[0049] In the above debugging method, the comparison module acquires multiple first data signals generated by the processor core of the module under test (DUT) running the instruction under test according to the program under test (UTT), and multiple second data signals generated by the processor core of the auxiliary module running synchronously with the DUT running the auxiliary instruction according to the auxiliary program. When the first and second data signals differ at a preset time, a comparison signal indicating a target anomaly is output. This enables real-time monitoring of the processor core running the instruction under test according to the program under test, without requiring the microprocessor to be in debug mode. Furthermore, this debugging method can completely reproduce the application scenario of the processor core running the instruction under test according to the program under test. When an anomaly occurs, the corresponding instruction and program under test can be quickly located, thus accurately pinpointing the location of the anomaly and simplifying debugging of the DUT in the microprocessor. Attached Figure Description
[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 This is a schematic diagram of the debugging module in some embodiments;
[0052] Figure 2 This is a schematic diagram of the debugging module in some other embodiments;
[0053] Figure 3 This is a schematic diagram of the debugging module in some embodiments;
[0054] Figure 4 This is a schematic diagram of the debugging module in some other embodiments;
[0055] Figure 5 This is a schematic diagram of the data buffer processing module in some embodiments;
[0056] Figure 6 This is a schematic diagram of the data processing pipeline in some embodiments of the data buffer processing module;
[0057] Figure 7 This is a schematic diagram of the data storage structure for multiple memory addresses in the first memory.
[0058] Figure 8 This is a schematic diagram of the comparison module in some embodiments;
[0059] Figure 9 This is a schematic diagram of the data buffer module in some embodiments;
[0060] Figure 10 This is a schematic diagram of the debugging module in another embodiment;
[0061] Figure 11 This is a schematic diagram of the debugging module in another embodiment;
[0062] Figure 12 This is a schematic diagram of the data buffer processing module in some other embodiments;
[0063] Figure 13 This is a schematic diagram of the debugging system in some embodiments;
[0064] Figure 14 This is a schematic diagram of the debugging system in some other embodiments;
[0065] Figure 15 This is a flowchart illustrating the debugging method in some embodiments. Detailed Implementation
[0066] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0068] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first memory may be referred to as a second memory, and similarly, a second memory may be referred to as a first memory. Both the first memory and the second memory are memories, but they are not the same memory.
[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "several" means at least one, such as one, two, etc., unless otherwise expressly specified.
[0070] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0071] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.
[0072] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0073] Figure 1 This is a schematic diagram of the debugging module in some embodiments, see [link / reference]. Figure 1 In this embodiment, a debugging module 100 is provided for testing a module under test 202 in a microprocessor. The module under test 202 includes a processor core 2021 under test, which is configured to run test instructions according to the program under test to generate multiple first data signals. The debugging module 100 includes an auxiliary module 102 and a comparison module 104.
[0074] The auxiliary module 102 includes a processor core 1021 that is the same as the processor core 2021 under test. The processor core 1021 is configured to run auxiliary instructions according to an auxiliary program to generate multiple second data signals. The auxiliary program is the same as the program under test, and the auxiliary instructions are the same as the instructions under test. The auxiliary module 102 and the module under test 202 run synchronously, and multiple preset times during the synchronous operation correspond to the multiple first data signals and the multiple second data signals, respectively.
[0075] The comparison module 104 is connected to the test module 202 and the auxiliary module 102 respectively, and is used to acquire the first data signal and the second data signal at each preset time. When the first data signal and the second data signal are different, the comparison signal representing the occurrence of the target abnormality is output. The target abnormality includes at least one of the test program abnormality and the test instruction abnormality.
[0076] Understandably, the processor core 2021 under test is configured to run multiple instructions under test based on multiple programs under test. These instructions and programs correspond to each other; the instructions under test are those executed by the processor core 2021 under test under normal operation, and the programs under test are the programs corresponding to those instructions. After executing an instruction under test based on any program under test, multiple corresponding first data signals are generated. The processor core 1021 is configured to run multiple auxiliary instructions based on multiple auxiliary programs. These auxiliary instructions and programs correspond to each other, and after executing an auxiliary instruction based on any auxiliary program, multiple corresponding second data signals are generated. As an example, the processor core 2021 under test includes RISC8 and RISC32 processor cores.
[0077] As an example, the first data signal includes register variables generated by the processor under test core 2021 when it runs the instruction under test according to the program under test. The register variables include the program pointer counter and the stack pointer, which can protect the field data during the process of running the instruction under test according to the program under test to the greatest extent.
[0078] During the synchronous operation of the auxiliary module 102 and the module under test 202, the auxiliary module 102 and the module under test 202 are configured to run the same auxiliary instructions and the instructions under test according to the same auxiliary program and the program under test, respectively. They also generate multiple first data signals and multiple second data signals. Any preset time during the synchronous operation corresponds to a set of first and second data signals. The comparison module 104 acquires the first and second data signals at each preset time. When the first and second data signals are different, it indicates that the program under test and the auxiliary program at the preset time corresponding to the first data signal are not actually the same, and the program under test has an anomaly at that preset time; and / or the instructions under test and the auxiliary instructions corresponding to the first data signal are not actually the same, and the instructions under test have an anomaly at that preset time. The comparison module outputs a comparison signal indicating the occurrence of the target anomaly.
[0079] Understandably, when the first data signal and the second data signal are the same, the comparison module 104 indicates that the program to be tested and the auxiliary program corresponding to the preset time of the first data signal are actually the same, and the instruction to be tested and the auxiliary instruction corresponding to the preset time of the first data signal are actually the same, thus confirming that the program to be tested and the instruction to be tested corresponding to the preset time of the first data signal are both normal.
[0080] In the aforementioned debugging module, the processor core 1021 in the auxiliary module 102 and the processor core 2021 under test in the module under test 202 are configured to run the same instructions according to the same program, generating multiple first data signals and multiple second data signals respectively. The comparison module 104 acquires the first and second data signals at preset times during the synchronous operation of the auxiliary module 102 and the module under test 202, and outputs a comparison signal indicating the occurrence of a target anomaly when the first and second data signals are different. This enables real-time monitoring of the processor core 2021 under test running the instructions under test according to the program under test, without requiring the microprocessor to be in debug mode. Furthermore, the process of this debugging module testing the module under test 202 in the microprocessor can completely reproduce the application scenario of the processor core 2021 under test running the instructions under test according to the program under test. When an anomaly occurs, the corresponding instructions and program under test can be quickly located, thereby accurately locating the location of the anomaly and simplifying the debugging of the module under test 202 in the microprocessor.
[0081] See Figure 1 In one embodiment, the module under test 202 further includes: a program under test storage module 2022, which is connected to the processor core 2021 under test and stores the program under test internally. The processor core 2021 under test acquires and executes the program under test corresponding to the program under test in its internal instruction set according to the program under test stored in the program under test storage module 2022. The auxiliary module 102 includes: an auxiliary program storage module 1022, which is connected to the processor core 1021 and stores the auxiliary program internally. The processor core 1021 acquires and executes the auxiliary program corresponding to the auxiliary program in its internal instruction set according to the auxiliary program stored in the auxiliary program storage module 1022.
[0082] Figure 2 For structural diagrams of the debugging module in other embodiments, see [link / reference]. Figure 2In one embodiment, the microprocessor further includes a data buffer processing module 204. The data buffer processing module 204 is connected to both the module under test (DUT) 202 and the comparison module 300, and is used to acquire and store multiple first data signals, as well as the correspondence between the multiple first data signals and the instruction under test and the program under test. It also sends the corresponding first data signal to the comparison module 300 according to each preset time. The data buffer processing module 204 stores multiple first data signals and the correspondence between the multiple first data signals and the instruction under test and the program under test. When the comparison module 104 determines that the first data signal and the second data signal are different, it can retrieve the instruction under test and the program under test corresponding to the first data signal from the data buffer processing module 204, thereby quickly locating the anomaly.
[0083] In one embodiment, the debugging module 100 is independent of the microprocessor 200. The debugging module 100 further includes a data buffer module 106. The data buffer module 106 is connected to both the auxiliary module 102 and the comparison module 104, and is used to acquire and store multiple second data signals, and send the corresponding second data signal to the comparison module 104 according to each preset time. The data buffer module 106 can store the second data signals and control the timing of their transmission to the comparison module. This avoids the difference between the transmission rate of the first data signal from the microprocessor 200 to the comparison module 104 in the debugging module 100 and the transmission rate of the second data signal from the auxiliary module 102 within the debugging module 100 to the comparison module 104, thus improving the accuracy of the debugging module 100 in detecting anomalies in preset programs and preset instructions.
[0084] Figure 3 For a schematic diagram of the debugging module in some embodiments, see [link / reference]. Figure 3In one embodiment, the debugging module 100 further includes a first debugging interface control unit 108, which is connected to the comparison module 104. The microprocessor 200 further includes a second debugging interface control unit 206, which is connected to both the data buffer processing module 204 and the first debugging interface control unit 108. The connection between the second debugging interface control unit 206 and the first debugging interface control unit 108 enables the connection between the debugging module 100 and the microprocessor 200. The data buffer processing module 204 receives a read instruction signal sent by the first debugging interface control unit 108, and sends the first data signal corresponding to each preset time to the comparison module 104 via the second debugging interface control unit 206 and the first debugging interface control unit 108. By setting the first debugging interface control unit 108 and the second debugging interface control unit 206, the connection and signal transmission between the independent data buffer processing module 204 in the microprocessor 200 and the comparison module 104 in the debugging module 100 are achieved.
[0085] Figure 4 For a schematic diagram of the debugging module in some other embodiments, see [link / reference]. Figure 4 The arrows indicate the direction of data signal or program transmission. The first debug interface control unit 108 and the second debug interface control unit 206 both include a JTAG unit. The program under test storage module 2022, the processor under test core 2021, the data buffer processing module 204, and the second debug interface control unit 206 are connected in sequence via a BUS bus. The auxiliary program storage module 1022, the processor core 1021, the data buffer module 106, the comparison module 104, and the first debug interface control unit 108 are connected in sequence via a BUS bus.
[0086] See Figure 3 and Figure 4 In some embodiments, the debugging module 100 further includes a third debugging interface control unit 110; the third debugging interface control unit 110 is connected to the comparison module 104 and is used to output the comparison signal generated by the comparison module 104 in the debugging module 100. As an example, the third debugging interface control unit 110 includes a JTAG unit.
[0087] Figure 5 This is a schematic diagram of the data buffer processing module in some embodiments, see [link / reference]. Figure 3 , Figure 4 and Figure 5 In one embodiment, the data buffer processing module 204 includes: a first state machine 2041, a first memory 2042, and a parallel-to-serial conversion unit 2043.
[0088] The first state machine 2041 is connected to the processor core 2021 under test in the module under test 202, and is used to receive a first clock signal including each preset time, and sequentially send the first data signal, the program under test and the instruction under test corresponding to each first data signal, the first data signal of the multiple parallel data sent by the processor core 2021 under test according to the first clock signal.
[0089] The first memory 2042 is connected to the processor under test (DUT) core 2021, the first state machine 2041, and the second debug interface control unit 206 in the module under test. It is used to store, according to the first clock signal and a corresponding preset time, the first data signal sent by the first state machine 2041, as well as the program under test and the instruction under test corresponding to the first data signal, in corresponding memory addresses. Multiple first data signals and multiple memory addresses correspond to each other. It also sends the first data signals sequentially according to the second clock signal in the read instruction signal. The first memory 2042 is a dual-port asynchronous FIFO memory; the process of storing the first data signals in the first memory 2042 according to the first clock signal does not affect the sending of the first data signals according to the second clock signal.
[0090] The parallel-to-serial conversion unit 2043 is connected to the first memory 2042 and the second debug interface control unit 206, respectively. It receives and converts the first data signal of the parallel data into a first data signal of the serial data, and sequentially sends the first data signal of the serial data to the second debug interface control unit 206 according to the second clock signal. The comparison module 104 compares the first data signal of the parallel data and the second data signal of the parallel data corresponding to the first data signal of the serial data.
[0091] Figure 6 This is a schematic diagram of the data processing pipeline of the data buffer processing module in some embodiments. Figure 7 This is a schematic diagram of the data storage structure for multiple memory addresses in the first memory. (See attached diagram) Figure 6 , Figure 7 As an example, the first state machine 2041 controls the first memory 2042 of the third-stage pipeline according to the second-stage pipeline (fetch, execute) of the processor under test core 2021. At each of the multiple preset times when the processor under test core 2021 executes the instruction under test according to the program under test, the first memory 2042 sequentially completes the storage, reading, and sending of the first data signal. See also Figure 5 Assuming there are (n+1) preset times, the first data signal at the (n+1) preset times, as well as the part of the program under test and the part of the instruction under test corresponding to the first data signal, are stored in (n+1) memory addresses respectively.
[0092] Figure 8 This is a schematic diagram of the comparison module in some embodiments, see [link / reference]. Figure 8 In one embodiment, the comparison module 104 includes a serial-to-parallel conversion unit 1041 and a first data comparison circuit 1042. The serial-to-parallel conversion unit 1041 is connected to the first debug interface control unit 108 and is used to receive and convert a first data signal of serial data into a first data signal of parallel data, and to send the first data signal of parallel data sequentially according to a first clock signal. The first data comparison circuit 1042 is connected to the serial-to-parallel conversion unit 1041 and the data buffer module 106 respectively, and is used to receive and compare the second data signal at a preset time with the first data signal of parallel data output by the serial-to-parallel conversion unit 1041. The serial-to-parallel conversion unit 1041 converts the first data signal of serial data transmitted from the data buffer processing module 204 in the independent microprocessor 200 to the comparison module 1041 in the debug module 100 into a first data signal of parallel data, so as to compare it with the second data signal of parallel data in the first data comparison circuit 1042.
[0093] Figure 9 This is a schematic diagram of the data buffer module in some embodiments, see [link / reference]. Figure 9 In one embodiment, the data buffer module 106 includes a second state machine 1061 and a second memory 1062. The second state machine 1061 is connected to the processor core 1021 in the auxiliary module 102, and is used to receive a first clock signal including multiple preset times, and sequentially send the second data signals of multiple parallel data sent by the processor core 1021 according to the first clock signal. The second memory 1062 is connected to the processor core 1021, the second state machine 1061 and the comparison module 104 in the auxiliary module 102, respectively, and is used to store the second data signals of the parallel data sent by the second state machine 1061 in corresponding storage addresses according to the first clock signal and the corresponding preset times, with multiple second data signals and multiple storage addresses corresponding to each other; and to sequentially send the second data signals of the parallel data to the comparison module 104 according to the first clock signal.
[0094] Figure 10 This is a schematic diagram of the debugging module in another embodiment. Figure 11 For a schematic diagram of the debugging module in another embodiment, see [link / reference]. Figure 10 , Figure 11 In one embodiment, the debugging module 100 is integrated inside the microprocessor 200, and the data buffer processing module 204 and the comparison module 104 are connected via a bus.
[0095] Figure 12For structural diagrams of the data buffer processing module in other embodiments, see [link / reference]. Figure 12 In one embodiment, the data buffer processing module 204 includes a third state machine 2044 and a third memory 2045. The third state machine 2044 is connected to the processor core 2021 under test in the module under test 202, and is used to receive and sequentially send multiple first data signals, the program under test corresponding to each first data signal, and the instruction under test according to a first clock signal including each preset time. The third memory 2045 is connected to the third state machine 2044, the processor core 2021 under test in the module under test 202, and the comparison module 104, respectively, and is used to store the first data signals sent by the third state machine 2044, as well as the program under test and the instruction under test corresponding to the first data signals, in corresponding preset times according to the first clock signal, with multiple first data signals and multiple storage addresses corresponding to each other; and to sequentially send the first data signals of parallel data to the comparison module 104 according to the first clock signal; wherein, the auxiliary module 102 sequentially sends the second data signals of parallel data to the comparison module 104 according to the first clock signal.
[0096] In one embodiment, the comparison module 104 includes a second data comparison circuit; the second data comparison circuit is connected to the third memory 2045 and the auxiliary module 102 respectively, and is used to receive and compare the first data signal of parallel data and the second data signal of parallel data.
[0097] In one embodiment, the comparison module 104 is further configured to output execution information corresponding to the first data signal when the first data signal and the second data signal are different. The execution information includes the instruction to be tested corresponding to the first data signal, the program to be tested corresponding to the first data signal, and the position information of the program to be tested running corresponding to the first data signal.
[0098] Based on the same inventive concept, this application also provides a debugging system. The solution provided by this debugging system is similar to the solution described in the debugging module above. Therefore, the specific limitations of the debugging module and microprocessor in the debugging system embodiments provided below can be found in the limitations of the debugging module above, and will not be repeated here.
[0099] Figure 13 This is a schematic diagram of the debugging system in some embodiments. Figure 14 For schematic diagrams of the debugging system in other embodiments, see [link / reference]. Figure 13 and Figure 14In this embodiment, a debugging system is provided, including: a debugging module 100 as described above, a microprocessor 200 as described above, and a host computer 300; the host computer 300 is connected to the debugging module 100 and is used to acquire a comparison signal and execution information corresponding to the first data signal when the first data signal and the second data signal are different, and to display the comparison signal and the execution information corresponding to the first data signal; the host computer 300 serves as a human-computer interaction interface; wherein, the execution information includes the instruction to be tested corresponding to the first data signal, the program to be tested corresponding to the first data signal, and the position information of the program to be tested running corresponding to the first data signal.
[0100] In the aforementioned debugging system, the processor core 1021 in the auxiliary module 102 of the debugging module 100 and the processor core 2021 under test in the module under test 202 are configured to run the same instructions according to the same program, generating multiple first data signals and multiple second data signals respectively. The comparison module 104 acquires the first and second data signals at preset times during the synchronous operation of the auxiliary module 102 and the module under test 202, and outputs a comparison signal indicating the occurrence of a target anomaly when the first and second data signals are different. This enables real-time monitoring of the processor core 2021 under test running the instructions under test according to the program under test, without requiring the microprocessor to be in debug mode. Furthermore, the process of testing the module under test 202 in the microprocessor can completely reproduce the application scenario of the processor core 2021 under test running the instructions under test according to the program under test. When an anomaly occurs, the corresponding instructions and program under test can be quickly located, thereby accurately locating the location of the anomaly and simplifying the debugging of the module under test 202 in the microprocessor 200.
[0101] See Figure 13 and Figure 14 In one embodiment, the debugging system further includes a debugging device 400; the debugging device 400 is connected to both the debugging module 100 and the host computer 300, and is used to convert data signals between the debugging module 100 and the host computer 300. As an example, the debugging device 400 includes a USB-JTAG protocol conversion device.
[0102] Based on the same inventive concept, this application also provides a debugging method. The solution provided by this debugging method is similar to the solution described in the debugging module above. Therefore, the specific limitations in the debugging method embodiments provided below can be found in the limitations in the debugging module above, and will not be repeated here.
[0103] Figure 15 This is a flowchart illustrating the debugging method in some embodiments; see [link / reference]. Figure 1 , Figure 15 In this embodiment, a debugging method is provided, including:
[0104] S102, acquire multiple first data signals generated by the processor core under test in the module under test according to the instructions under test executed by the program under test.
[0105] Specifically, the module under test 202 in the microprocessor includes a processor under test core 2021, which is configured to run test instructions according to the program under test to generate multiple first data signals; the comparison module 104 in the debug module 100 acquires the multiple first data signals generated by the processor under test core 2021 running test instructions according to the program under test.
[0106] S104: Obtain multiple second data signals generated by the processor core in the auxiliary module according to the auxiliary program running auxiliary instructions.
[0107] Specifically, the auxiliary module 102 in the debugging module 100 includes a processor core 1021, which is configured to run auxiliary instructions according to an auxiliary program to generate multiple second data signals. The auxiliary program is the same as the program under test, the auxiliary instructions are the same as the instructions under test, the auxiliary module and the program under test run synchronously, and multiple preset times during the synchronous operation correspond to the multiple first data signals and the multiple second data signals respectively. The comparison module 104 obtains the multiple second data signals generated by the processor core 1021 running the auxiliary instructions according to the auxiliary program.
[0108] S106, when the first data signal and the second data signal are different at a preset time, output a comparison signal that indicates the occurrence of a target anomaly.
[0109] When the first data signal and the second data signal are different at a preset time, the comparison module 104 outputs a comparison signal indicating the occurrence of a target anomaly, wherein the target anomaly includes at least one of the anomaly of the program under test and the anomaly of the instruction under test.
[0110] In the above debugging method, the comparison module 104 acquires multiple first data signals generated by the processor core under test (DUT) in the DUT module running the DUT instructions according to the DUT program, and multiple second data signals generated by the processor core in the auxiliary module running synchronously with the DUT module running the auxiliary program running the auxiliary instructions. When the first data signals and second data signals differ at a preset time, a comparison signal indicating a target anomaly is output. This enables real-time monitoring of the processor core 2021 running the DUT instructions according to the DUT program, without requiring the microprocessor to be in debug mode. Furthermore, this debugging method can completely reproduce the application scenario of the processor core 2021 running the DUT instructions according to the DUT program in the microprocessor. When an anomaly occurs, the corresponding DUT instructions and DUT program can be quickly located, thus accurately pinpointing the location of the anomaly and simplifying the debugging of the DUT module 202 in the microprocessor.
[0111] It should be understood that, although Figure 15 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 15 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0112] This disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the debugging method described above.
[0113] This disclosure provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the debugging method described above.
[0114] Those skilled in the art will understand that all or part of the steps in implementing the debugging methods of the above embodiments can be accomplished by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.
[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0116] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A debugging module, characterized in that, A test module for testing a module under test (DUT) in a microprocessor, the DUT including a processor core configured to execute test instructions according to a program under test (SUB) to generate multiple first data signals, the debug module including: An auxiliary module includes a processor core identical to the processor core under test. The processor core is configured to run auxiliary instructions according to an auxiliary program to generate multiple second data signals. The auxiliary program is identical to the program under test, and the auxiliary instructions are identical to the instructions under test. The auxiliary module and the module under test run synchronously, and multiple preset times during the synchronous operation correspond to the multiple first data signals and the multiple second data signals, respectively. The comparison module is connected to the module under test and the auxiliary module respectively, and is used to acquire the first data signal and the second data signal at each preset time. When the first data signal and the second data signal are different, the comparison signal representing the occurrence of the target anomaly is output. The target anomaly includes at least one of the anomaly of the program under test and the anomaly of the instruction under test.
2. The debugging module according to claim 1, characterized in that, The microprocessor also includes: A data buffer processing module is connected to the module under test and the comparison module respectively, and is used to acquire and store multiple first data signals, as well as the correspondence between the multiple first data signals and the instruction under test and the program under test, and to send the corresponding first data signal to the comparison module according to each preset time.
3. The debugging module according to claim 2, characterized in that, The debugging module is independent of the microprocessor, and the debugging module further includes: The data buffer module is connected to the auxiliary module and the comparison module respectively, and is used to acquire and store multiple second data signals, and send the corresponding second data signal to the comparison module according to each preset time.
4. The debugging module according to claim 3, characterized in that, The debugging module also includes: The first debugging interface control unit is connected to the comparison module; The microprocessor also includes: The second debugging interface control unit is connected to the data buffer processing module and the first debugging interface control unit, respectively. The data buffer processing module receives a read instruction signal sent by the first debugging interface control unit, and sends the first data signal corresponding to each preset time to the comparison module according to the read instruction signal.
5. The debugging module according to claim 4, characterized in that, The data buffer processing module includes: A first state machine is connected to the module under test and is used to receive and, according to a first clock signal including each preset time, sequentially send a plurality of first data signals, the program under test corresponding to each first data signal, and the instruction under test; The first memory is connected to the module under test, the first state machine, and the second debug interface control unit, respectively. It is used to store the first data signal sent by the first state machine, as well as the program under test and the instruction under test corresponding to the first data signal, in the corresponding storage address according to the first clock signal and the corresponding preset time. Multiple first data signals and multiple storage addresses correspond to each other. The first data signal is sent sequentially according to the second clock signal in the read instruction signal. The parallel-to-serial conversion unit is connected to the first memory and the second debugging interface control unit respectively. It is used to receive and convert the first data signal of parallel data into the first data signal of serial data, and send the first data signal of serial data to the second debugging interface control unit in sequence according to the second clock signal. The comparison module is used to compare the first data signal of the parallel data corresponding to the first data signal of the serial data and the second data signal of the parallel data.
6. The debugging module according to claim 5, characterized in that, The comparison module includes: A serial-to-parallel conversion unit, connected to the first debugging interface control unit, is used to receive and convert the first data signal of serial data into the first data signal of parallel data, and to send the first data signal of parallel data sequentially according to the first clock signal. The first data comparison circuit is connected to the serial-to-parallel conversion unit and the data buffer module, respectively, and is used to receive and compare the second data signal at a preset time with the first data signal of the parallel data output by the serial-to-parallel conversion unit.
7. The debugging module according to claim 3, characterized in that, The data buffer module includes: The second state machine, connected to the auxiliary module, is used to receive and sequentially send multiple second data signals according to a first clock signal including multiple preset times. The second memory is connected to the auxiliary module, the second state machine, and the comparison module, respectively. It is used to store the second data signals of the parallel data sent by the second state machine in the corresponding storage addresses according to the first clock signal and at the corresponding preset time. The multiple second data signals and multiple storage addresses correspond to each other. It also sends the second data signals of the parallel data to the comparison module according to the first clock signal.
8. The debugging module according to claim 2, characterized in that, The debugging module is integrated inside the microprocessor, and the data buffer processing module and the comparison module are connected via a bus.
9. The debugging module according to claim 8, characterized in that, The data buffer processing module includes: The third state machine is connected to the module under test and is used to receive and, according to the first clock signal including each preset time, sequentially send a plurality of first data signals, the program under test corresponding to each first data signal and the instruction under test; The third memory is connected to the third state machine, the module under test, and the comparison module, respectively. It is used to store the first data signal sent by the third state machine, as well as the program under test and the instruction under test corresponding to the first data signal, in the corresponding storage address according to the first clock signal and the corresponding preset time. Multiple first data signals and multiple storage addresses correspond to each other. It also sends the first data signals of parallel data to the comparison module in sequence according to the first clock signal. The auxiliary module sequentially sends the second data signal of the parallel data to the comparison module according to the first clock signal.
10. The debugging module according to claim 9, characterized in that, The comparison module includes: The second data comparison circuit is connected to the third memory and the auxiliary module respectively, and is used to receive and compare the first data signal of the parallel data and the second data signal of the parallel data.
11. The debugging module according to any one of claims 1-10, characterized in that, The comparison module is further configured to output execution information corresponding to the first data signal when the first data signal and the second data signal are different. The execution information includes the instruction to be tested corresponding to the first data signal, the program to be tested corresponding to the first data signal, and the position information of the program to be tested running corresponding to the first data signal.
12. The debugging module according to any one of claims 1-10, characterized in that, The module under test further includes: a program under test storage module, which is connected to the core of the processor under test and stores the program under test inside; The auxiliary module includes: An auxiliary program storage module is connected to the processor core and stores the auxiliary program inside.
13. A debugging system, characterized in that, include: A debugging module and a microprocessor, wherein the debugging module is as described in any one of claims 1-12, and the microprocessor is as described in any one of claims 1-12; The host computer, connected to the debugging module, is used to acquire and display a comparison signal and the execution information corresponding to the first data signal when the first data signal and the second data signal are different. The execution information includes the instruction to be tested corresponding to the first data signal, the program to be tested corresponding to the first data signal, and the location information of the program to be tested running corresponding to the first data signal.
14. A debugging method, characterized in that, include: Acquire multiple first data signals generated by the processor core under test in the module under test according to the instructions under test executed by the program under test; The processor core in the auxiliary module acquires multiple second data signals generated by the auxiliary program running auxiliary instructions based on the auxiliary instructions; The auxiliary module and the module under test operate synchronously, and multiple preset times during the synchronous operation correspond to the multiple first data signals and multiple second data signals respectively; the auxiliary program and the program under test are the same, and the auxiliary instructions and the instructions under test are the same; When the first data signal and the second data signal are different at a preset time, a comparison signal representing the occurrence of a target anomaly is output; the target anomaly includes at least one of the program under test anomaly and the instruction under test anomaly.
15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the debugging method of claim 14.