Controller, memory module, and operating method of memory module

Abstract

A memory module includes: a memory device comprising a memory cell array including a fault block comprising a faulty cell and a remapped block for replacing the faulty block; and a controller communicating with a host device and controlling the memory device via a compute fast link (CXL) interface. The controller may include fault flags and recovery information of remapped addresses corresponding to the remapped blocks redundantly stored in the memory device; may read data corresponding to a target address from the memory device based on receiving a first request; may identify whether the target address is a faulty address based on the data corresponding to the target address; and when the target address is determined to be a faulty address, may generate a second request including the remapped address based on the data corresponding to the target address.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0199841, filed on December 30, 2024, and Korean Patent Application No. 10-2025-0053320, filed on April 23, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a controller, a memory module including the controller, and a method of operating the memory module, and more specifically, to a controller based on a Compute Fast Link (CXL) interface, a memory module including the controller, and a method of operating the memory module. Background Technology

[0004] Currently, applications based on machine learning or artificial intelligence that require large-scale data processing are growing and developing rapidly. Consequently, the demand for memory resources, which often serve as a bottleneck for the performance of such services (e.g., learning or inference), is increasing rapidly.

[0005] Interconnect technologies based on the Compute Fast Link (CXL) interface have emerged to provide efficient scalability and composability of memory resources. Summary of the Invention

[0006] Embodiments of this disclosure provide a CXL device capable of more effectively recovering from memory device failures, a memory module including the CXL device, and a method for operating the memory module.

[0007] According to some embodiments, a memory module may include: a memory device including a memory cell array, the memory cell array including a fault block including a faulty cell and a remapping block for replacing the faulty block; and a controller configured to communicate with a host device and control the memory device via a compute fast link (CXL) interface. The controller may redundantly store recovery information, including a fault flag and a remapping address corresponding to the remapping block, in the memory device based on a fault address corresponding to the faulty block; may read data corresponding to a target address from the memory device based on a first request including a target address received from the host device; may identify whether the target address is a faulty address based on the data corresponding to the target address; and when it is determined that the target address is a faulty address, may generate a second request including a remapping address based on the data corresponding to the target address.

[0008] Additionally, the memory module may further include non-volatile memory that stores a list of fault addresses and the starting addresses of remapping regions. The list of fault addresses includes multiple fault addresses corresponding to multiple fault blocks included in the memory cell array, and the remapping region is a region of the memory cell array that includes multiple remapping blocks. During initialization, the controller can map different remapping addresses to multiple fault addresses based on the starting addresses of the remapping regions, and can redundantly store relevant recovery information, including the relevant remapping address and fault flag, based on each of the multiple fault addresses.

[0009] Furthermore, the controller can store fault flags in each of the multiple first regions of the fault block and store remapping addresses in each of the multiple second regions of the fault block. It can apply a majority voting method to the data corresponding to the multiple first regions among the data corresponding to the target address. When the fault flag is obtained as a result of the majority voting method, the remapping address can be obtained by applying a majority voting method to the data corresponding to the multiple second regions among the data corresponding to the target address, and a second request including the obtained remapping address can be generated.

[0010] In addition, fault flags may include the hash value of the fault address or a preset constant value.

[0011] Furthermore, the controller can store fault flags in each of some regions of the Error Correction Code (ECC) block corresponding to the fault block, and store remapping addresses in each of multiple regions of the fault block. It can check whether the data corresponding to some regions of the ECC block in the data corresponding to the target address corresponds to the fault flag. When the data corresponding to some regions corresponds to the fault flag, the remapping address can be obtained by applying a majority voting method to the data corresponding to multiple regions of the fault block in the data corresponding to the target address, and a second request including the obtained remapping address can be generated.

[0012] In addition, some areas of an ECC block may correspond to bits in the bits stored in the ECC block that are not used for ECC functions.

[0013] Additionally, the first request may include a first read request, which includes a target address. When a fault flag is identified from the data corresponding to the target address, the controller may identify the target address as a fault address and generate a second read request including a remapped address. The controller may read the data corresponding to the remapped address from the memory device based on the second read request and provide the data corresponding to the remapped address to the host device.

[0014] In addition, when a fault flag is not identified from the data corresponding to the target address, the controller can provide the data corresponding to the target address to the host device.

[0015] In addition, the controller may include a Bloom filter that outputs a given value based on a list of fault addresses when the input address is included in multiple fault addresses.

[0016] Furthermore, the first request may include a first write request, which includes a target address, and the controller may input the target address into a Bloom filter in response to receiving the first write request. When a given value is output from the Bloom filter, data corresponding to the target address may be read from the memory device, and when a given value is not output from the Bloom filter, data may be written to the area of ​​the memory cell array corresponding to the target address based on the first write request.

[0017] Furthermore, when a fault flag is identified from the data corresponding to the target address, the controller can identify the target address as a fault address and generate a second write request including the remapped address, and can write the data to the area of ​​the storage cell array corresponding to the remapped address based on the second write request.

[0018] Additionally, when a fault flag is not identified from the data corresponding to the target address, the controller can write the data to the region of the memory cell array corresponding to the target address based on the first write request.

[0019] In addition, the memory cell array may include a first fault block and a first remapping block for replacing the first fault block, and the controller may include a cache memory that stores mapping information in which a first fault address corresponding to the first fault block and a first remapping address corresponding to the first remapping block are mapped.

[0020] Furthermore, when a first request including a target address is received, the controller can identify whether the target address corresponds to a first fault address based on the mapping information stored in the cache memory. When the identification result based on the mapping information indicates that the target address corresponds to the first fault address, the controller can use the mapping information stored in the cache memory to generate a third request including a first remapped address.

[0021] According to some embodiments of this disclosure, a Fast Compute Link (CXL) device may include: a host interface that communicates with a host device using the CXL protocol; and a memory controller that controls the memory device and processes requests received from the host device through the host interface. The memory controller may include a repair engine for replacing faulty blocks in the memory device with remapped blocks. The repair engine may redundantly store recovery information, including a fault flag and a remapped address corresponding to the remapped block, in the memory device based on a fault address corresponding to the faulty block. It may also read data corresponding to a target address from the memory device based on a first request received from the host device, including a target address; identify whether the target address is a faulty address based on the data corresponding to the target address; and generate a second request including a remapped address based on the data corresponding to the target address when the target address is determined to be a faulty address.

[0022] Additionally, the CXL device may further include non-volatile memory storing a list of fault addresses and the starting addresses of remapping regions. The list of fault addresses includes multiple fault addresses corresponding to multiple fault blocks included in the memory device, and the remapping regions are regions of the memory device including multiple remapping blocks. During initialization, the repair engine can map different remapping addresses to multiple fault addresses based on the starting addresses of the remapping regions, and can redundantly store relevant recovery information, including the relevant remapping address and fault flags, in the memory device based on each of the multiple fault addresses.

[0023] Furthermore, the repair engine can store fault flags in each of the multiple first regions of the fault block and remap addresses in each of the multiple second regions of the fault block. It can apply a majority voting method to the data corresponding to the multiple first regions in the data corresponding to the target address. When the fault flag is obtained as a result of the majority voting method, the remap address can be obtained by applying a majority voting method to the data corresponding to the multiple second regions in the data corresponding to the target address, and a second request including the obtained remap address can be generated.

[0024] Furthermore, the repair engine can store fault flags in each of some regions of the Error Correction Code (ECC) block corresponding to the fault block, store remapping addresses in each of multiple regions of the fault block, check whether the data corresponding to some regions of the ECC block in the data corresponding to the target address corresponds to the fault flag, and when the data corresponding to some regions corresponds to the fault flag, obtain the remapping address by applying a majority voting method to the data corresponding to multiple regions of the fault block in the data corresponding to the target address, and generate a second request including the obtained remapping address.

[0025] According to some embodiments of this disclosure, a memory module may include: a memory device including a first fault block, a second fault block, a first remapping block corresponding to the first fault block, and a second remapping block corresponding to the second fault block; and a controller including a cache memory, communicating with a host device via a compute fast link (CXL) interface, and controlling the memory device. The controller may store mapping information in the cache memory, in which a first fault address corresponding to the first fault block and a first remapping address corresponding to the first remapping block are mapped. The controller may redundantly store recovery information, including a fault flag and a second remapping address corresponding to the second remapping block, in the memory device based on the second fault address corresponding to the second fault block. Furthermore, upon receiving a first request including the first fault address from the host device, the controller may generate a second request including the first remapping address based on the mapping information stored in the cache memory.

[0026] In addition, when the controller receives a third request including the second fault address from the host device, it can read the data corresponding to the second fault address from the memory device, obtain the second remapping address from the data corresponding to the second fault address through majority voting, and generate a fourth request including the obtained second remapping address. Attached Figure Description

[0027] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a block diagram of a memory module according to some embodiments of the present disclosure.

[0029] Figure 2 This is a diagram illustrating an example configuration of a memory cell array according to some embodiments of the present disclosure.

[0030] Figure 3 This is a block diagram illustrating the configuration of a memory module according to some embodiments of the present disclosure.

[0031] Figure 4 This is a diagram used to describe a method for storing and restoring information according to some embodiments of the present disclosure.

[0032] Figure 5 This is a diagram used to describe a method for obtaining a remapped address according to some embodiments of the present disclosure.

[0033] Figure 6 This is a diagram used to describe a method for storing and restoring information according to some embodiments of the present disclosure.

[0034] Figure 7 This is a diagram used to describe a method for obtaining a remapped address according to some embodiments of the present disclosure.

[0035] Figure 8 This is a flowchart illustrating the operation method of a memory module according to some embodiments of the present disclosure.

[0036] Figure 9 This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure.

[0037] Figure 10 This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure.

[0038] Figure 11 This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure.

[0039] Figure 12 This is a flowchart illustrating the operation method of a repair engine according to some embodiments of the present disclosure.

[0040] Figure 13 This is a diagram illustrating the order in which requests for different addresses are processed according to some embodiments of this disclosure.

[0041] Figure 14 This is a diagram illustrating the order in which requests for the same address are processed according to some embodiments of this disclosure. Detailed Implementation

[0042] Figure 1 This is a block diagram of a memory module according to some embodiments of the present disclosure.

[0043] According to some embodiments of this disclosure, the memory module 10 can automatically recover from hardware faults in the memory device 200 by remapping fault addresses corresponding to faulty blocks to remapped addresses corresponding to normal blocks. In this case, the faulty block and the normal block can be memory blocks included in the memory device 200 and can have a cache line size (e.g., 64 bytes). However, this disclosure is not limited thereto.

[0044] Therefore, according to some embodiments of this disclosure, the memory module 10 may redundantly store recovery information for remapping fault addresses to remapped addresses in the memory device 200 based on fault addresses. In this case, the recovery information may include a fault flag for identifying whether an input address is a fault address and a remapped address.

[0045] According to the above description, when a request including a fault address is received, the memory module 10 according to some embodiments of the present disclosure can read multiple recovery information from the memory device 200 based on the fault address, and can use the multiple recovery information to remap the fault address to a remapped address in real time.

[0046] Because a fault address corresponds to a fault block, the data stored in the fault block may contain errors. However, the memory module 10 according to some embodiments of this disclosure can redundantly store recovery information and obtain a remapped address from multiple recovery information sources through majority voting. Therefore, the reliability of the obtained remapped address can be improved.

[0047] Furthermore, since the memory module 10 according to some embodiments of this disclosure uses fault blocks to store recovery information, it is not necessary to allocate separate space in the memory device 200 to store remapped addresses.

[0048] Furthermore, because fault flags can be stored in a fault block or an error correction code (ECC) block associated with the fault block based on fault addresses, the number of accesses to memory device 200 for remapping operations can be reduced compared to the case where remapping addresses are stored in a separate space of memory device 200 instead of in the fault block. Based on the above description, the time required for remapping operations can be reduced.

[0049] Furthermore, faults in the memory device 200 can be recovered on a block-by-block basis, and hardware faults in the memory device 200 can be recovered flexibly without being limited by the number of fault blocks or the address space.

[0050] Therefore, according to some embodiments of this disclosure, the coverage of hardware faults that can be recovered in the memory device 200 can be significantly improved, and the memory module 10 can be configured using a memory device 200 with low quality.

[0051] refer to Figure 1 Please provide a detailed explanation. (Reference) Figure 1 The memory module 10 may include a controller 100 and a memory device 200. Figure 1 In this illustration, for convenience, memory module 10 is shown as including a memory device 200. However, this disclosure is not limited thereto. Memory module 10 may include multiple memory devices. In this case, each of the multiple memory devices included in memory module 10 can be connected to... Figure 1 This corresponds to the memory device 200 shown.

[0052] According to some implementations, memory module 10 may be a CXL (Compute Fast Link) type 3 DRAM device. For example, memory module 10 may be connected to the central processing unit (CPU), graphics processing unit (GPU), AI accelerator, memory device, etc. of a host device via a PCIe (Peripheral Component Interconnect Fast) interface.

[0053] Controller 100 can control memory device 200. For example, controller 100 can control memory device 200 based on requests from processors that support various applications such as server applications, personal computer (PC) applications, and mobile applications.

[0054] The controller 100 can communicate with a host device, including a processor, via a CXL interface and can control the memory device 200 according to the processor's requests. For this purpose, the controller 100 can support the CXL.io and CXL.mem protocols.

[0055] To control the memory device 200, the controller 100 may send commands and / or addresses to the memory device 200. In this case, the commands and / or addresses may correspond to requests received from the host device or requests generated by the controller 100. Furthermore, the controller 100 may send data to the memory device 200, or may receive data from the memory device 200. In this case, the data may be codewords (CWs).

[0056] The memory device 200 can receive and store codewords from the controller 100 in response to a write request from the controller 100. Furthermore, the memory device 200 can read the stored codewords in response to a read request from the controller 100, and can send the read codewords to the controller 100.

[0057] For example, memory device 200 can be configured to receive commands and / or addresses from controller 100, access a region of memory cell array 210 selected by the address, and execute operations indicated by the command for the selected region. In this case, the operation indicated by the command can be a write operation, a read operation, or a delete operation.

[0058] According to some implementations, memory device 200 may include volatile memory cells. For example, memory device 200 may include various DRAM devices, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, Low Power Double Data Rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, Graphics Double Data Rate Synchronous Graphics Random Access Memory (GDDR SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, and GDDR6 SGRAM.

[0059] In addition, according to some implementations, the memory device 200 may be a stacked memory device in which DRAM dies are stacked, such as high bandwidth memory (HBM), HBM2 or HBM3.

[0060] In addition, according to some implementations, the memory device 200 may include an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, an FRAM device, a PRAM device, a TRAM device, an MRAM device, etc.

[0061] Memory device 200 may include memory cell array 210. Memory cell array 210 may include a plurality of memory banks, memory banks 1 to n, each memory bank including memory cells for storing data. For ease of description, it is assumed in this specification that each memory bank includes DRAM cells. However, this is provided as an example, and each of the plurality of memory banks (memory banks 1 to n) may be implemented to include any other volatile memory cells besides DRAM cells. Furthermore, the plurality of memory banks (memory banks 1 to n) may be implemented to include memory cells of the same kind, or may be implemented to include memory cells of different kinds.

[0062] The memory cell array 210 may include multiple memory blocks. These memory blocks may include at least one faulty block and multiple normal blocks. A faulty block may be a memory block containing at least one faulty cell. In this case, the faulty cell may occur during the manufacturing process of the memory device 200 or due to the aging of the memory device 200 over time. A normal block may be a memory block that does not contain faulty cells. Each memory block may have the size of a cache line.

[0063] The memory cell array 210 can be divided into a normal region and a remapping region. The normal region may include at least one faulty block and a normal block. The remapping region may include remapping blocks. Remapping blocks may be normal blocks used to replace faulty blocks.

[0064] According to some embodiments of this disclosure, a faulty block can be replaced with a remapped block. For this purpose, the controller 100 may include a repair engine 110 and a non-volatile memory 120 for remapping faulty addresses to remapped addresses. Herein, a faulty address can be an address used to access a faulty block, and a remapped address can be an address used to access a remapped block.

[0065] The non-volatile memory 120 can store initial information for generating recovery information. The initial information may include a fault address list and the starting addresses of remapping regions. The fault address list includes multiple fault addresses corresponding to multiple fault blocks included in the memory cell array 210, and the remapping regions are regions of the memory cell array 210 that include multiple remapping blocks. In this case, the fault address list can be obtained during or after the manufacturing process of the memory module 10 through a test operation in which a given bit pattern is stored in and read from the memory device 200, and can be stored in the non-volatile memory 120. However, this disclosure is not limited thereto.

[0066] The repair engine 110 can redundantly store recovery information for recovering faulty blocks in the memory device 200 based on the fault address. The recovery information may include fault flags and remapping addresses corresponding to the remapping blocks.

[0067] For example, during the initialization operation of memory module 10 or controller 100, repair engine 110 can load initial information stored in non-volatile memory 120 and redundantly store recovery information in memory device 200 based on the loaded initial information.

[0068] Specifically, during the initialization operation, the repair engine 110 can map or assign multiple fault addresses included in the fault address list to different remapping addresses based on the starting address of the remapping region, and can generate recovery information corresponding to each fault address. In this case, each recovery information can include a remapping address mapped to the corresponding fault address and a fault flag. Based on the above description, the repair engine 110 can redundantly store the recovery information corresponding to each fault address in the memory device 200 based on the corresponding fault address.

[0069] According to some embodiments, based on the fault address, the repair engine 110 can store a fault flag in each of a plurality of first regions of the fault block, and can store a remapping address in each of a plurality of second regions of the fault block. According to some embodiments, based on the fault address, the repair engine 110 can store a fault flag in each of a plurality of regions of the ECC block corresponding to the fault block, and can store a remapping address in each of a plurality of regions of the fault block. In this case, the ECC block can be a region of the memory device 200 that stores parity data corresponding to the data stored in the fault block. Furthermore, some regions of the ECC block that store fault flags can be regions of the ECC block that do not store parity data. Based on the above description, recovery information can be redundantly stored in the memory device 200 based on the fault address.

[0070] Subsequently, when a request including a faulty address is received from the host device, the repair engine 110 can remap the faulty address to a remapped address, allowing the received request to be processed in the remapped block. Based on the above description, the faulty block can be replaced with a remapped block.

[0071] Specifically, based on receiving a first request including a target address from the host device, the repair engine 110 can read data corresponding to the target address from the memory device 200. In this case, the data corresponding to the target address may include data stored in the target block corresponding to the target address, and data stored in the error correction code (ECC) block corresponding to the target block. The ECC data of the data stored in the target block can be stored in the ECC block corresponding to the target block. Therefore, the data corresponding to the target address can be codeword data corresponding to the target address.

[0072] The repair engine 110 can identify whether a target address is a faulty address based on data corresponding to the target address. When the target address is identified as a faulty address, the repair engine 110 can generate a second request, including a remapped address, based on the data corresponding to the target address.

[0073] According to some implementations, as described above, fault flags can be redundantly stored in multiple first regions of the fault block, and remapping addresses can be redundantly stored in multiple second regions of the fault block. In this case, the repair engine 110 can apply a majority voting method to the data corresponding to the multiple first regions among the data corresponding to the target address. When the fault flag is obtained by applying the majority voting method, the repair engine 110 can obtain the remapping address by applying the majority voting method to the data corresponding to the multiple second regions among the data corresponding to the target address, and can generate a second request including the obtained remapping address.

[0074] According to some implementations, as described above, fault flags can be redundantly stored in some regions of the ECC block corresponding to the faulty block, and remapping addresses can be redundantly stored in multiple regions of the faulty block. In this case, the repair engine 110 can check whether the data corresponding to some regions of the ECC block among the data corresponding to the target address corresponds to the fault flag. When the check result indicates that the data corresponds to the fault flag, the repair engine 110 can obtain the remapping address by applying a majority voting method to the data corresponding to multiple regions of the faulty block among the data corresponding to the target address, and can generate a second request including the obtained remapping address.

[0075] The controller 100 can send commands and remapped addresses to the memory device 200, so that the second request can be processed in the remapped block.

[0076] As described above, when a request including a fault address is received from the host device, the repair engine 110 can replace the fault block with a remapped block by remapping the fault address to a remapped address.

[0077] Therefore, a CXL device capable of more effectively recovering from memory device failures, a memory module including the CXL device, and a method for operating the memory module can be provided.

[0078] Figure 2 This is a diagram illustrating an example configuration of a memory cell array according to some embodiments of the present disclosure. Figure 2 The memory cell array 210 can be with Figure 1 The memory cell array 210 of the memory device 200 corresponds to the memory device 200.

[0079] refer to Figure 2 The memory cell array 210 may include multiple memory blocks. Each of the multiple memory blocks may have a cache line size (e.g., 64 bytes). Assuming the host device and memory module 10 constitute a system using 64-bit addresses, eight addresses can be redundantly stored in one memory block.

[0080] The memory cell array 210 can be divided into a normal region and a remapping region. The remapping region may include remapping blocks for replacing faulty blocks. The normal region may include at least one faulty block containing the faulty cell "X" and normal blocks. Figure 2 In the example, the three fault blocks FB_1, FB_2 and FB_3 can be included in the normal area.

[0081] In this case, a list of fault addresses, including the first fault address corresponding to the first fault block FB_1, the second fault address corresponding to the second fault block FB_2, and the third fault address corresponding to the third fault block FB_3, and the starting address of the remapping region can be stored in the non-volatile memory 120.

[0082] During the initialization operation, based on the starting address of the remapping region, the repair engine 110 can map the first fault address to the first remapping address corresponding to the first remapping block RB_1, the second fault address to the second remapping address corresponding to the second remapping block RB_2, and the third fault address to the third remapping address corresponding to the third remapping block RB_3.

[0083] During initialization, the repair engine 110 can generate first recovery information including a fault flag and a first remapping address, and can redundantly store the first recovery information in the memory device 200 based on the first fault address. Furthermore, the repair engine 110 can generate second recovery information including a fault flag and a second remapping address, and can redundantly store the second recovery information in the memory device 200 based on the second fault address. Additionally, the repair engine 110 can generate third recovery information including a fault flag and a third remapping address, and can redundantly store the third recovery information in the memory device 200 based on the third fault address.

[0084] In this scenario, for example, the first mapping address can be stored in each of two or more of the eight regions of the first fault block FB_1, the second mapping address can be stored in each of two or more of the eight regions of the second fault block FB_2, and the third mapping address can be stored in each of two or more of the eight regions of the third fault block FB_3.

[0085] According to some implementations, fault flags and remapping addresses can be redundantly stored in all fault blocks. In this case, in an example implementation, fault flags can be stored in each odd-numbered region of the eight regions of the first fault block FB_1, and the first remapping address can be stored in each even-numbered region of the first fault block FB_1. Furthermore, fault flags can be stored in each odd-numbered region of the eight regions of the second fault block FB_2, and the second remapping address can be stored in each even-numbered region of the second fault block FB_2. Additionally, fault flags can be stored in each odd-numbered region of the eight regions of the third fault block FB_3, and the third remapping address can be stored in each even-numbered region of the third fault block FB_3. However, the implementation is not limited to this.

[0086] Meanwhile, although not shown in the accompanying drawings, the memory cell array 210 may include ECC blocks storing parity data corresponding to the data stored in the memory blocks. The size of the ECC block (e.g., 8 bytes or 16 bytes) may be smaller than the size of the memory blocks. In this case, according to some embodiments, the remapped address of the recovery information may be stored in the fault block, and the unused bits of the ECC may be used to store the fault flag of the recovery information. In some embodiments, the first remapped address may be stored in each of the eight regions of the first fault block FB_1, and the fault flag may be stored in some regions of the ECC block corresponding to the first fault block FB_1. Furthermore, the second remapped address may be stored in each of the eight regions of the second fault block FB_2, and the fault flag may be stored in some regions of the ECC block corresponding to the second fault block FB_2. Additionally, the third remapped address may be stored in each of the eight regions of the third fault block FB_3, and the fault flag may be stored in some regions of the ECC block corresponding to the third fault block FB_3. However, the embodiments are not limited to these.

[0087] As described above, during the initialization operation, recovery information for recovering the fault block can be redundantly stored in the memory device 200 using the fault block.

[0088] Subsequently, upon receiving a request including a fault address from the host device, controller 100 can read multiple recovery information based on the fault address. Furthermore, controller 100 can use the multiple recovery information to identify the fault address and obtain a remapped address. Based on the above description, controller 100 can remap a fault address to a remapped address by generating and processing a request including a remapped address.

[0089] Figure 3 This is a block diagram illustrating the configuration of a memory module according to some embodiments of the present disclosure. Reference Figure 3 The memory module 10 may include a controller 100 and a memory device 200. Figure 3 The memory module 10 can be with Figure 1 The memory module 10 corresponds to this.

[0090] In some implementations, the controller 100 may be implemented together with the memory device 200 in the same package. In other implementations, the controller 100 and the memory device 200 may be implemented using different packages and then interconnected.

[0091] The controller 100 can communicate with the host device based on the CXL protocol. Therefore, the controller 100, implemented using a separate package independent of the memory device 200, can be referred to as a CXL device, but this disclosure is not limited thereto.

[0092] refer to Figure 3 The controller 100 may include a repair engine 110, a non-volatile memory 120, a host interface 130, and a memory interface 140.

[0093] The host interface 130 may include a PCIe interface 131 and a CXL controller 132.

[0094] PCIe interface 131 may include a PCIe physical layer. Controller 100 can communicate with the host device or any other CXL device through PCIe interface 131 on a PCIe bus conforming to the CXL protocol. In this case, the CXL protocol may include the CXL.io protocol.

[0095] CXL controller 132 can provide repair engine 110 with requests received from the host device or any other CXL device via PCIe interface 131. Furthermore, CXL controller 132 can transmit responses from repair engine 110 to PCIe interface 131. For this purpose, CXL controller 132 can provide the CXL.mem protocol.

[0096] Memory interface 140 can communicate with memory device 200. For example, memory interface 140 can communicate with memory device 200 via a double data rate (DDR) interface. Memory interface 140 may include memory device controller 141 and ECC circuitry 142.

[0097] The memory device controller 141 can provide the memory device 200 with commands, addresses, and data corresponding to a request received from the repair engine 110, so that an operation corresponding to the request can be performed in the memory device 200, or the data returned from the memory device 200 can be transmitted to the repair engine 110.

[0098] ECC circuit 142 can generate parity information by performing ECC encoding on data received from repair engine 110 or CXL controller 132, and can generate codewords by adding the generated parity information to the data. Furthermore, ECC circuit 142 can perform ECC decoding on codewords received from memory device 200, and can correct errors in the data included in the codewords. According to some embodiments, ECC circuit 142 can insert fault flags into the codewords using bits not used for ECC function (i.e., ECC unused bits) from the bits stored in the ECC block of memory device 200.

[0099] The non-volatile memory 120 can store a list of fault addresses including multiple fault addresses and the starting address of the remapping region. According to some embodiments, the non-volatile memory 120 can be implemented using EEPROM or flash memory. Furthermore, the non-volatile memory 120 can be a serial presence detection (SPD) device containing various information about the memory module 10, but this disclosure is not limited thereto. When the non-volatile memory 120 is implemented using an SPD device, the SPD device can be implemented using a chip independent of the controller 100.

[0100] Repair engine 110 can process requests received from the host device via host interface 130 to transmit them to memory interface 140, and can also transmit responses received from memory device 200 via memory interface 140 to host interface 130. Specifically, when a request including a fault address is received from the host device, repair engine 110 can replace the fault block with a remapped block by remapping the fault address to a remapped address.

[0101] For this purpose, the repair engine 110 may include a request handler 111, an address remapper 112, and a response buffer 113.

[0102] The request handler 111 can control the processing order of requests received from the host device and requests generated by the request handler 111. To this end, the request handler 111 may include a request buffer 111a, a Bloom filter 111b, and a cache memory 111c.

[0103] Requests queued in request buffer 111a can be sequentially transmitted to memory interface 140 for sequential processing. Request buffer 111a can be a first-in, first-out (FIFO) buffer. Therefore, request handler 111 can control the processing order of requests by queuing them into request handler 111 according to the order of the required operations.

[0104] For example, in order to redundantly store recovery information generated based on initial information stored in non-volatile memory 120 in memory device 200 based on the corresponding fault address, request handler 111 can generate a write request for each fault address and queue the generated write requests into request buffer 111a. Furthermore, request handler 111 can queue requests received from the host device via host interface 130 into request buffer 111a. Additionally, request handler 111 can queue requests including remapped addresses provided by address remapper 112 into request buffer 111a. Furthermore, request handler 111 can generate requests including remapped addresses provided by cache memory 111c and queue the generated requests into request buffer 111a. Furthermore, request handler 111 can generate read requests including addresses filtered by Bloom filter 111b and queue the generated read requests into request buffer 111a.

[0105] Bloom filter 111b can be configured to output a given value when the input address is included in multiple fault addresses in a fault address list. Bloom filter 111b can be implemented, for example, using SRAM, and the setting operation of Bloom filter 111b can be performed during the initialization operation of memory module 10 or controller 100.

[0106] Meanwhile, when a write request including a target address is received through the host interface 130, the request handler 111 can input the received write request into the Bloom filter 111b. When a given value is output from the Bloom filter 111b, the request handler 111 can generate a read request including the target address and can queue the read request into the request buffer 111a.

[0107] The cache memory 111c can store mapping information where fault addresses and remapped addresses match. The cache memory 111c can be implemented using SRAM, but this disclosure is not limited thereto.

[0108] According to some implementations, during initialization, repair engine 110 can generate mapping information based on initial information stored in non-volatile memory 120, and can store the generated mapping information in cache memory 111c. For example, repair engine 110 can generate mapping information for each of at least some fault addresses by assigning remapped addresses to each of at least some fault addresses included in a fault address list, and can store the generated mapping information in cache 111c.

[0109] In this scenario, the repair engine 110 can select a predetermined number of fault addresses from a plurality of fault addresses included in the fault address list, and can generate mapping information corresponding to each selected fault address. In some embodiments, the repair engine 110 can select fault addresses from a plurality of fault addresses included in the fault address list that correspond to a fault block containing a relatively large number of fault units, and can generate mapping information corresponding to each selected fault address. For this purpose, the initial information stored in the non-volatile memory 120 may also include fault type information about each of the plurality of fault addresses included in the fault address list. The fault type information can indicate the degree of fault in the fault block corresponding to the relevant fault address. Based on the above description, the repair engine 110 can select fault addresses for generating mapping information based on the fault type information.

[0110] Meanwhile, according to some implementations, when the address remapping unit 112 identifies the target address as a fault address after the initialization operation, the address remapping unit 112 can generate mapping information by mapping the target address identified as a fault address to the remapping address, and can store the generated mapping information in the cache memory 111c.

[0111] When the received address corresponds to the mapping information stored in the cache memory 111c, the request handler 111 can use the mapping information to generate a request including the remapped address without additional operations, and can queue the generated request into the request buffer 111a.

[0112] When data corresponding to a target address is read from memory device 200, address remapping unit 112 can identify whether the target address is a fault address based on the data corresponding to the target address. For example, when a fault flag is identified from the data corresponding to the target address, address remapping unit 112 can identify the target address as a fault address.

[0113] Furthermore, when the target address is identified as a faulty address, the address remapping unit 112 can obtain a remapped address from the data corresponding to the target address and can generate a request including the remapped address. For example, the address remapping unit 112 can obtain the remapped address by applying a majority vote to the data corresponding to the target address. Based on the above description, the address remapping unit 112 can generate a request including the obtained remapped address for transmission to the request handler 111. The request transmitted to the request handler 111 can be queued in the request buffer 111a.

[0114] Furthermore, when the target address is identified as a faulty address, as described above, the address remapping unit 112 can generate mapping information by mapping the target address identified as a faulty address to the obtained remapped address, and can store the generated mapping information in the cache memory 111c.

[0115] Meanwhile, when a fault flag is not identified from the data corresponding to the target address, in some cases, the address remapping unit 112 may send the data corresponding to the target address to the response buffer 113, or may send the identification result indicating that the target address is not a fault address to the request handler 111.

[0116] The response buffer 113 can queue data transmitted from the address remapper 112 and can asynchronously return the data to the host device via the host interface 130. In this case, the reason why the data queued in the response buffer 113 is asynchronously transmitted to the host device is that the CXL interface has variable access latency and out-of-order characteristics, which will be described in detail later.

[0117] Below, we will describe example operations of the repair engine 110 depending on the operating scenario.

[0118] According to some embodiments of this disclosure, during initialization, the repair engine 110 can generate recovery information based on initial information stored in the non-volatile memory 120, and can redundantly store the generated recovery information in the memory device 200 based on the fault address. To this end, the request handler 111 can generate a write request including the fault address, and can queue the generated write request into the request buffer 111a.

[0119] Furthermore, according to some implementations, during initialization, the repair engine 110 may set the Bloom filter 111b based on a list of fault addresses stored in the non-volatile memory 120, such that a given value (e.g., "1") is output when the input address is included in multiple fault addresses.

[0120] Furthermore, according to some implementations, during the initialization operation, the repair engine 110 can generate mapping information based on the initial information stored in the non-volatile memory 120, in which fault addresses and remapping addresses are mapped, and the generated mapping information can be stored in the cache memory 111c.

[0121] Meanwhile, according to some implementations, after the initialization operation is completed, the repair engine 110 can receive a first read request including the target address from the host device. In this case, the request handler 111 can first check whether mapping information including the remapped address mapped to the target address exists in the cache memory 111c.

[0122] When the mapping information corresponding to the target address exists in the cache memory 111c, the request handler 111 can generate a second read request including the remapped address based on the mapping information, and can queue the generated second read request into the request buffer 111a.

[0123] When data corresponding to a remapped address is received from memory device 200 in response to a second read request, address remapper 112 can determine whether the remapped address is a fault address based on the data corresponding to the remapped address. Since there is no fault flag in the data corresponding to the remapped address, address remapper 112 can transfer the data corresponding to the remapped address to response buffer 113.

[0124] Meanwhile, when there is no mapping information corresponding to the target address in the cache memory 111c, the request handler 111 can queue the first read request to the request buffer 111a.

[0125] When the address remapper 112 receives data corresponding to the target address from the memory device 200 in response to the first read request, it can determine whether the target address is a fault address based on the data corresponding to the target address.

[0126] Since the fault flag was not identified from the data corresponding to the target address, the address remapping unit 112 can transfer the data corresponding to the target address to the response buffer 113.

[0127] However, when a fault flag is identified from the data corresponding to the target address, the address remapping unit 112 can identify the target address as a fault address and obtain the remapped address from the data corresponding to the target address. In this case, the address remapping unit 112 can generate a second read request including the remapped address and can send the generated second read request to the request handler 111.

[0128] When a second read request is received, the request handler 111 can check whether there is mapping information in the cache memory 111c that includes a remapped address mapped to the remapped address included in the second read request. Because the remapped address is a normal address, the mapping information including the remapped address mapped to the remapped address may not exist. Therefore, the request handler 111 can queue the second read request into the request buffer 111a.

[0129] When data corresponding to a remapped address is received from memory device 200 in response to a second read request, address remapper 112 can determine whether the remapped address is a fault address based on the data corresponding to the remapped address. Since there is no fault flag in the data corresponding to the remapped address, address remapper 112 can transfer the data corresponding to the remapped address to response buffer 113.

[0130] According to some implementations, when a target address is identified as a faulty address, the address remapping unit 112 can generate mapping information by mapping the target address to a remapped address, and can store the generated mapping information in the cache memory 111c. After storing the mapping information in the cache memory 111c in which the target address identified as a faulty address is mapped to the remapped address, when a third request including the same target address is received, the request handler 111 can immediately generate a fourth request including the remapped address using the mapping information stored in the cache memory 111c, and can queue the generated fourth request into the request buffer 111a. In this case, the third request and the fourth request can be either read requests or write requests.

[0131] Meanwhile, according to some implementations, after the initialization operation is completed, the repair engine 110 may receive a first write request including the target address from the host device. In this case, the request handler 111 may first check whether mapping information including the remapped address mapped to the target address exists in the cache memory 111c.

[0132] When the mapping information corresponding to the target address exists in the cache memory 111c, the request handler 111 can generate a second write request including the remapped address based on the mapping information, and can queue the generated second write request into the request buffer 111a. In this case, the operation corresponding to the write request can be performed based on the remapped address.

[0133] Meanwhile, when there is no mapping information corresponding to the target address in the cache memory 111c, the request handler 111 can input the target address into the Bloom filter 111b.

[0134] When no given value is output from Bloom filter 111b, request handler 111 can queue the first write request into request buffer 111a. In this case, the operation corresponding to the write request can be performed based on the target address.

[0135] When a given value is output from Bloom filter 111b, request handler 111 can generate a read request including the target address and queue the generated read request into request buffer 111a. When data corresponding to the target address is received from memory device 200, address remainder 112 can identify whether the target address is a fault address based on the data corresponding to the target address.

[0136] When a fault flag is not identified from the data corresponding to the target address, the address remapping unit 112 can send an identification result indicating that the target address is not a fault address to the request handler 111, and can queue the first write request in the request buffer 111a. In this case, the operation corresponding to the write request can be performed based on the target address.

[0137] However, when a fault flag is identified from the data corresponding to the target address, the address remapping unit 112 can identify the target address as a fault address and obtain a remapped address corresponding to the target address. In this case, the address remapping unit 112 can generate a second write request including the remapped address and can send the generated second write request to the request handler 111.

[0138] When a second write request is received, the request handler 111 can check whether there is mapping information in the cache memory 111c that includes a remapped address mapped to the remapped address included in the second write request. Since the remapped address is a normal address, the remapped address mapped to the remapped address may not exist. Therefore, the request handler 111 can input the second write request to the Bloom filter 111b. Since the remapped address is not a fault address, the Bloom filter 111b may not output a given value, and the request handler 111 can queue the second write request into the request buffer 111a. In this case, the operation corresponding to the write request can be performed based on the remapped address.

[0139] Due to the characteristics of the Bloom filter 111b, there may be a probability that a positive error could occur at the output, but there may not be a probability that a negative error could occur at the output. Therefore, according to the above-described embodiment of this disclosure, the writing of data into the fault block can be prevented.

[0140] According to some implementations, when a target address is identified as a faulty address, the address remapping unit 112 can store mapping information in the cache memory 111c where the target address is mapped to a remapped address. Then, when a third request including the same target address is received, the request handler 111 can use the mapping information stored in the cache memory 111c to immediately generate a fourth request including the remapped address, and can queue the generated fourth request into the request buffer 111a. In this case, the third and fourth requests can be read requests or write requests.

[0141] Figure 4 This is a diagram used to describe a method for storing and restoring information according to some embodiments of the present disclosure.

[0142] During initialization (or startup), the repair engine 110 can generate recovery information, including fault flags and remapped addresses, based on initial information stored in the non-volatile memory 120. (See reference...) Figure 4 The repair engine 110 can generate recovery information including a fault flag “10101100…1010” associated with a fault address and a remapped address “11110010…0000”.

[0143] In this scenario, according to some implementations, the fault flag may include a hash value of the fault address. Because the hash value varies depending on the fault address, the value of the fault flag can be determined differently for each recovery message. According to some implementations, the fault flag may include a preset constant value (or a preset bit pattern). In this case, the fault flag for all recovery messages may have the same value.

[0144] Simultaneously, the repair engine 110 can redundantly store the generated recovery information in the memory device 200 based on the fault address. According to some embodiments, the repair engine 110 can store both the fault flag and the remapping address in the fault block. For example, the repair engine 110 can store the fault flag in each of a plurality of first regions of the fault block, and can store the remapping address in each of a plurality of second regions of the fault block. (See reference...) Figure 4 The fault flag can be stored in each of the four odd-numbered regions out of the eight regions of the fault block, and the remapped address can be stored in each of the four even-numbered regions of the fault block. However, the implementation is not limited to this.

[0145] Figure 5 This is a diagram illustrating a method for obtaining a remapped address according to some embodiments of this disclosure. Figure 5 In the middle, assuming that it stores Figure 4 Recovery information.

[0146] According to some implementations, when reading data corresponding to a target address, the address remapping unit 112 can apply a majority voting method to the data corresponding to the target address and corresponding to multiple first regions of the faulty block. In this case, the multiple first regions can be regions storing fault flags among multiple regions of the faulty block.

[0147] refer to Figure 5 The address remapping unit 112 can obtain the fault flag "10101100...1010" by applying a majority vote method to the data corresponding to multiple first regions in bits.

[0148] When a fault flag is obtained, the address remapping unit 112 can obtain a remapped address by applying a majority vote to the data corresponding to multiple second regions of the faulty block within the data corresponding to the target address. In this case, the multiple second regions can be regions storing the remapped address among multiple regions of the faulty block.

[0149] refer to Figure 5 The address remapping unit 112 can obtain the remapped address "11110010...0000" by applying a majority voting method on a bit-by-bit basis to the data corresponding to multiple second regions. In this case, the address remapping unit 112 can generate a second request including the obtained remapped address and can provide the generated second request to the request handler 111.

[0150] Because a fault block comprises fault cells (or more), it can include errors in which bit values ​​are flipped. This will be stored in... Figure 4 The data in the fault block and Figure 5 By comparing the read data, it can be understood that some bits of the read data are flipped.

[0151] However, according to the embodiments of this disclosure, reliability can be improved because the fault flag and remapping address are redundantly stored in each of the multiple regions of the fault block, and recovery information is identified by applying a majority voting method.

[0152] The above example illustrates how a fault flag or remapped address can be obtained by applying majority voting on a bit-by-bit basis, but the implementation is not limited to this. For instance, a fault flag or remapped address can be obtained by applying majority voting on a bit-by-bit basis.

[0153] Figure 6 This is a diagram used to describe a method for storing and restoring information according to some embodiments of the present disclosure.

[0154] During initialization (or startup), the repair engine 110 can generate recovery information, including fault flags and remapped addresses, based on initial information stored in the non-volatile memory 120. (See reference...) Figure 6 The repair engine 110 can generate recovery information including a fault flag "1" associated with a fault address and a remapped address "11110010...0000". That is, according to some embodiments, the fault flag may include a single bit value. However, this disclosure is not limited thereto. According to some embodiments, two or more bit values ​​may be used to represent the fault flag.

[0155] Simultaneously, the repair engine 110 can redundantly store the generated recovery information in the memory device 200 based on the fault address. In this case, according to some embodiments, the repair engine 110 can store the remapped address in each of a plurality of regions of the fault block, and can store the fault flag in each of a plurality of regions of the ECC block corresponding to the fault block. In this document, a plurality of regions of the ECC block may be regions corresponding to bits in the bits stored in the ECC block that are not used for ECC function. That is, according to some embodiments, unused bits in the ECC parity bits may be used to store the fault flag.

[0156] refer to Figure 6 The remapped address can be stored in each of all eight regions of the fault block, and the fault flag can be stored in each region of the ECC block corresponding to the fourth bit of the parity bits. However, this disclosure is not limited thereto. The number of remapped addresses or fault flags stored based on the fault address can vary depending on the implementation.

[0157] Figure 7 This is a diagram illustrating a method for obtaining a remapped address according to some embodiments of this disclosure. Figure 7 In the middle, assuming that it stores Figure 6 Recovery information.

[0158] According to some implementations, when reading data corresponding to a target address, the address remapping unit 112 can check whether the data corresponding to certain areas of the ECC block within the data corresponding to the target address corresponds to a fault flag. In this case, certain areas of the ECC block can be areas where the fault flag is stored. (See reference...) Figure 7 The address remapper 112 can check whether the data corresponding to some areas of the ECC block corresponds to the fault flag "1".

[0159] When data corresponding to some regions of an ECC block corresponds to a fault flag, the address remapping unit 112 can obtain a remapped address by applying a majority vote to the data corresponding to multiple regions of the faulty block among the data corresponding to the target address. In this case, the multiple regions can be the regions storing the remapped addresses of the faulty block.

[0160] refer to Figure 7 The address remapping unit 112 can obtain the remapped address "11110010...0000" by applying a majority vote on data corresponding to multiple regions of the fault block where the remapped address is stored, on a bit-by-bit basis. In this case, the address remapping unit 112 can generate a second request including the obtained remapped address and can provide the generated second request to the request handler 111. The above describes the case of obtaining the remapped address by applying a majority vote on a bit-by-bit basis as an example, but the implementation is not limited to this.

[0161] At the same time, the storage will be Figure 6 The data in the fault block and Figure 7 By comparing the read data, it can be understood that some bits of the read data are flipped. However, according to the embodiments of this disclosure, reliability can be improved because the remapped address is redundantly stored in multiple regions of the faulty block and the remapped address is obtained by applying a majority voting method.

[0162] Figure 8 This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure. (See reference...) Figure 8 In operation S810, memory module 10 can redundantly store recovery information in memory device 200 based on the fault address corresponding to the fault block.

[0163] For example, memory module 10 may include non-volatile memory 120 that stores initial information including a list of fault addresses and the starting addresses of remapping regions. Therefore, during initialization, memory module 10 can assign different remapping addresses to multiple fault addresses included in the fault address list and can generate recovery information corresponding to each fault address. In this case, each recovery information may include a remapping address mapped to the corresponding fault address and a fault flag. Based on the above description, memory module 10 can redundantly store the recovery information corresponding to each fault address in memory device 200 based on the corresponding fault address.

[0164] According to some implementations, based on the fault address, the memory module 10 can store a fault flag in each of a plurality of first regions of the fault block, and can store a remapping address in each of a plurality of second regions of the fault block. In some implementations, based on the fault address, the memory module 10 can store a fault flag in each of some regions of the ECC block corresponding to the fault block, and can store a remapping address in each of a plurality of regions of the fault block.

[0165] Additionally, according to some embodiments, the memory module 10 may include a Bloom filter 111b, which is configured to output a given value when an input address is included in a plurality of fault addresses. During the initialization operation of the memory module 10, the Bloom filter 111b may be set based on the list of fault addresses as described above.

[0166] In operation S820, memory module 10 can read data corresponding to the target address from memory device 200 based on a first request including the target address.

[0167] In operation of S830, memory module 10 can identify whether the target address is a fault address based on the data corresponding to the target address.

[0168] According to some implementations, the memory module 10 can apply a majority voting method to the data corresponding to a plurality of first regions in the data corresponding to the target address, and when a fault flag is obtained as a result of the majority voting method, the memory module 10 can identify that the target address is a fault address.

[0169] According to some implementations, the memory module 10 can check whether the data corresponding to some areas of the ECC block in the data corresponding to the target address corresponds to a fault flag, and when the data corresponding to some areas of the ECC block corresponds to the fault flag, the memory module 10 can identify that the target address is a fault address.

[0170] When the target address is identified as a faulty address, in operation S840, the memory module 10 can generate a second request, including a remapped address, based on the data corresponding to the target address.

[0171] According to some implementations, when the target address is identified as a faulty address, the memory module 10 can obtain a remapping address by applying a majority voting method to the data corresponding to the target address and the data corresponding to multiple second regions, and can generate a second request including the obtained remapping address.

[0172] According to some implementations, the memory module 10 can obtain a remapping address by applying a majority voting method to the data corresponding to multiple regions of the fault block in the data corresponding to the target address, and can generate a second request including the obtained remapping address.

[0173] When storage module 10 performs an operation corresponding to the second request, the fault address can be remapped to the remapped address.

[0174] Figure 9 This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure. Figure 9 In this context, we assume the state after the initialization operation (e.g., operation S810) is completed.

[0175] refer to Figure 9 In operation S910, the memory module 10 can receive a first read request including a target address from the host device. In operation S920, the memory module 10 can read data corresponding to the target address from the memory device 200 according to the first read request. Operations S910 and S920 can be combined with... Figure 8 The operation corresponds to that of S820.

[0176] In operation S930, the memory module 10 can identify whether the target address is a fault address based on the data corresponding to the target address. For example, when a fault flag is identified from the data corresponding to the target address, the memory module 10 can identify the target address as a fault address; and when no fault flag is identified from the data corresponding to the target address, the memory module 10 can identify the target address as not a fault address. Operation S930 can be combined with... Figure 8 The operation corresponds to S830.

[0177] When the target address is identified as a faulty address, in operation S940, memory module 10 can generate a second read request including the remapped address. Operation S940 can be combined with... Figure 8 The operation corresponds to S840.

[0178] Subsequently, in operation S950, the memory module 10 can read the data corresponding to the remapped address from the memory device 200 based on the second read request; in operation S960, the memory module 10 can return the data corresponding to the remapped address to the host device.

[0179] Meanwhile, when the target address is not identified as a fault address in operation S930, the memory module 10 can return the data corresponding to the target address to the host device in operation S960.

[0180] Figure 10This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure. Figure 10 In this context, we assume the state after the initialization operation (e.g., operation S810) is completed.

[0181] refer to Figure 10 In operation S1010, the memory module 10 can receive a first write request including a target address from the host device. In operation S1020, the memory module 10 can input the target address into the Bloom filter 111b.

[0182] When a given value (e.g., "1") is output from Bloom filter 111b (a hit is achieved in operation S1020), in operation S1030, memory module 10 can read data corresponding to the target address from memory device 200. Operations S1010 and S1030 can be combined with... Figure 8 The operation corresponds to that of S820.

[0183] Subsequently, in operation S1040, the memory module 10 can identify whether the target address is a fault address based on the data corresponding to the target address. For example, when a fault flag is identified from the data corresponding to the target address, the memory module 10 can identify the target address as a fault address; and when no fault flag is identified from the data corresponding to the target address, the memory module 10 can identify the target address as not a fault address. Operation S1040 can be combined with... Figure 8 The operation corresponds to S830.

[0184] When the target address is identified as a faulty address, in operation S1050, memory module 10 can generate a second write request including the remapped address. Operation S1050 can be combined with... Figure 8 This corresponds to operation S840. Then, in operation S1060, memory module 10 can write data to the region of memory device 200 corresponding to the remapped address based on the second write request.

[0185] Meanwhile, when the output from the Bloom filter 111b is a value different from the given value (e.g., "0") (Miss in operation S1020), in operation S1060, the memory module 10 can write data to the region of the memory device 200 corresponding to the target address based on the first write request.

[0186] Furthermore, even if the target address is identified as not a fault address in operation S1040, in operation S1060, the memory module 10 can still write data to the area of ​​the memory device 200 corresponding to the target address based on the first write request.

[0187] At the same time, refer to Figure 10 The description includes some implementations of operation S1040. However, according to some implementations, operation S1040 can be omitted. That is, according to some implementations, when reading data corresponding to the target address in operation S1030, the memory module 10 can generate a second write request including the remapped address in operation S1050 without identifying a fault flag from the data corresponding to the target address.

[0188] Below, we will refer to Figure 11 This describes an implementation associated with cache memory 111c. Figure 11 This is a flowchart illustrating an operation method of a memory module according to some embodiments of the present disclosure.

[0189] refer to Figure 11 During operation S1110, memory module 10 can perform an initialization operation. For example, during the initialization operation, memory module 10 can generate recovery information based on initial information stored in non-volatile memory 120, and can redundantly store the generated recovery information in memory device 200 based on fault addresses. During the initialization operation, based on the list of fault addresses stored in non-volatile memory 120, memory module 10 can set Bloom filter 111b such that a given value (e.g., "1") is output when an input address is included in multiple fault addresses. Furthermore, during the initialization operation, memory module 10 can generate mapping information in which fault addresses and remapped addresses are mapped based on the initial information stored in non-volatile memory 120, and can store the generated mapping information in cache memory 111c.

[0190] In operation S1120, memory module 10 can receive a first request, including the target address, from the host device. In operation S1130, memory module 10 can check the mapping information stored in cache memory 111c to check if there is a remapped address mapped to the target address.

[0191] When a remapped address exists that is mapped to the target address, in operation S1140, memory module 10 can immediately generate a second request that includes the remapped address.

[0192] At the same time, when there is no remapped address mapped to the target address, the memory module 10 can obtain from Figure 9 Operating S920 or Figure 10 Operation S1020 performs the following operations. Specifically, when the first request received in operation S1120 is a first read request, the memory module 10 can execute... Figure 9The operations S920 and subsequent operations. Furthermore, when the first request received in operation S1120 is a first write request, the memory module 10 can execute... Figure 10 Operation S1020 and the operations following operation S1020.

[0193] Meanwhile, according to some implementations, the mapping information can be generated after the initialization operation and then stored in the cache memory 111c.

[0194] For example, when in Figure 9 When the target address is identified as a fault address in operation S930, the memory module 10 can generate mapping information and store it in the cache memory 111c. In this mapping information, the target address identified as a fault address and the remapping address are mapped. In this case, the memory module 10 can use the remapping address obtained in operation S940 to generate the mapping information.

[0195] In some implementations, when in Figure 10 When the target address is identified as a fault address in operation S1040, the memory module 10 can generate mapping information and store the generated mapping information in the cache memory 111c. In this mapping information, the target address identified as a fault address and the remapping address are mapped. In this case, the memory module 10 can use the remapping address obtained in operation S1050 to generate the mapping information.

[0196] After the mapping information that maps the target address identified as a fault address to the remapping address is stored in the cache memory 111c, when a third request including the same target address is received, the memory module 10 can use the mapping information stored in the cache memory 111c to immediately generate a fourth request including the remapping address.

[0197] Figure 12 This is a flowchart illustrating the operation method of a repair engine according to some embodiments of the present disclosure. Figure 12 In this context, we assume that memory device 200 is DRAM.

[0198] refer to Figure 12 During operation S1200, the repair engine 110 can perform initialization operations. Operation S1200 can be combined with... Figure 11This corresponds to operation S1110. For example, during the initialization operation, the repair engine 110 can redundantly store recovery information about each fault address included in the fault address list in the corresponding fault block of DRAM. Furthermore, during the initialization operation, the repair engine 110 can set a Bloom filter 111b to output a given value when any of the multiple fault addresses included in the fault address list is input. Additionally, during the initialization operation, the repair engine 110 can store mapping information about some of the fault addresses included in the fault address list in cache memory 111c.

[0199] During operation S1205, the repair engine 110 can receive requests based on the CXL.mem protocol. In this case, the request may include a read request or a write request to the target address.

[0200] In operation S1210, the repair engine 110 can check whether the mapping information corresponding to the target address exists in the cache memory 111c. When the mapping information corresponding to the target address exists in the cache memory 111c (yes in operation S1210), the repair engine 110 can execute operation S1215.

[0201] In operation S1215, the repair engine 110 can remap the target address to a remapped address based on the mapping information, and can process the request based on the remapped address. For example, the repair engine 110 can remap the target address to a remapped address by obtaining the remapped address from the mapping information and generating a request including the obtained remapped address. Based on the above description, the repair engine 110 can process a request based on the remapped address by processing the request including the remapped address. For example, when the request received in operation S1205 is a read request, the repair engine 110 can read data from the DRAM based on the remapped address. Furthermore, when the request received in operation S1205 is a write request, the repair engine 110 can write data into the DRAM based on the remapped address.

[0202] In this case, the operation of remapping addresses using the mapping information stored in cache memory 111c can be referred to as fast remapping. This is because remapping addresses using the mapping information stored in cache memory 111c is relatively faster than remapping addresses using recovery information stored in the faulty block. According to some implementations, the fast remapping operation can be performed by the aforementioned request handler 111.

[0203] In this scenario, during operation S1215, the repair engine 110 can return a response to the request to the host device based on the CXL.mem protocol. For example, the repair engine 110 can return data read in operation S1215 to the host device, or it can return the result of a write request processed in operation S1215 to the host device.

[0204] Meanwhile, when there is no mapping information corresponding to the target address in the cache memory 111c (No in operation S1210), the operation of the repair engine 110 can be changed according to the type of request.

[0205] For example, when the request received in operation S1205 is a read request (read in operation S1220), the repair engine 110 can execute operation S1225. In operation S1225, the repair engine 110 can read data from DRAM based on the target address.

[0206] Subsequently, in operation S1230, the repair engine 110 can identify whether the target address is a faulty address based on the read data. For example, when a fault flag is identified from the read data, the repair engine 110 can identify the target address as a faulty address. Furthermore, when no fault flag is identified from the read data, the repair engine 110 can identify the target address as not a faulty address. When the target address is identified as not a faulty address (No in operation S1230), the repair engine 110 can execute operation S1255. In operation S1255, the repair engine 110 can return the data read in operation S1225 (i.e., the data read based on the target address) to the host device based on the CXL.mem protocol.

[0207] When the target address is determined to be a faulty address (as indicated by "Yes" in operation S1230), the repair engine 110 can execute operation S1235. In operation S1235, the repair engine 110 can remap the target address to a remapped address and read data from DRAM based on the remapped address. For example, the repair engine 110 can obtain the remapped address by applying a majority voting method to the data read in operation S1225 and generate a read request including the obtained remapped address, thereby remapping the target address to the remapped address. Based on the above description, the repair engine 110 can read data based on the remapped address by processing the read request including the remapped address.

[0208] In this context, the operation of remapping the address using data read from the target address identified as the faulty address—that is, remapping the address using recovery information stored in the faulty block—can be referred to as slow remapping. According to some implementations, the slow remapping operation can be performed by the address remainder 112 described above.

[0209] In this scenario, during operation S1255, repair engine 110 can return data obtained based on the remapped address to the host device based on the CXL.mem protocol.

[0210] Meanwhile, when the request received in operation S1205 is a write request (a write request in operation S1220), the repair engine 110 can execute operation S1240. In operation S1240, the repair engine 110 can input the target address into the Bloom filter 111b.

[0211] When Bloom filter 111b does not output a given value based on the target address (a miss in operation S1240), repair engine 110 can execute operation S1250. The case where Bloom filter 111b outputs a value different from the given value can be determined as a case where the target address is not a faulty address. Therefore, in operation S1250, repair engine 110 can write data into DRAM based on the target address. In this case, in operation S1255, repair engine 110 can return the result of the write request to the host device based on the CXL.mem protocol.

[0212] Simultaneously, when Bloom filter 111b outputs a given value based on the target address (a hit in operation S1240), repair engine 110 can execute operation S1245. The case where Bloom filter 111b outputs a given value can be determined as the target address being a faulty address. Therefore, in operation S1245, repair engine 110 can read data from DRAM based on the target address and remap the target address to a remapped address. For example, repair engine 110 can remap the target address to a remapped address by applying a majority voting method to the data read based on the target address and generating a write request including the obtained remapped address. Because the remapping operation performed in operation S1245 uses data read based on the target address determined to be a faulty address by Bloom filter 111b, the remapping operation performed in operation S1245 can also be a slow remapping operation.

[0213] In operation S1250, the repair engine 110 can write data to DRAM based on the remapped address by processing a write request that includes the remapped address. In this case, in operation S1215, the repair engine 110 can return the result of the write request to the host device based on the CXL.mem protocol.

[0214] Furthermore, as described above, the memory module 10 or controller 100 according to embodiments of this disclosure can recover from hardware failures of the memory device 200 by storing recovery information in the memory device 200 and using the recovery information to remap the fault address to a remapped address during operation. In this case, storage space may be required for storing the recovery information, and the latency required to access the stored recovery information may increase. This can mean incurring both space and time overhead.

[0215] However, because the memory module 10 or controller 100 according to embodiments of the present disclosure redundantly stores recovery information in the unused space of the fault block or ECC block, the memory module 10 or controller 100 according to embodiments of the present disclosure can ensure reliability while reducing the space used by the memory device 200 for storing recovery information. Furthermore, as described above, the memory module 10 or controller 100 according to embodiments of the present disclosure can use a Bloom filter 111b and / or a cache memory 111c to minimize latency that may occur during remapping operations.

[0216] Meanwhile, the DDR interface has the following limitation: responses to requests generated by the host device must be returned sequentially within a given time. In other words, the JEDEC-compliant DDR interface has strict timing constraints and ordered characteristics. Conversely, unlike the DDR interface, the CXL interface allows variable access latency and has unordered characteristics.

[0217] Because the memory module 10 or controller 100 according to embodiments of the present disclosure is capable of using a CXL interface (e.g., PCIe physical layer and CXL.mem protocol), the memory module 10 or controller 100 according to embodiments of the present disclosure can operate by utilizing the aforementioned characteristics of the CXL interface. Based on the above description, latency losses due to two read operations performed to process a request including a fault address (i.e., a read operation based on the fault address and a read operation based on the remapped address) can be mitigated.

[0218] The following will refer to Figure 13 and Figure 14 This disclosure describes embodiments of the present disclosure related to requests from host devices that will be processed on the CXL interface. Figure 13 and Figure 14 In the diagram, ①, ②, and ③ indicate the order in which requests are input to memory module 10.

[0219] Figure 13 This shows the order in which requests from different addresses are processed. (Reference) Figure 13For example, memory module 10 may sequentially receive a first read request for fault address 0x00, a second read request for normal address 0x01, and a third read request for normal address 0x02.

[0220] Since the first read request is for a fault address, the memory module 10 can process the first read operation through two read operations (a read operation for fault address 0x00 and a read operation for remapped address 0xF0).

[0221] In this scenario, due to the characteristics of the CXL interface, the memory module 10 can process the second and third read requests even if a second and third read request are received simultaneously with the first read request. Furthermore, the memory module 10 can return responses to the second and third read requests to the host device even before the first read request is fully processed (e.g., even before a read request for the remapped address 0xF0 is generated). Based on the above description, the performance degradation caused by the additional access operations required to remap faulty addresses can be mitigated.

[0222] Figure 14 The order in which requests for the same address are processed is shown. According to some embodiments of this disclosure, when requests for the same address are received, the memory module 10 can process the requests in the order they were received.

[0223] refer to Figure 14 It can receive a first write request for fault address 0x00, and then it can receive a first read request for the same fault address 0x00. In this case, the memory module 10 can complete the processing of the first write request, and then it can process the first read request.

[0224] According to the various embodiments of the present disclosure described above, a CXL device capable of more effectively recovering from memory device failures, a memory module including the CXL device, and a method of operating the memory module can be provided.

[0225] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims that may be claimed, their equivalents, and the claims described later. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although the foregoing features may be described as functioning in certain combinations, in some cases, one or more features may be removed from the combination, transforming the combination into a sub-combination or a variation of the sub-combination.

[0226] Although this disclosure has been described with reference to its embodiments, those skilled in the art will understand that various changes and modifications can be made thereto without departing from the spirit and scope of this disclosure as set forth in the following claims.

Claims

1. A memory module, comprising: A memory device, comprising a memory cell array, wherein the memory cell array includes (i) a faulty block comprising a faulty cell and (ii) a remapping block for replacing the faulty block; and The controller is configured to communicate with the host device and control the memory device via a compute fast link (CXL) interface. The controller is configured as follows: Based on the fault address corresponding to the fault block, recovery information, including fault flags and remapping addresses corresponding to the remapping blocks, is redundantly stored in the memory device. Based on receiving a first request including the target address from the host device, read the data corresponding to the target address from the memory device; Based on the data corresponding to the target address, it is determined that the target address is a fault address; and Based on the determination that the target address is a faulty address, a second request, including the remapping address, is generated based on the data corresponding to the target address.

2. The memory module according to claim 1, comprising: The non-volatile memory is configured to store a list of fault addresses and the starting addresses of remapped regions. The list of fault addresses includes multiple fault addresses corresponding to multiple fault blocks included in the memory cell array, and the remapped regions include multiple remapped blocks in the memory cell array. During the initialization operation, the controller is configured as follows: Based on the starting address of the remapping region, multiple remapping addresses are mapped to multiple fault addresses respectively; and For each of the multiple fault addresses, corresponding recovery information associated with each of the multiple fault addresses is redundantly stored in a memory device, wherein the corresponding recovery information includes a remapped address and a fault flag.

3. The memory module according to claim 1, wherein, The controller is configured to: The fault flag is stored in each of the multiple first regions of the fault block, and the remapped address is stored in each of the multiple second regions of the fault block; For the data corresponding to the target address, apply the majority voting method to the data corresponding to multiple first regions; Based on the fault flag obtained as a result of applying a majority vote, a remapping address is obtained by applying a majority vote to data corresponding to multiple second regions within the data corresponding to the target address; and Generate a second request that includes the obtained remapped address.

4. The memory module according to claim 3, wherein, Fault flags include the hash value of the fault address or a preset constant value.

5. The memory module according to claim 1, wherein, The controller is configured to: The fault flag is stored in each of the multiple regions of the error correction code (ECC) block corresponding to the fault block, and the remapping address is stored in each of the multiple regions of the fault block; The data corresponding to the target address and the data corresponding to multiple areas of the ECC block include fault flags; Based on the determination that the data corresponding to the multiple regions includes fault flags, the remapping address is obtained by applying a majority voting method to the data corresponding to the multiple regions of the fault block in the data corresponding to the target address. as well as Generate a second request that includes the obtained remapped address.

6. The memory module according to claim 5, wherein, The multiple regions of the ECC block correspond to bits in the bits stored in the ECC block that are not used for ECC functions.

7. The memory module according to claim 1, wherein, The first request includes a first read request, and the first read request includes the target address. The controller is configured as follows: Based on identifying the fault flag from the data corresponding to the target address, the target address is determined to be a fault address and a second read request including the remapped address is generated; Based on the second read request, data corresponding to the remapped address is read from the memory device; and Provide the data corresponding to the remapped address to the host device.

8. The memory module according to claim 7, wherein, The controller is configured to provide data corresponding to the target address to the host device based on the fact that no fault flag is identified from the data corresponding to the target address.

9. The memory module according to claim 2, wherein, The controller includes: A Bloom filter is configured to output a given value based on a list of fault addresses, where the target address input to the Bloom filter is included in a list of fault addresses.

10. The memory module according to claim 9, wherein, The first request includes a first write request, and the first write request includes the target address. The controller is configured as follows: In response to receiving the first write request, the target address is input into the Bloom filter; Based on a given value, data corresponding to the target address is read from the memory device from the output of the Bloom filter; and Based on the fact that the given value is not output from the Bloom filter, data corresponding to the target address is written to the region of the storage cell array based on the first write request.

11. The memory module according to claim 10, wherein, The controller is configured to: Based on identifying fault flags from data corresponding to the target address, the target address is determined to be a fault address among multiple fault addresses, and a second write request including the remapped address is generated. as well as Based on the second write request, data corresponding to the remapped address is written to the region of the memory cell array.

12. The memory module according to claim 11, wherein, The controller is configured to write data corresponding to the target address into the region of the memory cell array based on a first write request, based on the fact that a fault flag is not identified from the data corresponding to the target address.

13. The memory module according to claim 1, wherein, The memory cell array includes: First fault block; and The first mapping block is used to replace the first faulty block. The controller includes: A cache memory is configured to store mapping information, the mapping information including a first fault address corresponding to a first fault block and a first remapping address corresponding to a first remapping block.

14. The memory module according to claim 13, wherein, The controller is configured to: Based on the first request received, which includes the target address, the target address is determined to correspond to the first fault address based on the mapping information stored in the cache memory. as well as Based on the determination that the target address corresponds to the first fault address, a third request including the first remapped address is generated using the mapping information stored in the cache memory.

15. A Computational Fast Link (CXL) device, comprising: The host interface is configured to communicate with the host device using the CXL protocol; as well as The memory controller is configured to control the memory device and process requests received from the host device via the host interface. The memory controller includes a repair engine configured to replace data in faulty blocks of the memory device with remapped blocks of the memory device. The repair engine is configured as follows: Based on the fault address corresponding to the fault block, recovery information, including fault flags and remapping addresses corresponding to the remapping blocks, is redundantly stored in the memory device. Based on receiving a first request including the target address from the host device, read the data corresponding to the target address from the memory device; Based on the data corresponding to the target address, it is determined that the target address is a fault address; and Based on the determination that the target address is a faulty address, a second request, including the remapping address, is generated based on the data corresponding to the target address.

16. The CXL device according to claim 15, comprising: The non-volatile memory is configured to store a list of fault addresses and the starting addresses of remapped regions. The list of fault addresses includes multiple fault addresses corresponding to multiple fault blocks included in the memory device, and the remapped regions include multiple remapped blocks of the memory device. During the initialization process, the repair engine is configured as follows: Based on the starting address of the remapping region, multiple remapping addresses are mapped to multiple fault addresses respectively; and For each of the multiple fault addresses, corresponding recovery information associated with each of the multiple fault addresses is redundantly stored in a memory device, wherein the corresponding recovery information includes a remapped address and a fault flag.

17. The CXL device according to claim 15, wherein, The repair engine is configured as follows: The fault flag is stored in each of the multiple first regions of the fault block, and the remapped address is stored in each of the multiple second regions of the fault block; For the data corresponding to the target address, apply the majority voting method to the data corresponding to multiple first regions; Based on the fault flag obtained as a result of the majority voting method, the remapping address is obtained by applying the majority voting method to the data corresponding to multiple second regions in the data corresponding to the target address. and Generate a second request that includes the obtained remapped address.

18. The CXL device according to claim 15, wherein, The repair engine is configured as follows: The fault flag is stored in each of the multiple regions of the error correction code (ECC) block corresponding to the fault block, and the remapping address is stored in each of the multiple regions of the fault block; Identify the data corresponding to multiple areas of the ECC block within the data corresponding to the target address, and determine which data corresponds to the fault flag. Based on determining the correspondence between data and fault flags corresponding to multiple regions, the remapping address is obtained by applying majority voting to the data corresponding to multiple regions of the fault block among the data corresponding to the target address. as well as Generate a second request that includes the obtained remapped address.

19. A memory module, comprising: The memory device includes a first fault block, a second fault block, a first remapping block corresponding to the first fault block, and a second remapping block corresponding to the second fault block; as well as The controller includes a cache memory and is configured to communicate with and control the memory device via a compute fast link (CXL) interface. The controller is configured as follows: The mapping information is stored in a high-speed cache memory. The mapping information includes the first fault address corresponding to the first fault block and the first remapping address corresponding to the first remapping block. Based on the second fault address corresponding to the second fault block, recovery information, including fault flags and the second remapping address corresponding to the second remapping block, is redundantly stored in the memory device; and Based on the first request received from the host device, which includes a first fault address, and based on the mapping information stored in the cache memory, a second request, which includes a first remapped address, is generated.

20. The memory module according to claim 19, wherein, The controller is configured to: Based on receiving a third request from the host device, including the second fault address, read data corresponding to the second fault address from the memory device; The second remapping address is obtained from the data corresponding to the second fault address through majority voting; and Generate a fourth request that includes the obtained second-level mapping address.

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