Server hardware circuits and their mode control methods, server

Abstract

This application provides a server hardware circuit and its mode control method, as well as a server, which can be used in the field of server technology. The server hardware circuit includes a first node motherboard, a second node motherboard, and an intermediate interconnect motherboard. The first node motherboard includes a first processor, a first baseboard management controller, and a first main control chip. The second node motherboard includes a second processor, a second baseboard management controller, and a second main control chip. A first bidirectional communication line connects the second node motherboard to the first node motherboard. The intermediate interconnect motherboard includes a third main control chip, and a second bidirectional communication line and a main power supply line connect the intermediate interconnect motherboard to both the first and second node motherboards. This application can flexibly switch between single-node / dual-node mode and single-path / dual-path mode according to actual business needs, greatly improving the adaptability and resource utilization of the server hardware and reducing the total cost of ownership of the data center.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a server hardware circuit and its mode control method, and a server. Background Technology

[0002] A server is a dedicated computer system in a network environment that provides core services such as data storage, processing, and resource sharing to other devices. Existing server architectures are typically divided into four fixed configuration modes: single-socket servers, dual-socket servers, single-node servers, and dual-node servers.

[0003] However, with the rapid development of technologies such as cloud computing, big data, and artificial intelligence, data centers have placed higher demands on the performance, flexibility, and cost-effectiveness of servers. The fixed configuration mode of traditional server architecture can no longer fully meet the diverse application scenarios of data centers.

[0004] Therefore, there is an urgent need for a server hardware architecture that can flexibly support multiple configuration modes such as single-node / dual-node and single-socket / dual-socket, and can dynamically switch according to business needs, in order to improve hardware resource utilization and reduce total cost of ownership. Summary of the Invention

[0005] This application provides a server hardware circuit and its mode control method, as well as a server, to solve the technical problem that existing servers, due to their fixed configuration mode server architecture, cannot dynamically switch according to business needs, resulting in reduced hardware resource utilization and increased total cost of ownership.

[0006] According to the first aspect disclosed in this application, this application provides a server hardware circuit, including...

[0007] The first node motherboard includes a first processor, a first baseboard management controller, and a first main control chip.

[0008] The second node motherboard includes a second processor, a second baseboard management controller, and a second main control chip; wherein, the second node motherboard is connected to the first node motherboard by a first bidirectional communication line.

[0009] The intermediate interconnect motherboard includes a third main control chip, and the intermediate interconnect motherboard is connected to the first node motherboard and the second node motherboard by a second bidirectional communication line and a main power supply line.

[0010] In one feasible implementation, the first bidirectional communication line includes at least one of I2C signal line, LTPI signal line, and GPIO signal line, as well as a UPI signal line connecting the first processor and the second processor.

[0011] In one feasible implementation, the second bidirectional communication line includes at least one of an I2C signal line and a GPIO signal line.

[0012] In one feasible implementation, an auxiliary power supply line is connected between the first node motherboard and the second node motherboard.

[0013] In one feasible implementation, the processor is provided with multiple memory interfaces and multiple I / O interfaces.

[0014] In one feasible implementation, the first main control chip includes a first timing control unit and a first logic control unit, the second main control chip includes a second timing control unit and a second logic control unit, and the third main control chip includes a third timing control unit and a third logic control unit.

[0015] According to a second aspect disclosed in this application, this application provides a mode control method for a server hardware circuit, applied to a first node motherboard in a server hardware circuit as described in any one of the first aspects, comprising:

[0016] Obtain the configuration mode input by the user; wherein, the configuration mode includes single-node mode, dual-node mode, single-path mode or dual-path mode;

[0017] Based on the configuration mode, the working state of the second node motherboard in the server hardware circuit is dynamically switched.

[0018] In one feasible implementation, based on the configuration mode, dynamically switching the operating state of the second node motherboard in the server hardware circuit includes:

[0019] If the configuration mode is a single-node mode or a single-path mode, the first bidirectional communication line between the first node motherboard and the second node motherboard is disconnected, and a power cut-off signal is sent to the intermediate interconnect motherboard in the server hardware circuit so that the intermediate interconnect motherboard disconnects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power cut-off signal.

[0020] If the configuration mode is a dual-node mode, the first bidirectional communication line between the first node motherboard and the second node motherboard is disconnected, and a power connection signal is sent to the intermediate interconnect motherboard so that the intermediate interconnect motherboard connects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power connection signal.

[0021] If the configuration mode is dual-path mode, then the first bidirectional communication line between the first node motherboard and the second node motherboard is connected, and a power connection signal is sent to the intermediate interconnect motherboard, so that the intermediate interconnect motherboard connects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power connection signal.

[0022] In one feasible implementation, the method further includes:

[0023] Obtain user-inputted operation information; wherein, the operation information includes upgrade information or configuration information;

[0024] If the operation information is upgrade information, then an upgrade signal is sent to the intermediate interconnect motherboard to control the intermediate interconnect motherboard to perform an upgrade operation;

[0025] If the operation information is configuration information, a configuration signal is sent to the intermediate interconnect motherboard so that the intermediate interconnect motherboard performs a configuration operation on the second node motherboard according to the configuration signal.

[0026] According to a third aspect disclosed in this application, this application provides a server including server hardware circuitry as described in any one of the first aspects.

[0027] Compared with the prior art, this application has the following beneficial effects:

[0028] This application provides a server hardware circuit and its mode control method, and a server. The server hardware circuit, composed of a first node motherboard, a second node motherboard, and an intermediate interconnecting motherboard, can control the on / off state of the bidirectional communication lines and main power lines between the motherboards. This allows the first and second node motherboards to operate as single-node or dual-node servers, or as single-socket or dual-socket servers, achieving flexible deployment of "one set of hardware, multiple configurations." This enables flexible switching between single-node / dual-node and single-socket / dual-socket modes according to actual business needs, greatly improving the adaptability and resource utilization of the server hardware and reducing the total cost of ownership of the data center. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0030] Figure 1 This is a schematic diagram of a server hardware circuit provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of a processor topology provided for an embodiment of this application;

[0032] Figure 3 This application provides a schematic diagram of a topological connection structure for two processors.

[0033] Figure 4 A schematic flowchart illustrating a mode control method for a server hardware circuit provided in an embodiment of this application;

[0034] Figure 5 A flowchart illustrating a method for upgrading / configuring server hardware circuitry provided in an embodiment of this application;

[0035] Figure 6 This is a schematic diagram of a multiplexing control architecture for the BIOS and BMC firmware SPI bus on a node motherboard, provided as an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures:

[0037] 110 - First Node Motherboard;

[0038] 111 - First Processor;

[0039] 112 - First baseboard management controller;

[0040] 113 - First main control chip;

[0041] 120 - Second Node Motherboard;

[0042] 121 - Second processor;

[0043] 122 - Second baseboard management controller;

[0044] 123 - Second main control chip;

[0045] 130 - Intermediate interconnect motherboard;

[0046] 131 - Third main control chip;

[0047] 140 - First bidirectional communication line;

[0048] 150-Auxiliary power supply line;

[0049] 160 - Main power supply line;

[0050] 170 - Second bidirectional communication line.

[0051] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0052] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0053] A server is a dedicated computer system in a network environment that provides core services such as data storage, processing, and resource sharing to other devices. Existing server architectures are typically divided into four fixed configuration modes: single-socket servers, dual-socket servers, single-node servers, and dual-node servers.

[0054] Among them, a single-socket server is equipped with a single CPU (Central Processing Unit), which is suitable for lightweight application scenarios, but its performance is limited; a dual-socket server is equipped with two CPUs, which improves performance through high-speed interconnection between the CPUs, but the hardware cost is high and there is resource waste in low-load scenarios; a single-node server is an independent single-node server unit with independent computing, storage and network resources; a dual-node server integrates two independent server nodes in the same chassis, sharing power and cooling system, but each node operates independently.

[0055] However, with the rapid development of technologies such as cloud computing, big data, and artificial intelligence, data centers have placed higher demands on the performance, flexibility, and cost-effectiveness of servers. The fixed configuration mode of traditional server architecture can no longer fully meet the diverse application scenarios of data centers.

[0056] Specifically, the shortcomings of the current traditional server architecture using a fixed configuration mode are mainly reflected in the following aspects:

[0057] First, the configuration mode is fixed. The server architecture configuration is determined at the factory and cannot be flexibly adjusted according to business needs. For example, a dual-socket server cannot be split into two independent single-socket nodes, and a single-CPU motherboard server cannot be expanded into a dual-node or dual-socket configuration.

[0058] Secondly, it lacks flexible switching capabilities. Dual-CPU motherboard servers can only be used as dual-processor servers and cannot be switched to two independent single-node servers, resulting in a waste of computing resources.

[0059] Third, cost optimization is difficult. Enterprises need to purchase different types of servers to cope with different application scenarios, which increases procurement and inventory management costs and makes it impossible to achieve "one set of hardware for multiple uses".

[0060] Fourth, scalability is limited. Single-CPU motherboard servers cannot achieve multiple configuration modes through simple expansion.

[0061] Therefore, there is an urgent need for a server hardware architecture that can flexibly support multiple configuration modes such as single-node / dual-node and single-socket / dual-socket, and can dynamically switch according to business needs, in order to improve hardware resource utilization and reduce total cost of ownership.

[0062] To address the aforementioned technical issues, this application proposes a server hardware circuit and its mode control method, as well as a server. The server hardware circuit, composed of a first node motherboard, a second node motherboard, and an intermediate interconnect motherboard, can flexibly switch between single-node mode / dual-node mode and single-path mode / dual-path mode according to actual business needs, greatly improving the adaptability and resource utilization of the server hardware and reducing the total cost of ownership of the data center.

[0063] The server hardware circuit and its mode control method, as well as the server technical solution provided in this application, are described in detail below through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for the same or similar content, descriptions may not be repeated in different embodiments.

[0064] Figure 1 This is a schematic diagram of a server hardware circuit provided in an embodiment of this application. (See attached diagram.) Figure 1 In some embodiments, the server hardware circuit includes a first node motherboard 110, a second node motherboard 120, and an intermediate interconnect motherboard 130; the first node motherboard 110 includes a first processor 111, a first baseboard management controller 112, and a first main control chip 113; the second node motherboard 120 includes a second processor 121, a second baseboard management controller 122, and a second main control chip 123; wherein, the second node motherboard 120 and the first node motherboard 110 are connected by a first bidirectional communication line 140; the intermediate interconnect motherboard 130 includes a third main control chip 131, and the intermediate interconnect motherboard 130 is connected to the first node motherboard 110 and the second node motherboard 120 by a second bidirectional communication line 170 and a main power supply line 160, respectively.

[0065] Specifically, the node motherboard includes functional modules such as a processor, baseboard management controller, and main control chip, and can operate independently as a single-node, single-processor server. Each node motherboard is equipped with a CPU socket, memory slots, PCIe (Peripheral Component Interconnect Express) expansion slots, and necessary peripheral interfaces.

[0066] Specifically, the intermediate interconnect motherboard 130 serves as an intermediate node, enabling firmware upgrades, power management, and configuration management for the two node motherboards.

[0067] Specifically, the CPU is the core device of a server, and its main function is to interpret computer instructions and process data in computer software.

[0068] Specifically, the Baseboard Management Controller (BMC) is a server remote management controller, part of the server hardware, used to provide remote monitoring and management functions, including system status monitoring, alarms, logging, and remote power on / off operations. The BMC is typically implemented based on the IPMI (Intelligent Platform Management Interface) standard and is an important component of server remote management.

[0069] Specifically, the main control chip CPLD (Complex Programmable Logic Device) is the core device for realizing programmable control of hardware logic. It mainly undertakes the tasks of coordinating and managing various hardware modules inside the server, signal scheduling and status control. Through flexible hardware logic configuration, it provides stable and reliable underlying control support for the server system and ensures that the components work together in an orderly manner.

[0070] Specifically, the first bidirectional communication line 140 is used to establish bidirectional communication between the first node motherboard 110 and the second node motherboard 120, so as to realize the transmission of communication signals between the first node motherboard 110 and the second node motherboard 120.

[0071] The opening and closing of the first bidirectional communication line 140 allows the first node motherboard 110 and the second node motherboard 120 to switch between single-channel and dual-channel modes. When the first bidirectional communication line 140 is open, the first node motherboard 110 and the second node motherboard 120 can exchange data through the first bidirectional communication line 140 to achieve collaborative work. When the first bidirectional communication line 140 is closed, the first node motherboard 110 and the second node motherboard 120 operate independently.

[0072] Specifically, the second bidirectional communication line 170 is used to establish bidirectional communication between the intermediate interconnect motherboard 130 and the first node motherboard 110, and between the intermediate interconnect motherboard 130 and the second node motherboard 120, so as to realize the transmission of communication signals between the intermediate interconnect motherboard 130 and the first node motherboard 110, and between the intermediate interconnect motherboard 130 and the second node motherboard 120.

[0073] Specifically, the main power line 160 is used to establish power supply channels between the intermediate interconnect motherboard 130 and the first node motherboard 110, and between the intermediate interconnect motherboard 130 and the second node motherboard 120, so that power can be supplied to the first node motherboard 110 and the second node motherboard 120 through the intermediate interconnect motherboard 130.

[0074] The switching of the main power line 160 allows the first node motherboard 110 and the second node motherboard 120 to switch between single-node and dual-node modes. When the main power line 160 between the intermediate interconnect motherboard 130 and the first node motherboard 110, or between the intermediate interconnect motherboard 130 and the second node motherboard 120, is disconnected, the corresponding node motherboard will stop working. When the main power line 160 between the intermediate interconnect motherboard 130 and the first node motherboard 110, or between the intermediate interconnect motherboard 130 and the second node motherboard 120, is connected, the corresponding node motherboard will operate normally.

[0075] The main power line 160 is powered by a 12V main power supply. The intermediate interconnect motherboard 130 provides 12V main power to the first node motherboard 110 and / or the second node motherboard 120 through the main power line 160. The first node motherboard 110 and / or the second node motherboard 120 then convert the 12V power supply into the voltage required by the core devices on the node motherboard (such as 1.0V, 1.2V, etc.) through their voltage regulator (VR) / electronic fuse (EFUSE).

[0076] In addition, the main power line 160 can also power external devices that are connected to the node motherboard via the PCIe bus standard, such as expansion cards, NVMe SSDs and other high-power devices.

[0077] In this embodiment, the server hardware circuit composed of the first node motherboard 110, the second node motherboard 120, and the intermediate interconnect motherboard 130 can control the on / off state of the bidirectional communication lines and the main power line 160 between the motherboards. This allows the first node motherboard 110 and the second node motherboard 120 to operate as single-node servers or dual-node servers, or as single-socket servers or dual-socket servers. This enables flexible deployment of "one set of hardware, multiple configurations," allowing for flexible switching between single-node mode / dual-node mode and single-socket mode / dual-socket mode according to actual business needs. This greatly improves the adaptability and resource utilization of the server hardware and reduces the total cost of ownership of the data center.

[0078] In some embodiments, the first bidirectional communication line 140 includes at least one of an I2C signal line, an LTPI signal line, and a GPIO signal line, as well as a UPI signal line connecting the first processor 111 and the second processor 121.

[0079] In this embodiment, at least one of I2C signal lines, LTPI signal lines, and GPIO signal lines, as well as the UPI signal line connecting the first processor 111 and the second processor 121, is used as the first bidirectional communication line 140 to realize bidirectional communication between the first node motherboard 110 and the second node motherboard 120.

[0080] Specifically, I2C (Inter-Integrated Circuit) is a two-wire serial bidirectional bus used to connect microcontrollers to external devices (such as sensors and memory). I2C signal lines are used for exchanging operational information, transmitting configuration data, and querying status between the first baseboard management controller 112 and the second baseboard management controller 122, and between the first main control chip 113 and the second main control chip 123.

[0081] LTPI (LVDS Tunneling Protocol & Interface) is a tunneling protocol based on LVDS (Low Voltage Differential Signaling) used to transmit low-speed signals between HPM (High Performance Module) and SCM (System Control Module). LTPI signal lines are used for data transmission between the first node motherboard 110 and the second node motherboard 120, supporting low-latency inter-node data exchange, suitable for applications such as real-time data monitoring and high-frequency status updates.

[0082] GPIO (General Purpose Input / Output) is a general-purpose pin on an integrated circuit that can be programmed to be in input or output mode and is used to connect external hardware signal lines. GPIO signal lines are used for data transmission between the first node motherboard 110 and the second node motherboard 120, for hardware upgrade status indication, interrupt notification, and simple control signal transmission, etc.

[0083] UPI (Ultra Path Interconnect) is a high-speed point-to-point interconnect technology designed by Intel for multiprocessor systems. It enables efficient data transfer between CPUs and between the CPU and other critical components (such as memory and accelerator cards). UPI signal lines are used for high-speed interconnection between the first processor 111 and the second processor 121, allowing direct communication between multiple processors. This is used for communication between CPUs and cache coherency maintenance in dual-socket or multi-socket servers.

[0084] In some embodiments, the second bidirectional communication line 170 includes at least one of an I2C signal line and a GPIO signal line.

[0085] In this embodiment, at least one of the I2C signal line and the GPIO signal line is used as the second bidirectional communication line 170 to realize bidirectional communication between the intermediate interconnect motherboard 130 and the first node motherboard 110, and between the intermediate interconnect motherboard 130 and the second node motherboard 120.

[0086] Specifically, the I2C signal line is used for communication between the third main control chip 131 and the first main control chip 113, and between the third main control chip 131 and the second main control chip 123, so as to realize functions such as firmware upgrade, power control request, configuration signal transmission, and status query of the main control chip.

[0087] Specifically, GPIO signal lines are used for the transmission of power control signals, reset signals, interrupt signals, and status indication signals.

[0088] See Figure 1 In some embodiments, an auxiliary power line 150 is connected between the first node motherboard 110 and the second node motherboard 120.

[0089] In this embodiment, by setting an auxiliary power line 150 between the first node motherboard 110 and the second node motherboard 120, firstly, it can supply power to the first node motherboard 110 and the second node motherboard 120, ensuring that the main control chip CPLD of the dual nodes is always powered, supporting the wake-up function of the baseboard management controller in standby mode; secondly, the auxiliary power line 150 ensures the continuous operation of programmable logic devices, maintaining the availability of communication channels and control logic between nodes; thirdly, it realizes auxiliary power redundancy, when the power module of one node fails, auxiliary power can be obtained from another node through inter-node interconnection, improving system reliability; fourthly, it supports power state coordination between nodes, by sharing auxiliary power, the dual nodes can still maintain the activity of the management channel when the main power is turned off, realizing true remote power control.

[0090] Specifically, the auxiliary power supply line 150 is powered by a 3V auxiliary power supply.

[0091] See Figure 2 In some embodiments, the processor is provided with multiple memory interfaces and multiple I / O interfaces.

[0092] In this embodiment, the memory interface is a dedicated channel between the CPU and main memory (RAM) for high-speed reading and writing of program instructions and data. The memory interface is the only path for the CPU to directly access memory, determining the data transfer rate (bandwidth) between the CPU and memory. The I / O interface acts as a bridge between the CPU and external devices (such as hard drives, expansion cards, etc.), managing communication with these devices.

[0093] Specifically, see Figure 2 The processor module (CPU) has a set of 8 DDR5 memory channels on each side, 8 channels on each side (DIMM0-DIMM7 and DIMM8-DIMM15), for a total of 16 DDR5 memory channels. Multiple memory interfaces allow the CPU to support a large number of memory modules, providing high memory bandwidth and capacity.

[0094] Specifically, there is a set of 8 X16 Gen6 interfaces on each side of the processor, for a total of 16 X16 Gen6 interfaces (each X16 Gen6 interface includes two MCIO X8 interfaces). These I / O interfaces may be used to connect external memory chips or other high-speed devices. Each X16 Gen6 interface can support 16-bit wide data transfer.

[0095] Specifically, see Figure 3 The two processors on the first node motherboard 110 and the second node motherboard 120 can communicate bidirectionally through the X16 Gen6 interface.

[0096] In some embodiments, the first main control chip 113 includes a first timing control unit and a first logic control unit, the second main control chip 123 includes a second timing control unit and a second logic control unit, and the third main control chip 131 includes a third timing control unit and a third logic control unit.

[0097] In this embodiment, the main control chip includes a timing control unit and a logic control unit. The timing control unit is used for clock signal management and signal timing synchronization, accurately controlling the triggering time, duration and transmission rhythm of various control signals and data signals, ensuring that logical operations are executed in a standardized manner under a unified timing, avoiding timing conflicts and improving system stability. The logic control unit is used to perform specific logical operations, signal judgment and functional decisions, and complete core logical processing such as data path selection, interface protocol parsing and state condition determination.

[0098] Figure 4 A flowchart illustrating a mode control method for server hardware circuitry provided in this application embodiment is shown below. Figure 4 In some embodiments, the mode control method for the server hardware circuit is applied to the first node motherboard in the aforementioned server hardware circuit, and its specific process includes the following steps:

[0099] S410, obtains the configuration mode input by the user; wherein, the configuration mode includes single-node mode, dual-node mode, single-path mode or dual-path mode.

[0100] Users can input the desired configuration mode through external input devices (such as keyboards).

[0101] Specifically, the mode control method applied to the first node motherboard in the server hardware circuitry means that the system defaults to single-node / single-processor mode and then switches to dual-node or dual-processor mode as needed. Furthermore, the first node motherboard simply refers to one of two node motherboards; it can be either the first node motherboard or the second node motherboard.

[0102] The S420 dynamically switches the operating state of the second node motherboard in the server hardware circuit based on configuration mode.

[0103] The system dynamically switches the operating state of the second node motherboard in the server hardware circuit through user-input configuration mode, thereby changing the operating mode of the entire system and enabling it to switch between single-node mode, dual-node mode, single-path mode, or dual-path mode.

[0104] Specifically, after the user inputs the configuration mode, the first-node motherboard uses a mode recognition circuit, hardware detection (such as GPIO configuration), or software configuration to identify the current system's operating mode, and then switches modes via interconnect paths. The interconnect path switching circuit includes multiplexers, switch matrices, or programmable logic devices, dynamically switching the state of the interconnect paths between CPUs according to the configuration mode.

[0105] Dual-socket mode: Enables high-speed interconnect pathways to achieve cache coherency protocols and memory sharing between CPUs;

[0106] Single / Dual Node Mode: Disable the interconnect path or configure it as an independent PCIe channel, and the two CPUs work completely independently.

[0107] Optionally, step S420 specifically includes:

[0108] S421, if the configuration mode is single-node mode or single-path mode, disconnect the first bidirectional communication line between the first node motherboard and the second node motherboard, and send a power cut-off signal to the intermediate interconnect motherboard in the server hardware circuit so that the intermediate interconnect motherboard disconnects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power cut-off signal.

[0109] In the configuration modes of single-node mode and single-path mode, a single node motherboard operates independently, while the other node motherboard can be powered down via power control.

[0110] Specifically, the first main control chip of the first node motherboard notifies the third main control chip of the intermediate interconnect motherboard via I2C or GPIO signals that the current mode is single-node mode or single-path mode. The third main control chip controls the power supply of the second node motherboard through corresponding control signals to prevent it from being powered on, and controls the configuration mode of the first node motherboard to be single CPU without UPI interconnect mode through corresponding configuration signals, so as to enable the first node motherboard to work independently in single-node mode and single-path mode.

[0111] S422, if the configuration mode is dual-node mode, disconnect the first bidirectional communication line between the first node motherboard and the second node motherboard, and send a power connection signal to the intermediate interconnect motherboard so that the intermediate interconnect motherboard connects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power connection signal.

[0112] In the dual-node configuration mode, the two node motherboards operate independently and do not communicate with each other, but they share the chassis, power supply and heat dissipation.

[0113] Specifically, the first main control chip of the first node motherboard notifies the third main control chip of the intermediate interconnect motherboard that the current mode is single node through I2C or GPIO signals. The third main control chip controls the power supply of the second node motherboard to power on through corresponding control signals, and controls the configuration mode of the first node motherboard to single CPU without UPI interconnect mode through corresponding configuration signals, so as to realize that the first motherboard node and the second node motherboard can work independently in dual node mode.

[0114] S423, if the configuration mode is dual-path mode, connects the first bidirectional communication line between the first node motherboard and the second node motherboard, and sends a power connection signal to the intermediate interconnect motherboard, so that the intermediate interconnect motherboard connects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power connection signal.

[0115] In the dual-path configuration, the two node motherboards communicate and collaborate with each other, and the CPUs of the two node motherboards work together through high-speed interconnection.

[0116] In this embodiment, the server deployment flexibility is greatly improved by dynamically switching the server hardware circuit configuration mode. It supports flexible switching between four configuration modes, allowing the same hardware to adapt to different application scenarios. In particular, the innovative design of a dual-CPU motherboard that can function as both a dual-socket server and a dual-node server allows users to dynamically adjust the server configuration according to business load without replacing hardware. The single-CPU motherboard design, which functions as both a single-node and single-socket server, provides an optimal cost solution for small-scale deployments.

[0117] Resource utilization is significantly improved. In light-load scenarios, the dual-socket server can be switched to dual-node mode, with each node independently serving different business functions, avoiding resource waste. In high-performance computing scenarios, the dual-node configuration can be switched to dual-socket mode to fully leverage the advantages of multi-CPU collaborative computing.

[0118] Total cost of ownership is reduced, eliminating the need for enterprises to purchase multiple types of servers (single-socket, dual-socket, single-node, dual-node, etc.), thus lowering procurement costs. A unified hardware platform simplifies inventory management, maintenance training, and spare parts stockpiling, reducing operating costs. Energy efficiency is optimized by dynamically adjusting configurations based on actual load, improving energy savings.

[0119] It boasts high scalability; a single-CPU motherboard can be easily expanded to a dual-node or dual-socket configuration without replacing major hardware components. Its modular design supports future technology upgrades, such as faster interconnect standards and next-generation CPUs. The architecture is designed to accommodate expansion to four-socket or multi-node configurations.

[0120] Optionally, in addition to mode switching, resource allocation and isolation mechanisms are also included. Specifically, these include:

[0121] Firstly, memory resource management. Single-socket mode / single-node mode: memory is directly connected to the corresponding CPU; dual-socket mode: unified memory access (UMA) or non-unified memory access across CPUs is achieved through interconnection paths; dual-node mode: each node has its own dedicated memory resources, completely isolated.

[0122] Secondly, PCIe resource allocation. Configurable PCIe lane allocation assigns PCIe lanes to different CPUs or nodes based on the working mode, supporting dynamic bifurcation of PCIe lanes to achieve flexible device connections.

[0123] Third, peripheral interface management. Each node is equipped with an independent Baseboard Management Controller (BMC) or a shared BMC to achieve out-of-band management. Network interfaces and storage interfaces can be allocated or shared according to the configuration mode.

[0124] Optionally, in addition to mode switching, a coordinated power supply and heat dissipation design is also included. Specifically, this includes:

[0125] Firstly, a unified power system. Whether in single-node, dual-node, or dual-path mode, all systems can share the same high-efficiency power system, improving energy efficiency.

[0126] Secondly, intelligent heat dissipation allocation: dynamically adjusts the allocation of heat dissipation resources for each node or CPU based on the current working mode and load.

[0127] Optionally, the cross-node point power control mechanism specifically includes:

[0128] The first baseboard management controller or the first main control chip of the first node motherboard identifies the current configuration mode according to the configuration PIN, and reads and writes the registers of the third main control chip of the intermediate interconnect board through the I2C bus. The third main control board of the intermediate interconnect board manages the power devices such as VR / EFUSE on the intermediate interconnect board by controlling the GPIO signal level, such as whether to supply the same power to the two motherboards or supply them independently.

[0129] Taking the power-on process of the first node motherboard controlling the power of the second node motherboard as an example (which is symmetrical to the process of the second node motherboard controlling the first node motherboard):

[0130] Step 1: The first baseboard management controller of the first node motherboard receives a remote power-on command for the second node motherboard.

[0131] Step 2: The first baseboard management controller sends a power control command to the third main control chip on the intermediate interconnect board through the interconnect interface.

[0132] Step 3: The third main control chip on the intermediate interconnect board parses the power control command and verifies the command's legality and permissions.

[0133] Step 4: The third main control chip sends a PowerEnable signal to the power management unit of the second node motherboard through the GPIO signal line.

[0134] Step 5: After receiving the Power Enable signal, the power management unit of the second node motherboard starts the 12V main power output.

[0135] Step 6: After the 12V main power supply of the second node motherboard is established and stabilized, the power management unit sends a Power Good signal to the third main control chip via GPIO.

[0136] Step 7: After receiving the Power Good signal, the third main control chip sends a System Power On signal to the second main control chip of the second node motherboard to start the power-on sequence of the second node motherboard.

[0137] Step 8: The second processor, memory and other components of the second node motherboard are powered on in sequence, and the system enters the POST (Power-On Self-Test) self-test stage.

[0138] Step 9: The third main control chip returns the power control operation result (success or failure) and the power status of the second node motherboard to the first baseboard management controller of the first node motherboard via I2C.

[0139] Step 10: The first baseboard management controller records the power operation log and notifies the operation initiator (user).

[0140] See Figure 5 In some embodiments, the method further includes:

[0141] S510 acquires user-inputted operation information, including upgrade information or configuration information.

[0142] In addition to switching configuration modes, users can also upgrade the intermediate interconnect motherboard or configure the second node motherboard by inputting operation information.

[0143] If the operation information is upgrade information, the S520 sends an upgrade signal to the intermediate interconnect motherboard to control the intermediate interconnect motherboard to perform the upgrade operation.

[0144] If the operation information is upgrade information, then the intermediate interconnect motherboard is controlled to perform the upgrade operation by sending an upgrade signal to the intermediate interconnect motherboard.

[0145] If the operation information is configuration information, the S530 sends a configuration signal to the intermediate interconnect motherboard so that the intermediate interconnect motherboard can perform configuration operations on the second node motherboard according to the configuration signal.

[0146] If the operation information is configuration information, a configuration signal is sent to the intermediate interconnect motherboard to control the second node motherboard to perform the configuration operation.

[0147] Optionally, firmware and software support specifically includes:

[0148] Firstly, the BIOS / BMC firmware. It supports multiple boot modes and can recognize the current configuration and perform corresponding hardware initialization.

[0149] Single-node mode: Only one node on the first node motherboard or the second node motherboard is working, while the other node is in a closed or not installed state. The working node is configured and confirmed through the third main control chip on the intermediate interconnect board, which can realize firmware upgrade, power management and configuration management of a single node.

[0150] Dual-node mode: The first node motherboard and the second node motherboard work simultaneously to achieve the following functions:

[0151] The two-way upgrade mechanism of the intermediate interconnect board: the first node motherboard upgrades the firmware of the third main control chip of the intermediate interconnect board through the first upgrade path, and the second node motherboard upgrades the firmware of the third main control chip of the intermediate interconnect board through the second upgrade path. The two upgrade paths are independent of each other, and either node can independently complete the firmware update operation of the third main control chip of the intermediate interconnect board. An arbitration mechanism is required here to avoid dual-node upgrade conflicts.

[0152] Cross-node power control mechanism: The first node motherboard sends power control commands to the second node motherboard via interconnection signals to perform power management operations such as power-on, power-off, and restart on the second node motherboard; the second node motherboard sends power control commands to the first node motherboard via interconnection signals to perform power management operations such as power-on, power-off, and restart on the first node motherboard.

[0153] In this embodiment, the maintainability and reliability between nodes in a traditional server architecture are insufficient. A single-node server typically only supports firmware upgrades for the main control chip, such as the CPLD, on a single board via a single path. In a dual-node configuration, if the main upgrade path fails, the main control chip on the interconnect board cannot complete the firmware update, affecting the maintainability and reliability of the system.

[0154] This embodiment enables a cross-node configuration management mechanism. The first node motherboard transmits configuration data and commands to the second node motherboard through the third main control chip on the intermediate interconnect board, thereby performing configuration management operations such as BIOS configuration, BMC configuration, and boot parameter settings on the second node motherboard. Correspondingly, the second node motherboard can also transmit configuration data and commands to the first node motherboard through the third main control chip on the intermediate interconnect board, thereby performing configuration management operations such as BIOS configuration, BMC configuration, and boot parameter settings on the first node motherboard.

[0155] Furthermore, the cross-node configuration management mechanism includes hardware-level configuration capabilities: the first baseboard management controller of the first node motherboard reads and writes the registers of the second master control chip of the second node motherboard via the I2C bus. The second master control chip of the second node motherboard is connected to the config strap pin of the second processor of the second node motherboard via GPIO signal lines. By controlling the GPIO signal level, it directly controls the CPU hardware configuration parameters, such as whether to configure it as a legacy CPU. Correspondingly, the second baseboard management controller of the second node motherboard can also control the config strap pin of the first processor of the first node motherboard through the same mechanism, using an arbitration mechanism to avoid configuration conflicts between nodes.

[0156] In summary, the dual-node motherboard can perform firmware upgrades on the intermediate interconnect board CPLD separately, the two nodes can control the power of the other node separately through the intermediate interconnect board CPLD, and the two nodes can configure the other node separately through the intermediate interconnect board CPLD.

[0157] Specifically, see Figure 6 , Figure 6 This is a schematic diagram of the multiplexing control architecture of the BIOS and BMC firmware SPI bus on the node motherboard. As can be seen, the core objective is to enable the CPU and BMC of the node motherboard to securely access the firmware Flash, perform dual Flash redundancy backup, and control firmware updates. All switching logic is uniformly arbitrated by the MB CPLD of the node motherboard.

[0158] In this architecture, the CPU of the node motherboard acts as the main processor, accessing the BIOS firmware Flash via the BIOS_SPI bus and receiving the STRAP_Signals boot configuration signal from the MB CPLD of the node motherboard. The BMC, as the baseboard management controller of the node motherboard, updates the firmware of the BIO SFlash via the BIOS_Update_SPI bus and accesses the BMC firmware BMC Flash via its own FW_SPI bus. Meanwhile, the MBP CPLD of the intermediate interconnecting motherboard outputs the MB_STRAP_Signals signal to provide the MB CPLD of the node motherboard with the basis for global boot configuration.

[0159] The entire SPI access link is time-division multiplexed through a multi-stage multiplexer (MUX): In the BIOS Flash access path, the first-stage MUX receives the CPU's normal access signal and the BMC's update signal, and after switching between two stages of MUX, it finally selects either BIOS FLASH0 or BIOS FLASH1; in the BMC Flash access path, the BMC's FW_SPI signal is switched between two stages of MUX, and finally selects either BMC FLASH0 or BMC FLASH1. The selection and enable signals (SEL & EN) of all MUXs are centrally controlled by the MB CPLD of the node motherboard to avoid bus conflicts.

[0160] This design achieves several key functions: First, both the BIOS and BMC employ dual Flash redundancy backups, allowing switching to the backup Flash in case of a primary Flash failure, preventing system boot failure or management function malfunction. Second, CPLD arbitration enables time-sharing access to the BIOS Flash by the CPU and BMC, supporting remote BIOS updates by the BMC while simultaneously cutting off CPU access during the update process to prevent system crashes. Third, two-level CPLDs jointly manage boot configuration signals, controlling the CPU's boot mode and boot address through hardware level control, providing a flexible and reliable boot control and fault recovery mechanism for the server platform.

[0161] In some embodiments, this application also provides a server, including the aforementioned server hardware circuitry.

[0162] In this embodiment, the server, through the server hardware circuit composed of the first node motherboard, the second node motherboard and the intermediate interconnect motherboard, can flexibly switch between single-node mode / dual-node mode and single-path mode / dual-path mode according to actual business needs, which greatly improves the adaptability and resource utilization of the server hardware and reduces the total cost of ownership of the data center.

[0163] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0164] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0165] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0166] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0167] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0168] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.

[0169] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A server hardware circuit, characterized in that, include: The first node motherboard includes a first processor, a first baseboard management controller, and a first main control chip. The second node motherboard includes a second processor, a second baseboard management controller, and a second main control chip; wherein, the second node motherboard is connected to the first node motherboard by a first bidirectional communication line. The intermediate interconnect motherboard includes a third main control chip, and the intermediate interconnect motherboard is connected to the first node motherboard and the second node motherboard by a second bidirectional communication line and a main power supply line.

2. The server hardware circuit according to claim 1, characterized in that, The first bidirectional communication line includes at least one of I2C signal line, LTPI signal line, and GPIO signal line, as well as a UPI signal line connecting the first processor and the second processor.

3. The server hardware circuit according to claim 1, characterized in that, The second bidirectional communication line includes at least one of I2C signal lines and GPIO signal lines.

4. The server hardware circuit according to any one of claims 1-3, characterized in that, An auxiliary power supply line connects the first node motherboard and the second node motherboard.

5. The server hardware circuit according to any one of claims 1-3, characterized in that, The processor is equipped with multiple memory interfaces and multiple I / O interfaces.

6. The server hardware circuit according to any one of claims 1-3, characterized in that, The first main control chip includes a first timing control unit and a first logic control unit, the second main control chip includes a second timing control unit and a second logic control unit, and the third main control chip includes a third timing control unit and a third logic control unit.

7. A mode control method for server hardware circuitry, characterized in that, The first node motherboard applied in the server hardware circuit as described in any one of claims 1-6 includes: Obtain the configuration mode input by the user; wherein, the configuration mode includes single-node mode, dual-node mode, single-path mode or dual-path mode; Based on the configuration mode, the working state of the second node motherboard in the server hardware circuit is dynamically switched.

8. The mode control method for server hardware circuits according to claim 7, characterized in that, Based on the configuration mode, dynamically switching the operating state of the second node motherboard in the server hardware circuit includes: If the configuration mode is a single-node mode or a single-path mode, the first bidirectional communication line between the first node motherboard and the second node motherboard is disconnected, and a power cut-off signal is sent to the intermediate interconnect motherboard in the server hardware circuit so that the intermediate interconnect motherboard disconnects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power cut-off signal. If the configuration mode is a dual-node mode, the first bidirectional communication line between the first node motherboard and the second node motherboard is disconnected, and a power connection signal is sent to the intermediate interconnect motherboard so that the intermediate interconnect motherboard connects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power connection signal. If the configuration mode is dual-path mode, then the first bidirectional communication line between the first node motherboard and the second node motherboard is connected, and a power connection signal is sent to the intermediate interconnect motherboard, so that the intermediate interconnect motherboard connects the main power line between the intermediate interconnect motherboard and the second node motherboard according to the power connection signal.

9. The mode control method for server hardware circuits according to claim 8, characterized in that, The method further includes: Obtain user-inputted operation information; wherein, the operation information includes upgrade information or configuration information; If the operation information is upgrade information, then an upgrade signal is sent to the intermediate interconnect motherboard to control the intermediate interconnect motherboard to perform an upgrade operation; If the operation information is configuration information, a configuration signal is sent to the intermediate interconnect motherboard so that the intermediate interconnect motherboard performs a configuration operation on the second node motherboard according to the configuration signal.

10. A server, characterized in that, Includes the server hardware circuitry as described in any one of claims 1-6.

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