A method, apparatus, and system for dynamic phase modulation of a photonic quantum chip.

Abstract

This invention proposes a dynamic phase modulation method, device, and system for optical quantum chips, comprising: receiving external instructions and parsing target parameters through a programmable logic device, converting the target parameters into digital control signals for corresponding channels; converting the digital control signals into analog excitation voltages using a high-precision digital-to-analog converter module; providing a deeply customized multi-channel low-power analog output system centered on an FPGA; strictly limiting the output power to the required range by configuring an independent high-precision, low-power DAC and output drive circuit for each channel, fundamentally eliminating power redundancy; and constructing a distributed waveform buffer and refresh network using the parallel processing capability and high-speed internal bus of the FPGA to ensure that all channels can update output values ​​synchronously and at high speed.

Description

Technical Field

[0001] This invention relates to the field of optical quantum chips, and more particularly to a method, apparatus, and system for dynamic phase modulation of optical quantum chips. Background Technology

[0002] In optical quantum computers based on integrated photonics, the manipulation of qubits (usually encoded in the patterns of photon paths, polarization, etc.), such as single-qubit gates and two-qubit gates, is often achieved through on-chip electro-optic modulators (such as Mach-Zehnder interferometer structures). By applying precise voltages or currents to these modulators, the phase of the light wave can be dynamically changed, thereby completing specific quantum gate operations. Currently, the industry typically uses commercial benchtop or modular programmable power supplies to drive single or a small number of modulators.

[0003] Existing devices of this type have the following drawbacks in the gating operation of photons: 1) Low channel density: A single device typically has only 1-4 channels. To drive an 8-mode quantum chip (8 modes require approximately 64 control channels), dozens or even hundreds of devices are needed, resulting in an extremely bloated system, high cost, and complex synchronization.

[0004] 2) Severe power redundancy: Optical quantum modulators are usually high-impedance capacitive loads, requiring very little drive power (less than 250mW), while traditional programmable power supplies are designed for general testing and often have an output power of tens of watts, resulting in huge energy waste and unnecessary thermal management problems.

[0005] 3) Limited refresh rate: Its communication interface and internal architecture are not designed for extremely high-speed sequential waveform refresh, resulting in insufficient real-time performance in applications that require rapid switching of a large number of channel voltages.

[0006] Therefore, a dynamic phase modulation method, device, and system for optical quantum chips are proposed to solve the above problems. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the defects of the existing technology. The present invention proposes a method, device and system for dynamic phase modulation of optical quantum chips.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a method for dynamic phase modulation of an optical quantum chip, comprising: The programmable logic device receives external instructions and parses them to obtain target parameters, which are then converted into digital control signals for the corresponding channels. The digital control signal is converted into an analog excitation voltage using a high-precision digital-to-analog converter module. The analog excitation voltage is then scaled and amplified in a closed loop according to a preset working mode by a voltage drive module or a current drive module to generate a control signal with a rated output power of less than or equal to 250mW, which is then applied to the modulator of the photonic quantum chip. The output status value of the control signal is acquired in real time, and the digital control signal output by the programmable logic device is dynamically adjusted according to the deviation between the output status value and the target parameter using a PID algorithm to compensate for the output fluctuation caused by circuit temperature drift and ensure that the phase control accuracy of the control signal is maintained at a refresh rate of not less than 10kHz.

[0009] Preferably, in constant current mode, the voltage drive module or current drive module controls the multiplexer through configuration pins to switch the analog excitation voltage to the current scaling circuit, and sends the scaled target voltage to the positive input terminal of the operational amplifier. The operational amplifier controls the power transistor to generate an output current that flows through a precision sampling resistor. The precision sampling resistor generates a feedback voltage that is connected to the negative input terminal of the operational amplifier. Through a high-gain closed-loop state, the feedback voltage is locked to the target voltage.

[0010] Preferably, in constant voltage mode, the voltage drive module or current drive module adjusts the analog excitation voltage through a voltage scaling circuit and drives the output voltage of the internally integrated power operational amplifier; The feedback voltage at the positive terminal of the load is led back to the feedback node of the power operational amplifier using a Kelvin connection, and the power operational amplifier dynamically compensates for the voltage drop caused by the resistance of the wires.

[0011] Preferably, the real-time acquisition of the output state value of the control signal includes: When the output voltage is constant, the output voltage is divided by a proportional resistor and then sent to the analog-to-digital converter module after passing through an impedance transformation operational amplifier. During constant current output, the current is converted into a voltage drop signal by a high-precision shunt resistor connected in series in the output circuit. The voltage drop signal is then amplified by a current sense amplifier with an input bias current of less than 10nA and sent to the analog-to-digital conversion module.

[0012] Preferably, the programmable logic device utilizes an external cache and employs a ping-pong cache structure or a circular cache structure to store the quantum gate operation waveform sequence, ensuring that no output interruption occurs when continuously updating output data.

[0013] Preferably, the total time consumed by the adjustment cycle and signal retrieval cycle of the PID algorithm is controlled within 100μs. The proportional element quickly reflects the deviation, the integral element eliminates the static error, and the derivative element predicts the trend of change, so that the error between the output parameter and the set parameter is controlled within 0.1%.

[0014] Secondly, a dynamic phase modulation device for a photonic quantum chip. A motherboard, wherein a high-speed communication interface and the programmable logic device are provided on the motherboard; At least one set of daughter boards, which are interconnected with the mother board via board-to-board connectors; The subboard integrates the high-precision digital-to-analog converter module, voltage drive module, current drive module, and analog-to-digital converter module, providing at least 64 independent control channels.

[0015] Thirdly, a dynamic phase modulation system for a photonic quantum chip. A programmable logic module is used to parse external instructions to obtain target parameters and convert the target parameters into digital control signals; A high-precision digital-to-analog converter module, connected to the programmable logic module, is used to convert the digital control signal into an analog excitation voltage; The driving module, connected to the high-precision digital-to-analog converter module, is used to scale the analog excitation voltage and amplify its power in a closed loop according to a preset working mode, so as to generate a control signal with a rated output power of less than or equal to 250mW, and apply the control signal to the modulator of the photonic quantum chip. A real-time acquisition module is connected to the output terminal of the drive module and is used to acquire the output status value of the control signal; The programmable logic module uses a PID algorithm to dynamically adjust the digital control signal based on the deviation between the output state value and the target parameter, in order to compensate for the output fluctuations caused by circuit temperature drift and maintain the phase control accuracy of the control signal at a refresh rate of not less than 10kHz.

[0016] Fourthly, an electronic device comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the dynamic phase modulation method of the optical quantum chip.

[0017] Fifthly, a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the dynamic phase modulation method for the optical quantum chip.

[0018] Compared with existing technologies, the beneficial effects of this invention include: abandoning the general high-power programmable power supply architecture and instead designing a deeply customized multi-channel low-power analog output system centered on an FPGA; by configuring each channel with an independent high-precision, low-power DAC and output driver circuit, the output power is strictly limited to the required range (e.g., within 250mW), fundamentally eliminating power redundancy; and utilizing the parallel processing capabilities and high-speed internal bus of the FPGA to construct a distributed waveform buffer and refresh network, ensuring that all channels can update output values ​​synchronously and at high speed. Attached Figure Description

[0019] The disclosure of this invention is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this invention. In the drawings, the same reference numerals are used to refer to the same parts. Wherein: Figure 1 A flowchart of a dynamic phase modulation method for an optical quantum chip provided in this application embodiment; Figure 2 The system architecture and interconnection block diagram provided for the embodiments of this application; Figure 3 The schematic diagram illustrates the motherboard hardware architecture according to the present invention.

[0020] Figure 4 The schematic diagram illustrates the hardware architecture of the sub-board according to the present invention.

[0021] Figure 5 A schematic diagram of a voltage / current driver circuit according to the present invention is shown.

[0022] Figure 6 The schematic diagram illustrates the output retrieval circuit diagram according to the present invention.

[0023] Figure 7 A schematic diagram of the dynamic phase modulation system of the optical quantum chip according to the present invention is shown.

[0024] Figure 8 A flowchart illustrating the process according to the present invention is shown schematically.

[0025] Figure 9 The diagram illustrates an electronic device schematic of the dynamic phase modulation method, apparatus, and system of the photonic quantum chip according to the present invention. Detailed Implementation

[0026] It is readily understood that, based on the technical solution of this invention, those skilled in the art can propose various interchangeable structural methods and implementations without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention.

[0027] Example 1, referring to Figures 1-4 As one embodiment of the present invention, a dynamic phase modulation method for an optical quantum chip is provided, comprising: S100: Receives external instructions through a programmable logic device, parses and obtains the target parameters, and converts the target parameters into digital control signals for the corresponding channel; S200: A high-precision digital-to-analog converter module converts digital control signals into analog excitation voltages. The voltage drive module or current drive module performs range scaling and closed-loop power amplification of the analog excitation voltages according to a preset working mode to generate a control signal with a rated output power of less than or equal to 250mW, which is then applied to the modulator of the photonic quantum chip. S300: Real-time acquisition of the output status value of the control signal, and dynamic adjustment of the digital control signal output by the programmable logic device based on the deviation between the output status value and the target parameter using a PID algorithm, in order to compensate for the output fluctuation caused by circuit temperature drift and ensure that the phase control accuracy of the control signal is maintained at a refresh rate of not less than 10kHz.

[0028] As can be imagined, to address the unavoidable temperature drift phenomenon during long-term circuit operation, the system constructs a real-time calibration mechanism based on state observation. By acquiring the actual output state value of the control signal at the modulator load in real time, and using an improved PID compensation algorithm to calculate the dynamic deviation between the output state value and the preset target parameter, since the integral part in the PID algorithm can effectively absorb the resistance shift caused by temperature rise, the system provides real-time feedback based on the deviation and dynamically fine-tunes the digital control flow output by the system-on-a-chip. This closed-loop correction logic is implemented at the hardware level through a pipeline accelerator, thereby ensuring that at an ultra-high refresh rate of no less than 10kHz, the interference of environmental thermal noise on the phase control accuracy is offset, so that the photonic quantum chip is always maintained in the preset quantum interference state.

[0029] By integrating programmable logic devices and high-precision digital-to-analog converter logic, the system achieves coordinated parallel output of multi-channel signals, significantly improving the integration density of the control link. Utilizing a driver module to scale the analog excitation voltage and perform closed-loop power amplification, coupled with a safety threshold limit for rated output power, ensures sufficient excitation energy for the modulator while effectively avoiding thermal damage to micro / nano structures caused by transient overload, enhancing the system's physical robustness. In particular, by introducing real-time acquisition with a refresh rate of at least 10kHz and a PID dynamic feedback mechanism, the system can instantly capture and negatively compensate for resistance shifts and gain temperature drift caused by electronic component heating during long-term circuit operation. This dynamic self-healing capability allows the output signal to cancel phase disturbances caused by environmental thermal noise in real time, fundamentally solving the problem of irreversible drift in phase control accuracy over time in existing technologies, and ensuring the long-term evolution stability of quantum gate operations under high-fidelity requirements.

[0030] Example 2, refer to Figures 1-6 As an embodiment of the present invention, a dynamic phase modulation method for optical quantum chips is provided based on the above embodiment.

[0031] S200: A high-precision digital-to-analog converter module converts digital control signals into analog excitation voltages. The voltage drive module or current drive module performs range scaling and closed-loop power amplification of the analog excitation voltages according to a preset working mode to generate a control signal with a rated output power of less than or equal to 250mW, which is then applied to the modulator of the photonic quantum chip. S201: In constant current mode, the voltage drive module or current drive module controls the multiplexer through the configuration pin to switch the analog excitation voltage to the current scaling circuit, and sends the scaled target voltage to the positive input terminal of the operational amplifier. The operational amplifier controls the power transistor to generate an output current that flows through a precision sampling resistor. The precision sampling resistor generates a feedback voltage that is connected to the negative input terminal of the operational amplifier. Through a high-gain closed-loop state, the feedback voltage is locked to the target voltage.

[0032] S202: In constant voltage mode, the voltage drive module or current drive module adjusts the analog excitation voltage through the voltage scaling circuit and drives the output voltage of the internally integrated power operational amplifier. The feedback voltage at the positive terminal of the load is fed back to the feedback node of the power operational amplifier using a Kelvin connection, and the power operational amplifier dynamically compensates for the voltage drop caused by the resistance of the wires.

[0033] S300: Real-time acquisition of the output status value of the control signal, and dynamic adjustment of the digital control signal output by the programmable logic device based on the deviation between the output status value and the target parameter using a PID algorithm, in order to compensate for the output fluctuation caused by circuit temperature drift and ensure that the phase control accuracy of the control signal is maintained at a refresh rate of not less than 10kHz.

[0034] S301: The output status values ​​of the real-time acquisition and control signals include: When the output voltage is constant, the output voltage is divided by a proportional resistor and then sent to the analog-to-digital converter module after passing through an impedance transformation operational amplifier. During constant current output, the current is converted into a voltage drop signal by a high-precision shunt resistor connected in series in the output circuit. The voltage drop signal is then amplified by a current sense amplifier with an input bias current of less than 10nA and sent to the analog-to-digital converter module.

[0035] S302: Programmable logic devices utilize external caches and employ ping-pong or circular cache structures to store quantum gate operation waveform sequences, ensuring that no output interruption occurs during continuous updates of output data.

[0036] S303: The total time consumed by the adjustment cycle and signal retrieval cycle of the PID algorithm is controlled within 100μs. The proportional element quickly reflects the deviation, the integral element eliminates the static error, and the derivative element predicts the trend of change, so that the error between the output parameter and the set parameter is controlled within 0.1%.

[0037] PID control algorithms are widely used in industrial control systems, such as temperature control, speed control, and position control. They can precisely regulate the control system by adjusting the PID parameters (proportional coefficient, integral time constant, and derivative time constant) according to the system's characteristics and requirements. The PID algorithm consists of three main parts: proportional (P), integral (I), and derivative (D).

[0038] Proportional link (P): It directly amplifies the current control deviation proportionally, which can quickly reflect the deviation and reduce the error, but cannot completely eliminate static error.

[0039] Integrating element (I): It integrates the deviation over all past time periods, which can eliminate static error, but may cause overshoot and oscillation.

[0040] Differential element (D): It predicts and adjusts based on the changing trend of the deviation, which can speed up the system's response and reduce overshoot.

[0041] The PID calculation formula is as follows: The PID algorithm intervenes twice, requiring two data conversions from ADC to DAC, with a total time consumption of (14.2 + 3.56) * 2 = 33.52 μs.

[0042] Therefore, from the time the host computer issues the command to the time the PID algorithm completes calibration and outputs the result, the total time is 6.9 + 20.5 + 2.56 + 33.52 = 63.48us < 100us, which meets the minimum 10K refresh rate requirement.

[0043] As can be conceivable, to address the unavoidable electronic temperature drift during long-term circuit operation, the system's PID algorithm strictly locks the total time of the adjustment cycle and signal retrieval cycle to within 100μs. According to physical test analysis, the time from the host computer issuing the command to the completion of command parsing is approximately 6.9μs; the total time for motherboard forwarding, daughterboard execution, and DAC establishment is approximately 34.26µs; combined with the 33.52µs time for ADC conversion and secondary PID adjustment, the total closed-loop time is approximately 63.48μs. Since this time is far less than the 100μs threshold, the system can perform compensation actions at a physical refresh rate of at least 10kHz. Through the rapid response of the proportional element to deviations, the cumulative elimination of static errors caused by temperature drift by the integral element, and the advanced prediction of voltage change trends by the derivative element, the system ultimately keeps the physical error between the output parameters and the set parameters constant within 0.1%, thereby achieving ultra-high precision dynamic control of the phase of the quantum chip on a macroscopic level.

[0044] By introducing constant current and constant voltage dual-mode driving logic, and combining it with Kelvin connection method and high-gain closed-loop feedback structure, real-time sensing and dynamic compensation of the voltage drop across the transmission line resistance are achieved. This ensures that the physical energy acting on the modulator end of the optical quantum chip is highly consistent with the preset target value. The differentiated sampling path constructed using high impedance buffer and low bias current detection technology effectively avoids the shunt interference generated by the sampling circuit on the main driving circuit, while obtaining a feedback signal with an extremely high signal-to-noise ratio. This significantly improves the system's sensitivity to temperature drift fluctuations. The use of a ping-pong or circular buffer architecture to store waveform sequences eliminates logical gaps in the data update process, ensuring the physical continuity of the quantum gate operation instruction stream. Combined with rigorously time-optimized hardware-level computing logic, the total time consumption of the closed-loop feedback link is compressed to less than 100 microseconds. This ensures that the system can adaptively and self-repair environmental thermal noise in a high-speed refresh state, ultimately keeping the output deviation constantly controlled at an extremely low level. This significantly enhances the determinism and phase fidelity in the optical quantum control process.

[0045] Example 3, referring to Figures 1-7 As an embodiment of the present invention, a dynamic phase modulation device for a photonic quantum chip is provided based on the above embodiment.

[0046] A dynamic phase modulation device for a photonic quantum chip, comprising, A motherboard, wherein a high-speed communication interface and the programmable logic device are provided on the motherboard; At least one set of daughter boards, which are interconnected with the mother board via board-to-board connectors; The subboard integrates the high-precision digital-to-analog converter module, voltage drive module, current drive module, and analog-to-digital converter module, providing at least 64 independent control channels.

[0047] As one might imagine, in order to achieve linear expansion of large-scale phase modulation channels within a limited physical space, the motherboard establishes a high-speed electrical connection with at least one set of daughterboards through board-to-board connectors with high signal integrity. This hardware decoupling design not only enhances the physical maintainability of the system, but more importantly, through the compact arrangement of board-to-board connectors and differential impedance matching design, it ensures the phase synchronization and extremely low transmission delay of multiple high-frequency control signals during cross-board transmission, thus laying the physical foundation for multi-mode coherent optical field modulation.

[0048] refer to Figure 3 The daughterboard includes a DAC, voltage and current drivers, voltage processing circuits, current processing circuits, and an ADC. The FPGA outputs digital control signals. After receiving these digital signals, the DAC converts them into weak analog voltage signals. The voltage and current drivers amplify the weak analog signals output by the DAC to give them sufficient driving capability, thereby generating output voltage and current signals that actually act on the load.

[0049] Inside the voltage and current processing circuits, the powerful output signal is sampled and divided to be proportionally reduced to a small analog quantity suitable for monitoring, so that the system can observe the output status in real time. These reduced analog quantities are then converted back into digital codes after entering the ADC.

[0050] The digital signal output by the ADC enters the FPGA, allowing the system to compare the actual output value with the initially set target value in real time. Through this closed-loop feedback mechanism, the FPGA can automatically correct the output command based on the difference, ensuring that the output voltage or current can maintain extremely high accuracy and stability under load changes or environmental interference.

[0051] Through a modular construction that decouples the motherboard and daughterboard, coupled with the electrical interconnection of high-speed communication interfaces and board-to-board connectors, physical isolation between control logic and drive execution is achieved. This significantly reduces electromagnetic interference from high-frequency digital signals to the analog drive link. Utilizing programmable logic devices as the core scheduling hub, along with highly integrated digital-to-analog converters, dual-mode drives, and feedback acquisition modules on a single daughterboard, the system can provide at least 64 independent control channels within a compact hardware space. This greatly improves the channel coverage density for multi-mode optical quantum chips. This distributed expansion architecture not only solves the bottleneck of limited channel size in traditional devices through physical-level parallel processing but also ensures the timing synchronization of multiple phase control signals through board-to-board connectors. This provides highly reliable and linearly scalable hardware support for large-scale quantum gate operations, significantly reducing the deployment complexity and maintenance costs of the experimental system.

[0052] Example 4, refer to Figures 1-7 As an embodiment of the present invention, a dynamic phase modulation system for an optical quantum chip is provided based on the above embodiment.

[0053] A dynamic phase modulation system for an optical quantum chip includes, A programmable logic module is used to parse external instructions to obtain target parameters and convert the target parameters into digital control signals; A high-precision digital-to-analog converter module, connected to the programmable logic module, is used to convert the digital control signal into an analog excitation voltage; The driving module, connected to the high-precision digital-to-analog converter module, is used to scale the analog excitation voltage and amplify its power in a closed loop according to a preset working mode, so as to generate a control signal with a rated output power of less than or equal to 250mW, and apply the control signal to the modulator of the photonic quantum chip. A real-time acquisition module is connected to the output terminal of the drive module and is used to acquire the output status value of the control signal; The programmable logic module uses a PID algorithm to dynamically adjust the digital control signal based on the deviation between the output state value and the target parameter, in order to compensate for the output fluctuations caused by circuit temperature drift and maintain the phase control accuracy of the control signal at a refresh rate of not less than 10kHz.

[0054] like Figure 4 This solution selects a low-power voltage / current drive circuit, with a maximum output current of 24mA and a maximum voltage of 12V, which meets the current driving requirements of quantum gates. The driver's VIN pin is connected to the output of the DAC, and its accuracy is determined by the DAC. The FPGA controls the multiplexer through configuration pins to switch the VIN voltage input to the corresponding range scaling circuit, adjusting the VIN voltage value proportionally to achieve the target V. TARGETSince VREF=4.096V and the maximum current is 24mA, in current output mode, This V TARGET The current I is fed into the positive input terminal of op-amp A1, and the output current is... OUT The current flows out from the drain of power transistor T2, passes through precision sampling resistor R3, and generates a signal similar to I. OUT Proportional feedback voltage V FB V FB =I OUT *R3, V FB Connecting to the negative input terminal of op-amp A1, op-amp A1 operates in a high-gain closed-loop state, continuously converting the V at the positive input terminal... TARGET V with negative input terminal FB By comparing and amplifying the difference between the two (i.e., the error voltage), A1 drives I by controlling T1 and T2 (transistor T1 is a small-signal transistor, and T2 is the power transistor for the final output current). OUT The change ultimately led to V FB Infinitely close to V TARGET This causes the error voltage to approach zero, V FB =V TARGET When the system reaches a steady state, V TARGET =V FB =I OUT ×R3, the output current is precisely locked to Output current I OUT With input command voltage V TARGET It exhibits a perfect linear relationship. The proportionality coefficient is the reciprocal of the sampling resistor R3. R3 uses a precision, low-temperature-drift thin-film resistor, thus ensuring high accuracy and high stability throughout the conversion process.

[0055] In constant voltage output mode, the FPGA switches the VIN input to a voltage scaling circuit, adjusting the VIN voltage value proportionally to achieve the target V. TARGET Because the maximum output voltage is 12V, The adjusted voltage drives an internally integrated power operational amplifier with a high output voltage swing, capable of outputting up to 12V (or higher, depending on the supply), and a high output current capability, allowing it to directly drive certain loads (e.g., ≥1kΩ). Its output is directly connected to the chip's V... OUT Pin. When the output current (I OUT When the resistance is large, the resistance R of the wire between the chip pin and the load is... WIRE This will cause a voltage drop, which will affect the load (R) LOAD The actual voltage across the terminals is lower than that of the chip V. OUT The voltage measured at the pin causes system errors. Connect the VSENSE+ pin directly to the load R using a separate wire.LOAD The positive terminal of the chip, along with the internal power amplifier, forms a closed-loop negative feedback system, but its feedback node is not taken from V. OUT Instead of using a separate pin, the power op-amp is taken from the VSENSE+ pin, allowing for dynamic adjustment of V. OUT The voltage at the pin is maintained until the voltage at the VSENSE+ pin is exactly equal to the target voltage V. TARGET .

[0056] Quantum gates operate in either constant current or constant voltage mode, so the voltage and current output channels can be shorted together, saving physical channels in the connector and making it easier for users to operate.

[0057] like Figure 5 The PID algorithm requires real-time reading and calibration of the voltage / current driver output. Therefore, it needs to sample the output and upload the output status to the FPGA in real time for PID calibration. Figure 5 It is a sampling and processing circuit that samples the output states of voltage and current respectively.

[0058] When outputting a constant voltage, to ensure that the signal input to the ADC chip is within its dynamic range of 0 to VREF, amplitude adjustment is required to ensure that the 12V voltage corresponds to the VREF value. Therefore, the circuit needs to add a proportional resistor for voltage division to maximize the voltage input to the ADC. The ratio of the voltage divider resistors is calculated. After passing through the voltage divider resistors, the signal is then passed through an operational amplifier (op-amp) for impedance transformation to reduce the impact of the ADC on the output voltage. The op-amp has a high input impedance (>5MΩ), so its impact is negligible for loads around 1KΩ. Pay attention to the selection of key op-amp parameters. The system output signal change rate is required to be greater than 10KHz, so the bandwidth-gain product should be greater than 1MHz to ensure complete and effective acquisition of the signal. Also, considering that the signal can be established quickly at full output (<1us), its slew rate parameter should be greater than 5V / us. In addition, it is necessary to select op-amps with low noise and low distortion parameters.

[0059] When outputting a constant current, the ADC cannot directly sample and quantize the current; it needs to convert the current value into a voltage value. According to Ohm's law, a voltage will be generated when current flows through a resistor. Therefore, in I... OUTA high-precision resistor RSHUNT (R4 in the diagram) is connected in series at the output. Current flowing through R4 generates a voltage drop VDO, converting the current value to a voltage value. While the series resistor has little impact on the target output current, if the resistor value is too large, the voltage / current driver will require a higher output voltage, exceeding its maximum output voltage. In this solution, the maximum voltage of the voltage / current driver is 12V. Considering the size, power, and accuracy of RSHUNT, the resistance of RSHUNT is kept within ten ohms. This results in a relatively small VDO voltage on RSHUNT, insufficient for direct ADC quantization. Therefore, a dedicated current-sensing amplifier is added to amplify the signal. The maximum resistance of RSHUNT is calculated by working backward from the maximum current. Due to the worst-case swing of the current-sensing amplifier to the voltage rail limitation, a maximum output of 4.9V can be achieved with a 5V supply. Therefore, for a target maximum current of 24mA, the amplifier gain is 25V / V. The resistance value is typically around 7.5Ω, and can be flexibly selected based on parameters such as the system's maximum current, amplifier gain, and voltage rail. The design must accommodate a detection range from microamps to milliamps, necessitating consideration of the amplifier's input bias current. This current ultimately flows through the shunt resistor and into the amplifier's IN- terminal. Therefore, only amplifiers with input bias currents significantly smaller than the required minimum measurement point can be used. For designs requiring microamp current measurements, a bias current less than 10nA is preferable to minimize the impact of this error in low-range measurements.

[0060] When the system is working, the current working state is clearly known. Therefore, in constant voltage mode, the FPGA will process the data of channel 1, and in constant current mode, it will process the data of channel 2.

[0061] Example 5, refer to Figures 1-9 This is one embodiment of the present invention.

[0062] Using a standard 19-inch chassis, it connects to the host computer via USB 3.0. Based on the 1U chassis size, a single daughterboard supports 64 output channels, and the motherboard supports 8 daughterboards, so the total number of channels supported is 512. If more power channels are needed, they can be expanded by cascading the chassis. For example, cascading two chassis can achieve 1024 power channels.

[0063] The host computer transmits data in 40-bit frames, including an 8-bit daughterboard ID, an 8-bit channel, 16 bits of data, and an 8-bit checksum. Assuming a USB 3.0 speed of 3Gbps, the time for the host computer to send data is... Motherboard FPGA parsing and forwarding time to daughterboard: One frame is 32 bits, including 8 bits of channel, 16 bits of data, and 8 bits of checksum. The LVDS interface rate is configured to 100Mbps, and the time to complete 64-channel data transmission is... For the FPGA execution time on the daughterboard, the DAC communication uses the SPI interface with a clock speed of 50Mbps. The DAC has 8 channels and requires 8 * 0.32 = 2.56 µs. The other SPI groups are independent interfaces and are processed in parallel by the FPGA.

[0064] If the DAC slew rate is 2V / μs and VREF is the full-scale voltage, then the full-scale output voltage time is... The internal settling time is 5µs, and the total time is approximately 7µs. The output settling time of the voltage / current drive circuit is 5µs. The op-amp's slew rate is selected as 10V / μs (an external op-amp can be flexibly selected with higher specifications according to system requirements). The full-amplitude output voltage is 12V, and the full-amplitude output voltage time is... The total time taken is 6.2us, so the maximum time from the DAC output to the drive voltage / current output is 7 + 6.2 = 14.2us.

[0065] The selected ADC parameters are 18-bit resolution, 2 channels, 1 MSPS / Ch, data acquisition period of 1µs, and data transmission time. The total time taken was 3.56us.

[0066] The workflow is as follows: 1. Initialization and Loading: After the system is powered on, the hardware devices are initialized, a full-channel automatic calibration is performed, and an initial calibration table is established.

[0067] 2. The software enters loop mode to check if there is any data.

[0068] 3. When the host computer sends refresh rate, target voltage, target current, and quantum gate operation waveform sequence data frames according to the protocol, the software enters interrupt mode, receives the data frames, and parses them to check if they are normal. If an error is found, the interrupt routine exits and continues to wait.

[0069] 4. Set voltage or voltage waveform sequence: When the data is parsed correctly, the voltage value is converted into a hexadecimal number and the DAC output voltage is controlled through the SPI interface. At the same time, the voltage / current driver is configured to voltage mode and the output refresh rate is set.

[0070] 5. Fine-tune the voltage: Read the voltage of the voltage driver through the ADC and fine-tune the output voltage to meet the target voltage requirement.

[0071] 6. Set the current value or current waveform sequence. Then convert the current value to a hexadecimal number and control the DAC output voltage through the SPI interface. At the same time, configure the voltage / current driver to current mode and the output refresh rate.

[0072] 7. Read the current value. The current sensor converts the output current into voltage, and the voltage value is read through the ADC.

[0073] 8. Fine-tune the current value. Fine-tune the output current to meet the target current requirement; 9. Repeat until the voltage and current settings for all channels are complete, then exit the loop. This embodiment also provides a schematic diagram of an electronic device structure for a dynamic phase modulation method, apparatus, and system for a quantum chip. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and its… The functions described herein are merely illustrative and are not intended to limit the implementation of the invention as described and / or claimed herein.

[0074] Electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0075] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication... Communication unit 19, such as a network interface card (NIC), modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0076] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as a... Methods, devices, and systems for dynamic phase modulation of optical quantum chips.

[0077] In some embodiments, the dynamic phase modulation method, apparatus, and system for a quantum optical chip can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the dynamic phase modulation method, apparatus, and system for a quantum optical chip described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the dynamic phase modulation method, apparatus, and system for a quantum optical chip by any other suitable means (e.g., by means of firmware).

[0078] The various implementations of the systems and technologies described above in this article can be applied to digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and systems-on-chips. The implementation may be carried out in a system of components (SOC), a load-programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementation in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0079] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0080] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable memory (EPM), and other similar media. Read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

[0081] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or an LCD (liquid crystal display) for displaying information to the user. The device includes a monitor and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback); and input from the user can be received in any form (including voice input, speech input, or haptic input).

[0082] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0083] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0084] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0085] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for dynamic phase modulation of an optical quantum chip, characterized in that, include: The programmable logic device receives external instructions and parses them to obtain target parameters, which are then converted into digital control signals for the corresponding channels. The digital control signal is converted into an analog excitation voltage using a high-precision digital-to-analog converter module. The analog excitation voltage is then scaled and amplified in a closed loop according to a preset working mode by a voltage drive module or a current drive module to generate a constant voltage or constant current control signal that acts on the modulator of the photonic quantum chip. The output status value of the control signal is acquired in real time, and the digital control signal output by the programmable logic device is dynamically adjusted according to the deviation between the output status value and the target parameter using a PID algorithm to compensate for the output fluctuation caused by circuit temperature drift and ensure that the phase control accuracy of the control signal is maintained under high refresh rate conditions.

2. The dynamic phase modulation method for a quantum chip according to claim 1, characterized in that, In constant current mode, the voltage drive module or current drive module controls the multiplexer through configuration pins to switch the analog excitation voltage to the current scaling circuit, and sends the scaled target voltage to the positive input terminal of the operational amplifier. The operational amplifier controls the power transistor to generate an output current that flows through a precision sampling resistor. The precision sampling resistor generates a feedback voltage that is connected to the negative input terminal of the operational amplifier. Through a high-gain closed-loop state, the feedback voltage is locked to the target voltage.

3. The dynamic phase modulation method for a quantum chip according to claim 1, characterized in that, In constant voltage mode, the voltage drive module or current drive module adjusts the analog excitation voltage through a voltage scaling circuit and drives the internally integrated power operational amplifier to output voltage. The feedback voltage at the positive terminal of the load is led back to the feedback node of the power operational amplifier using a Kelvin connection, and the power operational amplifier dynamically compensates for the voltage drop caused by the resistance of the wires.

4. The dynamic phase modulation method for a quantum chip according to claim 1, characterized in that, Real-time acquisition of the output state values ​​of the control signal includes: When the output voltage is constant, the output voltage is divided by a proportional resistor and then sent to the analog-to-digital converter module after passing through an impedance transformation operational amplifier. During constant current output, the current is converted into a voltage drop signal by a high-precision shunt resistor connected in series in the output circuit. The voltage drop signal is then amplified by a current sense amplifier with an input bias current of less than 10nA and sent to the analog-to-digital conversion module.

5. The dynamic phase modulation method for a quantum chip according to claim 4, characterized in that, The programmable logic device utilizes an external cache and employs a ping-pong cache structure or a circular cache structure to store the quantum gate operation waveform sequence, ensuring that no output interruption occurs when continuously updating output data.

6. The dynamic phase modulation method for a quantum chip according to claim 1, characterized in that, The total time consumed by the adjustment cycle and signal retrieval cycle of the PID algorithm is controlled within 100μs. The proportional element quickly reflects the deviation, the integral element eliminates the static error, and the derivative element predicts the trend of change, so that the error between the output parameter and the set parameter is controlled within 0.1%.

7. A dynamic phase modulation device for a photonic quantum chip, used to execute the dynamic phase modulation method for a photonic quantum chip according to any one of claims 1-6, characterized in that, include: A motherboard, wherein a high-speed communication interface and the programmable logic device are provided on the motherboard; At least one set of daughter boards, which are interconnected with the mother board via board-to-board connectors; The subboard integrates the high-precision digital-to-analog converter module, voltage drive module, current drive module, and analog-to-digital converter module, providing at least 64 independent control channels.

8. A dynamic phase modulation system for a photonic quantum chip, used to execute the dynamic phase modulation method for the photonic quantum chip according to any one of claims 1-6, characterized in that, include: A programmable logic module is used to parse external instructions to obtain target parameters and convert the target parameters into digital control signals; A high-precision digital-to-analog converter module, connected to the programmable logic module, is used to convert the digital control signal into an analog excitation voltage; The driving module, connected to the high-precision digital-to-analog converter module, is used to scale the analog excitation voltage and amplify its power in a closed loop according to a preset working mode, so as to generate a control signal with a rated output power of less than or equal to 250mW, and apply the control signal to the modulator of the photonic quantum chip. A real-time acquisition module is connected to the output terminal of the drive module and is used to acquire the output status value of the control signal; The programmable logic module uses a PID algorithm to dynamically adjust the digital control signal based on the deviation between the output state value and the target parameter, in order to compensate for the output fluctuations caused by circuit temperature drift and maintain the phase control accuracy of the control signal at a refresh rate of not less than 10kHz.

9. An electronic device, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the steps of the dynamic phase modulation method of the optical quantum chip according to any one of claims 1 to 6.

10. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the dynamic phase modulation method of the photonic quantum chip according to any one of claims 1 to 6.

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