Transmit driver and electronic device comprising a transmit driver

Abstract

A transmit driver and electronic devices including the transmit driver are provided. The transmit driver includes multiple stages. Each stage includes: an input circuit that transmits an input signal to a first node in response to a first clock signal; a node separation circuit connected between the first and second nodes and receiving a low gate voltage; a node control circuit that controls the voltage of a third node based on the voltage of the first node, a high gate voltage, and a low gate voltage; and an output circuit that outputs a high gate voltage as a transmit signal in response to the voltage of the third node, outputs a low gate voltage as a transmit signal in response to the voltage of the second node in a first mode, and outputs a second clock signal as a transmit signal in response to the voltage of the second node in a second mode.

Description

Technical Field

[0001] The embodiments generally relate to display devices, and more specifically to transmitter drivers and electronic devices including transmitter drivers. Background Technology

[0002] The display device may include: a display panel comprising multiple pixels, a data driver providing data signals to the multiple pixels, a scan driver providing scan signals to the multiple pixels, a transmit driver providing emission signals to the multiple pixels, and a controller controlling the data driver, the scan driver, and the transmit driver. The multiple pixels may emit light in response to the emission signals generated by the transmit driver.

[0003] To adjust the dimming level (or luminance level) of a display device, a dimming technique is being developed that adjusts the duration of the emission period for each pixel within each frame period. To achieve this dimming technique, the emission driver can adjust the duration of the on-time (e.g., low-period) of the emitted signal based on the display brightness value (“DBV”). Summary of the Invention

[0004] However, conventional transmit drivers may not be able to adjust the duration of the transmit signal conduction period to be less than two horizontal time intervals, and therefore may not be suitable for low brightness modes where the required transmit period duration is less than one horizontal time interval.

[0005] Some embodiments provide an emission driver suitable for both high brightness mode and low brightness mode.

[0006] Some embodiments provide electronic devices that include emission drivers suitable for both high-brightness and low-brightness modes.

[0007] In embodiments of this disclosure, a transmit driver comprising multiple stages is provided. At least one of the multiple stages includes: an input circuit that transmits an input signal to a first node in response to a first clock signal; a node separation circuit connected between the first node and a second node and receiving a low gate voltage having a first voltage level; a node control circuit that controls the voltage of a third node based on the voltage of the first node, a high gate voltage having a second voltage level higher than the first voltage level, and a low gate voltage; and an output circuit that outputs a high gate voltage as a transmit signal in response to the voltage of the third node, outputs a low gate voltage as a transmit signal in response to the voltage of the second node in a first mode, and outputs a second clock signal different from the first clock signal as a transmit signal in response to the voltage of the second node in a second mode.

[0008] In an embodiment, the output circuit can output a transmission signal having a low period of transmission with a transmission signal having a first voltage level that is longer than or equal to two horizontal time periods in a first mode, and can output a transmission signal having a low period of transmission with a transmission signal having a transmission signal shorter than or equal to one horizontal time period in a second mode.

[0009] In an embodiment, the first mode may be a high brightness mode in which the displayed brightness value is greater than or equal to the reference value, and the second mode may be a low brightness mode in which the displayed brightness value is less than the reference value.

[0010] In an embodiment, the second clock signal may be delayed by half a clock period compared to the first clock signal.

[0011] In an embodiment, the clock period may correspond to two horizontal time periods, and the second clock signal may be delayed by one horizontal time period compared to the first clock signal.

[0012] In one embodiment, the input circuit may include a first transistor, which includes a gate for receiving a first clock signal, a first terminal for receiving an input signal, and a second terminal connected to a first node.

[0013] In one embodiment, the node separation circuit may include a second transistor, which includes a gate for receiving a low gate voltage, a first terminal connected to the first node, and a second terminal connected to the second node.

[0014] In an embodiment, the output circuit may include a third transistor, a first capacitor, and a fourth transistor. The third transistor includes a gate connected to a third node, a first terminal receiving a high gate voltage, and a second terminal connected to an output node from which a signal is transmitted. The first capacitor includes a first electrode connected to a second node and a second electrode connected to the output node. The fourth transistor includes a gate connected to the second node, a first terminal connected to the output node, and a second terminal receiving a low gate voltage in a first mode and a second clock signal in a second mode.

[0015] In one embodiment, the node control circuit may include a fifth transistor, a sixth transistor, and a second capacitor. The fifth transistor includes a gate connected to the first node, a first terminal receiving a high gate voltage, and a second terminal connected to the third node. The sixth transistor includes a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage. The second capacitor includes a first electrode receiving a high gate voltage and a second electrode connected to the third node.

[0016] In an embodiment, the fifth transistor may be a P-type metal-oxide-semiconductor transistor, and the sixth transistor may be an N-type metal-oxide-semiconductor transistor.

[0017] In an embodiment, at least one stage may further include a carry circuit, which outputs a high gate voltage as a carry signal in response to the voltage of the third node, outputs a low gate voltage as a carry signal in response to the voltage of the second node in a first mode, and outputs a second clock signal as a carry signal in response to the voltage of the second node in a second mode.

[0018] In an embodiment, the carry circuit may include a seventh transistor and an eighth transistor. The seventh transistor includes a gate connected to a third node, a first terminal receiving a high gate voltage, and a second terminal connected to a carry node from which a carry signal is output. The eighth transistor includes a gate connected to a second node, a first terminal connected to a carry node, and a second terminal receiving a low gate voltage in a first mode and a second clock signal in a second mode.

[0019] In an embodiment, at least one stage may further include a carry circuit that outputs a high gate voltage as a carry signal in response to the voltage of the third node, outputs a small low gate voltage as a carry signal in response to the voltage of the second node in a first mode, and outputs a third clock signal as a carry signal in response to the voltage of the second node in a second mode. The third clock signal may have a phase substantially the same as the phase of the second clock signal and may have a small low gate voltage as a low voltage.

[0020] In an embodiment, the node control circuit may include: a fifth transistor that applies a high gate voltage to a fourth node in response to an input signal; a sixth transistor that applies a first clock signal to a third node in response to the voltage of the fourth node; a third capacitor that includes a first electrode connected to the fourth node and a second electrode receiving the first clock signal; a seventh transistor that is off in a first mode and applies the first clock signal to the third node in a second mode; an eighth transistor that is on in a first mode and off in a second mode; a ninth transistor that is connected in series with the eighth transistor between the line transmitting the high gate voltage and the third node, and applies a high gate voltage to the third node in response to the voltage of the first node in the first mode; and a second capacitor that includes a first electrode receiving the high gate voltage and a second electrode connected to the third node.

[0021] In an embodiment, the fifth transistor may include a gate for receiving an input signal, a first terminal for receiving a high gate voltage, and a second terminal connected to the fourth node; the sixth transistor may include a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal for receiving a first clock signal; the seventh transistor may include a gate for receiving a high gate voltage in a first mode and a low gate voltage in a second mode, a first terminal connected to the third node, and a second terminal for receiving the first clock signal; the eighth transistor may include a gate for receiving a low gate voltage in a first mode and a high gate voltage in a second mode, a first terminal for receiving a high gate voltage, and a second terminal; and the ninth transistor may include a gate connected to the first node, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the third node.

[0022] In the embodiments, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor may be P-type metal-oxide-semiconductor transistors.

[0023] In embodiments of this disclosure, an electronic device is provided, including: a processor that provides input image data; and a display device that receives the input image data from the processor and displays an image based on the input image data. The display device includes: a display panel including a plurality of pixels; a data driver that provides data signals to the plurality of pixels; a scan driver that provides scan signals to the plurality of pixels; a transmission driver including a plurality of stages that sequentially provide transmission signals to the plurality of pixels; and a controller that controls the data driver, the scan driver, and the transmission driver. At least one of the multiple stages includes: an input circuit that transmits an input signal to a first node in response to a first clock signal; a node separation circuit connected between the first node and a second node and receiving a low gate voltage having a first voltage level; a node control circuit that controls the voltage of a third node based on the voltage of the first node, a high gate voltage having a second voltage level higher than the first voltage level, and a low gate voltage; and an output circuit that outputs a high gate voltage as a corresponding transmit signal in response to the voltage of the third node, outputs a low gate voltage as a corresponding transmit signal in response to the voltage of the second node in a first mode, and outputs a second clock signal different from the first clock signal as a corresponding transmit signal in response to the voltage of the second node in a second mode.

[0024] In this embodiment, the controller can receive a display brightness value, and when the display brightness value is greater than or equal to a reference brightness value, it can determine the mode of the display device as a first mode, and when the display brightness value is less than the reference brightness value, it can determine the mode of the display device as a second mode.

[0025] In an embodiment, the controller can provide the transmitter driver with a start signal having a low period of time, which is longer than or equal to two horizontal time periods, wherein the start signal has a first voltage level, in a first mode, and can provide the transmitter driver with a start signal having a low period of time, which is shorter than or equal to one horizontal time period, in a second mode.

[0026] In an embodiment, in a first mode, the controller can provide a low gate voltage to the output circuits of multiple stages. In a second mode, the controller can provide one of a first clock signal and a second clock signal to the output circuits of the odd-numbered stages of the multiple output circuits, and can provide the remaining (additional) one of the first clock signal and the second clock signal to the output circuits of the even-numbered stages of the multiple output circuits.

[0027] As described above, in the transmitter driver and electronic device of the embodiments, the output circuit of at least one stage can output a low gate voltage as a transmitter signal in a first mode (e.g., high brightness mode) and can output a clock signal as a transmitter signal in a second mode (e.g., low brightness mode). Therefore, the transmitter driver is applicable not only to high brightness modes in which the conduction period (e.g., low period) of the transmitter signal is longer than or equal to two horizontal time periods, but also to low brightness modes in which the conduction period of the transmitter signal is shorter than or equal to one horizontal time period. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating an embodiment of the transmit driver.

[0030] Figure 2 This is a timing diagram illustrating an embodiment of the operation of the transmit driver in a first mode.

[0031] Figure 3 This is a timing diagram illustrating an embodiment of the operation of the transmit driver in a second mode.

[0032] Figure 4 This is a timing diagram for describing another embodiment of the operation of the transmit driver in the second mode.

[0033] Figure 5 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver.

[0034] Figure 6 It is used to describe Figure 5 Timing diagram of an embodiment of the operation of the level in the first mode.

[0035] Figure 7It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the first time period.

[0036] Figure 8 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the second time period.

[0037] Figure 9 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the third time period.

[0038] Figure 10 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the fourth time period.

[0039] Figure 11 It is used to describe Figure 5 Timing diagram of an embodiment of the operation of the level in the second mode.

[0040] Figure 12 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the fifth time period.

[0041] Figure 13 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the sixth time period.

[0042] Figure 14 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the seventh time period.

[0043] Figure 15 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver.

[0044] Figure 16 It is used to describe Figure 15 Timing diagram of an embodiment of the operation of the level in the first mode.

[0045] Figure 17 It is used to describe Figure 15 Timing diagram of an embodiment of the operation of the level in the second mode.

[0046] Figure 18 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver.

[0047] Figure 19 It is used to describe Figure 18 Timing diagram of an embodiment of the operation of the level in the first mode.

[0048] Figure 20 It is used to describe Figure 18Timing diagram of an embodiment of the operation of the level in the second mode.

[0049] Figure 21 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver.

[0050] Figure 22 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the first time period.

[0051] Figure 23 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the second time period.

[0052] Figure 24 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the third time period.

[0053] Figure 25 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the fourth time period.

[0054] Figure 26 It is used to describe Figure 21 Timing diagram of an embodiment of the operation of the level in the second mode.

[0055] Figure 27 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the fifth time period.

[0056] Figure 28 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the sixth time period.

[0057] Figure 29 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the seventh time period.

[0058] Figure 30 This is a block diagram illustrating an embodiment of a display device including a transmit driver.

[0059] Figure 31 This is a block diagram illustrating an embodiment of an electronic device including a display device. Detailed Implementation

[0060] In the following description, embodiments are illustrated more fully with reference to the accompanying drawings. The same or similar reference numerals always refer to the same or similar elements.

[0061] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0062] It should be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0063] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another. Therefore, “first element,” “first component,” “first area,” “first layer,” or “first segment” discussed below may be referred to as a second element, second component, second area, second layer, or second segment without departing from the teachings of this document.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless otherwise expressly stated herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that the terms “comprising” and / or “including,” or “containing” and / or “comprises”, when used in this specification, designate the presence of the recorded features, areas, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0065] Furthermore, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that relative terms are intended to cover different orientations of the device other than those depicted in the figures. For example, if the device in one of the figures is flipped, an element described as being on the “lower” side of other elements will subsequently be oriented on the “upper” side of other elements. Thus, depending on the specific orientation of the figure, the exemplary term “lower” may cover both “lower” and “upper” orientations. Similarly, if the device in one of the figures is flipped, an element described as being “below” or “under” other elements will subsequently be oriented “above” other elements. Thus, the exemplary term “below” or “under” may cover both “upper” and “lower” orientations.

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant technical context and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0067] Figure 1 This is a block diagram illustrating an embodiment of the transmit driver. Figure 2 This is a timing diagram illustrating an embodiment of the operation of the transmit driver in a first mode. Figure 3 This is a timing diagram illustrating an embodiment of the operation of the transmit driver in a second mode, and Figure 4 This is a timing diagram for describing another embodiment of the operation of the transmit driver in the second mode.

[0068] Reference Figure 1 The transmit driver 100 in the embodiments may include multiple stages STG1, STG2, STG3, STG4, etc. The transmit driver 100 may be implemented as a shift register in which the multiple stages STG1, STG2, STG3, STG4, etc., sequentially output transmit signals EM1, EM2, EM3, EM4, etc. In some embodiments, the transmit driver 100 may be formed on the display panel of the display device. In embodiments, for example, the transmit driver 100 may be integrated or formed on the substrate of the display panel, but is not limited thereto.

[0069] Multiple stages, such as STG1, STG2, STG3, and STG4, can sequentially output transmit signals EM1, EM2, EM3, and EM4 based on a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2. The first stage STG1 can receive the start signal FLM as an input signal. In some embodiments, each of subsequent stages STG2, STG3, and STG4 can receive the transmit signals EM1, EM2, EM3, and EM4 of the previous stage as input signals. For example, in one embodiment, the second stage STG2 can receive the first transmit signal EM1 of the first stage STG1 as an input signal, the third stage STG3 can receive the second transmit signal EM2 of the second stage STG2 as an input signal, and the fourth stage STG4 can receive the third transmit signal EM3 of the third stage STG3 as an input signal. In other embodiments, for example, each of subsequent stages STG2, STG3, and STG4 can receive the carry signals CR1, CR2, CR3, and CR4 of the previous stage as input signals. In an embodiment, for example, the second-level STG2 can receive the first carry signal CR1 of the first-level STG1 as an input signal, the third-level STG3 can receive the second carry signal CR2 of the second-level STG2 as an input signal, and the fourth-level STG4 can receive the third carry signal CR3 of the third-level STG3 as an input signal.

[0070] In some embodiments, each odd-numbered STG1, STG3, etc., may receive an input signal in response to a first clock signal CLK1, and each even-numbered STG2, STG4, etc., may receive an input signal in response to a second clock signal CLK2. Furthermore, in some embodiments, the second clock signal CLK2 may be a signal delayed by half a clock period compared to the first clock signal CLK1. In embodiments, for example, the clock periods (or clock cycles) of the first clock signal CLK1 and the second clock signal CLK2 may correspond to two horizontal time periods, and the second clock signal CLK2 may be a signal delayed by one horizontal time period compared to the first clock signal CLK1.

[0071] The transmit driver 100 in this embodiment can output transmit signals EM1, EM2, EM3, EM4, etc., with a low time period LP1 that is longer than or equal to two horizontal time periods 2H in the first mode MODE1. Figure 2 As shown, and in the second mode MODE2, it can output transmit signals EM1, EM2, EM3, EM4, etc., with a low time period LP2 shorter than or equal to a horizontal time period of 1H, such as... Figure 3As shown in the illustration. In an embodiment, for example, a horizontal time period 1H may be the time allocated to one pixel row of the display panel, and may have a time length determined by dividing the time length of a frame period FP by the number of pixel rows of the display panel. In some embodiments, a first mode MODE1 may be a high brightness mode in which the displayed apparent brightness value (“DBV”) is greater than or equal to a reference value, while a second mode MODE2 may be a low brightness mode in which the DBV is less than the reference value. Here, DBV may represent the brightness of the display device corresponding to the maximum gray level (e.g., 255 gray levels).

[0072] In an embodiment, such as Figure 2 As shown, in the first mode MODE1, for example, the first stage STG1 can receive a start signal FLM having a low period LP1 longer than or equal to two horizontal time periods 2H, and can output a first transmit signal EM1 having a low period LP1 longer than or equal to two horizontal time periods 2H by delaying the start signal FLM by one horizontal time period 1H. Furthermore, the second stage STG2 can output a second transmit signal EM2 having a low period LP1 longer than or equal to two horizontal time periods 2H by delaying the first transmit signal EM1 by one horizontal time period 1H; the third stage STG3 can output a third transmit signal EM3 having a low period LP1 longer than or equal to two horizontal time periods 2H by delaying the second transmit signal EM2 by one horizontal time period 1H; and the fourth stage STG4 can output a fourth transmit signal EM4 having a low period LP1 longer than or equal to two horizontal time periods 2H by delaying the third transmit signal EM3 by one horizontal time period 1H. Thus, in the first mode MODE1, multiple levels STG1, STG2, STG3, STG4, etc., can sequentially output transmission signals EM1, EM2, EM3, EM4, etc., with a low time period LP1 longer than or equal to two horizontal time periods 2H by delaying or shifting the input signal by a horizontal time period 1H (or half of the clock period of the first clock signal CLK1 and the second clock signal CLK2). Furthermore, in some embodiments, in the first mode MODE1, as DBV increases, in order to increase the transmission time of each pixel within the frame time period FP, the time length of the low time period LP1 of the start signal FLM can be increased, and multiple levels STG1, STG2, STG3, STG4, etc., can output transmission signals EM1, EM2, EM3, EM4, etc., with a low time period LP1 whose time length has increased (e.g., in units of two horizontal time periods 2H), based on the start signal FLM with its increased low time period LP1.

[0073] In addition, such as Figure 3As shown, in the second mode MODE2, the first stage STG1 can receive a start signal FLM with a low time period LP2 shorter than or equal to one horizontal time period 1H, and can output a first transmit signal EM1 with a low time period LP2 shorter than or equal to one horizontal time period 1H by delaying the start signal FLM by one horizontal time period 1H. Furthermore, the second stage STG2 can output a second transmit signal EM2 with a low time period LP2 shorter than or equal to one horizontal time period 1H by delaying the first transmit signal EM1 by one horizontal time period 1H; the third stage STG3 can output a third transmit signal EM3 with a low time period LP2 shorter than or equal to one horizontal time period 1H by delaying the second transmit signal EM2 by one horizontal time period 1H; and the fourth stage STG4 can output a fourth transmit signal EM4 with a low time period LP2 shorter than or equal to one horizontal time period 1H by delaying the third transmit signal EM3 by one horizontal time period 1H. Thus, in the second mode MODE2, multiple levels STG1, STG2, STG3, STG4, etc. can sequentially output transmission signals EM1, EM2, EM3, EM4, etc., with a low time period LP2 shorter than or equal to a horizontal time period 1H by delaying or shifting the input signal by a horizontal time period 1H (or half of the clock period of the first clock signal CLK1 and the second clock signal CLK2).

[0074] although Figure 3 An embodiment is shown in which multiple stages STG1, STG2, STG3, STG4, etc., output transmission signals EM1, EM2, EM3, EM4, etc., having a low-segment LP2 corresponding to a horizontal time period 1H. However, multiple stages STG1, STG2, STG3, STG4, etc., can also output transmission signals EM1, EM2, EM3, EM4, etc., having a low-segment LP2 shorter than a horizontal time period 1H. In the embodiment, for example, as DBV decreases, such as Figure 4As shown, multiple stages STG1, STG2, STG3, STG4, etc., can receive a first clock signal CLK1 and a second clock signal CLK2 having a low-segment LP shorter than a horizontal time period 1H, and can output transmission signals EM1, EM2, EM3, EM4, etc., having a low-segment LP shorter than a horizontal time period 1H. That is, in the second mode MODE2, as DBV decreases, in order to reduce the transmission time of each pixel within the frame time period FP, multiple stages STG1, STG2, STG3, STG4, etc., can output transmission signals EM1, EM2, EM3, EM4, etc., having a low-segment LP shorter than a horizontal time period 1H, based on the first clock signal CLK1 and the second clock signal CLK2 having a low-segment LP shorter than a horizontal time period 1H. In this case, the start signal FLM can have a low-segment LP2' corresponding to or shorter than a horizontal time period 1H.

[0075] To output transmit signals EM1, EM2, EM3, EM4, etc., with a low time period LP1 longer than or equal to two horizontal time periods of 2H in the first mode MODE1, and to output transmit signals EM1, EM2, EM3, EM4, etc., with a low time period LP2 shorter than or equal to one horizontal time period of 1H in the second mode MODE2, the odd-numbered STG1, STG3, etc. (or the output circuits of the odd-numbered STG1, STG3, etc.) can receive a low gate voltage VGL with a relatively low voltage level (e.g., logic low level, also referred to as the first voltage level) in the first mode MODE1, and can receive a second clock signal CLK2 in the second mode MODE2. Furthermore, the even-numbered STG2, STG4, etc. (or the output circuits of the even-numbered STG2, STG4, etc.) can receive a low gate voltage VGL in the first mode MODE1, and can receive a first clock signal CLK1 in the second mode MODE2. See below for reference. Figures 5 to 29 Describe the operation of each level STG1, STG2, STG3, STG4, etc. in the first mode MODE1 and the second mode MODE2.

[0076] Figure 5 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver.

[0077] refer to Figure 5 The stage 200 of the transmit driver in the embodiment may include an input circuit 210 that transmits the input signal SIN to the first node Q1, a node separation circuit 230 connected between the first node Q1 and the second node Q2, a node control circuit 250 that controls the voltage of the third node QB, and an output circuit 270 that outputs the transmit signal EM.

[0078] Input circuit 210 can receive a first clock signal CLK1 and can transmit the input signal SIN to the first node Q1 in response to the first clock signal CLK1. In some embodiments, when stage 200 is the first stage of the transmit driver, the input signal SIN can be the start signal FLM, and when stage 200 is a stage after the first stage, the input signal SIN can be the transmit signal PEM of the previous stage.

[0079] In some embodiments, the input circuit 210 may include a first transistor T1. In an embodiment, for example, the first transistor T1 may include a gate for receiving a first clock signal CLK1, a first terminal for receiving an input signal SIN, and a second terminal connected to a first node Q1.

[0080] The node separation circuit 230 may include a second transistor T2 connected between the first node Q1 and the second node Q2 and including a gate that receives a low gate voltage VGL. Because the second transistor T2 receives a low gate voltage VGL at its gate for turning on the second transistor T2, the second transistor T2 may also be referred to as an always-on transistor (“AOT”). Furthermore, when the voltage of the second node Q2 rises, the second transistor T2 can prevent the voltage of the second node Q2 from being transmitted to the first node Q1. In some embodiments, the second transistor T2 may include a gate that receives the low gate voltage VGL, a first terminal connected to the first node Q1, and a second terminal connected to the second node Q2.

[0081] Node control circuit 250 can control the voltage of third node QB based on the voltage of first node Q1 (and / or the voltage of second node Q2), a high gate voltage VGH having a relatively high voltage level (e.g., a logic high level, also referred to as a second voltage level), and a low gate voltage VGL. In an embodiment, for example, node control circuit 250 can provide a high gate voltage VGH to third node QB when the voltage of first node Q1 is low, and can provide a low gate voltage VGL to third node QB when the voltage of second node Q2 is high.

[0082] In some embodiments, the node control circuit 250 may include a fifth transistor T5, a sixth transistor T6, and a second capacitor C2. In an embodiment, for example, the fifth transistor T5 may include a gate connected to the first node Q1, a first terminal receiving a high gate voltage VGH, and a second terminal connected to the third node QB. The sixth transistor T6 may include a gate connected to the second node Q2, a first terminal connected to the third node QB, and a second terminal receiving a low gate voltage VGL. The second capacitor C2 may include a first electrode receiving a high gate voltage VGH and a second electrode connected to the third node QB. In some embodiments, the fifth transistor T5 may be, but is not limited to, a P-type metal-oxide-semiconductor (“PMOS”) transistor, and the sixth transistor T6 may be, but is not limited to, an N-type metal-oxide-semiconductor (“NMOS”) transistor.

[0083] Output circuit 270 can receive a high gate voltage VGH, the voltage of the second node Q2, and the voltage of the third node QB. It can also receive a low gate voltage VGL in a first mode MODE1, and a second clock signal CLK2, different from the first clock signal CLK1 provided to input circuit 210, in a second mode MODE2. In some embodiments, the first mode MODE1 can be a high brightness mode where DBV is greater than or equal to a reference value, and the second mode MODE2 can be a low brightness mode where DBV is less than a reference value, but is not limited thereto. Furthermore, in some embodiments, the second clock signal CLK2 can be delayed by half a clock period compared to the first clock signal CLK1. In embodiments, for example, the clock periods of the first clock signal CLK1 and the second clock signal CLK2 can correspond to two horizontal time periods, and the second clock signal CLK2 can be delayed by one horizontal time period compared to the first clock signal CLK1. Although Figure 5 An embodiment is shown in which level 200 is an odd number of levels, but in the case where level 200 is an even number of levels, input circuit 210 can receive the second clock signal CLK2 instead of the first clock signal CLK1, and output circuit 270 can receive the first clock signal CLK1 instead of the second clock signal CLK2 in the second mode MODE2.

[0084] Output circuit 270 can respond to the voltage of the third node QB by outputting a high gate voltage VGH as a transmit signal EM, can respond to the voltage of the second node Q2 in the first mode MODE1 by outputting a low gate voltage VGL as a transmit signal EM, and can respond to the voltage of the second node Q2 in the second mode MODE2 by outputting a second clock signal CLK2 as a transmit signal EM. In an embodiment, for example, output circuit 270 can output a high gate voltage VGH as a transmit signal EM when the voltage of the third node QB is low, can output a low gate voltage VGL as a transmit signal EM in the first mode MODE1 when the voltage of the second node Q2 is low, and can output a second clock signal CLK2 as a transmit signal EM in the second mode MODE2 when the voltage of the second node Q2 is low. Therefore, refer to the following Figures 6 to 14 The output circuit 270 can output a low-segment transmission signal EM with a duration of longer than or equal to two horizontal time periods in the first mode MODE1, wherein the transmission signal EM has a relatively low voltage level (or a first voltage level), and can output a low-segment transmission signal EM with a duration of shorter than or equal to one horizontal time period in the second mode MODE2.

[0085] In some embodiments, the output circuit 270 may include a third transistor T3, a first capacitor C1, and a fourth transistor T4. In one embodiment, for example, the third transistor T3 may include a gate connected to a third node QB, a first terminal receiving a high gate voltage VGH, and a second terminal connected to an output node NO from which it outputs a transmit signal EM. The first capacitor C1 may include a first electrode connected to a second node Q2 and a second electrode connected to the output node NO. The fourth transistor T4 may include a gate connected to the second node Q2, a first terminal connected to the output node NO, and a second terminal receiving a low gate voltage VGL in the first mode MODE1 and a second clock signal CLK2 in the second mode MODE2.

[0086] In some embodiments, a portion of the first transistor T1 to the sixth transistor T6 of stage 200 may be PMOS transistors, while the remainder of the first transistor T1 to the sixth transistor T6 may be NMOS transistors. In embodiments, as... Figure 5 As shown, for example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be PMOS transistors, while the sixth transistor T6 can be an NMOS transistor, but is not limited thereto. In other embodiments, all of the first transistors T1 to the sixth transistor T6 of stage 200 can be PMOS transistors. In still other embodiments, all of the first transistors T1 to the sixth transistor T6 of stage 200 can be NMOS transistors.

[0087] In the following text, see references Figures 5 to 10 Description of an embodiment of the operation of level 200 in the first mode MODE1.

[0088] Figure 6 It is used to describe Figure 5 Timing diagram of an embodiment of the operation of the level in the first mode. Figure 7 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the first time period. Figure 8 It is used to describe Figure 5 A circuit diagram illustrating an embodiment of the operation of the stage in the second time period. Figure 9 It is used to describe Figure 5 A circuit diagram illustrating an embodiment of the operation of the stage in the third time period, and Figure 10 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the fourth time period.

[0089] Reference Figure 5 and Figure 6 In the first mode MODE1, stage 200 can receive an input signal SIN with a low time interval longer than or equal to two horizontal time intervals, and can output a transmit signal EM by delaying the input signal SIN by one horizontal time interval. In some embodiments, when the input signal SIN is high and the first clock signal CLK1 is low, stage 200 can output a transmit signal EM with a high level, and when the input signal SIN is low and the first clock signal CLK1 is low, stage 200 can output a transmit signal EM with a low level.

[0090] In an embodiment, such as Figure 6 and Figure 7As shown, for example, during a first time period TP1 in which the input signal SIN has a high level H and the first clock signal CLK1 has a high level H, the first transistor T1 can be turned off in response to the first clock signal CLK1 having a high level H. Therefore, the input signal SIN is not transmitted to the first node Q1, the voltage of the first node Q1 can have a low level L as the previous level, and the voltage of the second node Q2 can have a boosted low level BL as the previous level. The fifth transistor T5 can be turned on in response to the voltage of the first node Q1 and can transmit a high gate voltage VGH to the third node QB. Therefore, the voltage of the third node QB can have a high level H. The third transistor T3 can be turned off in response to the voltage of the third node QB, and the sixth transistor T6 can be turned off in response to the voltage of the second node Q2. The fourth transistor T4 can be turned on in response to the voltage of the second node Q2 and can output a low gate voltage VGL as a transmit signal EM. Therefore, a transmit signal EM with a low level L can be output at the output node NO.

[0091] like Figure 6 and Figure 8 As shown, during the second time period TP2, in which the input signal SIN has a high level H and the first clock signal CLK1 has a low level L, the first transistor T1 can turn on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a high level H. The fifth transistor T5 can turn off in response to the voltage of the first node Q1. The second transistor T2 can turn on in response to a low gate voltage VGL, and can transmit the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a high level H. The fourth transistor T4 can turn off in response to the voltage of the second node Q2. The sixth transistor T6 can turn on in response to the voltage of the second node Q2, and can transmit the low gate voltage VGL to the third node QB. Therefore, the voltage of the third node QB can have a low level L. The third transistor T3 can turn on in response to the voltage of the third node QB, and can output a high gate voltage VGH as the transmit signal EM. Therefore, a transmit signal EM with a high level H can be output at output node NO. Furthermore, stage 200 can output a transmit signal EM with a high level H during the period between the second time period TP2 and the third time period TP3.

[0092] After that, as Figure 6 and Figure 9As shown, during the third time period TP3, where the input signal SIN has a low level L and the first clock signal CLK1 has a high level H, the first transistor T1 can be turned off in response to the first clock signal CLK1 having a high level H. Therefore, the input signal SIN is not transmitted to the first node Q1, and the voltage of the first node Q1 can have a high level H as the previous level, and the voltage of the second node Q2 can also have a high level H as the previous level. The fifth transistor T5 can be turned off in response to the voltage of the first node Q1, and the second transistor T2 can be turned on in response to the low gate voltage VGL. The fourth transistor T4 can be turned off in response to the voltage of the second node Q2. The sixth transistor T6 can be turned on in response to the voltage of the second node Q2 and can transmit the low gate voltage VGL to the third node QB. Therefore, the voltage of the third node QB can have a low level L. The third transistor T3 can be turned on in response to the voltage of the third node QB and can output a high gate voltage VGH as the transmit signal EM. Therefore, even when the input signal SIN changes to a low level L, stage 200 can still output a transmit signal EM with a high level H at the output node NO.

[0093] like Figure 6 and Figure 10 As shown, during the fourth time period TP4, in which the input signal SIN has a low level L and the first clock signal CLK1 has a low level L, the first transistor T1 can be turned on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a low level L. The fifth transistor T5 can be turned on in response to the voltage of the first node Q1, and can transmit the high gate voltage VGH to the third node QB. Therefore, the voltage of the third node QB can have a high level H. The third transistor T3 can be turned off in response to the voltage of the third node QB.

[0094] Furthermore, during the fourth time period TP4, the second transistor T2 can be turned on in response to a low gate voltage VGL, and can transfer the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a low level L. The fourth transistor T4 can be turned on in response to the voltage of the second node Q2, and can transfer the low gate voltage VGL to the output node NO. Therefore, the voltage of the output node NO connected to the second electrode of the first capacitor C1 can change from a high level H to a low level L. Furthermore, when the voltage of the output node NO or the voltage of the second electrode of the first capacitor C1 decreases from a high level H to a low level L, through the coupling of the first capacitor C1, the voltage of the first electrode of the first capacitor C1 or the voltage of the second node Q2 can also decrease from a low level L to a boosted low level BL. The boosted low level BL can be lower than the low gate voltage VGL applied to the gate of the second transistor T2, and therefore the second transistor T2 can prevent the voltage of the second node Q2 with the boosted low level BL from being transferred to the first node Q1. Furthermore, the fourth transistor T4 can be fully or fully turned on in response to the voltage of the second node Q2 with a boost low level BL, and can output a transmit signal EM with a low level L that is substantially the same as the low gate voltage VGL.

[0095] Stage 200 can continuously output a transmit signal EM with a low level L during the period following the fourth time period TP4, until the input signal SIN changes to a high level H and the first clock signal CLK1 changes to a low level L in the next frame period. Therefore, in the first mode MODE1, stage 200 can output a transmit signal EM with a low period of time longer than or equal to two horizontal time periods.

[0096] In the following text, see references Figure 5 and Figures 11 to 14 Description of an embodiment of the operation of level 200 in the second mode MODE2.

[0097] Figure 11 It is used to describe Figure 5 A timing diagram of an embodiment of the operation of the level in the second mode. Figure 12 It is used to describe Figure 5 A circuit diagram illustrating an embodiment of the operation of the stage in the fifth time period. Figure 13 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the level in the sixth time period, and Figure 14 It is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the seventh time period.

[0098] Reference Figure 5 and Figure 11In the second mode MODE2, stage 200 can receive an input signal SIN with a low time interval shorter than or equal to a horizontal time interval, and can output a transmit signal EM by delaying the input signal SIN by a horizontal time interval. In some embodiments, when the input signal SIN is low and the first clock signal CLK1 is low, stage 200 can receive the input signal SIN, and after receiving the input signal SIN, when the second clock signal CLK2 is low, stage 200 can output a transmit signal EM with a low level.

[0099] In an embodiment, such as Figure 11 and Figure 12 As shown, for example, in the fifth time period TP5 where the input signal SIN has a low level L and the first clock signal CLK1 has a low level L, the first transistor T1 can turn on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a low level L. The fifth transistor T5 can turn on in response to the voltage of the first node Q1, and can transmit the high gate voltage VGH to the third node QB. Therefore, the voltage of the third node QB can have a high level H. The third transistor T3 can turn off in response to the voltage of the third node QB. Furthermore, the second transistor T2 can turn on in response to the low gate voltage VGL, and can transmit the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a low level L. The sixth transistor T6 can turn off in response to the voltage of the second node Q2. Although the fourth transistor T4 receives the low gate voltage VGL in the first mode MODE1, the fourth transistor T4 can receive the second clock signal CLK2 in the second mode MODE2. Furthermore, the fourth transistor T4 can be turned on in response to the voltage of the second node Q2, and can output a second clock signal CLK2 with a high level H as the transmit signal EM. Therefore, in the fifth time period TP5, even when the input signal SIN has a low level L, stage 200 can still output the transmit signal EM with a high level H at the output node NO.

[0100] like Figure 11 and Figure 13As shown, during the sixth time period TP6, in which the input signal SIN has a high level H and the first clock signal CLK1 has a high level H, the first transistor T1 can be turned off in response to the first clock signal CLK1 having a high level H. Therefore, the input signal SIN is not transmitted to the first node Q1, and the voltage of the first node Q1 can have a low level L as the previous level. The fifth transistor T5 can be turned on in response to the voltage of the first node Q1, the voltage of the third node QB can have a high level H, and the third transistor T3 can be turned off in response to the voltage of the third node QB.

[0101] Furthermore, during the sixth time period TP6, the second clock signal CLK2 can decrease from a high level H to a low level L, and therefore, the voltage at the output node NO from which the second clock signal CLK2 is output can decrease from a high level H to a low level L. Additionally, when the voltage at the output node NO or the voltage at the second electrode of the first capacitor C1 decreases from a high level H to a low level L, through the coupling of the first capacitor C1, the voltage at the first electrode of the first capacitor C1 or the voltage at the second node Q2 can also decrease from a low level L to a boosted low level BL. The boosted low level BL can be lower than the low gate voltage VGL applied to the gate of the second transistor T2, and therefore the second transistor T2 can prevent the voltage of the second node Q2 with the boosted low level BL from being transmitted to the first node Q1. Furthermore, the fourth transistor T4 can be fully turned on in response to the voltage of the second node Q2 with the boosted low level BL, and can output a transmit signal EM with a low level L that is substantially the same as the voltage level (or low level L) of the second clock signal CLK2. Therefore, in the sixth time period TP6, even when the input signal SIN has a high level H, stage 200 can still output a transmit signal EM with a low level L at the output node NO.

[0102] like Figure 11 and Figure 14As shown, during the seventh time period TP7, in which the input signal SIN has a high level H and the first clock signal CLK1 has a low level L, the first transistor T1 can turn on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a high level H. The fifth transistor T5 can turn off in response to the voltage of the first node Q1. The second transistor T2 can turn on in response to a low gate voltage VGL, and can transmit the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a high level H. The fourth transistor T4 can turn off in response to the voltage of the second node Q2. The sixth transistor T6 can turn on in response to the voltage of the second node Q2, and can transmit the low gate voltage VGL to the third node QB. Therefore, the voltage of the third node QB can have a low level L. The third transistor T3 can turn on in response to the voltage of the third node QB, and can output a high gate voltage VGH as the transmit signal EM. Therefore, in the seventh time period TP7, stage 200 can output a transmit signal EM with a high level H at the output node NO.

[0103] Stage 200 can continuously output a transmit signal EM with a high level H during the period following the seventh time period TP7, until the input signal SIN changes to a low level L and the first clock signal CLK1 and the second clock signal CLK2 sequentially change to a low level L in the next frame period. Therefore, stage 200 can output a transmit signal EM with a short period of time shorter than or equal to one horizontal time period in the second mode MODE2.

[0104] In a conventional transmitter driver, each stage can output a transmit signal with a low-segment duration longer than or equal to two horizontal time periods. However, in the transmitter driver of this embodiment, stage 200 can output a transmit signal EM with a low-segment duration longer than or equal to two horizontal time periods not only in a first mode MODE1, but also in a second mode MODE2 with a low-segment duration shorter than or equal to one horizontal time period. That is, the transmitter driver of this embodiment can operate normally not only in a first mode MODE1 (e.g., high brightness mode) where the low-segment duration of the transmit signal EM is longer than or equal to two horizontal time periods, but also in a second mode MODE2 (e.g., low brightness mode) where the low-segment duration of the transmit signal EM is shorter than or equal to one horizontal time period.

[0105] Figure 15 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver. Figure 16 It is used to describe Figure 15 Timing diagram of an embodiment of the operation of the level in the first mode, and Figure 17It is used to describe Figure 15 Timing diagram of an embodiment of the operation of the level in the second mode.

[0106] refer to Figure 15 The stage 300 of the transmit driver in this embodiment may include an input circuit 210, a node separation circuit 230, a node control circuit 250, an output circuit 270, and a carry circuit 390 for outputting a carry signal CR. In addition to stage 300, it may also include a carry circuit 390, and may receive the carry signal PCR from the previous stage instead of the transmit signal from the previous stage as the input signal SIN. Figure 15 Level 300 can be compared with Figure 5 The Class 200 has essentially the same configuration and essentially the same operation.

[0107] The carry circuit 390 can receive the high gate voltage VGH, the voltage of the second node Q2, and the voltage of the third node QB. It can also receive the low gate voltage VGL in the first mode MODE1, and a second clock signal CLK2, different from the first clock signal CLK1 provided to the input circuit 210, in the second mode MODE2. The carry circuit 390 can output the high gate voltage VGH as the carry signal CR in response to the voltage of the third node QB; it can output the low gate voltage VGL as the carry signal CR in response to the voltage of the second node Q2 in the first mode MODE1; and it can output the second clock signal CLK2 as the carry signal CR in response to the voltage of the second node Q2 in the second mode MODE2.

[0108] In some embodiments, the carry circuit 390 may include a seventh transistor T7 and an eighth transistor T8. In one embodiment, for example, the seventh transistor T7 may include a gate connected to the third node QB, a first terminal receiving a high gate voltage VGH, and a second terminal connected to the carry node NC from which it outputs a carry signal CR. The eighth transistor T8 may include a gate connected to the second node Q2, a first terminal connected to the carry node NC, and a second terminal receiving a low gate voltage VGL in the first mode MODE1 and a second clock signal CLK2 in the second mode MODE2.

[0109] In the first mode MODE1, as follows Figure 16As shown, stage 300 can receive an input signal SIN with a low time interval longer than or equal to two horizontal time intervals, and can output a transmit signal EM with a low time interval longer than or equal to two horizontal time intervals and a carry signal CR with a low time interval longer than or equal to two horizontal time intervals by delaying the input signal SIN by one horizontal time interval. The transmit signal EM output from stage 300 can be provided to the pixels of the display panel, and the carry signal CR output from stage 300 can be provided to the next stage as the input signal SIN for the next stage.

[0110] In addition, in the second mode MODE2, such as Figure 17 As shown, stage 300 can receive an input signal SIN with a low time interval shorter than or equal to one horizontal time interval, and can output a transmit signal EM with a low time interval shorter than or equal to one horizontal time interval and a carry signal CR with a low time interval shorter than or equal to one horizontal time interval by delaying the input signal SIN by one horizontal time interval. Therefore, the transmit driver including stage 300 can operate normally not only in a first mode MODE1 (e.g., high brightness mode) in which the low time interval of the transmit signal EM is longer than or equal to two horizontal time intervals, but also in a second mode MODE2 (e.g., low brightness mode) in which the low time interval of the transmit signal EM is shorter than or equal to one horizontal time interval.

[0111] Figure 18 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver. Figure 19 It is used to describe Figure 18 Timing diagram of an embodiment of the operation of the level in the first mode, and Figure 20 It is used to describe Figure 18 Timing diagram of an embodiment of the operation of the level in the second mode.

[0112] refer to Figure 18 The stage 400 of the transmit driver in this embodiment may include an input circuit 210, a node separation circuit 230, a node control circuit 250, an output circuit 270, and a carry circuit 490 for outputting a carry signal CR'. Except that the carry circuit 490 can receive a small low gate voltage sVGL in the first mode MODE1 and a third clock signal CLK3 in the second mode MODE2, and the low voltage of the carry signal CR' and the input signal SIN' is a small low gate voltage sVGL, Figure 18 Level 400 can be compared with Figure 15 The Class 300 has essentially the same configuration and essentially the same operation.

[0113] In the first mode MODE1, the carry circuit 490 can receive a small low gate voltage sVGL with an absolute value smaller than the absolute value of the low gate voltage VGL, and can output the small low gate voltage sVGL as a carry signal CR' with a low level. Furthermore, the carry signal CR' with the small low gate voltage sVGL can be provided to the next stage as an input signal SIN' for the next stage. Therefore, the voltage difference between the high and low voltages of the input signal SIN' and the voltage difference between the high and low voltages of the internal nodes of stage 400 (e.g., the first node Q1) can be reduced, and the power consumption of stage 400 and the transmit driver can be reduced.

[0114] In the embodiment, under the first mode MODE1, such as Figure 19 As shown, for example, the first clock signal CLK1, the second clock signal CLK2, the third node QB, and the transmit signal EM can have a low gate voltage VGL as a low voltage, and the second node Q2 can have a boosted low gate voltage BVGL as a low voltage. However, the input signal SIN', the carry signal CR', and the first node Q1 can have a small low gate voltage sVGL as a low voltage, where the small low gate voltage sVGL has an absolute value smaller than the absolute value of the low gate voltage VGL. Therefore, the power consumption of stage 400 and the transmit driver can be reduced. Furthermore, stage 400 can receive the input signal SIN' having a low period of longer than or equal to two horizontal time periods, and can output the transmit signal EM having a low period of longer than or equal to two horizontal time periods and the carry signal CR' having a low period of longer than or equal to two horizontal time periods by delaying the input signal SIN' by one horizontal time period.

[0115] In the second mode MODE2, the carry circuit 490 can receive a third clock signal CLK3 with a phase substantially the same as the second clock signal CLK2 and a low gate voltage sVGL as a low voltage, and can output a low gate voltage sVGL as a carry signal CR' with a low level. Therefore, in the second mode MODE2, the transmit signal EM and the carry signal CR' can have substantially the same phase, but the voltage difference between the high and low voltages of the carry signal CR' can be reduced compared to the voltage difference between the high and low voltages of the transmit signal EM, thereby reducing the power consumption of stage 400 and the transmit driver.

[0116] In the embodiment, under the second mode MODE2, such as Figure 20As shown, for example, the first clock signal CLK1, the second clock signal CLK2, the third node QB, and the transmit signal EM can all have a low gate voltage VGL as a low voltage; the second node Q2 can sequentially have a small low gate voltage sVGL and a boosted low gate voltage BVGL as low voltages; and the third clock signal CLK3, the input signal SIN', the carry signal CR', and the first node Q1 can all have a small low gate voltage sVGL as a low voltage, where the small low gate voltage sVGL has an absolute value smaller than the absolute value of the low gate voltage VGL. Therefore, the power consumption of stage 400 and the transmit driver can be reduced. Furthermore, stage 400 can receive an input signal SIN' with a low time interval shorter than or equal to a horizontal time interval, and can output a transmit signal EM with a low time interval shorter than or equal to a horizontal time interval and a carry signal CR' with a low time interval shorter than or equal to a horizontal time interval by delaying the input signal SIN' by a horizontal time interval. Therefore, the transmitter driver including stage 400 can operate normally not only in a first mode MODE1 (e.g., high brightness mode) in which the low period of the transmitted signal EM is longer than or equal to two horizontal time periods, but also in a second mode MODE2 (e.g., low brightness mode) in which the low period of the transmitted signal EM is shorter than or equal to one horizontal time period.

[0117] Figure 21 This is a circuit diagram illustrating an embodiment of the stage of the transmit driver.

[0118] refer to Figure 21 The stage 500 of the transmit driver in the embodiment may include an input circuit 210, a node separation circuit 230, a node control circuit 550, and an output circuit 270. The configuration of the node control circuit 550 of stage 500 can be... Figure 5 The node control circuit 250 of stage 200 is different. Furthermore, it differs from... Figure 5 The sixth transistor T6 is an NMOS transistor, unlike stage 200. All of the transistors in stage 500, including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5', the sixth transistor T6', the seventh transistor T7', the eighth transistor T8', and the ninth transistor T9, can be PMOS transistors.

[0119] The node control circuit 550 may include a fifth transistor T5', a sixth transistor T6', a seventh transistor T7', an eighth transistor T8', a ninth transistor T9, a second capacitor C2, and a third capacitor C3. In the first mode MODE1, the seventh transistor T7' can be turned off, the eighth transistor T8' can be turned on, and the node control circuit 550 can control the voltage of the third node QB by applying a first clock signal CLK1 to the third node QB via the sixth transistor T6' or by applying a high gate voltage VGH to the third node QB via the eighth transistor T8' and the ninth transistor T9. Furthermore, in the second mode MODE2, the seventh transistor T7' can be turned on, the eighth transistor T8' can be turned off, and the node control circuit 550 can control the voltage of the third node QB by applying a first clock signal CLK1 to the third node QB via the seventh transistor T7' (and / or the sixth transistor T6').

[0120] The fifth transistor T5' can apply a high gate voltage VGH to the fourth node N4 in response to the input signal SIN. The sixth transistor T6' can apply a first clock signal CLK1 to the third node QB in response to the voltage of the fourth node N4. The third capacitor C3 can be connected between the fourth node N4 and the line transmitting the first clock signal CLK1. The seventh transistor T7' can receive a high gate voltage VGH in the first mode MODE1 and a low gate voltage VGL in the second mode MODE2. The eighth transistor T8' can receive a low gate voltage VGL in the first mode MODE1 and a high gate voltage VGH in the second mode MODE2. The ninth transistor T9 can be connected in series with the eighth transistor T8' between the line transmitting the high gate voltage VGH and the third node QB, and can apply a high gate voltage VGH to the third node QB in response to the voltage of the first node Q1 in the first mode MODE1. The second capacitor C2 can be connected between the line transmitting the high gate voltage VGH and the third node QB.

[0121] In some embodiments, the fifth transistor T5' may include a gate for receiving the input signal SIN, a first terminal for receiving a high gate voltage VGH, and a second terminal connected to the fourth node N4. The sixth transistor T6' may include a gate connected to the fourth node N4, a first terminal connected to the third node QB, and a second terminal connected to the fifth node N5 and receiving the first clock signal CLK1. The seventh transistor T7' may include a gate for receiving a high gate voltage VGH in the first mode MODE1 and a low gate voltage VGL in the second mode MODE2, a first terminal connected to the third node QB, and a second terminal connected to the fifth node N5 and receiving the first clock signal CLK1. The eighth transistor T8' may include a gate for receiving a low gate voltage VGL in the first mode MODE1 and a high gate voltage VGH in the second mode MODE2, a first terminal for receiving the high gate voltage VGH, and a second terminal connected to the ninth transistor T9. The ninth transistor T9 may include a gate connected to the first node Q1, a first terminal connected to the second terminal of the eighth transistor T8', and a second terminal connected to the third node QB. The second capacitor C2 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the third node QB. The third capacitor C3 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5 and receiving the first clock signal CLK1.

[0122] Furthermore, in some embodiments, such as Figure 21 As shown, all of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5', sixth transistor T6', seventh transistor T7', eighth transistor T8', and ninth transistor T9 included in stage 500 can be PMOS transistors. In other embodiments, at least one of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5', sixth transistor T6', seventh transistor T7', eighth transistor T8', and ninth transistor T9 can be an NMOS transistor.

[0123] In the following text, see references Figure 6 and Figures 21 to 25 An example of the operation of level 500 in the first mode MODE1.

[0124] Figure 22 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the first time period. Figure 23 It is used to describe Figure 21 A circuit diagram illustrating an embodiment of the operation of the stage in the second time period. Figure 24 It is used to describe Figure 21A circuit diagram illustrating an embodiment of the operation of the stage in the third time period, and Figure 25 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the fourth time period.

[0125] Reference Figure 6 and Figure 21 In the first mode MODE1, stage 500 can receive an input signal SIN with a low time interval longer than or equal to two horizontal time intervals, and can output a transmit signal EM by delaying the input signal SIN by one horizontal time interval.

[0126] In an embodiment, such as Figure 6 and Figure 22 As shown, for example, during a first time period TP1 in which the input signal SIN has a high level H and the first clock signal CLK1 has a high level H, the first transistor T1 can be turned off in response to the first clock signal CLK1 having a high level H. Therefore, the input signal SIN is not transmitted to the first node Q1, the voltage of the first node Q1 can have a low level L as the previous level, and the voltage of the second node Q2 can have a boosted low level BL as the previous level. Furthermore, the fifth transistor T5' can be turned off in response to the input signal SIN, and the voltage of the fourth node N4 can have a high level H as the previous level. The voltage of the fifth node N5 can have a high level H based on the first clock signal CLK1. The sixth transistor T6' can be turned off in response to the voltage of the fourth node N4, and the seventh transistor T7' can be turned off in response to a high gate voltage VGH. The eighth transistor T8' can be turned on in response to a low gate voltage VGL, and the ninth transistor T9 can be turned on in response to the voltage of the first node Q1. The eighth transistor T8' and the ninth transistor T9 can transmit a high gate voltage VGH to the third node QB. Therefore, the voltage of the third node QB can have a high level H, and the third transistor T3 can be turned off in response to the voltage of the third node QB. The fourth transistor T4 can be turned on in response to the voltage of the second node Q2 and can output a low gate voltage VGL as a transmit signal EM. Therefore, a transmit signal EM with a low level L can be output at the output node NO.

[0127] like Figure 6 and Figure 23As shown, during the second time period TP2 in which the input signal SIN has a high level H and the first clock signal CLK1 has a low level L, the first transistor T1 can turn on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a high level H. The second transistor T2 can turn on in response to a low gate voltage VGL, and can transmit the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a high level H. The fourth transistor T4 can turn off in response to the voltage of the second node Q2. The fifth transistor T5' can turn off in response to the input signal SIN, and the seventh transistor T7' can turn off in response to a high gate voltage VGH. In addition, the eighth transistor T8' can turn on in response to a low gate voltage VGL, and the ninth transistor T9 can turn off in response to the voltage of the first node Q1. The voltage of the fifth node N5 to which the first clock signal CLK1 is applied can decrease from a high level H to a low level L. When the voltage at the fifth node N5 or the voltage at the second electrode of the third capacitor C3 decreases from a high level H to a low level L, the voltage at the first electrode of the third capacitor C3 or the voltage at the fourth node N4 can also decrease from a high level H to a low level L through the coupling of the third capacitor C3. The sixth transistor T6' can turn on in response to the voltage at the fourth node N4 and can transmit the first clock signal CLK1 with a low level L to the third node QB. Therefore, the voltage at the third node QB can have a low level L. The third transistor T3 can turn on in response to the voltage at the third node QB and can output a high gate voltage VGH as a transmit signal EM. Therefore, a transmit signal EM with a high level H can be output at the output node NO. In addition, stage 500 can output a transmit signal EM with a high level H during the period between the second time period TP2 and the third time period TP3.

[0128] After that, as Figure 6 and Figure 24As shown, during the third time period TP3, in which the input signal SIN has a low level L and the first clock signal CLK1 has a high level H, the first transistor T1 can be turned off in response to the first clock signal CLK1 having a high level H. Therefore, the input signal SIN is not transmitted to the first node Q1, the voltage of the first node Q1 can have a high level H as the previous level, the second transistor T2 can be turned on in response to a low gate voltage VGL, and the voltage of the second node Q2 can have a high level H as the previous level. The fourth transistor T4 can be turned off in response to the voltage of the second node Q2. The fifth transistor T5' can be turned on in response to the input signal SIN and can transmit a high gate voltage VGH to the fourth node N4. Therefore, the voltage of the fourth node N4 can have a high level H. The voltage of the fifth node N5 can have a high level H based on the first clock signal CLK1. The sixth transistor T6' can be turned off in response to the voltage of the fourth node N4, and the seventh transistor T7' can be turned off in response to a high gate voltage VGH. Furthermore, the eighth transistor T8' can be turned on in response to a low gate voltage VGL, and the ninth transistor T9 can be turned off in response to the voltage of the first node Q1. Therefore, the voltage of the third node QB can have a low level L as the previous level. The third transistor T3 can be turned on in response to the voltage of the third node QB and can output a high gate voltage VGH as the transmit signal EM. Therefore, even when the input signal SIN changes to a low level L, stage 500 can output a transmit signal EM with a high level H at the output node NO.

[0129] like Figure 6 and Figure 25As shown, during the fourth time period TP4, in which the input signal SIN has a low level L and the first clock signal CLK1 has a low level L, the first transistor T1 can turn on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a low level L. The fifth transistor T5' can turn on in response to the input signal SIN, and can transmit a high gate voltage VGH to the fourth node N4. Therefore, the voltage of the fourth node N4 can have a high level H. The voltage of the fifth node N5 can have a low level L based on the first clock signal CLK1. The sixth transistor T6' can turn off in response to the voltage of the fourth node N4, and the seventh transistor T7' can turn off in response to the high gate voltage VGH. The eighth transistor T8' can turn on in response to the low gate voltage VGL, the ninth transistor T9 can turn on in response to the voltage of the first node Q1, and the eighth transistor T8' and the ninth transistor T9 can transmit the high gate voltage VGH to the third node QB. Therefore, the voltage of the third node QB can be high (H), and the third transistor T3 can be turned off in response to the voltage of the third node QB. The second transistor T2 can be turned on in response to a low gate voltage VGL, and can transfer the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can be low (L). The fourth transistor T4 can be turned on in response to the voltage of the second node Q2, and can transfer the low gate voltage VGL to the output node NO. Therefore, the voltage of the output node NO connected to the second electrode of the first capacitor C1 can change from high (H) to low (L). Furthermore, when the voltage of the output node NO or the voltage of the second electrode of the first capacitor C1 decreases from high (H) to low (L), through the coupling of the first capacitor C1, the voltage of the first electrode of the first capacitor C1 or the voltage of the second node Q2 can also decrease from low (L) to the boost low (BL). The boost low level BL can be lower than the low gate voltage VGL applied to the gate of the second transistor T2, and therefore the second transistor T2 can prevent the voltage of the second node Q2 with the boost low level BL from being transmitted to the first node Q1. Furthermore, the fourth transistor T4 can be fully or fully turned on in response to the voltage of the second node Q2 with the boost low level BL, and can output a transmit signal EM with a low level L having a voltage level substantially the same as the low gate voltage VGL.

[0130] Stage 500 can continuously output a transmit signal EM with a low level L during the period following the fourth time period TP4, until the input signal SIN changes to a high level H and the first clock signal CLK1 goes low L in the next frame period. Therefore, in the first mode MODE1, stage 500 can output a transmit signal EM with a low period of time longer than or equal to two horizontal time periods.

[0131] In the following text, see references Figure 21 and Figures 26 to 29 An example of the operation of level 500 in the second mode MODE2.

[0132] Figure 26 It is used to describe Figure 21 A timing diagram of an embodiment of the operation of the level in the second mode. Figure 27 It is used to describe Figure 21 A circuit diagram illustrating an embodiment of the operation of the stage in the fifth time period. Figure 28 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the level in the sixth time period, and Figure 29 It is used to describe Figure 21 A circuit diagram of an embodiment of the operation of the stage in the seventh time period.

[0133] Reference Figure 21 and Figure 26 In the second mode MODE2, stage 500 can receive an input signal SIN with a short time interval shorter than or equal to a horizontal time interval, and can output a transmit signal EM by delaying the input signal SIN by a horizontal time interval.

[0134] In an embodiment, such as Figure 26 and Figure 27As shown, for example, in the fifth time period TP5' where the input signal SIN has a low level L and the first clock signal CLK1 has a low level L, the first transistor T1 can be turned on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a low level L. The fifth transistor T5' can be turned on in response to the input signal SIN, and can transmit a high gate voltage VGH to the fourth node N4. Therefore, the voltage of the fourth node N4 can have a high level H. The voltage of the fifth node N5 can have a low level L based on the first clock signal CLK1. The eighth transistor T8' can be turned off in response to the high gate voltage VGH, and the ninth transistor T9 can be turned on in response to the voltage of the first node Q1. The seventh transistor T7' can be turned on in response to the low gate voltage VGL, and can transmit the first clock signal CLK1 to the third node QB. Therefore, the voltage of the third node QB can have a low level L. The third transistor T3 can be turned on in response to the third node QB and can transmit the high gate voltage VGH to the output node NO. Furthermore, the second transistor T2 can be turned on in response to the low gate voltage VGL and can transmit the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a low level L. The fourth transistor T4 can be turned on in response to the voltage of the second node Q2 and can transmit the second clock signal CLK2 with a high level H to the output node NO. Therefore, in the fifth time period TP5', even when the input signal SIN has a low level L, stage 500 can still output a transmit signal EM with a high level H at the output node NO through the third transistor T3 and the fourth transistor T4.

[0135] like Figure 26 and Figure 28As shown, during the sixth time period TP6' in which the input signal SIN has a high level H and the first clock signal CLK1 has a high level H, the first transistor T1 can be turned off in response to the first clock signal CLK1 having a high level H. Therefore, the input signal SIN is not transmitted to the first node Q1, and the voltage of the first node Q1 can have a low level L as the previous level. Furthermore, the fifth transistor T5' can be turned off in response to the input signal SIN, the voltage of the fourth node N4 can have a high level H as the previous level, and the sixth transistor T6' can be turned off in response to the voltage of the fourth node N4. The voltage of the fifth node N5 can have a high level H based on the first clock signal CLK1. The eighth transistor T8' can be turned off in response to a high gate voltage VGH, and the ninth transistor T9 can be turned on in response to the voltage of the first node Q1. The seventh transistor T7' can be turned on in response to a low gate voltage VGL and can transmit the first clock signal CLK1 to the third node QB. Therefore, the voltage of the third node QB can have a high level H. The third transistor T3 can be turned off in response to the voltage of the third node QB. Furthermore, during the sixth time period TP6', the second clock signal CLK2 can decrease from a high level H to a low level L, and therefore, the voltage of the output node NO from which the second clock signal CLK2 is output can decrease from a high level H to a low level L. Additionally, when the voltage of the output node NO or the voltage of the second electrode of the first capacitor C1 decreases from a high level H to a low level L, through the coupling of the first capacitor C1, the voltage of the first electrode of the first capacitor C1 or the voltage of the second node Q2 can also decrease from a low level L to a boosted low level BL. The boosted low level BL can be lower than the low gate voltage VGL applied to the gate of the second transistor T2, and therefore the second transistor T2 can prevent the voltage of the second node Q2 with the boosted low level BL from being transmitted to the first node Q1. Furthermore, the fourth transistor T4 can be fully turned on in response to the voltage of the second node Q2 with the boosted low level BL, and can output a transmit signal EM with a low level L that is substantially the same as the voltage level (or low level L) of the second clock signal CLK2. Therefore, in the sixth time period TP6', even when the input signal SIN has a high level H, stage 500 can still output a transmit signal EM with a low level L at the output node NO.

[0136] like Figure 26 and Figure 29As shown, during the seventh time period TP7' in which the input signal SIN has a high level H and the first clock signal CLK1 has a low level L, the first transistor T1 can turn on in response to the first clock signal CLK1 having a low level L, and can transmit the input signal SIN to the first node Q1. Therefore, the voltage of the first node Q1 can have a high level H. The second transistor T2 can turn on in response to a low gate voltage VGL, and can transmit the voltage of the first node Q1 to the second node Q2. Therefore, the voltage of the second node Q2 can have a high level H. The fourth transistor T4 can turn off in response to the voltage of the second node Q2. The fifth transistor T5' can turn off in response to the input signal SIN, the eighth transistor T8' can turn off in response to a high gate voltage VGH, and the ninth transistor T9 can turn off in response to the voltage of the first node Q1. The voltage of the fifth node N5 to which the first clock signal CLK1 is applied can decrease from a high level H to a low level L. When the voltage at the fifth node N5 or the voltage at the second electrode of the third capacitor C3 decreases from a high level H to a low level L, the voltage at the first electrode of the third capacitor C3 or the voltage at the fourth node N4 can also decrease from a high level H to a low level L through the coupling of the third capacitor C3. The sixth transistor T6' can turn on in response to the voltage at the fourth node N4, and the seventh transistor T7' can turn on in response to a low gate voltage VGL. Therefore, the sixth transistor T6' and the seventh transistor T7' can transmit the first clock signal CLK1 with a low level L to the third node QB, and the voltage at the third node QB can have a low level L. The third transistor T3 can turn on in response to the voltage at the third node QB and can output a high gate voltage VGH as the transmit signal EM. Therefore, in the seventh time period TP7', stage 500 can output the transmit signal EM with a high level H at the output node NO.

[0137] Level 500 can continuously output a transmit signal EM with a high level H during the period following the seventh time period TP7', until the input signal SIN changes to a low level L and the first clock signal CLK1 and the second clock signal CLK2 sequentially change to a low level L in the next frame period. For example... Figure 26As shown, even when the voltage of the third node QB periodically transitions between high level H and low level L and the third transistor T3 is periodically turned off, the transmit signal EM can remain at high level H until the fourth transistor T4 is turned on. Therefore, stage 500 can output a transmit signal EM with a low period shorter than or equal to one horizontal time period in the second mode MODE2. That is, the transmit driver in the embodiment can operate normally not only in the first mode MODE1 (e.g., high brightness mode) where the low period of the transmit signal EM is longer than or equal to two horizontal time periods, but also in the second mode MODE2 (e.g., low brightness mode) where the low period of the transmit signal EM is shorter than or equal to one horizontal time period.

[0138] Figure 30 This is a block diagram illustrating an embodiment of a display device including a transmit driver.

[0139] refer to Figure 30 The display device 1000 in the embodiment may include: a display panel 1010 including a plurality of pixels PX; a data driver 1030 providing data signals DS to the plurality of pixels PX; a scan driver 1050 providing scan signals SS to the plurality of pixels PX; a transmit driver 1070 providing transmit signals EM to the plurality of pixels PX; and a controller 1090 controlling the data driver 1030, the scan driver 1050 and the transmit driver 1070.

[0140] Display panel 1010 may include data lines, scan lines, emission lines, and a plurality of pixels PX connected to the data lines, scan lines, and emission lines. Each pixel PX may emit light in response to an emission signal EM provided from emission driver 1070. In some embodiments, each pixel PX may emit light when the emission signal EM has a low level, and therefore the emission period of pixel PX may correspond to the low period of the emission signal EM, but is not limited thereto. Furthermore, each pixel PX may include a light-emitting element, and display panel 1010 may be a light-emitting display panel. In some embodiments, the light-emitting element may be, but is not limited to, a micro light-emitting diode. In other embodiments, the light-emitting element may be an organic light-emitting diode (“OLED”), a nano light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0141] The data driver 1030 can generate a data signal DS based on the data control signal DCTRL received from the controller 1090 and the output image data ODAT, and can provide the data signal DS to multiple pixels PX via data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. In some embodiments, the data driver 1030 and the controller 1090 can be implemented as a single integrated circuit, and this single integrated circuit may also be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In other embodiments, the data driver 1030 and the controller 1090 can be implemented as separate integrated circuits.

[0142] The scan driver 1050 can generate a scan signal SS based on the scan control signal SCTRL received from the controller 1090, and can sequentially provide the scan signal SS to multiple pixels PX line by line via scan lines. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. Furthermore, in some embodiments, the scan driver 1050 may be integrated or formed in the display panel 1010. In other embodiments, the scan driver 1050 may be implemented using one or more integrated circuits.

[0143] The transmit driver 1070 can generate a transmit signal EM based on a transmit control signal EMCTRL received from the controller 1090, and can sequentially provide the transmit signal EM to multiple pixels PX row by row via transmit lines. In some embodiments, the transmit control signal EMCTRL may include, but is not limited to, a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2. The transmit driver 1070 may include... Figure 1 The diagram shows multiple stages STG1, STG2, STG3, STG4, etc., that sequentially provide the transmitted signal EM to multiple pixels PX. In some embodiments, such as Figure 1As shown, the odd-numbered stages STG1, STG3, etc. (or the output circuits of the odd-numbered stages STG1, STG3, etc.) of the transmitter driver 1070 can receive a low gate voltage VGL in the first mode MODE1 and a second clock signal CLK2 in the second mode MODE2. Furthermore, the even-numbered stages STG2, STG4, etc. (or the output circuits of the even-numbered stages STG2, STG4, etc.) of the transmitter driver 1070 can receive a low gate voltage VGL in the first mode MODE1 and a first clock signal CLK1 in the second mode MODE2. Therefore, the transmitter driver 1070 can output a transmitter signal EM with a low time period longer than or equal to two horizontal time periods in the first mode MODE1, and can output a transmitter signal EM with a low time period shorter than or equal to one horizontal time period in the second mode MODE2. In some embodiments, the transmitter driver 1070 can be integrated or formed in the display panel 1010. In other embodiments, the transmitter driver 1070 can be implemented using one or more integrated circuits.

[0144] Controller 1090 (e.g., a timing controller) can receive input image data IDAT and control signal CTRL from an external processor (e.g., a graphics processing unit (“GPU”), application processor (“AP”), or graphics card). In some embodiments, the input image data IDAT may be red, green, and blue (“RGB”) image data including red, green, and blue image data. The control signal CTRL may include a depth-of-field (DBV) representing the brightness of the display device 1000 corresponding to the maximum gray level (e.g., 255 gray levels). In some embodiments, when the DBV is greater than or equal to a reference viewing brightness value, controller 1090 may determine the mode of the display device 1000 as a first mode MODE1, and when the DBV is less than the reference viewing brightness value, it may determine the mode of the display device 1000 as a second mode MODE2. In the first mode MODE1, the controller 1090 can provide the transmit driver 1070 with a start signal FLM having a short duration longer than or equal to two horizontal time periods, and can provide a low gate voltage VGL to the output circuits of the multiple stages STG1, STG2, STG3, STG4, etc. of the transmit driver 1070. Furthermore, in the second mode MODE2, the controller 1090 can provide the transmit driver 1070 with a start signal FLM having a short duration shorter than or equal to one horizontal time period, can provide a second clock signal CLK2 to the output circuits of odd-numbered stages STG1, STG3, etc., and can provide a first clock signal CLK1 to the output circuits of even-numbered stages STG2, STG4, etc. In some embodiments, the control signal CTRL may also include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 1090 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTL based on the input image data IDAT and the control signal CTRL. The controller 1090 can control the operation of the data driver 1030 by providing output image data ODAT and data control signal DCTRL to the data driver 1030, control the operation of the scan driver 1050 by providing scan control signal SCTRL to the scan driver 1050, and control the operation of the transmit driver 1070 by providing transmit control signal EMCTRL to the transmit driver 1070.

[0145] In the display device 1000 of the embodiment, the output circuit of at least one stage of the transmitter driver 1070 can output a low gate voltage VGL as a transmitter signal EM in a first mode MODE1, and can output a clock signal (e.g., a first clock signal CLK1 or a second clock signal CLK2) as a transmitter signal EM in a second mode MODE2. Therefore, the transmitter driver 1070 can operate normally not only in the first mode MODE1 (e.g., high brightness mode) in which the conduction period (e.g., low period) of the transmitter signal EM is longer than or equal to two horizontal time periods, but also in the second mode MODE2 (e.g., low brightness mode) in which the conduction period of the transmitter signal EM is shorter than one horizontal time period.

[0146] Figure 31 This is a block diagram illustrating an embodiment of an electronic device including a display device.

[0147] refer to Figure 31 Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (“I / O”) device 1140, a power supply 1150, and a display device 1160. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc.

[0148] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be connected to other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 can also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0149] Memory device 1120 may store data for the operation of electronic device 1100. In embodiments, for example, memory device 1120 may include at least one non-volatile memory device, such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device, such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (“mobile DRAM”) device, and the like.

[0150] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 can be connected to other components via a bus or other communication link.

[0151] In the display device 1160, the output circuit of at least one stage of the transmitter driver can output a low gate voltage as a transmitter signal in a first mode (e.g., high brightness mode) and can output a clock signal as a transmitter signal in a second mode (e.g., low brightness mode). Therefore, the transmitter driver is applicable not only to high brightness modes in which the conduction period (e.g., low period) of the transmitter signal is longer than or equal to two horizontal time periods, but also to low brightness modes in which the conduction period of the transmitter signal is shorter than or equal to one horizontal time period.

[0152] The inventive concept can be applied to any electronic device 1100 including display device 1160. In embodiments, for example, the inventive concept can be applied to virtual reality (“VR”) devices, augmented reality (“AR”) devices, mixed reality (“MR”) devices, extended reality (“XR”) devices, mobile phones, smartphones, televisions (“TV”) (e.g., digital TV, 3D TV, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptops, tablets, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0153] The foregoing is illustrative of the embodiments and should not be construed as limiting them. Although several embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting oneself to the disclosed illustrative embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A transmit driver, comprising multiple stages, wherein the stages include: The input circuit is configured to transmit an input signal to the first node in response to a first clock signal; A node separation circuit is connected between the first node and the second node and is configured to receive a low gate voltage having a first voltage level. The node control circuit is configured to control the voltage of the third node based on the voltage of the first node, a high gate voltage having a second voltage level higher than the first voltage level, and the low gate voltage. as well as The output circuit is configured to output a high gate voltage as a transmit signal in response to the voltage of the third node, to output a low gate voltage as the transmit signal in response to the voltage of the second node in a first mode, and to output a second clock signal different from the first clock signal as the transmit signal in response to the voltage of the second node in a second mode.

2. The transmit driver according to claim 1, wherein, The output circuit outputs the transmission signal having a low period of time longer than or equal to two horizontal time periods in the first mode, and outputs the transmission signal having a low period of time shorter than or equal to one horizontal time period in the second mode, wherein the transmission signal has the first voltage level in the low period of time.

3. The transmit driver according to claim 1, wherein, The first mode is a high-brightness mode that displays a brightness value greater than or equal to a reference value, and The second mode is a low-brightness mode where the display brightness value is less than the reference value.

4. The transmit driver according to claim 1, wherein, The second clock signal is delayed by half a clock period compared to the first clock signal.

5. The transmit driver according to claim 4, wherein, The clock period corresponds to two horizontal time periods, and The second clock signal is delayed by a horizontal time period compared to the first clock signal.

6. The transmit driver according to claim 1, wherein, The input circuit includes: The first transistor includes a gate for receiving the first clock signal, a first terminal for receiving the input signal, and a second terminal connected to the first node.

7. The transmit driver according to claim 1, wherein, The node separation circuit includes: The second transistor includes a gate for receiving the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the second node.

8. The transmit driver according to claim 1, wherein, The output circuit includes: The third transistor includes a gate connected to the third node, a first terminal receiving the high gate voltage, and a second terminal connected to an output node that outputs the transmit signal; A first capacitor includes a first electrode connected to the second node and a second electrode connected to the output node; and The fourth transistor includes a gate connected to the second node, a first terminal connected to the output node, and a second terminal that receives the low gate voltage in the first mode and the second clock signal in the second mode.

9. The transmit driver according to claim 1, wherein, The node control circuit includes: The fifth transistor includes a gate connected to the first node, a first terminal receiving the high gate voltage, and a second terminal connected to the third node; The sixth transistor includes a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving the low gate voltage; and The second capacitor includes a first electrode that receives the high gate voltage and a second electrode connected to the third node.

10. The transmit driver according to claim 9, wherein, The fifth transistor is a P-type metal-oxide-semiconductor transistor, and The sixth transistor is an N-type metal-oxide-semiconductor transistor.

11. The transmit driver according to claim 9, wherein, The level also includes: The carry circuit is configured to output a high gate voltage as a carry signal in response to the voltage of the third node, output a low gate voltage as a carry signal in response to the voltage of the second node in the first mode, and output a second clock signal as a carry signal in response to the voltage of the second node in the second mode.

12. The transmit driver according to claim 11, wherein, The carry circuit includes: The seventh transistor includes a gate connected to the third node, a first terminal receiving the high gate voltage, and a second terminal connected to the carry node outputting the carry signal; and The eighth transistor includes a gate connected to the second node, a first terminal connected to the carry node, and a second terminal that receives the low gate voltage in the first mode and the second clock signal in the second mode.

13. The transmit driver according to claim 1, wherein, The level also includes: A carry circuit is configured to output a high gate voltage as a carry signal in response to the voltage of the third node, output a small low gate voltage as a carry signal in response to the voltage of the second node in the first mode, having an absolute value smaller than the absolute value of the low gate voltage, and output a third clock signal as the carry signal in response to the voltage of the second node in the second mode. The third clock signal has the same phase as the second clock signal and has the small low gate voltage as a low voltage.

14. The transmit driver according to claim 1, wherein, The node control circuit includes: The fifth transistor is configured to apply the high gate voltage to the fourth node in response to the input signal; The sixth transistor is configured to apply the first clock signal to the third node in response to the voltage of the fourth node; The third capacitor includes a first electrode connected to the fourth node and a second electrode that receives the first clock signal; The seventh transistor is configured to be turned off in the first mode and to apply the first clock signal to the third node in the second mode; The eighth transistor is configured to be turned on in the first mode and turned off in the second mode; A ninth transistor, connected in series with the eighth transistor between the line transmitting the high gate voltage and the third node, and configured to apply the high gate voltage to the third node in response to the voltage of the first node in the first mode; and The second capacitor includes a first electrode that receives the high gate voltage and a second electrode connected to the third node.

15. The transmit driver according to claim 14, wherein, The fifth transistor includes a gate for receiving the input signal, a first terminal for receiving the high gate voltage, and a second terminal connected to the fourth node. The sixth transistor includes a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal for receiving the first clock signal. The seventh transistor includes a gate that receives the high gate voltage in the first mode and the low gate voltage in the second mode, a first terminal connected to the third node, and a second terminal that receives the first clock signal. The eighth transistor includes a gate that receives the low gate voltage in the first mode and the high gate voltage in the second mode, a first terminal that receives the high gate voltage, and a second terminal. The ninth transistor includes a gate connected to the first node, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the third node.

16. The transmit driver according to claim 15, wherein, The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type metal-oxide-semiconductor transistors.

17. Electronic devices, including: The processor is configured to provide input image data; as well as A display device configured to receive the input image data from the processor and display an image based on the input image data, the display device comprising: The display panel includes multiple pixels; A data driver is configured to provide data signals to the plurality of pixels; A scan driver is configured to provide scan signals to the plurality of pixels; A transmit driver includes multiple stages that sequentially provide transmit signals to the plurality of pixels, wherein the stages include: The input circuit is configured to transmit an input signal to the first node in response to a first clock signal; A node separation circuit is connected between the first node and the second node and is configured to receive a low gate voltage having a first voltage level. A node control circuit is configured to control the voltage of a third node based on the voltage of the first node, a high gate voltage having a second voltage level higher than the first voltage level, and the low gate voltage; and An output circuit is configured to output a high gate voltage as a corresponding transmit signal among the transmit signals in response to the voltage of the third node, output a low gate voltage as the corresponding transmit signal in response to the voltage of the second node in a first mode, and output a second clock signal different from the first clock signal as the corresponding transmit signal in response to the voltage of the second node in a second mode; and The controller is configured to control the data driver, the scan driver, and the transmit driver.

18. The electronic device according to claim 17, wherein, The controller receives a display brightness value, and determines the mode of the display device as the first mode when the display brightness value is greater than or equal to a reference brightness value, and determines the mode of the display device as the second mode when the display brightness value is less than the reference brightness value.

19. The electronic device according to claim 17, wherein, The controller provides the transmitter driver with a start signal having a low period of time longer than or equal to two horizontal time periods in the first mode, and provides the start signal with a low period of time shorter than or equal to one horizontal time period in the second mode, wherein the start signal has the first voltage level during the low period of time.

20. The electronic device according to claim 17, wherein, In the first mode, the controller provides the low gate voltage to the output circuits of the plurality of stages, and In the second mode, the controller provides one of the first clock signal and the second clock signal to the odd-numbered output circuits among the plurality of output circuits, and provides the remaining one of the first clock signal and the second clock signal to the even-numbered output circuits among the plurality of output circuits.

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