Digital drive circuits and methods applicable to strong overload conditions of grid-type converters

Abstract

This invention discloses a digital drive circuit suitable for strong overload conditions of grid-type converters, including an FPGA. The FPGA has a PWM signal input terminal, square wave signal output terminals S1 and S2, a control signal output terminal, and a data processing terminal I. G(peak) The data receiving terminals Ov1~Ov3 and the square wave signal output terminals S1 and S2 are connected to a variable voltage circuit. The control signal output terminal is connected to a gate drive circuit. The data processing terminal I... G(peak) A junction temperature acquisition circuit is connected, and data receiving terminals Ov1~Ov3 are connected to an overload monitoring circuit; the output terminal of the variable voltage circuit is connected to the gate drive circuit. This invention discloses a digital drive circuit and method suitable for strong overload conditions in grid-type converters, solving the problem of low transient overload capability of power electronic devices in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of power device overload performance improvement technology, specifically relating to a digital drive circuit suitable for strong overload conditions of grid-type converters, and also to a digital drive method suitable for strong overload conditions of grid-type converters. Background Technology

[0002] During grid faults or sudden load changes, power electronic converters need to output high-power current to support the grid for a short period. However, existing power electronic devices have limited overload output capabilities. High-power output can cause a rapid accumulation of heat inside the devices and a rapid increase in junction temperature, leading to device failure or malfunction. Therefore, to ensure the long-term stable operation of the grid, it is essential to effectively manage transient thermal loads and improve the transient overload capability of power electronic devices.

[0003] Currently, there are three main methods to improve the transient overload capability of power electronic devices: paralleling multiple devices, improving the system's heat dissipation capacity, or using wide-bandgap semiconductors. However, paralleling devices increases hardware costs, and heat dissipation capacity is limited by material costs and physical limitations. Using wide-bandgap semiconductors, such as typical SiC MOSFETs, offers superior electrothermal characteristics including high frequency, high temperature, and low loss. Compared to IGBTs, SiC MOSFETs have a lower internal junction temperature under the same overload. Combined with novel digital drive circuits and methods, the junction temperature can be further managed, improving the overload capability of power electronic devices. Therefore, designing suitable digital drive circuits and methods to optimize the SiC MOSFET state under overload is crucial for enhancing the device's overload capability. Summary of the Invention

[0004] The primary objective of this invention is to provide a digital drive circuit suitable for strong overload conditions in grid-type converters, thereby addressing the problem of low transient overload capability of power electronic devices in the prior art.

[0005] The second objective of this invention is to provide a digital drive method suitable for strong overload conditions of grid-type converters.

[0006] The first technical solution adopted in this invention is a digital drive circuit suitable for strong overload conditions of grid-type converters, connected to the SiC MOSFET under test, including an FPGA. The FPGA has a PWM signal input terminal, square wave signal output terminals S1 and S2, a control signal output terminal, and a data processing terminal I. G(peak) With data receiving terminals Ov1~Ov3; Square wave signal output terminals S1 and S2 are respectively connected to variable voltage circuits, control signal output terminal is connected to gate drive circuit, and data processing terminal I... G(peak)It is connected to a junction temperature acquisition circuit, and the data receiving terminals Ov1~Ov3 are connected to an overload monitoring circuit; the output terminal of the variable voltage circuit is connected to the gate drive circuit.

[0007] The first technical solution of this invention is also characterized in that, The variable voltage circuit consists of a low-pass filter, a voltage follower OPA1, and a power management chip U1 connected in series. The low-pass filter is composed of a resistor R1 and a capacitor C1. One end of resistor R1 is connected to the square wave signal output terminal S1 or S2 of the FPGA, and the other end of resistor R1 is connected to capacitor C1 and the positive input terminal of voltage follower OPA1. The other end of capacitor C1 is connected to ground. The negative input terminal of voltage follower OPA1 is connected to its own output terminal, and the output terminal of voltage follower OPA1 is connected to the feedback pin of power management chip U1. V OUT Output pins of power management chip U1 V OUT include V OUT1 and V OUT2 , V OUT1 and V OUT2 They are connected to the gate drive circuit respectively.

[0008] The gate drive circuit includes 5 switching devices K1~K5 and a drive resistor R. G and the acquisition resistor R acq Switches K1 to K5 are connected to the control signal output terminal respectively, and one end of switch K1 is connected to... V OUT1 The other end of switching device K1 is connected to switching device K2 and drive resistor R. G One end of the switching device K2 is grounded, and the other end of the driving resistor R is connected. G The other end is connected to the gate of the SiC MOSFET; one end of the switching device K3 is connected to... V OUT2 The other end of switching device K3 is connected to the source of switching device K4 and the SiC MOSFET; one end of switching device K5 is connected to... V OUT1 The other end of the switching device K5 is connected to the acquisition resistor R. acq One end, the sampling resistor R acq The other end is connected to the gate of the SiC MOSFET.

[0009] The junction temperature acquisition circuit includes a differential operational amplifier U2, whose input terminal is connected to the acquisition resistor R in the gate resistor network. acqThe differential operational amplifier U2 is electrically connected to operational amplifier U3 at both ends. Resistors R2 and R3 are connected to the negative input of operational amplifier U3. The other end of resistor R2 is connected to the bias voltage VEE, and the other end of resistor R3 is connected to the output of operational amplifier U3. The output of operational amplifier U3 is electrically connected to transconductance operational amplifier U4. Diodes D1 and D2 are connected to the output of transconductance operational amplifier U4. The other end of diode D1 is grounded, and the other end of diode D2 is connected to MOSFET Q1 and resistor R4. MOSFET Q1 is connected to the power supply VCC and is also connected to resistor R5 and voltage buffer U5. The negative input of transconductance operational amplifier U4 is connected to the output of voltage buffer U5. Resistor R4 is connected to capacitor C2, with the other end of capacitor C2 grounded. The other end of resistor R5 is also grounded. Voltage buffer U5 is connected to an ADC. The ADC output is connected to the FPGA's data processing terminal I. G(peak) connect.

[0010] The overload monitoring circuit includes a sampling resistor R, which is connected to three current sensing amplifiers INA1, INA2, and INA3. Current limiting resistors R6 to R11 are connected between the sampling resistor R and the three current sensing amplifiers. R6 and R7 are connected between current sensing amplifier INA1 and the sampling resistor R. R8 and R9 are connected between current sensing amplifier INA2 and the sampling resistor R. R10 and R11 are connected between current sensing amplifier INA3 and the sampling resistor R. Comparators U6, U7, and U8 are connected to the outputs of current sensing amplifiers INA1, INA2, and INA3, respectively. The negative input pins of comparators U6, U7, and U8 are connected to reference voltages Vref1, Vref2, and Vref3, respectively. The outputs of comparators U6, U7, and U8 are connected to the data receiving terminals Ov1 to Ov3 of the FPGA.

[0011] The second technical solution adopted in this invention is a digital drive method applicable to strong overload conditions of grid-type converters. It acquires the overload indication signal of SiC MOSFET in real time, and intermittently acquires the gate peak current to obtain junction temperature data at a sampling frequency lower than the switching frequency. When it is determined that the device is overloaded or the junction temperature exceeds the threshold, the duty cycle of the control signal of the variable voltage circuit is adjusted to change the amplitude of the turn-on gate voltage and the turn-off gate voltage. The higher the degree of overload, the greater the adjustment range of the gate voltage amplitude, and the amplitude increment is limited at low overload to suppress electrical stress. The loss is reduced by dynamically adjusting the gate voltage, and a closed-loop feedback is formed based on the junction temperature data until the junction temperature recovers to within the safe threshold.

[0012] The second technical solution of the present invention is further characterized in that, Specifically, the following steps are included: S1 samples the drain current of the SiC MOSFET in real time through the overload monitoring circuit, compares the sampled voltage with multiple preset reference voltages, generates overload indication signals corresponding to different overload levels, and transmits them to the FPGA; S2, the junction temperature acquisition circuit acquires the gate peak current signal related to the junction temperature of the SiC MOSFET at a set acquisition time, and transmits it to the FPGA to be converted into junction temperature data; S3, the FPGA compares the junction temperature data with the preset safe junction temperature threshold, and at the same time determines the current overload level based on the overload indication signal; S4. If the junction temperature data exceeds the safe junction temperature threshold or the current overload level indicator device is in an overload state, the FPGA adjusts the control signal output to the variable voltage circuit to change the amplitude of the gate voltage on and gate voltage off of the gate drive circuit. S5 applies the adjusted turn-on and turn-off gate voltages to the SiC MOSFET to reduce device turn-on losses, turn-off losses, and conduction losses, thereby reducing junction temperature; S6. After adjusting the gate voltage, repeat S2 to S4 until the junction temperature data is lower than the safe junction temperature threshold, thus forming a closed-loop feedback control.

[0013] In S1, multiple preset reference voltages correspond to reference voltage values ​​for 1x overload, 2x overload, and 3x overload, respectively. Three overload indication signals Ov1, Ov2, and Ov3 are generated through three comparison branches. The FPGA determines the current overload level based on the logic combination of Ov1 to Ov3. The higher the overload level, the greater the adjustment of the gate voltage amplitude.

[0014] The specific steps for the junction temperature acquisition circuit in S2 to obtain the gate peak current signal are as follows: The FPGA closes switches K4 and K5 during the PWM high level according to the preset acquisition frequency, so that the gate drive circuit switches to the acquisition mode; in the acquisition mode, the turn-on voltage passes through the acquisition resistor R acq Applied to the gate of the SiC MOSFET, and at the sampling resistor R acq The gate peak current is generated; the junction temperature acquisition circuit affects the acquisition resistor R. acq The voltage across the terminals is differentially amplified, biased, peak held, and converted from analog to digital to obtain a digital signal that is linearly related to the junction temperature; the acquisition frequency is lower than the switching frequency of the SiC MOSFET.

[0015] S4 employs a tiered adjustment strategy when adjusting the gate voltage amplitude in the FPGA: When the overload is 1 or 2 times and the junction temperature exceeds the limit, the increase in gate voltage amplitude is limited to reduce the electrical stress of the device switching, taking into account both the device junction temperature and electrical stress. When the overload is 3 times, the main focus is on the device junction temperature, ensuring that the junction temperature drops to within the safe threshold, and allowing the gate voltage amplitude to be the maximum gate voltage that the device can withstand.

[0016] In S4, the control signals for the FPGA to adjust the variable voltage circuit are square wave signals S1 and S2. By changing the duty cycle of the square wave signals, and through low-pass filtering, voltage follower OPA1 and power management chip U1 feedback control, the gate voltage on and gate voltage off can be adjusted. The gate drive circuit achieves turn-on, turn-off, and acquisition mode switching through the combination control of five switching devices K1~K5: In turn-on mode, switches K1 and K4 are closed, so that the turn-on voltage passes through the drive resistor R. G In turn-off mode, switches K3 and K2 are closed, causing the turn-off voltage to be applied to the gate in reverse; in acquisition mode, switches K5 and K4 are closed, causing the turn-on voltage to be applied to the gate through the acquisition resistor R. acq Applied to the gate.

[0017] The beneficial effects of this invention are: (1) The circuit and method provided by the present invention can effectively reduce the junction temperature of SiC MOSFET devices under overload. The circuit status is monitored in real time by the overload monitoring circuit. When the device is overloaded, the gate voltage is adjusted in time to reduce the junction temperature of the device. The junction temperature monitoring circuit determines whether the current junction temperature of the device is within the safe threshold and whether the gate voltage needs to be adjusted again. The closed-loop circuit design enables the device to withstand long-term overload and improves the overload capacity of the device.

[0018] (2) The present invention takes into account the contradiction between junction temperature and electrical stress under overload conditions, and sets up overload monitoring circuits of different degrees. Under low overload conditions, a lower gate voltage (greater than the driving voltage under normal conditions) is selected, which can reduce the junction temperature of the device and ensure that the device works within a safe junction temperature range, and also avoid excessive electrical stress on the device when switching. Attached Figure Description

[0019] Figure 1 This is a connection diagram of the digital drive circuit and method applicable to the strong overload condition of grid-type converters according to the present invention; Figure 2 This is a schematic diagram of the variable voltage circuit of the present invention; Figure 3 This is a schematic diagram of the gate drive circuit of the present invention; Figure 4 This is a schematic diagram of the gate drive circuit of the present invention. Figure 5 This is a schematic diagram of the junction temperature acquisition circuit of the present invention; Figure 6 This is a schematic diagram of the overload monitoring circuit of the present invention. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0021] Example 1 like Figure 1 As shown, this embodiment provides a digital drive circuit suitable for strong overload conditions of grid-type converters, connected to the SiC MOSFET under test, including an FPGA. The FPGA has a PWM signal input terminal, square wave signal output terminals S1 and S2, a control signal output terminal, and a data processing terminal I. G(peak) The data receiving terminals Ov1~Ov3 and the square wave signal output terminals S1 and S2 are connected to a variable voltage circuit. The control signal output terminal is connected to a gate drive circuit. The data processing terminal I... G(peak) It is connected to a junction temperature acquisition circuit, and the data receiving terminals Ov1~Ov3 are connected to an overload monitoring circuit; the output terminal of the variable voltage circuit is connected to the gate drive circuit.

[0022] The FPGA receives external PWM signals, processes them, and generates control signals for the gate drive circuit. This causes the SiC MOSFET device to turn on when the PWM signal is high and turn off when the PWM signal is low. A sampling frequency is set. After counting to the sampling frequency, the junction temperature is sampled during the next cycle's PWM high level. The counter is then reset to count the next sampling frequency and resume normal on / off operation. The normal on / off state of the SiC MOSFET device is controlled by the drive resistor R. G Junction temperature is achieved by using a sampling resistor R. acq This is achieved by using a sampling frequency much lower than the switching frequency of SiC MOSFETs, reducing the self-heating of the sampling resistor, and improving sampling accuracy and junction temperature monitoring accuracy.

[0023] The FPGA outputs square wave signals S1 and S2 to the variable voltage circuit, which regulates the output voltage of the gate drive circuit. This changes the drive voltage when the junction temperature rises or the device is overloaded, lowering the junction temperature and allowing the device to operate for a longer period under strong overload conditions without damage, thus improving the short-term overload capability of power electronic devices. The overload monitoring circuit monitors the current flowing through the SiC MOSFET device through a sampling resistor R, compares it with reference voltages corresponding to different overload levels, and generates three overload signals Ov1, Ov2, and Ov3, which are sent to the FPGA. The FPGA then determines the overload level of the SiC MOSFET device, using this as a criterion for whether the drive voltage needs to be changed.

[0024] Example 2 Based on Example 1, such as Figure 2As shown in the figure, this embodiment provides a specific structure of a variable voltage circuit. The variable voltage circuit consists of a low-pass filter, a voltage follower OPA1, and a power management chip U1 connected in series. The low-pass filter consists of a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the square wave signal output terminal S1 or S2 of the FPGA, and the other end of the resistor R1 is connected to the capacitor C1 and the positive input terminal of the voltage follower OPA1. The other end of the capacitor C1 is connected to ground. The negative input terminal of the voltage follower OPA1 is connected to its own output terminal, and the output terminal of the voltage follower OPA1 is connected to the feedback pin of the power management chip U1. V OUT Output pins of power management chip U1 V OUT include V OUT1 and V OUT2 , V OUT1 and V OUT2 They are connected to the gate drive circuit respectively.

[0025] In this embodiment, the FPGA outputs high-frequency control signals S1 or S2 with different duty cycles. These signals are transmitted through a low-pass filter (composed of R1 and C1) to attenuate the high-frequency signals and generate a stable voltage signal on the capacitor. The signal is then passed through a voltage follower OPA1 to generate a signal with strong load-carrying capacity. This signal acts on the feedback pin of the power management chip U1, causing the chip's output voltage to change with the feedback pin voltage, thus forming a variable voltage circuit controlled by the FPGA.

[0026] Furthermore, resistor R1 in the low-pass filter also has a current-limiting function to prevent excessive current from damaging the capacitor; capacitor C1 charges when the input control signal is high and discharges when it is low, while filtering out high-frequency ripple in the control signal to prevent ripple from damaging the power management chip; voltage follower OPA1 has a high input impedance, so it will not affect the output voltage value of the low-pass filter, and has a low output impedance and strong driving capability, enabling it to drive the feedback pin of power management chip U1, thus achieving control over the voltage output of the low-pass filter. V OUT1 The OPA1 provides control over the variable voltage circuit and isolates the front-end low-pass filter from the back-end power management chip, preventing mutual interference and avoiding unstable output, howling, or oscillation of the variable voltage circuit.

[0027] This embodiment has two variable voltage circuits, one of which is in the gate drive circuit. V OUT1 , V OUT2The power supply, combined with the gate drive circuit, generates variable turn-on and turn-off gate voltages, achieving controllable adjustment of both voltages. Adjusting the dual gate voltages can further reduce the junction temperature of the SiC MOSFET device under overload conditions, improving the device's overload capability.

[0028] Example 3 Based on the above embodiments, such as Figure 3 As shown, this embodiment provides a specific structure of the gate drive circuit, which includes five switching devices K1~K5 and a drive resistor R. G and the acquisition resistor R acq Switches K1 to K5 are connected to the control signal output terminal respectively, and one end of switch K1 is connected to... V OUT1 The other end of switching device K1 is connected to switching device K2 and drive resistor R. G One end of the switching device K2 is grounded, and the other end of the driving resistor R is connected. G The other end is connected to the gate of the SiC MOSFET; one end of the switching device K3 is connected to... V OUT2 The other end of switching device K3 is connected to switching device K4 and the source of the SiC MOSFET; one end of switching device K5 is connected to... V OUT1 The other end of the switching device K5 is connected to the acquisition resistor R. acq One end, the sampling resistor R acq The other end is connected to the gate of the SiC MOSFET.

[0029] In this embodiment, the gate drive circuit consists of five sets of switching devices. The switching devices K1~K5 are controlled by the FPGA output signal terminal to realize the turn-on and turn-off of the SiC MOSFET device and the junction temperature acquisition.

[0030] When the SiC MOSFET device needs to be turned on, switching devices K1 and K4 are closed simultaneously, forming a switch from... V OUT1 The current flows from the loop to ground (GND). V OUT1 Initially, current flows through switching device K1 and gate drive resistor R respectively. G The SiC MOSFET device and switching device K4 are returned to GND. A connection is formed between the gate and source of the SiC MOSFET device. V OUT1 When the gate-source voltage is high, it is greater than the device threshold voltage, thus turning on the device.

[0031] When the SiC MOSFET device needs to be turned off, switching devices K2 and K3 close simultaneously, forming a switch from... V OUT2The current flows from the loop to ground (GND). V OUT2 Initially, current flows through switch K3, the SiC MOSFET device, and the gate drive resistor R, respectively. G And switch K2, back to GND. A gate-source junction is formed between the gate and source of the SiC MOSFET device. V OUT2 When the gate-source voltage is low, the gate-source voltage is less than the device threshold voltage, thus turning off the device.

[0032] When it is necessary to acquire the junction temperature of the SiC MOSFET, switching devices K5 and K4 are closed simultaneously, forming a current from... V OUT1 The current flows from the loop to ground (GND). V OUT1 Initially, current flows through switching device K5 and sampling resistor R respectively. acq The SiC MOSFET device and switching device K4 are returned to GND. A connection is formed between the gate and source of the SiC MOSFET device. V OUT1 When the gate-source voltage is high, exceeding the device threshold voltage, the device is turned on. Simultaneously, a peak gate current is generated across the acquisition resistor. This data is acquired by the junction temperature acquisition circuit and converted into junction temperature data by the FPGA. This embodiment uses a gate drive resistor R... G Using equal-valued acquisition resistors avoids adverse effects on the switching of SiC MOSFET devices during the acquisition process.

[0033] Example 4 Based on the above embodiments, such as Figure 4 As shown, this embodiment provides a schematic diagram of the gate drive circuit. PWM is an externally input control signal. After receiving the signal, the FPGA monitors the rising and falling edges of the PWM in real time and counts the rising edges. When the count value is f / 1000, it switches to the acquisition mode during turn-on. That is, the FPGA outputs a high level to close switching devices K5 and K4, and outputs a low level to open switching devices K1, K2, and K3, allowing the gate current to flow through the acquisition resistor R. acq A gate peak current is generated, completing one gate peak current acquisition at a frequency of 1000Hz. A high-level output on the falling edge of the PWM signal closes switching devices K2 and K3, while a low-level output opens switching devices K1, K4, and K5, creating a negative voltage between the gate and source. This voltage is then transmitted through the drive resistor R. G The SiC MOSFET is turned off. When the count value is less than f / 1000, a high-level output is given on the rising edge of the PWM to close switching devices K1 and K4, and a low-level output is given to open switching devices K2, K3, and K5, forming a positive voltage between the gate and source, which is then applied through the drive resistor R. GThe SiC MOSFET is turned on; a high-level output on the falling edge of the PWM signal closes switching devices K2 and K3, and a low-level output opens switching devices K1, K4, and K5, creating a negative voltage between the gate and source, which is then transmitted through the driving resistor R. G Drive the SiC MOSFET to turn off.

[0034] Example 5 Based on the above embodiments, such as Figure 5 As shown, this embodiment provides the specific structure of the junction temperature acquisition circuit. The junction temperature acquisition circuit includes a differential operational amplifier U2, and the input terminal of the differential operational amplifier U2 is connected to the acquisition resistor R in the gate resistor network. acq The differential operational amplifier U2 is electrically connected to operational amplifier U3 at both ends. Resistors R2 and R3 are connected to the negative input of operational amplifier U3. The other end of resistor R2 is connected to the bias voltage VEE, and the other end of resistor R3 is connected to the output of operational amplifier U3. The output of operational amplifier U3 is electrically connected to transconductance operational amplifier U4. Diodes D1 and D2 are connected to the output of transconductance operational amplifier U4. The other end of diode D1 is grounded, and the other end of diode D2 is connected to MOSFET Q1 and resistor R4. MOSFET Q1 is connected to the power supply VCC and is also connected to resistor R5 and voltage buffer U5. The negative input of transconductance operational amplifier U4 is connected to the output of voltage buffer U5. Resistor R4 is connected to capacitor C2, with the other end of capacitor C2 grounded. The other end of resistor R5 is also grounded. Voltage buffer U5 is connected to an ADC. The ADC output is connected to the FPGA's data processing terminal I. G(peak) connect.

[0035] In this embodiment, junction temperature acquisition is achieved using the gate peak current method within the temperature-sensitive electrical parameter method. This electrical parameter exhibits good linearity with junction temperature and is unaffected by bus voltage or load current. This invention uses a sampling resistor to acquire the gate peak current when the SiC MOSFET device is turned on. The acquired result is then processed into a digital signal and transmitted to the FPGA, where it is converted into junction temperature data. Furthermore, this embodiment employs an intermittent acquisition method, where the acquisition frequency is much lower than the device switching frequency. This effectively suppresses self-heating of the sampling resistor, avoiding the impact of self-heating on acquisition accuracy.

[0036] Among them, the differential operational amplifier U2 will sample the resistor R acqThe differential voltage is converted into a single-ended signal. Operational amplifier U3, in conjunction with resistors R2 and R3, adds a negative bias voltage to the single-ended signal output by differential operational amplifier U2, reducing the output voltage amplitude and preventing excessive amplitude from affecting the operation of subsequent circuits. Transconductance operational amplifier U4 has the characteristic of large output current. By charging holding capacitor C2 through resistor R4, the collected peak current information can be stored in capacitor C2. Diode D1 clamps the output voltage of transconductance operational amplifier U4 to prevent damage to subsequent components due to excessive voltage. Diode D2 is a high-speed switching diode, which quickly turns on when the input signal is high and quickly turns off when the input signal is low. Field-effect transistor Q1 and resistor R5 together form a source follower to transmit the signal stored in capacitor C2. At the same time, the source follower can increase the input impedance of the subsequent voltage buffer U5, thereby reducing the leakage current of the holding capacitor. Voltage buffer U5 drives and amplifies the received peak signal, outputting a peak signal with stronger driving capability. The ADC converts the analog signal output from the voltage buffer U5 into a digital signal, transmits it to the FPGA for data processing, converts it back into an analog voltage signal inside the FPGA, and calculates the junction temperature based on the relationship between junction temperature and peak current.

[0037] Example 6 Based on the above embodiments, such as Figure 6 As shown in the figure, this embodiment provides a specific structure of an overload monitoring circuit. The overload monitoring circuit includes a sampling resistor R, which is connected to three current sensing amplifiers INA1, INA2, and INA3. Current limiting resistors R6 to R11 are connected between the sampling resistor R and the three current sensing amplifiers, respectively. R6 and R7 are connected between the current sensing amplifier INA1 and the sampling resistor R, R8 and R9 are connected between the current sensing amplifier INA2 and the sampling resistor R, and R10 and R11 are connected between the current sensing amplifier INA3 and the sampling resistor R. Comparators U6, U7, and U8 are connected to the output terminals of the current sensing amplifiers INA1, INA2, and INA3, respectively. Comparators U6, U7, and U8 are all voltage comparators. The negative input pins of comparators U6, U7, and U8 are connected to reference voltages Vref1, Vref2, and Vref3, respectively. The output terminals of comparators U6, U7, and U8 are connected to the data receiving terminals Ov1 to Ov3 of the FPGA.

[0038] In this embodiment, the overload monitoring circuit is divided into three branches, each corresponding to one of the three overload conditions of the SiC MOSFET device in the current transformer: 1x overload (full load operation, 100% rated current), 2x overload, and 3x overload (current is 2 or 3 times the rated current, respectively). The three-stage overload monitoring circuit is designed to balance junction temperature and electrical stress. In this invention, increasing the gate voltage can effectively reduce the device junction temperature, but it also increases electrical stress. Besides setting up external protection circuits, efforts should be made to avoid excessive electrical stress. Therefore, a three-stage overload monitoring circuit is designed. Under low overload conditions, a gate voltage slightly higher than the normal drive voltage is selected, which can reduce the junction temperature without causing excessive electrical stress. Under higher overload conditions, priority is given to keeping the device junction temperature within a safe range.

[0039] Taking the 1x overload monitoring branch as an example, the circuit is described as follows: A sampling resistor R is connected in series from the source of the SiC MOSFET to the external connection. Current flows through the sampling resistor and generates a voltage drop. This voltage is used as input and passes through current-limiting resistors R6 and R7 to the current sensing amplifier INA1, such as INA240. After a specific gain (determined by the current sensing amplifier model), it is converted into a voltage value. Comparator U6 compares this voltage with the reference voltage Vref1 under 1x overload. The high or low level of the output of comparator U6 determines whether the SiC MOSFET device is under 1x overload. The formula for calculating the reference voltage Vref1 is: (1); Where 1 represents an overload factor of 1, I represents the current flowing through the SiC MOSFET under full load, and R represents the resistance value of the sampling resistor. This represents the gain of the current-sensing amplifier.

[0040] The preamplifier circuits for 2x and 3x overload are completely identical, differing only in the reference voltages used to determine the overload. The formulas for calculating the reference voltages Vref2 and Vref3 are as follows: Vref2=2IRβ(2; Vref3=3IRβ(3; The overload status of SiC MOSFETs is determined by the following rules: When the output of the 1x overload monitoring circuit is low, the system is not overloaded and no adjustment of the gate voltage is required; when the output is high, the outputs of the 2x and 3x overload monitoring circuits need to be checked. If both outputs are low, the system is considered to be under 1x overload; if the output of the 2x overload monitoring circuit is high, the output of the 3x overload monitoring circuit needs to be checked. If its output is low, the system is considered to be under 2x overload; if both the 2x and 3x overload monitoring outputs are high, the system is considered to be under 3x overload.

[0041] Example 7 This embodiment provides a digital drive method suitable for strong overload conditions of grid-type converters. It employs the digital drive circuit for strong overload conditions of grid-type converters provided in the above embodiment. An FPGA is used to comprehensively determine the output signals of the overload monitoring circuit and the junction temperature acquisition circuit, acquiring the overload indication signal of the SiC MOSFET in real time. The gate peak current is intermittently acquired at a acquisition frequency lower than the switching frequency to obtain junction temperature data. When a device is determined to be overloaded or the junction temperature exceeds a threshold, the duty cycle of the control signal of the variable voltage circuit is adjusted to change the amplitude of the turn-on and turn-off gate voltages. The higher the overload level, the larger the gate voltage amplitude adjustment, and the amplitude increment is limited at low overload levels to suppress electrical stress. Losses are reduced by dynamically adjusting the gate voltage, and a closed-loop feedback is formed based on the junction temperature data until the junction temperature recovers to within the safe threshold.

[0042] Example 8 Based on Example 7, the specific steps include: S1 samples the current flowing through the SiC MOSFET in real time through the overload monitoring circuit, compares the sampled voltage with multiple preset reference voltages, generates overload indication signals corresponding to different overload levels, and transmits them to the FPGA; In S1, multiple preset reference voltages correspond to reference voltage values ​​for 1x overload, 2x overload, and 3x overload, respectively. Three overload indication signals Ov1, Ov2, and Ov3 are generated through three comparison branches. The FPGA determines the current overload level based on the logic combination of Ov1 to Ov3. The higher the overload level, the greater the adjustment of the gate voltage amplitude.

[0043] S2, the junction temperature acquisition circuit acquires the gate peak current signal related to the junction temperature of the SiC MOSFET at a set acquisition time, and transmits it to the FPGA to be converted into junction temperature data; The specific steps for the junction temperature acquisition circuit in S2 to obtain the gate peak current signal are as follows: The FPGA closes switches K4 and K5 during the PWM high level according to the preset acquisition frequency, so that the gate drive circuit switches to the acquisition mode; in the acquisition mode, the turn-on voltage passes through the acquisition resistor R acq Applied to the gate of the SiC MOSFET, and at the sampling resistor R acq The gate peak current is generated; the junction temperature acquisition circuit affects the acquisition resistor R. acq The voltage across the terminals is differentially amplified, biased, peak held, and converted from analog to digital to obtain a digital signal that is linearly related to the junction temperature; the acquisition frequency is lower than the switching frequency of the SiC MOSFET.

[0044] S3, the FPGA compares the junction temperature data with the preset safe junction temperature threshold, and at the same time determines the current overload level based on the overload indication signal; S4. If the junction temperature data exceeds the safe junction temperature threshold or the current overload level indicator device is in an overload state, the FPGA adjusts the control signal output to the variable voltage circuit to change the amplitude of the gate voltage on and gate voltage off of the gate drive circuit. S4 employs a tiered adjustment strategy when adjusting the gate voltage amplitude in the FPGA: When the overload is 1 or 2 times and the junction temperature exceeds the limit, the increase in gate voltage amplitude is limited to reduce the electrical stress of the device switching, taking into account both the device junction temperature and electrical stress. When the overload is 3 times, the main focus is on the device junction temperature, ensuring that the junction temperature drops to within the safe threshold, and allowing the gate voltage amplitude to be the maximum gate voltage that the device can withstand.

[0045] In S4, the control signals for the FPGA to adjust the variable voltage circuit are square wave signals S1 and S2. By changing the duty cycle of the square wave signals, and through low-pass filtering, voltage follower OPA1 and power management chip U1 feedback control, the gate voltage on and gate voltage off can be adjusted. The gate drive circuit achieves switching between turn-on, turn-off, and acquisition modes through the combination control of five switching devices K1~K5: In turn-on mode, switches K1 and K4 are closed, so that the turn-on voltage passes through the drive resistor R. G In turn-off mode, switches K3 and K2 are closed, causing the turn-off voltage to be applied to the gate in reverse; in acquisition mode, switches K5 and K4 are closed, causing the turn-on voltage to be applied to the gate through the acquisition resistor R. acq Applied to the gate.

[0046] S5 applies the adjusted turn-on and turn-off gate voltages to the SiC MOSFET to reduce device turn-on losses, turn-off losses, and conduction losses, thereby reducing junction temperature; S6. After adjusting the gate voltage, repeat S2 to S4 until the junction temperature data is lower than the safe junction temperature threshold, thus forming a closed-loop feedback control.

Claims

1. A digital drive circuit suitable for strong overload conditions of grid-type converters, connected to the SiC MOSFET under test, characterized in that, The FPGA includes a PWM signal input terminal, square wave signal output terminals S1 and S2, a control signal output terminal, and a data processing terminal I. G(peak) With data receiving terminals Ov1~Ov3; The square wave signal output terminals S1 and S2 are respectively connected to a variable voltage circuit, the control signal output terminal is connected to a gate drive circuit, and the data processing terminal I... G(peak) A junction temperature acquisition circuit is connected, and the data receiving terminals Ov1~Ov3 are connected to an overload monitoring circuit; the output terminal of the variable voltage circuit is connected to the gate drive circuit.

2. The digital drive circuit for strong overload conditions of grid-type converters according to claim 1, characterized in that, The variable voltage circuit consists of a low-pass filter, a voltage follower OPA1, and a power management chip U1 connected in series. The low-pass filter is composed of a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the square wave signal output terminal S1 or S2 of the FPGA, and the other end of the resistor R1 is connected to the capacitor C1 and the positive input terminal of the voltage follower OPA1. The other end of the capacitor C1 is connected to ground. The negative input terminal of the voltage follower OPA1 is connected to its own output terminal, and the output terminal of the voltage follower OPA1 is connected to the feedback pin of the power management chip U1. V OUT The output pin of the power management chip U1 V OUT include V OUT1 and V OUT2 The V OUT1 and V OUT2 They are connected to the gate drive circuit respectively.

3. The digital drive circuit for strong overload conditions of grid-type converters according to claim 2, characterized in that, The gate drive circuit includes five switching devices K1~K5 and a drive resistor R. G and the acquisition resistor R acq The switching devices K1~K5 are respectively connected to the control signal output terminal, and one end of the switching device K1 is connected to... V OUT1 The other end of the switching device K1 is connected to the switching device K2 and the driving resistor R. G One end of the switching device K2 is grounded, and the other end of the driving resistor R is connected to ground. G The other end is connected to the gate of the SiC MOSFET; one end of the switching device K3 is connected to V OUT2 The other end of the switching device K3 is connected to the source of the switching device K4 and the SiC MOSFET; one end of the switching device K5 is connected to V OUT1 The other end of the switching device K5 is connected to the acquisition resistor R. acq One end of the acquisition resistor R acq The other end is connected to the gate of the SiC MOSFET.

4. The digital drive circuit for strong overload conditions of grid-type converters according to claim 3, characterized in that, The junction temperature acquisition circuit includes a differential operational amplifier U2, the input terminal of which is connected to the acquisition resistor R in the gate resistor network. acq The differential operational amplifier U2 is electrically connected to operational amplifier U3 at both ends. The negative input of operational amplifier U3 is connected to resistors R2 and R3. The other end of resistor R2 is connected to a bias voltage VEE, and the other end of resistor R3 is connected to the output of operational amplifier U3. The output of operational amplifier U3 is electrically connected to transconductance operational amplifier U4. The output of transconductance operational amplifier U4 is connected to diodes D1 and D2. The other end of diode D1 is grounded. The other end of diode D2 is connected to a field-effect transistor Q1 and resistor R4. Field-effect transistor Q1 is connected to power supply VCC and is also connected to resistor R5 and voltage buffer U5. The negative input of transconductance operational amplifier U4 is connected to the output of voltage buffer U5. Resistor R4 is connected to capacitor C2, with the other end of capacitor C2 grounded. The other end of resistor R5 is grounded. Voltage buffer U5 is connected to an ADC. The output of the ADC is connected to the data processing terminal I of the FPGA. G(peak) connect.

5. The digital drive circuit for strong overload conditions of grid-type converters according to claim 4, characterized in that, The overload monitoring circuit includes a sampling resistor R, which is connected to three current sensing amplifiers INA1, INA2, and INA3. Current limiting resistors R6 to R11 are connected between the sampling resistor R and the three current sensing amplifiers. R6 and R7 are connected between the current sensing amplifier INA1 and the sampling resistor R. R8 and R9 are connected between the current sensing amplifier INA2 and the sampling resistor R. R10 and R11 are connected between the current sensing amplifier INA3 and the sampling resistor R. The outputs of the current sensing amplifiers INA1, INA2, and INA3 are connected to comparators U6, U7, and U8, respectively. The negative input pins of the comparators U6, U7, and U8 are connected to reference voltages Vref1, Vref2, and Vref3, respectively. The outputs of the comparators U6, U7, and U8 are connected to the data receiving terminals Ov1 to Ov3 of the FPGA.

6. A digital drive method applicable to strong overload conditions of grid-type converters, characterized in that, Using the digital driving circuit described in claim 5, the overload indication signal of the SiC MOSFET is acquired in real time, and the gate peak current is intermittently acquired at a sampling frequency lower than the switching frequency to obtain junction temperature data. When the device is determined to be overloaded or the junction temperature exceeds the threshold, the duty cycle of the control signal of the variable voltage circuit is adjusted to change the amplitude of the turn-on gate voltage and the turn-off gate voltage. The higher the degree of overload, the greater the adjustment range of the gate voltage amplitude, and the amplitude increment is limited at low overload to suppress electrical stress. The loss is reduced by dynamically adjusting the gate voltage, and a closed-loop feedback is formed based on the junction temperature data until the junction temperature recovers to within the safe threshold.

7. The digital drive method for strong overload conditions of grid-type converters according to claim 6, characterized in that, Specifically, the following steps are included: S1 samples the drain current of the SiC MOSFET in real time through the overload monitoring circuit, compares the sampled voltage with multiple preset reference voltages, generates overload indication signals corresponding to different overload levels, and transmits them to the FPGA; S2, the junction temperature acquisition circuit acquires the gate peak current signal related to the junction temperature of the SiC MOSFET at a set acquisition time, and transmits it to the FPGA to be converted into junction temperature data; S3, the FPGA compares the junction temperature data with the preset safe junction temperature threshold, and at the same time determines the current overload level based on the overload indication signal; S4. If the junction temperature data exceeds the safe junction temperature threshold or the current overload level indicator device is in an overload state, the FPGA adjusts the control signal output to the variable voltage circuit to change the amplitude of the gate voltage on and gate voltage off of the gate drive circuit. S5 applies the adjusted turn-on and turn-off gate voltages to the SiC MOSFET to reduce the device's turn-on loss, turn-off loss, and conduction loss, thereby reducing the junction temperature. S6. After adjusting the gate voltage, repeat S2 to S4 until the junction temperature data is lower than the safe junction temperature threshold, thus forming a closed-loop feedback control.

8. The digital drive method for strong overload conditions of grid-type converters according to claim 7, characterized in that, The multiple preset reference voltages mentioned in S1 correspond to reference voltage values ​​of 1x overload, 2x overload, and 3x overload, respectively. Three overload indication signals Ov1, Ov2, and Ov3 are generated through three comparison branches. The FPGA determines the current overload level based on the logic combination of Ov1 to Ov3. The higher the overload level, the greater the adjustment of the gate voltage amplitude.

9. The digital drive method for grid-type converters under severe overload conditions according to claim 8, characterized in that, The specific steps for the junction temperature acquisition circuit in S2 to obtain the gate peak current signal are as follows: The FPGA closes switches K4 and K5 during the PWM high level according to the preset acquisition frequency, so that the gate drive circuit switches to the acquisition mode; in the acquisition mode, the turn-on voltage passes through the acquisition resistor R acq Applied to the gate of the SiC MOSFET, and at the sampling resistor R acq The gate peak current is generated; the junction temperature acquisition circuit affects the acquisition resistor R. acq The voltage across the terminals is differentially amplified, biased, peak held, and converted from analog to digital to obtain a digital signal that is linearly related to the junction temperature; the acquisition frequency is lower than the switching frequency of the SiC MOSFET.

10. The digital drive method for strong overload conditions of grid-type converters according to claim 9, characterized in that, S4 employs a tiered adjustment strategy when adjusting the gate voltage amplitude in the FPGA: When the overload is 1 or 2 times and the junction temperature exceeds the limit, the increase in gate voltage amplitude is limited to reduce the electrical stress on the device switching; when the overload is 3 times, the junction temperature is ensured to drop to within the safe threshold, and the gate voltage amplitude is taken as the maximum gate voltage that the device can withstand. In S4, the control signals for the FPGA to adjust the variable voltage circuit are square wave signals S1 and S2. By changing the duty cycle of the square wave signals, and through low-pass filtering, voltage follower OPA1 and power management chip U1 feedback control, the gate voltage on and gate voltage off can be adjusted. The gate drive circuit achieves switching between turn-on, turn-off, and acquisition modes through the combined control of five switching devices K1~K5: In the turn-on mode, switches K1 and K4 are closed, so that the turn-on voltage passes through the drive resistor R. G Applied to the gate; In the shutdown mode, closing switches K3 and K2 causes the shutdown voltage to be applied to the gate in reverse. In acquisition mode, close switches K5 and K4, allowing the turn-on voltage to pass through the acquisition resistor R. acq Applied to the gate.

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