Power device gate resistance structure, power device and preparation method of power module

Abstract

This invention belongs to the field of power device technology, specifically relating to a power device gate resistor structure, a power device, and a method for fabricating a power module. This invention achieves flexible configuration of the gate resistor by setting several independent resistor units on at least one side of the gate PAD, and connecting both ends of each resistor unit to the resistor PAD while isolating it from the gate PAD. During power module fabrication, the final equivalent gate resistance value required for each chip can be accurately calculated based on individual test data of each chip (such as saturation voltage drop, threshold voltage, switching speed, Rg, etc.) and the parasitic inductance differences of the current paths of parallel chips in the module layout. Then, the corresponding resistor units are connected between the gate PAD and the gate busbar in series or parallel using a bonding process. This design breaks the limitations of traditional fixed gate resistors inside chips, enabling personalized gate resistance adjustment based on the characteristics of each chip and its specific location in the module.

Description

Technical Field

[0001] This invention belongs to the field of power device technology, specifically relating to a power device gate resistor structure, a power device, and a method for fabricating a power module. Background Technology

[0002] Power electronic devices such as GTOs, GCTs, IGBTs, Diodes, and MOSFETs are widely used as switching devices in aerospace, military, energy, and industrial fields. IGBTs and MOSFETs, due to their shared MOS structure on the front side, can effectively control the switching on and off of the communication via gate voltage, thus achieving control over the conduction and turn-off of the IGBT / MOSFET. Because of their superior switching speed and lower switching losses, they are suitable for higher frequency applications; IGBTs can operate from hundreds of Hz to hundreds of kHz, while MOSFETs can even reach MHz. With the development of current technology and advancements, the switching speed of IGBT / MOSFET devices is becoming increasingly faster, especially after the widespread application of wide-bandgap materials, which has significantly improved switching speeds.

[0003] Modern power electronics applications demand increasingly higher integration and power density in power semiconductor devices. This typically requires parallel packaging of multiple chips within the same package, or parallel connection of multiple products to meet these requirements. Regardless of the package or parallel connection method, multiple switching chips are connected in parallel. However, variations in chip manufacturing processes inevitably lead to differences in the electrical characteristics of different chips, such as saturation voltage drop, threshold voltage, and switching speed. Furthermore, in high-integration packages, inductance differences are unavoidable (design layout limitations, terminal electrode pin requirements, etc.). Especially in high-frequency packaging applications, these parasitic inductance differences are more likely to cause switching voltage and current oscillations, leading to repeated over-protection triggers or premature device failure. This parallel oscillation problem caused by inconsistent device parameters and excessive speed is particularly pronounced in SiC MOS or SiC IGBTs.

[0004] In high-frequency, high-power applications, common methods to improve switching current and voltage oscillation include: adding drive resistors at the system level, adding snubber capacitors, optimizing DBC (Dual Circuit Breaker) or bonding trace layout in the product package, optimizing inductance, and designing the Rg (Reverse Gaussian Grading) within the chip. However, these solutions all have some shortcomings and limitations. 1. By increasing the driving resistor and the absorption capacitor, the overall cost of the device increases (mainly due to increased design complexity and overall size). On the other hand, larger resistors and capacitors will cause the switching speed of the device to slow down significantly, resulting in increased losses and temperature rise. As a result, in order to ensure reliable use, users have to reduce the output power. 2. Optimizing the DBC or bonding trace layout of modules / single tubes in product packaging can improve the oscillation problem to some extent, but it is usually limited by the size of the module / single tube and the circuit topology, and cannot completely solve the oscillation problem. 3. Designing an internal gate resistor (Rg) within the chip is more effective than the methods mentioned above. However, current methods design a fixed Rg for each chip, with the gate signal transmission path being: Gate PAD1 (pad) -- Rg design -- gate trace -- cell. This Rg design is rigid and fixed; if too small, it cannot effectively solve the oscillation problem; if too large, it will also lead to excessive device losses. Furthermore, due to wafer manufacturing processes, in-plane distribution, inter-wafer differences, and batch differences all contribute to significant variations between chips. This is especially true in current new technology generation small-pitch products using trench polysilicon for Rg design, where differences in trench etching, polysilicon doping, etc., exacerbate parameter inconsistencies. A single fixed Rg design cannot cover these significant differences, making it difficult to strike a good balance between effectively suppressing oscillations and minimizing device losses when multiple chips are connected in parallel. Summary of the Invention

[0005] The purpose of this invention is to provide a power device gate resistor structure, a power device, and a method for fabricating a power module, in order to solve the failure problems caused by uneven current and oscillation between multiple chips in the same topology position or between bridge arms or phases in different topology positions when connected in parallel due to differences in the characteristics of each parallel chip caused by differences in chip process or unavoidable differences in parasitic inductance when the parallel module is laid out.

[0006] This application provides a gate resistor structure for a power device, including: A plurality of resistor units disposed on at least one side of the gate PAD; Both ends of the resistor unit are connected to resistors PAD; The resistor PAD is isolated from the gate PAD.

[0007] In one embodiment of this application, at least one end of a resistor PAD of a resistor unit is connected to a gate PAD via a first connector, and the other end is connected to a gate busbar via a second connector.

[0008] In one embodiment of this application, the first connector includes a connecting wire.

[0009] In one embodiment of this application, the first connector includes a connecting wire and a jumper metal; The jumper metal is disposed between the gate PAD and the resistor unit; The jumper metal is connected to the gate PAD; The resistor PAD is connected to the jumper metal via a connecting wire.

[0010] In one embodiment of this application, at least two resistor units are connected in parallel between the gate PAD and the gate busbar.

[0011] In one embodiment of this application, at least two resistor units are connected in series between the gate PAD and the gate busbar.

[0012] In one embodiment of this application, a dielectric isolation layer is disposed beneath the gate PAD and the resistor PAD; The resistor unit is a polycrystalline silicon resistor disposed within a dielectric isolation layer; The two ends of the polycrystalline silicon resistor are connected to the corresponding resistor PAD through contact holes.

[0013] In one embodiment of this application, a dielectric isolation layer is disposed beneath the gate PAD and the resistor PAD; A substrate layer is disposed below the dielectric isolation layer; The resistor unit is a trench resistor extending into the substrate layer; The two ends of the trench resistor are connected to the corresponding resistor PAD through contact holes.

[0014] Accordingly, the present invention provides a power device including the power device gate resistor structure described above.

[0015] Accordingly, the present invention also provides a method for fabricating a power module using the power device described above, comprising: Obtain individual test data for each chip to be packaged; By combining the parasitic inductance differences of the current paths of each parallel chip in the module layout, the final equivalent gate resistance required by each chip is calculated, and the corresponding bonding strategy is determined. That is, several resistor units are connected between the gate PAD and the gate busbar in a separate, series or parallel manner.

[0016] The beneficial effects of this invention are: This invention achieves flexible configuration of the gate resistor by setting several independent resistor units on at least one side of the gate PAD, and connecting both ends of each resistor unit to the resistor PAD while isolating it from the gate PAD. During power module fabrication, the final equivalent gate resistor value required for each chip can be accurately calculated based on the individual test data of each chip (such as saturation voltage drop, threshold voltage, switching speed, Rg, etc.) and the parasitic inductance differences of the current paths of each parallel chip in the module layout. Then, the corresponding resistor units are connected between the gate PAD and the gate busbar in series or parallel through a bonding process. This design breaks the limitations of the traditional fixed gate resistor inside the chip, and can perform personalized gate resistor adjustment according to the characteristics of each chip and its specific position in the module. By optimizing the gate drive conditions of each parallel chip, the switching voltage and current oscillations caused by differences in chip process and inconsistencies in parasitic parameters are effectively suppressed, and the current sharing characteristics of multiple chips in parallel are improved, thereby improving the overall reliability and operating efficiency of the power module. At the same time, it avoids the problems of increased switching losses due to excessively large fixed gate resistors and the inability to suppress oscillations due to excessively small fixed gate resistors, achieving a good balance between suppressing oscillations and reducing losses. In addition, the resistor unit can be in different forms such as polysilicon resistors or trench resistors, which are compatible with existing semiconductor manufacturing processes and are easy to mass-produce.

[0017] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the gate resistor structure of a power device according to a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the power device gate resistor structure according to another preferred embodiment of the present invention; Figure 3 This is a schematic diagram of the gate resistor structure of a power device according to another preferred embodiment of the present invention; Figure 4 This is a schematic diagram of a trench resistor according to a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of a jumper metal according to a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of the gate resistor according to a preferred embodiment of the present invention; Figure 7 This is a schematic diagram of the gate resistor of another preferred embodiment of the present invention; Figure 8 This is a cross-sectional view of a polycrystalline silicon resistor according to a preferred embodiment of the present invention; Figure 9 This is a cross-sectional view of a polysilicon resistor and jumper metal according to a preferred embodiment of the present invention; Figure 10 This is a cross-sectional view of a trench resistor according to a preferred embodiment of the present invention; Figure 11 This is a cross-sectional view of a trench resistor and jumper metal according to a preferred embodiment of the present invention.

[0021] In the picture: Gate PAD1, resistor unit 2, polysilicon resistor 21, trench resistor 22, resistor PAD3, first connector 4, connecting line 41, jumper metal 42, second connector 5, gate bus bar 6, dielectric isolation layer 100, contact hole 200, substrate layer 300, passivation layer 400. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] This application provides a power device gate resistor structure, a power device, and a method for fabricating a power module, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, in the following embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0024] See Figures 1 to 4 In one embodiment, the power device gate resistor structure includes: a plurality of resistor units 2 disposed on at least one side of the gate PAD1; both ends of the resistor unit 2 are connected to resistors PAD3; the resistors PAD3 are isolated from the gate PAD1.

[0025] In this embodiment, by placing the resistor unit 2 on at least one side of the gate PAD1, and connecting both ends of each resistor unit 2 to a resistor PAD3 isolated from the gate PAD1, a hardware foundation is provided for flexible configuration of the gate resistor. This structural design makes each resistor unit 2 a basic unit that can be independently selected to be connected to the gate drive path. For example, when a smaller equivalent gate resistance is required, multiple resistor units 2 can be connected in parallel; when a larger equivalent gate resistance is required, multiple resistor units 2 can be connected in series; of course, the number of resistor units 2 connected can also be selected as needed. The isolation setting of the resistor PAD3 ensures that no electrical connection is formed between each resistor unit 2 and the gate PAD1 before bonding, avoiding interference with the gate signal, and also providing the possibility for subsequent personalized bonding according to specific needs. This design fundamentally changes the traditional fixed gate resistance mode, giving power devices the ability to dynamically adjust the gate resistance, enabling them to better adapt to the gate drive requirements under different chip characteristics and module layouts.

[0026] In some embodiments, see Figure 1 Several resistor units 2 can be arranged on both sides of the gate PAD1; see [link to relevant documentation]. Figure 2 and Figure 4 Several resistor units 2 can be provided on one side of the gate PAD1; see [link to relevant documentation]. Figure 3 Several resistor units 2 can be set on multiple sides of the gate PAD1. The specific selection can be made according to design requirements.

[0027] In one embodiment of this application, further see... Figure 3 , Figure 6 and Figure 7 At least one resistor PAD3 at one end of resistor unit 2 is connected to gate PAD1 via first connector 4, and the other end is connected to gate busbar 6 via second connector 5.

[0028] In this embodiment, a selected resistor unit 2 can be connected to the gate drive path via the connection of the first connector 4 and the second connector 5. When a resistor unit 2 needs to be connected, simply connect the resistor PAD3 at one end of the resistor unit 2 to the gate PAD1 via the first connector 4, and simultaneously connect the resistor PAD3 at the other end of the resistor unit 2 to the gate busbar 6 via the second connector 5. This allows the resistor unit 2 to be connected in series in the gate signal transmission path, thereby contributing its resistance value. This connection method is simple and direct, and can be achieved through bonding and other processes, providing a convenient means for flexibly configuring the gate resistance according to individual chip differences and module layout. For example, if the switching speed of a chip is too fast, and the gate resistance needs to be increased to suppress oscillation, one or more resistor units 2 can be selected for connection; if another chip has a lower threshold voltage due to process differences, and a smaller gate resistance is needed to ensure sufficient driving capability, fewer resistor units 2 can be selected for connection, or a combination of resistor units 2 with smaller resistance values ​​can be selected.

[0029] Optional, see Figure 3 The first connector 4 may consist only of the connecting wire 41. The second connector 5 may also be the connecting wire 41. The connecting wire 41 may be a bonding wire, which connects the resistor PAD3 to the gate PAD1 and the resistor PAD3 to the gate busbar 6 using an ultrasonic bonding process. Bonding wires have good conductivity and mechanical strength, enabling reliable electrical connections. Furthermore, the process is mature, cost-effective, and suitable for mass production. This method of connection using only the connecting wire 41 is simple in structure, convenient in operation, and suitable for scenarios where connection path requirements are not high.

[0030] In some embodiments, when the gate current Ig is small, a thinner bonding wire can usually be used, such as 5mil aluminum wire. The size of resistor PAD3 can be 0.4mm*0.4mm. If copper or gold wire is used for bonding, the bonding wire diameter can be smaller and resistor PAD3 can be further reduced.

[0031] In other embodiments, see Figure 5 , Figure 6 and Figure 7The first connector 4 includes a connecting line 41 and a jumper metal 42; the jumper metal 42 is disposed between the gate PAD1 and the resistor unit 2; the jumper metal 42 is connected to the gate PAD1; the resistor PAD3 is connected to the jumper metal 42 via the connecting line 41. Introducing the jumper metal 42 optimizes the connection path between the gate PAD1 and the resistor unit 2. The jumper metal 42 is typically formed during chip manufacturing through metal deposition and photolithography processes, exhibiting lower resistance and better current distribution characteristics. When the distance between the gate PAD1 and the resistor unit 2 is large or direct bonding is difficult, the jumper metal 42 can serve as an intermediate transition, shortening the length of the connecting line 41, reducing parasitic inductance and resistance, thereby improving the transmission quality of the gate signal. For example, in some high-density chip layouts, the space around the gate PAD1 is limited. Directly bonding the resistor PAD3 to the gate PAD1 may result in crossovers or excessively dense bonding wires. By introducing jumper metal 42, the signal from the gate PAD1 can be first guided to jumper metal 42, and then bonded to the resistor PAD3 from jumper metal 42. This allows for more flexible planning of the bonding path, improving package reliability and process yield. Jumper metal 42 can be connected to the gate PAD1 using the same or different metal layers, depending on the chip's process and design requirements.

[0032] In one embodiment, see Figure 6 At least two resistor units 2 are connected in parallel between the gate PAD1 and the gate bus 6. The parallel connection of the resistor units 2 is achieved by connecting one end of the resistor PAD3 to the gate PAD1 via a first connector 4, and the other end of the resistor PAD3 to the gate bus 6 via a second connector 5. Parallel connection reduces the equivalent gate resistance value, making it suitable for scenarios requiring increased gate drive current, faster switching speed, or reduced drive losses. For example, when a chip has a high threshold voltage and requires a larger gate drive current for rapid turn-on, multiple resistor units 2 can be connected in parallel to reduce the total resistance of the gate circuit, thereby providing a larger drive current. Furthermore, different numbers of parallel resistor units 2 can be selected to obtain different equivalent resistance values, further enhancing the flexibility of gate resistance configuration. For example, if the resistance value of a single resistor unit 2 is R, then the equivalent resistance of two identical resistor units 2 connected in parallel is R / 2, three in parallel is R / 3, and so on, allowing for finer resistance value adjustment.

[0033] In one embodiment, see Figure 6 and Figure 7At least two resistor units 2 are connected in series between the gate PAD1 and the gate bus 6. Multiple resistor units 2 are connected end-to-end sequentially. Specifically, one end of the first resistor unit 2 (PAD3) is connected to the gate PAD1 via a first connector 4, and the other end (PAD3) is connected to one end of the second resistor unit 2 (PAD3) via a connecting wire. The other end of the second resistor unit 2 (PAD3) is then connected to the gate bus 6 via a second connector 5, thus achieving series connection of the resistor units 2. Series connection increases the equivalent gate resistance value, suitable for scenarios requiring slower switching speeds and suppression of voltage or current oscillations during switching. For example, when the chip experiences severe voltage overshoot or oscillations during switching, multiple resistor units 2 can be connected in series to increase the gate resistance, limit the rate of change of the gate current, thereby reducing the switching speed and suppressing oscillations. Similar to parallel connection, the number of series resistor units 2 can be flexibly selected according to the required equivalent resistance value. When the resistance of a single resistor unit 2 is R, the equivalent resistance of n series resistor units 2 is nR, thus achieving coverage from small to large resistance values.

[0034] In some embodiments, the resistor unit 2 may be as follows: Figures 1 to 3 The polysilicon resistor 21 shown can also be as follows: Figure 4 The trench resistor 22 is shown.

[0035] For details, see Figure 8 and Figure 9 In one embodiment of this application, a dielectric isolation layer 100 is disposed below the gate PAD1 and resistor PAD3; the resistor unit 2 is a polysilicon resistor 21 disposed within the dielectric isolation layer 100; the two ends of the polysilicon resistor 21 are respectively connected to the corresponding resistor PAD3 through contact holes 200. The dielectric isolation layer 100 may be made of insulating materials such as silicon oxide and silicon nitride, and its function is to electrically isolate the gate PAD1, resistor PAD3, and resistor unit 2 from the underlying substrate layer 300 or other conductive structures to prevent leakage and interference. The polysilicon resistor 21 is formed by doping polysilicon material with specific impurities (such as phosphorus, boron, etc.) within the dielectric isolation layer 100, and its resistance value can be precisely adjusted by controlling the doping concentration, length, and width of the polysilicon. The polysilicon resistor 21 has good temperature stability and process compatibility, and is a commonly used resistor form in semiconductor manufacturing. The contact hole 200 is a through-hole formed in the dielectric isolation layer 100 through photolithography and etching processes. It is filled with metal (such as tungsten, aluminum, etc.) and is used to make ohmic contact between the two ends of the polysilicon resistor 21 and the resistor PAD3 above it, ensuring that the current can flow smoothly through the resistor unit 2. This structural design enables the resistor unit 2 to achieve good isolation and electrical connection with other parts of the chip, ensuring the accuracy and stability of the resistance value.

[0036] For details, see Figure 10 and Figure 11 In another embodiment of this application, a dielectric isolation layer 100 is disposed below the gate PAD1 and resistor PAD3; a substrate layer 300 is disposed below the dielectric isolation layer 100; the resistor unit 2 is a trench resistor 22 extending into the substrate layer 300; the two ends of the trench resistor 22 are respectively connected to the corresponding resistor PAD3 through contact holes 200. Unlike the polysilicon resistor 21, the trench resistor 22 is formed by etching trenches in the substrate layer 300 (usually a silicon substrate) and then filling or forming a high-resistivity material (such as polysilicon or silicide with a low doping concentration) in the trenches. The trench resistor 22 can utilize the depth space of the substrate layer 300 to achieve a large resistance value on a small chip area, which is beneficial for chip miniaturization design. The dielectric isolation layer 100 also serves to isolate the gate PAD1, resistor PAD3 from the trench resistor 22 and the substrate layer 300. The two ends of the trench resistor 22 are connected to the resistor PAD3 through contact holes 200. Its resistance value can be controlled by the depth, width, and length of the trench and the resistivity of the filling material. This type of resistor unit 2 can provide a high resistance value and good heat dissipation performance, making it suitable for applications requiring high resistance values ​​or high power dissipation.

[0037] See Figure 9 and Figure 11 A jumper metal 42 can be provided between resistor PAD3 and gate PAD1; a passivation layer 400 can be provided between resistor PAD3, gate PAD1, and jumper metal 42. The passivation layer 400 is typically made of silicon nitride or silicon oxide, and its main function is to protect the underlying metal PADs and jumper metal 42 from environmental contamination and corrosion, while also preventing physical damage to these metal structures during subsequent packaging processes. In areas requiring bonding, the passivation layer 400 is etched to create windows, exposing the surface of resistor PAD3 or jumper metal 42, so that electrical connections can be achieved via connection lines 41 (such as bonding wires). Jumper metal 42 and gate PAD1 can be directly connected through the same metal layer, or connected to the underlying metal layer through a metal via, depending on the chip's metal wiring hierarchy design.

[0038] Accordingly, one embodiment of this application also provides a power device, including the power device gate resistor structure described above.

[0039] Accordingly, one embodiment of this application also provides a method for fabricating a power module using the power device described above, comprising: Obtain individual test data for each chip to be packaged; Based on the parasitic inductance differences of the current paths of each parallel chip in the module layout, the final equivalent gate resistance required by each chip is calculated, and the corresponding bonding strategy is determined. That is, several resistor units 2 are connected between the gate PAD1 and the gate busbar 6 in a separate, series or parallel manner.

[0040] Specifically, when acquiring individual test data for each chip to be packaged, key parameters such as threshold voltage, transconductance, gate capacitance, and on-resistance can be included, ultimately generating test result files or maps. These parameters directly affect the switching characteristics of the chip. For example, chips with lower threshold voltages are easier to turn on at the same gate drive voltage and may require a larger gate resistance to slow down the turn-on speed and avoid excessive inrush current; while chips with higher threshold voltages may require a smaller gate resistance to ensure reliable turn-on. Transconductance and gate capacitance are related to the gate drive current requirement and the switching speed. Chips with large transconductance have a strong ability to control the drain current with the gate current and a relatively fast switching speed, and may need to optimize the dynamic characteristics during the switching process by adjusting the gate resistance.

[0041] The parasitic inductance differences in the current paths of parallel chips in the module layout (which can be extracted through SPICE simulation at the initial stage of package layout design) are considered because multiple chips are typically connected in parallel in power modules to increase output power. However, due to layout and routing limitations, the current path lengths and directions of the parallel chips cannot be completely identical, leading to differences in parasitic inductance among the chips. Parasitic inductance generates additional voltage spikes and oscillations during switching, and the differences in parasitic inductance among different chips result in uneven current distribution during switching, affecting the overall performance and reliability of the module. For example, a chip with smaller parasitic inductance experiences a faster current rise during turn-on, easily handling a larger current share, which may cause the chip to overheat and be damaged. Therefore, it is necessary to adjust the gate resistance of each chip based on these parasitic inductance differences, thereby adjusting the switching speed of each chip by changing the gate resistance value, and thus balancing the current distribution among the chips.

[0042] The process of calculating the final equivalent gate resistance required for each chip and determining the corresponding bonding strategy is a comprehensive consideration of individual chip characteristics and parasitic parameters of the module layout. First, a baseline gate resistance range is initially determined based on individual chip test data. Then, simulation analysis is performed to analyze the differences in parasitic inductance of the current paths of each chip in the module layout, simulating the switching waveforms, current distribution, and overall module losses and EMI (electromagnetic interference) levels of each chip under different gate resistance values. For example, for chips with large parasitic inductance, to compensate for their slow current rise, their gate resistance can be appropriately reduced to accelerate their turn-on speed; for chips with small parasitic inductance, their gate resistance can be appropriately increased to slow their turn-on speed, thus allowing the current of each parallel chip to rise and fall more evenly. After determining the final equivalent gate resistance value required for each chip, the specific bonding method is determined based on the individual resistance value of resistor unit 2 and the number that can be connected in series or parallel. For example, if the calculated equivalent gate resistance required for a chip is 2R (where R is the resistance value of a single resistor unit), then two resistor units 2 can be connected in series; if the required equivalent gate resistance is R / 2, then two resistor units 2 can be connected in parallel. In this way, the gate resistance of each chip can be precisely customized, ultimately optimizing the performance of the power module and improving its reliability.

[0043] In some embodiments, during the chip layout design stage, by evaluating the consistency differences of various parameters under the chip manufacturing process (such as differences in resistance, capacitance, etc. caused by in-wafer, inter-wafer, and inter-batch structures and doping differences, which are communicated with the process line and can usually be provided) and the differences in parameters such as parasitic inductance of each chip current path in the final packaging scheme (which can be extracted through SPICE simulation), the required number of resistor units 2 and the corresponding resistor PAD3 size for a single chip can be accurately determined, and a reasonable module packaging bonding scheme can be planned accordingly. Subsequently, when performing chip layout design, whether polysilicon resistors or trench resistors are used, customized designs can be made according to the requirements determined in the first step. Specifically, for polysilicon resistors, the size of a single resistor can be achieved by precisely controlling the three key parameters of polysilicon length, width, and sheet resistance. For trench resistors, the size of a single trench resistor can be designed by adjusting parameters such as trench width, depth, length (i.e., current path direction), number of trenches, and sheet resistance. This method of deducing chip layout design parameters from the package layout ensures that the gate resistor structure is highly matched with the electrical characteristics and packaging requirements of the entire power module, laying a solid foundation for subsequent module fabrication and performance optimization.

[0044] In some applications, when multiple chips need to be packaged in parallel, they are often large-sized chips (e.g., >10*10mm).2 Then, they are connected in parallel within the same package to increase the outflow of a single module (>800A). Based on a single chip size of 100mm... 2 Calculations show that the design with 4 resistor units occupies only 1.28 mm² of area. 2 It accounts for 1.28% of the area of ​​a single chip. If the chip size increases or the pad size decreases, the Rg design will account for an even smaller proportion of the area of ​​a single chip.

[0045] In some application scenarios, the power device gate resistor structure of this invention integrates multiple resistor units on the chip, occupying ≤1.28% of the area of ​​a single chip, with minimal and negligible impact on chip characteristics. All the multiple resistor units integrated on the chip can be measured in the wafer-level testing at the end of the chip manufacturing process, obtaining accurate Rg results for each chip. This provides a precise basis for determining whether and how to connect subsequent resistors.

[0046] In some applications, to reduce overall size, module dimensions are often subject to extremely strict limitations. When arranging complex topologies within a limited package size, significant differences (typically >10%) in stray inductance between bridge arms and phases are inevitable. Multiple resistor unit designs and measurable resistor unit results allow for differentiated layout bonding based on these stray inductance differences. Precise matching of inductors and chip gate resistors can be achieved within the same chip or parallel connection, reducing or even eliminating switching oscillations and providing greater design freedom to address the stray inductance differences in complex module topologies. Furthermore, matching multiple resistor unit designs and package bonding allows for different gate resistor sizes, providing greater redundancy for resistance and structural differences in wafer manufacturing and reducing requirements on wafer fabrication lines. In addition, layout design is only required in the early stages of development; resistor unit size, trench width, etc., can all be determined through layout design, compatible with conventional IGBT or MOS processes, without requiring additional manufacturing processes and without affecting costs.

[0047] It should be noted that all the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0048] In the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0049] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A gate resistor structure for a power device, characterized in that, include: A plurality of resistor units (2) disposed on at least one side of the gate PAD (1); Both ends of the resistor unit (2) are connected to resistor PAD (3); The resistor PAD (3) is isolated from the gate PAD (1).

2. The power device gate resistor structure according to claim 1, characterized in that, At least one resistor PAD (3) at one end of a resistor unit (2) is connected to the gate PAD (1) via a first connector (4), and the other end is connected to the gate busbar (6) via a second connector (5).

3. The power device gate resistor structure according to claim 2, characterized in that, The first connector (4) includes a connecting line (41).

4. The power device gate resistor structure according to claim 2, characterized in that, The first connector (4) includes a connecting wire (41) and a jumper metal (42). The jumper metal (42) is disposed between the gate PAD (1) and the resistor unit (2); The jumper metal (42) is connected to the gate PAD (1); The resistor PAD (3) is connected to the jumper metal (42) via a connecting wire (41).

5. The power device gate resistor structure according to claim 2, characterized in that, At least two resistor units (2) are connected in parallel between the gate PAD (1) and the gate bus (6).

6. The power device gate resistor structure according to claim 2, characterized in that, At least two resistor units (2) are connected in series between the gate PAD (1) and the gate bus (6).

7. The power device gate resistor structure according to claim 1, characterized in that, A dielectric isolation layer (100) is disposed below the gate PAD (1) and the resistor PAD (3). The resistor unit (2) is a polysilicon resistor (21) disposed in the dielectric isolation layer (100); The two ends of the polysilicon resistor (21) are connected to the corresponding resistor PAD (3) through contact holes (200).

8. The power device gate resistor structure according to claim 1, characterized in that, A dielectric isolation layer (100) is disposed below the gate PAD (1) and the resistor PAD (3). A substrate layer (300) is disposed below the dielectric isolation layer (100). The resistor unit (2) is a trench resistor (22) extending into the substrate layer (300). The two ends of the trench resistor (22) are connected to the corresponding resistor PAD (3) through the contact hole (200).

9. A power device, characterized in that, Includes the power device gate resistor structure as described in any one of claims 1-8.

10. A method for fabricating a power module using the power device as described in claim 9, characterized in that, include: Obtain individual test data for each chip to be packaged; Based on the parasitic inductance differences of the current paths of each parallel chip in the module layout, the final equivalent gate resistance required by each chip is calculated, and the corresponding bonding strategy is determined. That is, several resistor units (2) are connected between the gate PAD (1) and the gate bus (6) in a separate, series or parallel manner.

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