A method for fabricating back-gate field-effect transistors based on two-dimensional P-type TMDs

Abstract

This invention discloses a method for fabricating back-gate field-effect transistors based on two-dimensional P-type TMDs, belonging to the field of semiconductor devices. The method includes: growing two-dimensional P-type TMDs on a cleaned substrate, defining a channel region and fabricating source and drain electrodes to obtain the transistor to be processed; subjecting the transistor to a low-oxygen partial-voltage treatment to induce oxygen atoms to fill vacant anion sites in the crystal lattice; and simultaneously performing oxygen substitution doping on some non-vacant anion sites in the crystal lattice. The method provided by this invention can achieve controllable oxygen substitution doping of P-type two-dimensional semiconductors while maintaining the integrity of the main two-dimensional crystal structure and avoiding oxide formation. This significantly improves the hole mobility and on-state current of P-type transistors, reduces metal contact resistance, and improves device performance. It eliminates the need for complex surface functionalization or doping steps, meets CMOS back-end interconnect compatibility requirements, and is suitable for the fabrication and integration of large-area two-dimensional P-type logic devices and analog / sensor chips.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, and more specifically, relates to a method for fabricating a back-gate field-effect transistor based on two-dimensional P-type TMDs. Background Technology

[0002] As silicon-based integrated circuit technology approaches its physical limits, the continuation of Moore's Law faces significant challenges. To further shrink device size and improve performance, academia and industry have turned their attention to novel channel materials. Two-dimensional semiconductor materials, especially transition metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS2), molybdenum distearate (MoTe2), and tungsten diselenide (WSe2), are considered ideal candidates for next-generation ultra-low-power, high-performance transistors due to their atomically thin thickness, excellent electrostatic gate control capabilities, tunable band gaps, and relatively high theoretical mobility. Among them, P-type TMDs, such as MoTe2 and WSe2, which are predominantly hole-conducting, are key P-type channel materials for realizing two-dimensional CMOS complementary logic.

[0003] However, transistors based on P-type TMDs have the following defects: Taking two-dimensional selenide materials (such as WSe2) as an example, during the growth of WSe2, since the saturated vapor pressure of selenium (Se) is much higher than that of transition metals (W), selenium atoms in the lattice are very easy to volatilize and escape during the high-temperature growth or cooling stage, forming selenium vacancies. This leads to: (1) Selenium vacancies introduce donor-type energy level defects in the band gap of the material, which will provide electrons to the conduction band, making the material exhibit partial N-type doping, which severely compensates for the P-type carriers (holes), making it difficult for WSe2 transistors to achieve P-type devices with high on-state current and low off-state leakage current; (2) High-density defect states will firmly "pin" the Fermi level near the conduction band. When a high work function metal is used as the contact electrode, the Fermi level of the metal cannot be effectively aligned with the top of the valence band of the semiconductor, resulting in a huge Schottky barrier and increased contact resistance.

[0004] Because two-dimensional materials are extremely thin, traditional three-dimensional semiconductor doping techniques such as ion implantation are difficult to apply directly. Therefore, how to achieve effective doping without destroying the main crystal structure is a key technical challenge for the development of two-dimensional P-type TMDs devices. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a method for fabricating back-gate field-effect transistors based on two-dimensional P-type TMDs, which can improve the hole mobility and on-state current of P-type transistors, reduce metal contact resistance, and improve device performance without destroying the main crystal lattice structure.

[0006] To achieve the above objectives, according to a first aspect of the present invention, a method for fabricating a back-gate field-effect transistor based on two-dimensional P-type TMDs is provided, comprising: S1. After growing two-dimensional P-type TMDs on a cleaned substrate, the channel region is defined and the source and drain are fabricated to obtain the transistor to be processed. S2, at a preset low temperature, the transistor to be processed is subjected to low oxygen partial pressure treatment, so that oxygen atoms fill the vacant anion sites in the crystal lattice, and at the same time, substitutional doping is performed on some non-vacant anion sites in the crystal lattice to obtain the prepared back gate field effect transistor. The preset low temperature range is 100~300 ℃, and the oxygen pressure range of the low oxygen partial pressure treatment is 10 ℃. -3 ~5 Torr.

[0007] Preferably, in step S2, the transistor is subjected to low-temperature and low-oxygen partial pressure treatment in a vacuum annealing furnace; the heating rate of the vacuum annealing furnace is in the range of 10~30 ℃ / min.

[0008] Preferably, the time range of the low oxygen partial pressure treatment is 1 to 3 hours.

[0009] Preferably, the substrate is a heavily doped low-resistivity silicon substrate with a silicon dioxide dielectric film.

[0010] Preferably, the source and drain are made of any high work function metal material, or any combination of two high work function metal materials.

[0011] Preferably, the high work function metal material is palladium, platinum, or gold.

[0012] Preferably, the thickness of the source and drain electrodes ranges from 30 to 100 nm.

[0013] According to a second aspect of the present invention, a back-gate field-effect transistor based on two-dimensional P-type TMDs is provided, which is prepared by means of the method described in the first aspect.

[0014] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: The method provided by this invention utilizes low-temperature, low-pressure oxygen treatment to fill anion vacancies in the lattice of two-dimensional P-type TMDs materials at the atomic scale with oxygen atoms, and to replace some non-vacant anion sites, forming oxygen substitutional doping. Since oxygen has a higher electronegativity than chalcogens (Se, Te), oxygen substitutional doping can induce local charge redistribution, equivalent to introducing an acceptor level, with the Fermi level shifting towards the valence band top, thereby increasing hole concentration and reducing metal contact resistance, thus obtaining high-quality transistor devices. This method, without significantly damaging the bulk lattice of the two-dimensional material, utilizes the difference in electronegativity and bonding characteristics between oxygen and the original anions to induce local charge redistribution and Fermi level shift through a small amount of substitutional doping. This achieves simultaneous optimization of P-type carrier density and contact barrier in the channel and contact regions, and its process temperature and oxygen partial pressure are within the acceptable range for CMOS back-end processes, thus possessing the feasibility for practical integration applications. The technical principle and mechanism of the method provided by this invention are as follows: (1) Under appropriate low temperature and low oxygen partial pressure conditions, the introduced oxygen atoms occupy some of the sites of group VI anions (Se, Te, etc.) in a substitutional form to form stable WO bonds; (2) Since oxygen atoms have stronger electronegativity, that is, stronger electron-accepting ability, after replacing group VI anions, they induce local charge redistribution, causing adjacent transition metal atoms and adjacent lattice regions to exhibit a "relatively electron-deficient" state. From the perspective of energy band, this can be equivalent to the Fermi level moving towards the valence band. By introducing similar acceptor doping, the equivalent hole concentration is increased, and the mobility is improved. (3) Oxygen substitution doping increases the P-type doping level in the contact region, which reduces the width of the interface depletion layer and thins the barrier, which is conducive to hole injection through tunneling or thermal excitation. At the same time, the density of related interface defect states is reduced and the Fermi level pinning effect is weakened, thereby effectively reducing the Schottky barrier.

[0015] In summary, the method provided by the present invention has the following significant advantages: (1) the mobility of the two-dimensional semiconductor material back gate field-effect transistor is improved; (2) the contact resistance of the two-dimensional semiconductor material back gate field-effect transistor is reduced; (3) the whole process is a dry thermal process, which does not involve any wet chemical reagents, is fully compatible with existing semiconductor back-end processes (BEOL), and is easy to integrate into standard production lines. Attached Figure Description

[0016] Figure 1 This is one of the flowcharts of the back-gate field-effect transistor fabrication method based on two-dimensional P-type TMDs provided in the embodiments of the present invention; Figure 2 This is the second flowchart of the method for fabricating a back-gate field-effect transistor based on two-dimensional P-type TMDs provided in the embodiments of the present invention. Figure 2In the diagrams (a) to (e), respectively, the substrate selection, the growth of two-dimensional P-type TMDs, the definition of the channel region, the fabrication of the source and drain, and the low oxygen partial pressure treatment are shown. Figure 3 A schematic diagram of the microscopic atomic structure provided by an embodiment of the present invention, in which oxygen atoms replace anion sites in the crystal lattice or fill anion vacancies at the atomic scale; Figure 3 (a) in the diagram is a schematic diagram of a crystal lattice structure with some anion vacancies. Figure 3 (b) is a schematic diagram of the lattice structure after oxygen atom substitution doping; Figure 4 In the figure, (a) and (b) are the transfer characteristic curves and mobility comparison graphs of the device without low oxygen partial pressure treatment and the device after low oxygen partial pressure treatment, respectively. Figure 5 This is a comparison of the performance of a monolayer WSe2 material back-gate field-effect transistor fabricated on a 100 nm SiO2 substrate before and after oxygen atom substitution doping. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0018] Existing two-dimensional semiconductor doping approaches mainly fall into two categories: one is surface charge transfer or adsorption doping, such as using metal chlorides or organic molecules to form a charge transfer layer on the surface of two-dimensional materials, thereby modulating the Fermi level; the other is introducing substitute impurity atoms, such as introducing group V elements like Nb and Ta to replace W atoms during growth or post-processing, achieving substitution or interstitial doping. These methods can alter carrier types or densities to some extent, but often suffer from problems such as insufficient doping stability, complex processes, poor compatibility, or the introduction of new scattering centers. In particular, surface charge transfer doping is sensitive to environmental and temperature conditions, which is detrimental to large-scale process integration.

[0019] On the other hand, thermal annealing is widely used in existing research to improve the performance of two-dimensional semiconductor devices. Annealing in an inert atmosphere or vacuum is mainly used to remove organic residues and physically adsorbed molecules from the sample surface, thereby reducing interfacial contamination and some shallow level traps. However, this type of annealing usually does not change the carrier concentration at the intrinsic band structure level, making it difficult to solve the problem of insufficient doping in p-type TMDs. Some existing studies have also used sulfur / selenium atmospheres to compensate for chalcogen vacancies, but this requires strict control over the atmosphere and temperature and is difficult to integrate with subsequent metal deposition, dielectric deposition, and other processes. Meanwhile, in TMD systems, especially WSe2, it is generally understood that oxygen easily induces excessive oxidation on the material surface and even in the bulk phase, generating WO3. x Oxygen-containing annealing of P-type two-dimensional semiconductors such as WSe2 is typically avoided in back-end processes, as it disrupts the conductive channel, leading to decreased mobility and device performance degradation.

[0020] In summary, the following prominent issues still exist in the doping and contact engineering of two-dimensional TMDs such as P-type WSe2: First, there is a lack of stable, controllable, and CMOS back-end processes for acceptor doping technology, making it difficult to significantly improve hole concentration and conductivity while ensuring lattice integrity; Second, existing processes often require high temperatures or strong oxidation conditions, which do not match the thermal budget of back-end metal interconnects and high-k dielectrics in advanced integrated circuits, and are not conducive to compatibility with semiconductor back-end processes (BEOL).

[0021] Based on this, embodiments of the present invention provide a method for fabricating a back-gate field-effect transistor based on two-dimensional P-type TMDs, comprising: S1. After growing two-dimensional P-type TMDs on a cleaned substrate, the channel region is defined and the source and drain are fabricated to obtain the transistor to be processed.

[0022] Preferably, the substrate is a heavily doped low-resistivity silicon substrate with a silicon dioxide dielectric film.

[0023] Preferably, the source and drain electrodes are made of any high work function metal material, or any combination of two high work function metal materials. That is, the metal materials used for the source and drain electrodes are one or a combination of two high work function metals such as palladium, platinum, and gold. This is beneficial for reducing the Schottky barrier, forming ohmic contacts, and reducing contact resistance. The metal deposition is completed by electron beam evaporation, thermal evaporation, or magnetron sputtering metal thin film preparation processes.

[0024] Preferably, the thickness of the source and drain electrodes ranges from 30 to 100 nm.

[0025] Specifically, such as Figure 2As shown, in step S1, a heavily doped low-resistivity silicon substrate 1 with a silicon dioxide dielectric thin film 2 is selected, the substrate is cleaned with RCA-1 solution, and high-quality P-type two-dimensional TMDs semiconductor material 3, such as WSe2 which is mainly hole-conducting, is deposited on the selected substrate by chemical vapor deposition. The channel region is defined by reactive ion etching, and the source and drain metal electrodes 4 are prepared by electron beam exposure and electron beam evaporation to complete the preliminary preparation of the two-dimensional semiconductor material back gate field effect transistor.

[0026] The substrate includes a dielectric thin film and a substrate, wherein the dielectric thin film is silicon dioxide of different thicknesses and the substrate is heavily doped low-resistivity silicon.

[0027] As an example, such as Figure 2 As shown, step S1 may specifically include: Step S101: Select a heavily doped low-resistivity silicon substrate with a silicon dioxide dielectric film, and clean the substrate with RCA-1 solution. Specifically, mix 5 parts of deionized water, 1 part of ammonia solution, and 1 part of hydrogen peroxide solution and heat. Place the low-resistivity silicon substrate to be cleaned face up in the solution and clean for 10 minutes. Then, clean the residual solution with deionized water and dry with nitrogen gas. The thickness of the substrate is 250~500 μm. Step S102: A P-type two-dimensional semiconductor channel material, such as WSe2, which is mainly hole-conducting, is grown on the substrate by chemical vapor deposition (CVD). The channel material is a single layer or several layers with a thickness of 0.7 nm to 5 nm. The channel material includes various P-type two-dimensional transition metal chalcogenide materials such as tungsten diselenide (WSe2). Step S103: A marking layer is prepared on the substrate by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process to serve as a marker for alignment of the layout layer; Step S104: On the substrate on which the two-dimensional semiconductor material is grown, the active region is defined by processes such as spin coating photoresist, baking photoresist, photolithography, and development. After development, the active region is isolated by reactive ion etching (RIE). Step S105: The source and drain are prepared by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and stripping process.

[0028] S2, the transistor to be processed is subjected to low oxygen partial pressure treatment at a preset low temperature so that oxygen atoms fill the vacant anion sites in the crystal lattice, and at the same time, substitutional doping is performed on some non-vacant anion sites in the crystal lattice to obtain the prepared back gate field effect transistor. The preset low temperature range is 100~300 ℃, and the oxygen pressure range of the low oxygen partial pressure treatment is 10 ℃. -3 ~5 Torr; Preferably, in step S2, the transistor is subjected to low-temperature and low-oxygen partial pressure treatment in a vacuum annealing furnace; the heating rate of the vacuum annealing furnace is in the range of 10~30 ℃ / min.

[0029] Preferably, the time range of the low oxygen partial pressure treatment is 1 to 3 hours.

[0030] Specifically, in step S2, the transistor to be processed undergoes a low-temperature, low-oxygen partial pressure treatment to induce oxygen atoms to substitute and dope the anion vacancies and some anion sites present in the crystal lattice. That is, during the low-temperature, low-oxygen partial pressure treatment, such as... Figure 2 As shown, oxygen atoms diffuse into the extremely thin two-dimensional semiconductor, namely two-dimensional P-type TMDs, to fill the vacant anion sites in the lattice, while replacing some of the non-vacant anion sites, thereby forming stronger MO bonds with transition metal cations.

[0031] Preferably, a vacuum annealing furnace can be used to perform low-temperature, low-oxygen partial pressure treatment on the field-effect transistor device to be processed. The processing temperature in the vacuum annealing furnace is 100~300 degrees Celsius, which is below the safe upper limit for BEOL (Back-End of Line) reliability, wherein the oxygen pressure in the low-oxygen partial pressure treatment is 10. -3 ~5 Torr, processing time is 1~3h, and the heating rate of the vacuum annealing furnace is controlled at 10~30 ℃ / min.

[0032] The microscopic mechanism of the above-mentioned low-temperature and low-pressure oxygen treatment is as follows: After oxygen atoms replace the anion sites in the crystal lattice (forming substitutional doping) or fill the anion vacancies, due to the stronger electronegativity of oxygen atoms, that is, the stronger electron-accepting ability, the electron cloud density around them is relatively increased, making the adjacent transition metal atoms and adjacent crystal lattice regions exhibit a "relatively electron-deficient" state. From the energy band perspective, this can be equivalent to the Fermi level moving towards the valence band, introducing a similar acceptor doping, increasing the equivalent hole concentration, enhancing P-type conductivity, increasing the effective carrier density of the channel, and increasing the on-state current of the transistor device.

[0033] The contact resistance reduction mechanism of the two-dimensional semiconductor field-effect transistor after step S2 is as follows: First, the enhanced P-type doping near the contact reduces the width of the depletion layer at the metal / semiconductor interface and thins the effective barrier, which is conducive to holes entering the channel through tunneling or thermal emission, thereby reducing the Schottky barrier resistance; Second, the interface state density reduced by anion defects weakens the Fermi level pinning effect, and the advantage of high work function metals in facilitating hole injection is more fully reflected, further reducing the contact resistance.

[0034] Therefore, the method provided by the present invention utilizes oxygen at low temperature and low pressure to replace anion sites in the crystal lattice with oxygen atoms (forming substitutional doping) or fill anion vacancies at the atomic scale, thereby improving carrier mobility, reducing the contact resistance of field-effect transistors, and improving device performance. The method solves the problems of low mobility and high contact resistance caused by chalcogen vacancies in existing two-dimensional materials by using a small amount of oxygen substitution doping.

[0035] Taking a monolayer WSe2 back-gate field-effect transistor fabricated on a 100 nm SiO2 substrate and optimized using low-temperature, low-oxygen partial pressure treatment, as an example, ... Figure 2 As shown in (a), the provided substrate comprises two parts: a low-resistivity, highly doped silicon substrate and a 100 nm SiO2 gate dielectric film, with a total substrate thickness of 525 ± 25 μm. The substrate is cleaned with RCA-1 solution, requiring strict control of operating conditions such as temperature, concentration, and cleaning time to ensure cleaning effectiveness and substrate surface quality. When preparing the solution for cleaning the silicon wafer, first add 150 mL of deionized water to a beaker, then slowly inject 30 mL of ammonia solution into the deionized water, and seal the beaker opening with aluminum foil. Heat the beaker to 70 °C on a hot plate, then slowly inject 30 mL of hydrogen peroxide solution into the beaker, and seal the beaker opening again with aluminum foil. Once a large number of bubbles appear in the solution, remove the substrate to be cleaned from the wafer cassette and place it face up in the solution for cleaning for ten minutes. A large number of bubbles can be observed on the silicon wafer surface during the cleaning process. After cleaning, remove the silicon wafer and rinse it in pure deionized water to remove any residual RCA-1 solution. After cleaning, use a nitrogen gun to dry the substrate surface.

[0036] like Figure 2 As shown in (b), high-quality monolayer WSe2 material was deposited by chemical vapor deposition on a 100 nm SiO2 dielectric film. The growth process employed salt-assisted CVD, with the corresponding powder and boat placed in the appropriate positions within a muffle furnace and argon / hydrogen mixed gas introduced. The reaction was carried out at 890 °C. The reaction process mainly consisted of two steps: Step 1: WO2(s) + KCl(s) → WO x Cl y (g) involves the melting and vaporization of WO2 powder and salt, forming nuclei on the silicon wafer; the second step: WO x Cl y (g) + Se(g) → W x Se y (s) is the result of its further reaction with Se vapor. This repeated process expands the grain boundaries, forming a highly crystalline, high-quality monolayer WSe2 film.

[0037] Subsequently, a marker layer was prepared on a substrate with a high-quality monolayer WSe2 film by spin-coating photoresist, baking the photoresist, photolithography, development, evaporation deposition of metal, and lift-off processes to serve as a marker for alignment of the layout layer. In this embodiment, firstly, polymethyl methacrylate (PMMA A4) electron beam photoresist was dropped onto the cleaned substrate, covering two-thirds of the substrate surface. The photoresist was then spin-coated using a spin coater at 3000 rpm for 60 seconds. Next, the photoresist was baked on a hot plate at 180 degrees Celsius for 90 seconds. Then, electron beam lithography was used to expose the marked layer as the layout. A developer solution with a mass ratio of methyl isobutyl ketone (MIBK) to isopropanol (IPA) of 1:3 was selected. The substrate was immersed in the developer solution for 50 seconds, then removed and cleaned with IPA for 30 seconds, followed by nitrogen washing. Dry with an air gun; when evaporating and depositing metal, use an electron beam evaporation device to deposit the metal. The deposited metals include, but are not limited to, one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron, such as depositing a combination of 20nm nickel and 40nm gold; during stripping, immerse the substrate in an acetone solution at 50 degrees Celsius for 30 minutes and then rinse with a syringe to peel off the photoresist and metal from the unexposed areas. After stripping, clean with IPA and then dry with a nitrogen gun.

[0038] like Figure 2 As shown in (c), the active region is defined by etching the surrounding channel material. The active region is defined through processes such as spin-coating photoresist, photoresist baking, photolithography, and development. After development, reactive ion etching (RIE) is used to etch the isolated active region. The etching of the isolated active region uses reactive ion etching in a CF4 / Ar atmosphere.

[0039] like Figure 2 As shown in (d), source and drain metal electrodes are fabricated on the channel. The source and drain metal electrodes are one or a combination of two high work function metals such as palladium, platinum, and gold. Metal deposition is completed by electron beam evaporation, thermal evaporation, or magnetron sputtering metal thin film fabrication processes. Specifically, it is fabricated by spin-coating photoresist, baking photoresist, photolithography, development, evaporation deposition, and lift-off processes. In particular, the source and drain metal layers can be deposited by evaporation, and the deposition thickness can be including but not limited to 30-100 nm. Preferably, in one embodiment of the present invention, when fabricating the source and drain electrodes, the evaporated and deposited metals are 10 nm of platinum and 20 nm of gold. Thus, the initial fabrication of a single-layer WSe2 material back-gate field-effect transistor is completed.

[0040] like Figure 2As shown in (e), the fabricated field-effect transistor device is subjected to low-temperature, low-oxygen partial-pressure treatment in an annealing furnace, which induces oxygen atoms to substitute and dope selenium sites (especially vacancy defects) in the crystal lattice. During this process, oxygen atoms diffuse to the surface and near-surface layers of the two-dimensional semiconductor, partially replacing anion sites. Specifically, in this embodiment, the fabricated WSe2 back-gate field-effect transistor is placed in an annealing furnace, and the residual air in the chamber is evacuated to a high vacuum. The treatment temperature is 200 degrees Celsius, the oxygen flow rate is controlled at 20 sccm using a flow meter, the low-pressure oxygen atmosphere in the furnace is maintained at approximately 3-4 Torr, the annealing time is 2 hours, and the heating rate is controlled at 20 °C / min.

[0041] Those skilled in the art should understand that the quantity of solution, heating temperature, time, and thickness of deposited metal in this embodiment are for illustrative purposes only and should not be construed as limiting the invention. Specifically, the photoresist mentioned in the above preparation process includes conventional photoresist and electron beam photoresist; photolithography includes conventional photolithography and electron beam photolithography; and evaporation deposition includes thermal evaporation deposition and electron beam evaporation deposition.

[0042] like Figure 3 As shown, the physical mechanism of the method provided by this invention is based on the substitutional filling effect of oxygen atoms on anion vacancies. Taking the aforementioned WSe2 back-gate transistor as an example, during the chemical vapor deposition preparation and subsequent micro / nano fabrication of WSe2, Se atoms are easily lost in the crystal lattice to form vacancy defects, such as... Figure 3 As shown in (a) above. These vacancies lead to dangling bonds in transition metal atoms (W), introducing deep-level defect states into the material's bandgap. These not only act as scattering centers, reducing carrier mobility, but also induce severe Fermi level pinning. This invention utilizes the fact that oxygen (O) and selenium (Se) belong to Group VI of the periodic table, have the same number of valence electrons, and are chemically compatible. Driven by thermal activation energy provided under specific temperature and low oxygen pressure conditions, and under appropriate low temperature and low oxygen partial pressure conditions, the introduced oxygen atoms occupy some Group VI anion sites in a substitutional form, while also filling selenium vacancies. For example... Figure 3As shown in (b), oxygen atoms can precisely occupy selenium sites and form stable WO covalent bonds with the surrounding transition metal atoms, i.e., W, to complete lattice repair. This "oxygen substitution doping" process will trigger the following processes: (1) Since oxygen atoms have stronger electronegativity, i.e. stronger electron-accepting ability, the electron cloud density around them is relatively increased, making the adjacent W atoms and adjacent lattice regions exhibit a "relatively electron-deficient" state. From the energy band perspective, this can be equivalent to the Fermi level moving towards the valence band, i.e., introducing an electrical effect similar to acceptor doping, which increases the equivalent hole concentration and mobility; (2) Oxygen substitution doping increases the P-type doping level in the contact region, reduces the width of the interface depletion layer and thins the barrier, which is conducive to hole injection through tunneling or thermal excitation. At the same time, the density of related interface defect states decreases, the Fermi level pinning effect weakens, and thus effectively reduces the Schottky barrier. This microscopic doping mechanism brings two significant improvements: first, it increases the equivalent hole concentration, which significantly improves the field-effect mobility; second, it effectively reduces the interface state density at the contact interface, relieves Fermi level pinning, and enables the formation of ohmic contacts with lower potential barriers between the metal and the semiconductor, thereby reducing the contact resistance.

[0043] Figure 4 This is a comparison of the driving voltage and source / drain current relationships before and after oxygen substitution doping treatment of a monolayer WSe2 back-gate field-effect transistor fabricated on a 100 nm SiO2 substrate. Figure 4 As shown, by using oxygen substitution doping in two-dimensional semiconductor materials with anions and anion vacancy defects, the carrier mobility in the channel can be improved, thereby significantly increasing the on-state current of the back gate field-effect transistor made of monolayer WSe2 material. Figure 5 This image shows a comparison of extraction performance parameters before and after oxygen substitution doping for monolayer WSe2 back-gate field-effect transistors fabricated on a 100 nm SiO2 substrate. After oxygen substitution doping, the subthreshold swing of monolayer WSe2 back-gate field-effect transistors of the same size decreased from 3000–4000 mV / dec to 600–1000 mV / dec; the interface state density increased from greater than 10... 13 cm -2 eV -1 Reduced to 10 12 cm -2 eV -1 The hole carrier mobility of transistors ranges from approximately 40 to 60 cm⁻¹. 2 / V·s increased to 100~150 cm 2 / V·s; Contact resistance was extracted using TLM, reducing it from 2.2~2.5 kΩ·μm to 0.5~0.7 kΩ·μm. The method provided by this invention utilizes oxygen diffusion to fill larger anion vacancies, substituting doping of anions and anion vacancy defects in two-dimensional semiconductor materials at the atomic scale. This increases the equivalent hole concentration, significantly improving field-effect mobility, effectively reducing the interface state density at the contact interface, and relieving Fermi level pinning. This allows for the formation of a lower barrier ohmic contact between the metal and semiconductor, thereby reducing contact resistance. Compared to untreated devices, the oxygen-substituting-doped devices exhibit more than double the hole carrier mobility, a significant decrease in contact resistance, and a several-fold increase in on-state current.

[0044] In summary, the method provided by this invention, based on low-temperature oxygen substitution doping of P-type two-dimensional transition metal chalcogenides to reduce the contact resistance of field-effect transistors and improve device performance, can effectively solve the problems of existing P-type two-dimensional semiconductor devices, such as the lack of stable, controllable doping techniques compatible with CMOS back-end processes and the incompatibility between existing processes and semiconductor back-end processes (BEOL), thus obtaining high-quality, high-performance devices. Furthermore, the method is simple in process, has controllable parameters, and is compatible with existing CMOS processes. It is applicable to various P-type two-dimensional semiconductors and different device structures (back gate, top gate, partial gate, etc.), which is beneficial for realizing high-performance P-type two-dimensional transistors and their logic circuits.

[0045] This invention provides a transistor based on two-dimensional P-type TMDs, which is prepared using the preparation method described in any of the above embodiments.

[0046] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a back-gate field-effect transistor based on two-dimensional P-type TMDs, characterized in that, include: S1. After growing two-dimensional P-type TMDs on a cleaned substrate, the channel region is defined and the source and drain are fabricated to obtain the transistor to be processed. S2, at a preset low temperature, the transistor to be processed is subjected to low oxygen partial pressure treatment, so that oxygen atoms fill the vacant anion sites in the crystal lattice, and at the same time, substitutional doping is performed on some non-vacant anion sites in the crystal lattice to obtain the prepared back gate field effect transistor. The preset low temperature range is 100~300 ℃, and the oxygen pressure range of the low oxygen partial pressure treatment is 10 ℃. -3 ~5 Torr.

2. The method as described in claim 1, characterized in that, In step S2, the transistor is subjected to low-temperature and low-oxygen partial pressure treatment in a vacuum annealing furnace; the heating rate of the vacuum annealing furnace is in the range of 10~30 ℃ / min.

3. The method as described in claim 1 or 2, characterized in that, The time range for the low oxygen partial pressure treatment is 1 to 3 hours.

4. The method as described in claim 1, characterized in that, The substrate is a heavily doped low-resistivity silicon substrate with a silicon dioxide dielectric thin film.

5. The method as described in claim 1, characterized in that, The source and drain electrodes are made of any high work function metal material, or any combination of two high work function metal materials.

6. The method as described in claim 5, characterized in that, The high work function metallic material is palladium, platinum, or gold.

7. The method as described in claim 5, characterized in that, The thickness of the source and drain electrodes ranges from 30 to 100 nm.

8. A back-gate field-effect transistor based on two-dimensional P-type TMDs, characterized in that, It is prepared by the method described in any one of claims 1-7.

Images