Image sensor and method of manufacturing the same

Abstract

This invention provides an image sensor and a method for manufacturing the same. The method for manufacturing the image sensor includes the following steps: A semiconductor substrate is provided, having a front surface and a back surface opposite to the front surface. A photosensitive region is formed in the semiconductor substrate. A floating diffusion region adjacent to the photosensitive region is formed for receiving image charges from the photosensitive region. A dielectric layer is formed on the front surface of the semiconductor substrate. A gate electrode is formed in the dielectric layer, electrically coupled to the photosensitive region and the floating diffusion region. A deep trench isolation structure adjacent to the photosensitive region is formed by an etching process. The deep trench isolation structure extends from the dielectric layer on the front surface of the semiconductor substrate toward the back surface. The deep trench isolation structure has an upper surface flush with the top surface of the dielectric layer.

Description

Technical Field

[0001] This invention relates to an image sensor with a deep trench isolation structure and a method for manufacturing the same. Background Technology

[0002] Generally, an image sensor includes multiple pixels arranged in a matrix and generates optical signals from the pixels to obtain a two-dimensional image signal. Therefore, within each pixel, a photoelectric conversion component is provided to generate a charge based on incident light, and circuitry is provided for outputting the signal generated by the photoelectric conversion component.

[0003] Each pixel can be configured as follows. A photodiode serves as the photoelectric conversion component. Light-generated charges (e.g., electrons or holes) from the photodiode in response to incident light are transferred via a transfer transistor to a coupled floating diffusion region. The signal from the floating diffusion region is supplied to the gate of a source follower transistor, which varies as a function of the incident light measured by the photodiode. The image signal from the source follower transistor is output to the output line via a select transistor. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the bit line and converted into a digital value to provide information representing the external scene.

[0004] Image sensors include deep trench isolation structures positioned between adjacent pixels to suppress crosstalk (e.g., electrical and / or optical) between photodiodes. Deep trench isolation (DTI) structures are filled with dielectric or polysilicon. However, current DTI structures filled with dielectric or polysilicon are not highly reflective and exhibit some degree of transparency. Therefore, DTI structures cannot effectively meet the requirements of excellent optical isolation and the high reflectivity of the DTI filling material to redirect scattered photons back into the pixel. Summary of the Invention

[0005] A method for manufacturing an image sensor includes the following steps: Providing a semiconductor substrate having a front surface and a back surface opposite the front surface. Forming a photosensitive region in the semiconductor substrate. Forming a floating diffusion region adjacent to the photosensitive region to receive image charge therefrom. Forming a gate electrode on the side adjacent to the photosensitive region. Forming a deep trench isolation (DTI) structure adjacent to the photosensitive region by an etching process. A dielectric layer (e.g., an oxide-based material) is disposed on the front surface of the semiconductor substrate. The DTI structure extends from the dielectric layer on the front surface of the semiconductor substrate toward the back surface of the semiconductor substrate. The DTI structure is filled with a reflective metallic material. In some embodiments, the material filling process is performed on the front surface of the semiconductor substrate. In some embodiments, the material filling process is performed on the back surface of the semiconductor substrate.

[0006] Using the image sensor disclosed herein, it is possible to form a deep trench isolation (DTI) structure that can achieve excellent electrical and optical isolation by filling the DTI structure with a highly reflective metallic material and redirecting scattered photons back into the pixel. Attached Figure Description

[0007] The embodiments of this disclosure will be described based on the following drawings, wherein:

[0008] Figures 1 to 11 This is a schematic diagram illustrating an exemplary fabrication process of an image sensor deep trench isolation (DTI) structure according to an embodiment of the present disclosure;

[0009] Figure 12 The block diagram illustrates the DTI structure formation process according to an embodiment of the present disclosure;

[0010] Figures 13 to 17 For illustrative purposes only, this diagram illustrates another embodiment of the present disclosure. Figure 6 A cross-sectional view of the image sensor DTI structure fabrication process after the shown steps; and

[0011] Figure 18 The block diagram illustrates a DTI structure formation process according to another embodiment of the present disclosure.

[0012] Symbol Explanation: 10: Image sensor; 50: Photoresist mask; 110: Semiconductor substrate; 111: Front surface; 112: Epitaxial layer; 113, 113': Back surface; 114: Photosensitive region; 114a: First side; 114b: Second side; 116: Floating diffusion region; 117: LDD region / doped region; 121, 137, OP, OP1, OP2: Openings; 122: HTO layer; 124: Sidewall spacer Components; 132: Gate electrode; 134: Gate dielectric layer; 138: Oxide layer; 140: P+ substrate; 152: Oxide layer; 154, 214, 216, 326, 352: High-k dielectric layers; 160, 160': Deep trench isolation structure; 162: Reflective metal material; 163: Tip portion; 164: Process void; 165: Back side; 166: Metal mesh; 172: Dielectric material layer; 174 : Metal contacts; 182, 186: Bonding layers; 182a, 186a: Interlayer dielectric layers; 182b, 186b: Metal layers; 190: Logic substrate; 212: Thin oxide layer; 218, 328: Buffer oxide layers; 222, 322: Color filters; 224, 324: Composite mesh; 230, 330: Microlenses; 310: IMD layer; 312: Undoped silicon oxide thin film; 314: Doped silicon oxide thin film; 37 0: Substrate; D1: First depth; D2: Second depth; D3: Third depth; D4: Fourth depth; PR: Photoresist film; R1: Region; S101, S102, S103, S104, S105, S106, S201, S202, S203, S204, S205, S206, S207, S208: Step; TC: Trench cavity; W1: First width; W2: Second width; W3: Third width. Detailed Implementation

[0013] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be implemented without one or more of these specific details, or can be implemented using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects. Note that the embodiments described below do not limit this disclosure. Configurations formed by selectively combining multiple icons are also included in this disclosure.

[0014] In this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0015] It should be understood that although the terms first, second, third, etc., may be used in the disclosure and claims to describe various components, these components should not be limited by these terms and should not be used to determine the process sequence or formation sequence of the related components. Unless otherwise indicated, these terms are used only to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of the disclosed embodiments.

[0016] Several technical terms are used in this specification. Unless specifically defined herein or the context in which they are used explicitly implies otherwise, these terms shall be used with their usual meaning in the relevant technical field. It should be noted that component names and symbols may be used interchangeably in this document (e.g., Si vs. silicon); however, they have the same meaning.

[0017] Figures 1 to 11 This is a schematic cross-sectional view illustrating the formation process of the deep trench isolation (DTI) structure 160 of the image sensor 10 according to an embodiment of the present disclosure. Figure 12 To illustrate the block diagram, the fabrication process of the DTI structure 160 according to an embodiment of this disclosure is explained. For example... Figure 11 As shown, according to some embodiments, the DTI structure 160 can be used in an image sensor chip (e.g., a front illumination (FSI) image sensor chip or a back illumination (BSI) image sensor chip).

[0018] Reference Figure 1 and Figure 12 In the formation step S101, a semiconductor substrate 110 is provided. The semiconductor substrate 110 may include, for example, an active layer of bulk silicon, doped or undoped silicon, or a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a semiconductor material layer, such as silicon, formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate such as a silicon or glass substrate. Alternatively, the semiconductor substrate 110 may include another elemental semiconductor, such as germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used.

[0019] Semiconductor substrate 110 has a front surface 111 and a back surface 113 opposite to the front surface 111. Active devices such as transistors can be formed on the front surface 111. As described in more detail below, in this embodiment, a DTI structure 160 can be formed from the front surface 111 of the semiconductor substrate 110. Those skilled in the art will understand that in some embodiments, similar methods can also be applied to DTI structures formed from the back surface 113 of the semiconductor substrate 110.

[0020] Refer again Figure 1 and Figure 12 In the formation step S102, a photosensitive region 114 may be formed or otherwise disposed in the semiconductor substrate 110 and adjacent to the front surface 111. The photosensitive region 114 may be included in a photosensitive device. In some embodiments, the photosensitive region 114 may be formed, for example, by implanting suitable ions. In some embodiments, impurity ions may be implanted into an epitaxial layer 112 within the semiconductor substrate 110. In some embodiments, the epitaxial layer 112 may be formed on a substrate or bulk substrate. In some embodiments, the photosensitive region 114 is configured to convert optical signals (e.g., photons) into electrical signals and may include a PN junction photodiode, a PNP phototransistor, an NPN phototransistor, etc. In the illustrated embodiment, the photosensitive region 114 may include an n-type doped region formed within a p-type semiconductor layer (e.g., at least a portion of the semiconductor substrate 110). In some embodiments, the p-type semiconductor layer may be an epitaxial layer 112. In some embodiments, the p-type semiconductor substrate may isolate and reduce electrical crosstalk between adjacent photosensitive regions 114.

[0021] Reference Figure 2 and Figure 12 In step S103 of the formation process, in some embodiments, a lightly doped source / drain (LDD) region 117 is formed adjacent to the front surface 111 of the semiconductor substrate 110 and adjacent to the first side 114a of the photosensitive region 114. In some embodiments, the floating diffusion region 116 may include an N+ doped region, which can be formed by annealing to activate the dopant to improve the crystal structure of the material and can be configured to store carriers transferred from the photodiode. In some embodiments, the lightly doped source / drain (LDD) region 117 may be formed or otherwise disposed between the floating diffusion region 116 and the photosensitive region 114.

[0022] In some embodiments, a dielectric layer, such as a high-temperature oxide (HTO) layer 122, may be formed on the front surface 111 of the semiconductor substrate 110. In some embodiments, the selected thickness of the HTO layer 122 may range from 5 nanometers to approximately 10 nanometers. In some embodiments, the HTO layer 122 may be formed of aluminum oxide (AlO), tantalum oxide (TaO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO), or combinations thereof.

[0023] Reference Figure 3 A gate dielectric layer 134 is formed within the HTO layer 122 using photolithography processes (e.g., masking and etching processes). In this embodiment, reference is made to... Figure 12 In the formation step S104, a gate electrode 132 can be formed on the gate dielectric layer 134 and between the photodiode in the floating diffusion region 116 and the photosensitive region 114. For example... Figure 3 As shown, a gate dielectric layer 134 is disposed between the gate electrode 132 and the front surface 111 of the semiconductor substrate 110, and the gate electrode 132 is adjacent to the first side 114a of the photosensitive region 114. The gate electrode 132 selectively couples the floating diffusion region 116 to the photodiode of the photosensitive region 114 in response to a control voltage applied thereto. In this embodiment, the gate electrode 132 can serve as a transfer gate to transfer the photocharge generated by the photodiode formed in the photosensitive region 114 to the floating diffusion region 116.

[0024] Refer again Figure 3 In some embodiments, sidewall spacers 124 may be formed to surround the sidewalls of the gate electrode 132. In some embodiments, the sidewall spacers 124 may be formed of, for example, a nitride film (e.g., silicon nitride (SiN)). Figure 4 As shown, both the gate electrode 132 and the sidewall spacer 124 may be further covered by the HTO layer 122. In some embodiments, another dielectric layer, such as a SiN nitride layer 136, may be further formed and stacked on the HTO layer 122. In some embodiments, both the HTO layer 122 and the nitride layer 136 are completely formed on the front surface 111 of the semiconductor substrate 110. The deposition of the nitride layer 136 can block oxidation of the source / drain regions (e.g., doped regions such as floating diffusion region 116 or doped region 117), thereby preventing oxidation-enhanced diffusion during manufacturing processes (e.g., annealing).

[0025] In this embodiment, the deep trench isolation formation region R1 may be located within the semiconductor substrate 110 and adjacent to the second side 114b of the photosensitive region 114 for subsequent processes forming the DTI structure 160.

[0026] Reference Figure 5An oxide layer 138 (a second oxide layer) can be formed over the nitride layer 136 and the HTO layer 122 to form an oxide-nitride-oxide (ONO) stack. Specifically, in this embodiment, the nitride layer 136 is disposed between the second oxide layer 138 and the HTO layer 122. In some embodiments, a photoresist film PR with a corresponding pattern of openings OP disposed above the formation region R1 can be blanket-coated (e.g., spin-coated) to cover the ONO stack. In some embodiments, the width of the openings OP can be approximately 10-20 micrometers. In this embodiment, the photoresist film PR is used as a photomask to etch and pattern the underlying layers (HTO layer 122, nitride layer 136, and oxide layer 138) for forming the DTI trenches of the DTI structure 160.

[0027] Reference Figure 5 and Figure 6 The ONO stack is etched, and then the photoresist film PR is removed. For example... Figure 5 and Figure 6 As shown, the region R1 is further etched by removing substrate material from the semiconductor substrate 110 to form a trench cavity TC therein. In some embodiments, the semiconductor substrate 110 may be bonded to a wafer substrate, such as a P+ substrate 140, after the trench cavity TC is formed. In some embodiments, the trench cavity TC may be etched to a depth slightly exceeding the remaining thickness after the semiconductor substrate 110 is bonded to the P+ substrate 140 and thinned.

[0028] In this embodiment, the trench cavity TC extends from the front surface 111 of the semiconductor substrate 110 into the semiconductor substrate 110 and toward the back surface 113 of the semiconductor substrate 110. It is understood that the etching process of the semiconductor substrate 110 can be performed using an acceptable etching process, which can be performed at a relatively low temperature to reduce damage to other features within the image sensor, such as electrical components, interconnect structures, etc.

[0029] In some embodiments, the semiconductor substrate 110 is formed of silicon. The etching process is performed using dry etching methods, including but not limited to inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resonance (ECR), reactive ion etching (RIE), etc. Process gases include, for example, fluorine-containing gases (such as SF6, CF4, CHF3, NF3), chlorine-containing gases (such as Cl2), Br2, HBr, BCl3, and / or similar gases. In some embodiments, the photoresist film PR is consumed during the etching process described above. In other embodiments, the remaining portion of the photoresist film PR may be removed, for example, in a plasma ashing and / or wet stripping process. In this etching process, polymer residues on the oxide layer 138 and the trench cavity TC sidewalls are removed by diluting HF to expose the nitride layer 136 beneath the oxide layer 138.

[0030] In this embodiment, as Figure 6 As shown, the etching process can slightly undercut the HTO layer 122 beneath the nitride layer 136. An opening 121 (first opening) is formed in the HTO layer 122, which may have a width greater than the opening 137 (second opening) formed in the nitride layer 136. (Refer to...) Figure 6 After the trench cavity TC is formed by the etching process, the sidewalls of the trench cavity TC can be uniformly oxidized using an in-situ steam generator (ISSG) reactor (not shown) to form an oxide layer 152. In the illustrated embodiment, the thickness of the oxide layer 152 conformally lining the sidewalls of the trench cavity can be in the range of approximately 5 to 15 nanometers. In the illustrated embodiment, the thermal cycling in the above oxidation process can also be used as... Figure 4 The final activation annealing process of the doped region 117 and the floating diffusion region 116 shown.

[0031] In some embodiments, such as can be selectively retained on the semiconductor substrate 110 Figure 6 The nitride layer 136 is shown. In one embodiment, which fills a trench from the back surface 113 of the semiconductor substrate 110, as will be further described in the following paragraphs of this disclosure, the nitride layer 136 may remain in situ to form a sealed trench cavity TC. Figure 6 and Figure 12As shown in the formation process S105, the trench cavity TC can have an arcuate shape due to the etching process. That is, the trench cavity TC may include a neck portion having a trench width larger than the rest. In some embodiments, the trench cavity TC may slope outward from its upper portion toward the opening 121 of the HTO layer 122. Specifically, the trench cavity TC may have a first width W1 of about 70 nm to 150 nm at a first depth D1, and slope from the first depth D1 to a neck portion of the trench cavity TC having a second width W2 of about 80 nm to 170 nm at a second depth D2 that is greater than the first depth D1 relative to the front surface 111. In some embodiments, the trench cavity TC may further slope inward from the neck portion having the second width W2 to a lower portion at a third depth D3 that is greater than the second depth D2 relative to the front surface 111, the lower portion having a third width W3 of about 70 nm to 150 nm. Figure 6 As shown, the groove width of the groove cavity TC at a depth (e.g., a fourth depth D4) that is farther or greater than the third depth D3 relative to the front surface 111 can be the same as the third width W3 at the third depth D3.

[0032] Reference Figure 7 In some embodiments, the nitride layer 136 can be removed by a thermal phosphoric acid etching process to expose the opening 121 of the HTO layer 122. Alternatively, a high-k dielectric layer 154 with a fixed negative charge can be deposited on the oxide layer 152 on the sidewall of the trench cavity TC using, for example, atomic layer deposition (ALD). These processes can be used to form metal-oxide-semiconductor (MOS) structures with a high critical voltage Vt and to passivate the sidewalls of the trench cavity TC. In this embodiment, the high-k dielectric layer 154 with a fixed negative charge disposed on p-silicon can attract holes near the surface of the trench cavity TC sidewall, forming a hole accumulation or enrichment region to passivate the sidewall surface of the trench cavity TC. This creates a hole accumulation region on the sidewall of the trench cavity TC, which would otherwise require sidewall doping. Therefore, high-temperature processes (greater than 700 degrees Celsius) that could damage the device structure are no longer necessary.

[0033] Refer again Figure 7 In step S106, in some embodiments, a reflective metal material 162 with high reflectivity, such as aluminum, can be used to fill the trench cavity TC. The reflective metal material 162 can be deposited within the opening of the trench cavity TC exposed from the front surface 111 of the semiconductor substrate 110 via chemical vapor deposition (CVD) or ALD processes to fill the trench cavity TC, forming a deep trench isolation (DTI) structure 160. Figure 7As shown, in this embodiment, the reflective metal material 162 may also fill the opening 121 of the HTO layer 122 and blanket the surface of the HTO layer 122. In some other embodiments, the reflective metal material 162 may also include silver (Ag) or other materials with high reflectivity.

[0034] It is understood that by depositing a highly reflective metallic material (e.g., Al or Ag) in the trench cavity TC to form the DTI structure 160, excellent electrical and optical isolation can be achieved. Furthermore, the high reflectivity of the reflective metallic material 162 can redirect incident light back to the photosensitive region 114 of the corresponding pixel. Therefore, crosstalk between pixels can be significantly reduced and avoided.

[0035] In some embodiments, at least one process void 164 may be formed within the reflective metal material 162 during the formation of the DTI structure 160. It should be noted that the presence of the process void 164 within the filled reflective metal material 162 can reduce internal strain generated during the deposition process.

[0036] Reference Figure 8 A back-etch process can be performed on portions of the reflective metallic material 162 covering the blanket-covered HTO layer 122. Subsequently, a dielectric material layer 172 (e.g., an inter-metal dielectric (IMD) layer) is deposited over the HTO layer 122 and the filled reflective metallic material 162 covering the opening 121 for subsequent processing. In some embodiments, the top or upper surface of the filled reflective metallic material 162 is flush with or aligned with the HTO layer 122. The dielectric material layer 172 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, spin-coated dielectric, or a low-k dielectric. In some embodiments, the dielectric material layer 172 may be further etched and patterned to form openings penetrating the dielectric material layer 172 for filling with metallic material to serve as metal contacts 174. Metal contacts 174 penetrating the dielectric layer 172 can be electrically connected to the transmission gate (gate electrode 132), the floating diffusion region 116, the LDD region 117, and optionally to the reflective metal material 162 filled in the DTI structure 160. Metal contacts 174 can couple to the reflective metal material 162 filled in the DTI structure 160 to receive a bias voltage, such as a negative bias voltage for sidewall surface passivation.

[0037] Reference Figure 9 The dielectric material layer 172 disposed on the semiconductor substrate 110 can be bonded to the logic substrate 190 (e.g., an ASIC wafer) via a bonding process using bonding layers 182 and 186 (e.g., oxide bonding or hybrid bonding). Bonding layers 182 and 186 may respectively include interlayer dielectric (ILD) layers 182a and 186a and metal layers 182b and 186b distributed therein. Figure 8 and Figure 9 As shown, a thinning process is performed on the P+ substrate 140 bonded to the back surface 113 of the semiconductor substrate 110 using mechanical polishing and wet etching processes, and the thinning process is stopped when the semiconductor substrate 110 reaches the target thickness. In addition, a highly selective dry etching process is performed on the back surface 113 of the semiconductor substrate 110 to expose the tip portion 163 of the back side of the DTI structure 160.

[0038] Reference Figure 10 A planarization process, such as chemical mechanical polishing (CMP), can be performed to remove the tip portion 163 on the back side of the DTI structure 160 and the back side of the semiconductor substrate 110. By performing the above planarization process, the back surface 113' of the semiconductor substrate 110 formed by the process is coplanar or aligned with the back surface 165 of the DTI structure 160. Figure 10 As shown, a thin oxide layer 212 (first high-k dielectric layer) can then be deposited on the back surface 113' and the back surface 165 of the DTI structure 160 to passivate the back surface 113' of the semiconductor substrate 110.

[0039] Reference Figure 11 In some embodiments, another high-k dielectric layer 214 (a second high-k dielectric layer) may be deposited on the thin oxide layer 212 (the first high-k dielectric layer) as an additional passivation layer. In some embodiments, a third high-k dielectric layer 216 may be formed on the second high-k dielectric layer 214 as an anti-reflective layer for forming optical components thereon.

[0040] like Figure 11 As shown, a buffer oxide layer 218 can be disposed on the antireflective layer (third high-k dielectric layer 216) to prepare the back surface for deposition of color filters 222 and composite mesh 224 thereon. In some embodiments, composite mesh 224 may comprise a stack of metallic mesh and low-refractive-index (low-n) mesh. In some embodiments, the low-n mesh may comprise a low-n dielectric material, such as an oxide (e.g., SiO2) or hafnium oxide (e.g., HfO2), or a material having a refractive index lower than that of color filter 222. The refractive index of the low-n mesh is lower than that of the material of color filter 222, thereby isolating adjacent color filters 222 to mitigate optical crosstalk and increase the effective size of color filter 222 (e.g., by directing incident light from both sides of color filter 222 to the center of color filter 222). The metallic mesh blocks light, thereby isolating adjacent color filters 222 and reducing crosstalk. In some embodiments, the metallic mesh may comprise, for example, tungsten, copper, or aluminum-copper. Figure 11 As shown, in this embodiment, a microlens 230 can be further disposed on the composite grid 224 and the color filter 222 to form a back-illuminated image sensor 10.

[0041] like Figure 12 The formation steps of the DTI structure 160 shown in this embodiment, by forming the DTI structure 160 after source / drain implantation and gate formation, allow the application of a high-temperature process, which can heal and repair the damaged trench surface of the trench cavity TC caused by the etching process.

[0042] Figures 13 to 18 Explanation in Figure 6 Another embodiment of the manufacturing process following the manufacturing steps shown. Figure 18 This is a schematic block diagram illustrating the formation process of a DTI structure according to another embodiment of the present disclosure.

[0043] Reference Figure 13 and Figure 18 , Figure 18 The formation steps S201, S202, S203, and S204 shown are... Figure 12 The formation steps S101, S102, S103, and S104 shown are the same or similar. Therefore, the description of the same or similar formation process of DTI structure 160 will not be repeated here.

[0044] Reference Figure 13 and Figure 18 The forming steps S205 and S206 shown are as follows: Figure 6 After the trench cavity TC and the oxide layer 152 on its sidewalls are formed, the first opening OP1 of the trench cavity TC, the opening 121 of the HTO layer 122, and the opening 137 of the nitride layer 136 can be sealed by depositing an IMD 310 layer, which includes, for example, an undoped silicon oxide (USG) film 312 deposited by plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the IMD layer 310 may further include a doped silicon oxide film 314, which may be doped with phosphorus and boron (BPSG) or phosphorus only (PSG), and the doped silicon oxide film 314 is deposited on the USG film 312 by a PECVD process. In some embodiments, the thickness of the USG film 312 may be approximately 90-120 nanometers, but is not limited thereto, and other desired thicknesses of the USG film 312 may be adopted based on the actual needs in the manufacturing process. In this embodiment, by depositing a heavily doped silicon oxide film, for example, doped with BPSG or PSG, the heavily doped silicon oxide film can act as an absorber for mobile ions.

[0045] Reference Figure 13 and Figure 14 A polishable doped silicon oxide thin film 314 can be polished and subsequently bonded to a substrate 370, which includes, for example, a dielectric layer, a hybrid bonding layer, and an ASIC wafer. Figure 13 and Figure 14as well as Figure 18 As shown in step S207, a thinning process, such as mechanical polishing, wet etching, and CMP, can be performed on the back surface 113 of the semiconductor substrate 110 to expose the second opening OP2 of the trench cavity TC, which is perpendicular to the first opening OP1. The oxide layer 152 can be removed by silicon etching or by wet etching with HF. In this embodiment, a first high-k dielectric layer 352 as a passivation layer can be further deposited on the sidewall of the trench cavity TC. The first high-k dielectric layer 352 can also blanket the back surface 113 of the semiconductor substrate 110 formed after the thinning process.

[0046] Reference Figures 13 to 15 and Figure 18 The formation step S208 shown allows a reflective metal material 162, such as Al or Ag, to be filled into the trench cavity TC through a second opening OP2 exposed from the back surface 113 of the semiconductor substrate 110. A portion of the deposited reflective metal material 162 can blanket the back surface 113 of the semiconductor substrate 110. In an embodiment, reference is made to... Figures 13 to 15 The lateral width of the second opening OP2 can be smaller than the lateral width of the first opening OP1.

[0047] Reference Figure 16 A photoresist mask 50 can be deposited on a portion of the reflective metal material 162 covering the back surface 113 for etching and patterning the reflective metal material 162 and a portion for forming a metal mesh 166 connected to the DTI structure 160. In the etching process described above, the reflective metal material 162 covering the photosensitive region 114 is etched and removed to avoid affecting the photodiode path / sensitivity. In some embodiments, the etching process of the reflective metal material 162 described above can be performed by a combination of dry etching and wet etching processes to prevent damage to the passivation layer (high-k dielectric layer 352).

[0048] Reference Figure 17 Another (second) high-k dielectric layer 326 may be disposed on the passivation layer (high-k dielectric layer 352), which covers the metal mesh 166 as an anti-reflection layer. In some embodiments, such as Figure 17As shown, a buffer oxide layer 328 can then be deposited on the antireflective layer (high-κ dielectric layer 326) to prepare a back surface for depositing color filters 322 and composite mesh 324 thereon. In some embodiments, composite mesh 324 may include a metallic mesh and a low-refractive-index (low-n) mesh. In some embodiments, the low-n mesh may include a dielectric material, such as silicon oxide (e.g., SiO2) or hafnium oxide (e.g., HfO2), or a material having a refractive index less than that of color filters 322. The refractive index of the low-n mesh is less than that of color filters 322, thereby isolating adjacent color filters 322 and acting as a light guide to increase the effective size of color filters 322 (e.g., by guiding incident light from both sides of color filters 322 to the center of color filters 322). The metallic mesh blocks light, thereby isolating adjacent color filters 322 and reducing crosstalk. The metallic mesh may include, for example, tungsten, copper, or aluminum-copper.

[0049] In this embodiment, refer to Figure 17 A portion of the filled reflective metallic material 162, extending vertically to and protruding from the back surface 113 of the semiconductor substrate 110, may serve as part of the metallic mesh 166. For example... Figure 13 and Figure 17 The structure shown seals the opening OP1 of the DTI structure 160' by partially filling the trench cavity TC with a USG film 312 for subsequent manufacturing processes such as oxide layer formation. Figure 17 As shown, the DTI structure 160' may include at least one process void 164 formed within the filled reflective metallic material 162 for releasing internal material strain generated therein during the deposition process described above. In this embodiment, a microlens 330 may be further disposed above the composite mesh 324 and the color filter 322 to form the image sensor 10.

[0050] In this disclosure, reference is made to Figure 12 and Figure 17 The resulting structures of the DTI structures 160 and 160' of the image sensor 10 can be obtained respectively from... Figure 6 The trench cavity TC exposed on the front surface 111 of the semiconductor substrate 110 shown is formed by filling the front side of the reflective metal material 162, or by... Figure 14 The back surface 113 of the semiconductor substrate 110 shown is backfilled by an exposed opening OP2. Both front-side and back-side filling processes can be applied and performed based on the availability of manufacturing equipment in different manufacturing facilities. In both manufacturing processes, the DTI structures 160 and 160' are formed after the implanted source and drain regions, the transfer gate, and the floating diffusion region are formed. Therefore, the DTI structures 160 and 160' can be subjected to high-temperature processes to cure and repair trench surface damage caused by the etching process.

[0051] The description of the above-described examples of the invention, including those in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications may be possible within the scope of the invention, as will be recognized by those skilled in the art.

[0052] These modifications can be made to the invention based on the detailed description above. The terminology used in the following claims should not be construed as limiting the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is defined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

Claims

1. A method for manufacturing an image sensor, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a front surface and a back surface opposite to the front surface; A photosensitive region is formed in the semiconductor substrate; A floating diffusion region is formed adjacent to the photosensitive region, the floating diffusion region being used to receive image charge from the photosensitive region; A dielectric layer is formed on the front surface of the semiconductor substrate; A gate electrode is formed in the dielectric layer, and the gate electrode is electrically coupled to the photosensitive region and the floating diffusion region; as well as A deep trench isolation structure is formed adjacent to the photosensitive region, wherein the deep trench isolation structure extends from the dielectric layer on the front surface of the semiconductor substrate toward the back surface, wherein the deep trench isolation structure has an upper surface flush with the top surface of the dielectric layer.

2. The method according to claim 1, characterized in that, At least one of the process voids is formed in the reflective metal material within the deep trench isolation structure.

3. The method according to claim 2, characterized in that, The reflective metallic material mentioned above includes aluminum or silver.

4. The method according to claim 1, characterized in that, The steps for forming the deep trench isolation structure include forming a trench cavity by an etching process, the trench cavity extending from the dielectric layer on the front surface of the semiconductor substrate toward the back surface, wherein an oxide layer is formed on the sidewalls of the trench cavity by a thermal oxidation process, wherein the trench cavity has an opening on the top surface of the dielectric layer on the front surface of the semiconductor substrate, and a reflective metallic material is deposited into the trench cavity from the opening.

5. The method according to claim 4, characterized in that, The method further includes bonding the semiconductor substrate to the wafer substrate after forming the trench cavity.

6. The method according to claim 5, characterized in that, in, The step of forming the dielectric layer on the front surface of the semiconductor substrate prior to forming the trench cavity includes: A portion of the dielectric layer is formed on the front surface of the semiconductor substrate to encapsulate the gate electrode; and A nitride layer is deposited on the dielectric layer, wherein the dielectric layer includes a high-temperature oxide layer.

7. The method according to claim 1, characterized in that, It further includes spacers forming an outer wall surrounding the gate electrode.

8. The method according to claim 1, characterized in that, The method further includes performing a thinning process on the back surface of the semiconductor substrate after forming the deep trench isolation structure to expose the tip portion of the deep trench isolation structure from the back surface.

9. The method according to claim 1, characterized in that, The method further includes forming an intermetallic dielectric layer on the front surface of the semiconductor substrate, the intermetallic dielectric layer encapsulating the gate electrode.

10. The method according to claim 9, characterized in that, Further includes bonding the logic wafer to the intermetallic dielectric layer.

11. A method for manufacturing an image sensor, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a front surface and a back surface opposite to the front surface; A photosensitive region is formed in the semiconductor substrate; A floating diffusion region is formed adjacent to the photosensitive region, the floating diffusion region being used to receive image charge from the photosensitive region; A transmission gate is formed adjacent to the photosensitive region; A dielectric layer is formed on the front surface of the semiconductor substrate; The dielectric layer and the semiconductor substrate are etched to form a trench cavity adjacent to the photosensitive region, wherein the trench cavity has a first opening on the front surface of the semiconductor substrate and the trench cavity extends from the front surface of the semiconductor substrate toward the back surface. The trench cavity is sealed with an undoped silicon oxide layer over the first opening on the front side of the semiconductor substrate. A thinning process is performed on the back surface of the semiconductor substrate until the second opening of the trench cavity, which is perpendicular to the first opening, is exposed from the back surface; as well as The trench cavity is filled with a reflective metallic material from the second opening to form a deep trench isolation structure in the semiconductor substrate.

12. The method according to claim 11, characterized in that, The method further includes depositing a high-κ dielectric passivation layer on the sidewall of the trench cavity before filling the reflective metallic material into the trench cavity.

13. The method according to claim 11, characterized in that, This further includes depositing a doped silicon oxide layer on the undoped silicon oxide layer.

14. The method according to claim 13, characterized in that, The doped silicon oxide layer is doped with phosphorus or a combination of phosphorus and boron.

15. The method according to claim 11, characterized in that, The portion of the reflective metallic material protrudes from the second opening and covers the back surface of the semiconductor substrate, wherein a patterned etching process is performed on the portion of the reflective metallic material to form a portion of a metal mesh over the deep trench isolation structure.

16. An image sensor, characterized in that, include: A semiconductor substrate having a front surface and a back surface opposite to the front surface; A photosensitive region is disposed in the semiconductor substrate; Gate electrode, adjacent to the side of the photosensitive region; A floating diffusion region is placed adjacent to the photosensitive region to receive image charge from the photosensitive region; A dielectric layer having a first opening disposed on the front surface of the semiconductor substrate; as well as A deep trench isolation structure adjacent to the photosensitive region, wherein the deep trench isolation structure is configured to align with a first opening of the dielectric layer and extend through the semiconductor substrate, wherein the deep trench isolation structure is filled with a reflective metallic material layer.

17. The image sensor according to claim 16, characterized in that, The deep trench isolation structure includes a second opening exposed from the front surface of the semiconductor substrate, wherein the second opening adjacent to the deep trench isolation structure is aligned with a first opening adjacent to the dielectric layer and sealed by an undoped silicon oxide layer.

18. The image sensor according to claim 17, characterized in that, The deep trench isolation structure includes a third opening exposed from the back surface of the semiconductor substrate, wherein the reflective metallic material protrudes outward from the third opening to form a portion of a metallic mesh on the back surface of the semiconductor substrate.

19. The image sensor according to claim 16, characterized in that, The upper surface of the portion of the reflective metallic material filling the first opening in the dielectric layer is flush with the upper surface of the dielectric layer, wherein the dielectric layer includes at least one of a high-temperature oxide layer and a nitride layer.

20. The image sensor according to claim 16, characterized in that, The device further includes a contact disposed in an intermetallic dielectric layer on the dielectric layer, wherein the contact is coupled to the deep trench isolation structure to receive a bias voltage.

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