Semiconductor structure and its fabrication method, electronic devices

Abstract

This application provides a semiconductor structure, its fabrication method, and an electronic device. The semiconductor structure includes: a heat sink; at least two chips, wherein the at least two chips are stacked above the heat sink along a first direction; each chip includes a device layer and a metal layer formed by three-dimensional stacking technology; microchannels, wherein the microchannels include a channel inlet, a channel outlet, and a channel body; the channel body includes: a first channel body, a second channel body, and a plurality of third channel bodies, wherein the first channel body and the second channel body both extend along the first direction and are located in at least one edge region of the chip; each third channel body is located in a metal layer of the chip; one end of the first channel body is connected to the channel inlet, the other end of the first channel body is connected to one end of each third channel body, the other end of each third channel body is connected to one end of the second channel body, and the other end of the second channel body is connected to the channel outlet.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] With Moore's Law constantly evolving, 3D integration technology, which utilizes wafers to fabricate multilayer transistors, has great potential in improving system computing power and integration, as well as enhancing the functionality of computing systems. It is an important direction for integrated circuit system integration.

[0003] In related technologies, heat dissipation structures for 3D integration technology are still implemented at the packaging or system level, causing heat to accumulate inside the transistor, which can easily lead to serious performance degradation and reliability problems. Summary of the Invention

[0004] This application provides a semiconductor structure and its fabrication method, as well as an electronic device, which can achieve high-density integrated transistors through 3D integration technology while realizing a system heat dissipation solution, thereby significantly reducing the risk of thermal runaway and improving the reliability of the semiconductor structure.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a semiconductor structure, including: a heat sink carrier; at least two chips, wherein the at least two chips are located above the heat sink carrier and stacked along a first direction; each chip includes a device layer formed by three-dimensional stacking technology and a metal layer connected to the device layer; the first direction is the same as the stacking direction of the device layer; a microchannel, wherein the microchannel includes a channel inlet, a channel outlet, and a channel body, the channel inlet is located on one of the at least two chips away from the heat sink carrier, and the channel outlet is located on the heat sink carrier; the channel body includes: a first channel body, a second channel body, and a plurality of third channel bodies, wherein the first channel body and the second channel body both extend along the first direction and are located in at least one edge region of the chip; each third channel body is located in a metal layer of the chip; one end of the first channel body is connected to the channel inlet, the other end of the first channel body is connected to one end of each third channel body, the other end of each third channel body is connected to one end of the second channel body, and the other end of the second channel body is connected to the channel outlet.

[0007] This application provides a method for fabricating a semiconductor structure, which can be used to fabricate the aforementioned semiconductor structure. The method may include: forming a heat sink carrier, wherein a flow channel outlet is formed on the heat sink carrier; forming at least two chips; bonding the chips of the at least two chips together in pairs along a first direction; and bonding the at least two chips and the heat sink carrier together; wherein the fabrication process of each chip includes: fabricating an upper device layer and an upper metal layer connected to the upper device layer; fabricating a lower device layer and a lower metal layer connected to the lower device layer; forming a third flow channel body in the upper metal layer and / or the lower metal layer; and forming a first flow channel body portion and a second flow channel body portion communicating with the third flow channel body in at least one edge region of the chip; after bonding, the first flow channel body portions of the at least two chips constitute a first flow channel body, and the first flow channel body has a flow channel inlet at one end away from the heat sink carrier; the second flow channel body portions of the at least two chips form a second flow channel body, and the second flow channel body communicates with the flow channel outlet.

[0008] This application provides an electronic device, including: a circuit board and the semiconductor structure described above.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, at least two chips are stacked on top of a heat sink along a first direction, and each chip is also formed by stacking in the first direction using three-dimensional stacking technology, thereby integrating multiple chips (which can be referred to as 3D stacked chips) in the first direction. Furthermore, a microchannel is formed between the multiple 3D stacked chips and the heat sink. The inlet of the microchannel is located on the 3D stacked chip furthest from the heat sink, and the outlet is located on the heat sink. The cooling medium can flow sequentially from the 3D stacked chip furthest from the heat sink through the middle 3D stacked chips, and finally to the outlet on the heat sink, thus forming a heat dissipation system within the stacked 3D stacked chips. This effectively reduces the risk of thermal runaway caused by heat accumulation between the multiple 3D stacked chips and improves the reliability of the semiconductor structure. Simultaneously, the main body of the microchannel consists of three parts: a first channel body, a second channel body, and a third channel body. The third channel body is integrated in the metal layer within the 3D stacked chip, close to the heat-generating structure within the 3D stacked chip, and is used to complete the heat exchange between the cooling medium and the heat-generating structure. The first and second flow channels are both located at the edge of the 3D stacked chip and extend along the first direction. They are used to input cooling medium into the third flow channel and receive the cooled medium after heat exchange from the third flow channel, respectively. Through the cooperation of the first, second, and third flow channels, the risk of thermal runaway caused by heat accumulation inside each 3D stacked chip can be effectively reduced, thereby improving the reliability of the semiconductor structure.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 1 .

[0014] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application.

[0015] Figures 3 to 10 This is a schematic diagram of a first fabrication process for a semiconductor structure provided in an embodiment of this application.

[0016] Figure 11 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 2 .

[0017] Figure 12 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 3 .

[0018] Figures 13 to 15 This is a schematic diagram of a fabrication process for a heat dissipation carrier provided in an embodiment of this application.

[0019] Figure 16 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 4 .

[0020] Figure 17 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 5 .

[0021] Figures 18 to 24 This is a schematic diagram of a second fabrication process for a semiconductor structure provided in an embodiment of this application.

[0022] Figure 25 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 6 .

[0023] Figure 26 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 7 .

[0024] Figures 27 to 28This is a schematic diagram of a third fabrication process for a semiconductor structure provided in an embodiment of this application.

[0025] Figures 29 to 31 This is a schematic diagram of a fourth fabrication process for a semiconductor structure provided in an embodiment of this application.

[0026] Figure 32 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0027] The reference numerals and names in the figure are as follows:

[0028] 1. Heat sink carrier; 2. 3D stacked chip; 21. Bottom chip; 22. Middle chip; 23. Top chip; 24. Device layer; 25. Metal layer; 26. Sub-chip; 31. Flow channel inlet; 32. Flow channel outlet; 33. First flow channel body; 331. First flow channel body portion; 34. Second flow channel body; 341. Second flow channel body portion; 35. Third flow channel body; 36. First sub-flow channel; 37. Second sub-flow channel; 38. Flow channel via; 40. Silicon wafer; 41. Upper device layer; 42. Lower metal layer; 43. Higher metal layer; 44. Sacrificial layer; 45. Carrier wafer; 46. Trench; 47. Via; 48. Lower device layer; 50. L-shaped bend; 51. Edge region; 52. Device region. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] In the following description, the terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0032] Flip FETs (FFETs), as a groundbreaking stacked transistor technology, have profound implications for sub-nanometer logic nodes. By stacking front-side N-type transistors (NFETs) and back-side P-type transistors (PFETs) back-to-back, they achieve symmetrical bifacial devices and interconnects, thus circumventing the complex process challenges of high aspect ratio vertical patterning required for Complementary Field-Effect Transistors (CFETs). Their potential lies in their superior process friendliness, such as naturally split gates, broad multi-threshold voltage adjustability, and design flexibility enabled by bifacial complementary metal-oxide-semiconductor (CMOS), while also supporting better scalability and routing capabilities, laying a solid foundation for future 3D integration technologies.

[0033] Monolithic 3D Integration (M3D) is a 3D integration technology that achieves high-density integration by stacking multiple device layers (such as logic and memory) on the front side of the wafer. This technology typically utilizes only front-side wafer resources, improving performance through layer stacking.

[0034] Flip 3D (F3D) integration technology, as a groundbreaking 3D integration solution, is significant because it innovatively utilizes both sides of a wafer to integrate 3D transistor stacking (such as FFET), 3D bi-sided interconnects, various 3D chip stacking methods (such as face-to-face, back-to-back, and face-to-face bonding), and bi-sided monolithic 3D integration into one. This effectively solves the manufacturing challenges in traditional 3D integration and foreshadows its widespread application in high-density co-integration of logic or memory, 3D packaging expansion, and future heterogeneous computing, opening up a new dimension for semiconductor scaling.

[0035] However, current heat dissipation solutions for these three 3D technologies remain at the packaging or system level, failing to reach the device or wafer level. For example, semiconductor structures fabricated using F3D integration technology involve 3D transistor stacking, double-sided interconnects, and multi-chip vertical integration, with heat sources originating at the transistor level and metal traces. If heat is dissipated only from the outside of the package, the heat must traverse complex multi-layered structures (including dielectric layers and bonding interfaces) to be dissipated, resulting in long paths and high thermal resistance. This leads to heat accumulation internally, forming localized hotspots, especially in high-power-density lower-layer transistor regions, potentially causing severe performance degradation and reliability issues. Therefore, elevating heat dissipation solutions to the transistor level is crucial to unlocking the full potential of F3D integration technology.

[0036] To address the aforementioned technical problems, embodiments of this application provide a semiconductor structure and its fabrication method, as well as an electronic device, which can realize high-density integrated circuits through 3D integration technology while simultaneously implementing a system heat dissipation solution, thereby significantly reducing the risk of thermal runaway and improving the reliability of the semiconductor structure.

[0037] In a first aspect, embodiments of this application provide a semiconductor structure. Figure 1 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 1 . Figure 1 Image (a) shows a top view of the semiconductor structure. The top view includes the active region and the edge region. The B1-B2 section represents the length of the semiconductor device along the gate region (page number). Figure X The A1-A2 cross section is the cross section of the semiconductor device along the channel direction (Y direction of the layout) within the device region; the A3-A4 cross section is the cross section of the semiconductor device along the channel direction (Y direction of the layout) within the edge region. Figure 1 (b) shows a cross-sectional view of the semiconductor structure along the B1-B2 plane. Figure 1 (c) shows a cross-sectional view of the semiconductor structure along the A1-A2 plane. Figure 1 (d) in the figure shows a cross-sectional view of the semiconductor structure along the A3-A4 plane.

[0038] See Figure 1 As shown, the semiconductor structure in this embodiment may include a heat sink 1, at least two chips (i.e., 3D stacked chips 2), and microchannels. Here, the heat sink 1 supports at least two 3D stacked chips 2 and together with the at least two 3D stacked chips 2 forms the microchannels. In some embodiments, the channel outlet 32 ​​of the microchannel may be located on the heat sink 1. That is, the channel outlet 32 ​​of the microchannel may be integrated into the heat sink 1. In some embodiments, the position and shape of the channel outlet 32 ​​in the heat sink 1 can be flexibly set according to actual heat dissipation requirements, and this embodiment does not limit this.

[0039] In some embodiments, the flow channel outlet 32 ​​can be a groove on the surface of the heat sink 1, with the groove opening facing at least two 3D stacked chips 2. It is understood that after the heat sink 1 is bonded to at least two 3D stacked chips 2, the cooling medium can flow through the at least two 3D stacked chips 2 into the groove and out of the semiconductor structure guided by the groove wall. In some embodiments, the flow channel outlet 32 ​​can be a discharge channel inside the heat sink 1. The inlet and outlet of this discharge channel are connected. It is understood that the cooling medium can flow through at least two 3D stacked chips 2 and the inlet, enter the discharge channel, and flow out of the semiconductor structure from the outlet.

[0040] In some embodiments, the cooling medium may be a liquid cooling medium (such as deionized water, fluorinated liquid, etc.), a gaseous cooling medium (such as nitrogen, air, etc.), or a phase change cooling medium (such as a refrigerant (i.e., hydrofluorocarbons, hydrofluoroolefins, etc.)).

[0041] In some embodiments, at least two 3D stacked chips 2 are located above the heat sink 1 and are stacked along a first direction. Each 3D stacked chip 2 is formed by stacking along the first direction using three-dimensional stacking techniques (including the aforementioned FFET, M3D, and F3D). That is, multiple device layers 24 in each 3D stacked chip 2 are stacked along the first direction, and multiple 3D stacked chips 2 are also stacked along the first direction. Thus, the semiconductor structure forms multiple stacked device layers 24 along the first direction, effectively improving the integration level of the semiconductor structure.

[0042] In some embodiments, each 3D stacked chip 2 further includes a metal layer 25 connected to the device layer 24. In some embodiments, the metal layer 25 is a metal trace structure that provides signals and power to transistors. In some embodiments, the metal layer 25 is located on one or both sides of the device layer 24; this application does not limit the specific embodiments. In some embodiments, the metal layer 25 may have multiple layers, each layer having metal traces housed within a dielectric layer. Adjacent metal traces may be perpendicular to each other and connected through metal vias. Alternatively, adjacent metal traces may be parallel to each other and connected through metal vias. In some embodiments, the metal layer 25 may have 18 layers, each comprising metals M0 to M17.

[0043] In some embodiments, the device layers 24 in each 3D stacked chip 2 can be multiple. For example, the device layers 24 in each 3D stacked chip 2 can be two, three, or four device layers, etc. The metal layers 25 in each 3D stacked chip 2 can be one or more, and this embodiment does not limit this. For example, when there is one metal layer 25 in each 3D stacked chip 2, the multiple device layers can be connected to a single metal layer. When there are multiple metal layers 25 in each 3D stacked chip 2, the multiple device layers can be connected to different metal layers respectively.

[0044] In some embodiments, the microchannel may include a channel inlet 31, a channel outlet 32, and a channel body. The channel body may include a first channel body 33, a second channel body 34, and a plurality of third channel bodies 35. The channel inlet 31 is located on one of the at least two 3D stacked chips 2 furthest from the heat sink 1. That is, when the heat sink 1 is located at the bottom layer, the channel inlet 31 of the microchannel can be integrated into the topmost 3D stacked chip 2. In some embodiments, the position and shape of the channel inlet 31 in the 3D stacked chip 2 can be flexibly set according to actual heat dissipation requirements, and this application embodiment does not limit this.

[0045] In some embodiments, the first flow channel body 33 is a hollow structure, and one end of the first flow channel body 33 can be connected to the flow channel inlet 31. Here, the flow channel inlet 31 can be an independently set structure or an opening of the first flow channel body 33, and this application embodiment does not limit it in this way.

[0046] In some embodiments, each of the plurality of third channel bodies 35 may be located in one metal layer 25 of the 3D stacked chip 2. Here, depending on the heat dissipation requirements, the third channel body 35 may be disposed in one or more metal layers 25 of the 3D stacked chip 2, and this application embodiment does not limit this. For example, when the 3D stacked chip 2 includes two metal layers, front and back, the third channel body 35 may be disposed in both metal layers, or it may be disposed in either of the two metal layers, and this application embodiment does not limit this.

[0047] In some embodiments, the arrangement of the third channel body 35 in the metal layer 25 can be compatible with the arrangement of the metal traces in the metal layer 25, meaning that the third channel body 35 and the metal traces do not interfere with each other. It is understood that the absence of interference between the third channel body 35 and the metal traces prevents the cooling medium from affecting the operation of the metal traces. Simultaneously, the microchannels must also be disconnected from other conductive structures in the 3D stacked chip 2 to reduce the impact on the integrated circuitry within the semiconductor structure.

[0048] In some embodiments, each third channel body 35 may be located in a metal layer 25 of the 3D stacked chip 2, and the multiple third channel bodies 35 have different heights along a first direction. After one end of the first channel body 33 is connected to the channel inlet 31, the other end of the first channel body 33 may extend to different heights along the first direction, respectively connecting to the multiple third channel bodies 35. Here, the first channel body 33 may connect to one end of each third channel body 35, so that the cooling medium enters the multiple third channel bodies 35 after passing through the first channel body 33, thereby realizing simultaneous heat dissipation of multiple metal layers 25 in the semiconductor structure.

[0049] In some embodiments, the second flow channel body 34 is a hollow structure and can extend to different heights along the first direction. One end of the second flow channel body 34 can be connected to the end of a plurality of third flow channel bodies 35 that is not connected to the first flow channel body 33, and the other end is connected to the flow channel outlet 32.

[0050] In some embodiments, both the first channel body 33 and the second channel body 34 may be located in the edge region of the 3D stacked chip 2 within a cross-section perpendicular to the first direction. Here, the cross-section of the 3D stacked chip 2 perpendicular to the first direction is parallel to the plane shown in the top view. In some embodiments, the semiconductor structure may include at least one edge region 51, and the first channel body 33 and the second channel body 34 may be located within the same edge region 51 or within different edge regions 51. This application embodiment does not limit this.

[0051] In some embodiments, the semiconductor structure includes a device region 52. There is one device region 52, which is used to fabricate and form the device structure. In some embodiments, there may be one edge region 51, which may be located on one side of the device region 52. In some embodiments, there may be two edge regions 51, located on opposite sides of the device region 52. In some embodiments, there may be four edge regions 51 connected end-to-end, such that the edge regions 51 can surround the periphery of the device region 52. See, for example... Figure 1 In the top view shown in (a), the edge region 51 may be the region located on the periphery of the device region 52.

[0052] Understandably, the first flow channel body 33 and the second flow channel body 34 are located in the edge region 51 of the semiconductor structure, thereby effectively reducing damage to the structure within the device region 52 and improving the rationality of the microchannel layout.

[0053] In this embodiment, at least two chips are stacked on top of a heat sink along a first direction, and each chip is also formed by stacking in the first direction using three-dimensional stacking technology, thereby integrating multiple chips (which can be referred to as 3D stacked chips) in the first direction. Furthermore, a microchannel is formed between the multiple 3D stacked chips and the heat sink. The inlet of the microchannel is located on the 3D stacked chip furthest from the heat sink, and the outlet is located on the heat sink. The cooling medium can flow sequentially from the 3D stacked chip furthest from the heat sink through the middle 3D stacked chips, and finally to the outlet on the heat sink, thus forming a heat dissipation system within the stacked 3D stacked chips. This effectively reduces the risk of thermal runaway caused by heat accumulation between the multiple 3D stacked chips and improves the reliability of the semiconductor structure. Simultaneously, the main body of the microchannel consists of three parts: a first channel body, a second channel body, and a third channel body. The third channel body is integrated in the metal layer within the 3D stacked chip, close to the heat-generating structure within the 3D stacked chip, and is used to complete the heat exchange between the cooling medium and the heat-generating structure. The first and second flow channels are both located at the edge of the 3D stacked chip and extend along the first direction. They are used to input cooling medium into the third flow channel and receive the cooled medium after heat exchange from the third flow channel, respectively. Through the cooperation of the first, second, and third flow channels, the risk of thermal runaway caused by heat accumulation inside each 3D stacked chip can be effectively reduced, thereby improving the reliability of the semiconductor structure.

[0054] In some embodiments, see Figure 1 As shown, each of the plurality of third flow channel bodies 35 may include at least two sub-flow channels and a flow channel through-hole 38 located between any two sub-flow channels. In some embodiments, the at least two sub-flow channels may include: a first sub-flow channel 36 and / or a second sub-flow channel 37. The first sub-flow channel 36 may extend along a second direction, and the second sub-flow channel 37 may extend along a third direction. The second direction is perpendicular to the first direction, for example, the layout Y direction. The third direction is perpendicular to both the first and second directions, for example, the layout Y direction. Figure X Direction. As can be seen, the sub-channels all extend in a direction perpendicular to the first direction, while the channel through-hole 38 can extend in the first direction to connect any two sub-channels.

[0055] In some embodiments, the at least two sub-channels may include at least two first sub-channels 36. In some embodiments, the at least two sub-channels may include at least two second sub-channels 37. In some embodiments, the at least two sub-channels may include at least one first sub-channel 36 and at least one second sub-channel 37.

[0056] Understandably, the metal traces in the metal layer 25 can extend along the second direction and / or the third direction. Therefore, the sub-channels in the third channel body 35 can also be divided into a first sub-channel 36 extending along the second direction and a second sub-channel 37 extending along the third direction. Thus, the first sub-channel 36 extending along the second direction can be arranged parallel to the metal traces extending along the second direction, and the second sub-channel 37 extending along the third direction can be arranged parallel to the metal traces extending along the third direction, thereby achieving compatibility between the third channel body 35 and the metal layer 25.

[0057] In the embodiments of this application, a three-dimensional flow channel structure can be formed through at least two sub-flow channels and flow channel through holes, which further improves the heat dissipation performance of the heat dissipation system.

[0058] In some embodiments, see Figure 1 As shown, the first flow channel body 33 connects to one of the at least two sub-flow channels, and the second flow channel body 34 connects to the other of the at least two sub-flow channels. The end cross-sectional shape of the sub-flow channel connected to the first flow channel body 33 and the second flow channel body 34 is straight, broken, or curved.

[0059] Understandably, the first flow channel body 33 and the second flow channel body 34 are connected to different sub-flow channels. Thus, the positions of the first flow channel body 33 and the second flow channel body 34 can be set according to the positions of the sub-flow channels they are connected to, thereby improving the flexibility of the layout of the first flow channel body 33 and the second flow channel body 34.

[0060] In some embodiments, the first channel body 33 connects to the first sub-channel 36, the first sub-channel 36 extends along a second direction, and the first channel body 33 may be disposed along the second direction in the edge region 51 of the 3D stacked chip 2. In some embodiments, the first channel body 33 connects to the second sub-channel 37, the second sub-channel 37 extends along a third direction, and the first channel body 33 may be disposed along the third direction in the edge region 51 of the 3D stacked chip 2.

[0061] In some embodiments, the first flow channel body 33 connects to the first of at least two sub-flow channels, and the second flow channel body 34 connects to the last of at least two sub-flow channels. Here, the first sub-flow channel may be one of the at least two sub-flow channels connected to only one flow channel through-hole 38, and the last sub-flow channel is another of the at least two sub-flow channels connected to only one flow channel through-hole 38.

[0062] Understandably, the cooling medium can flow into the third channel body 35 from the first sub-channel, be transferred between different sub-channels in sequence, and then flow out of the third channel body 35 from the last sub-channel. Based on this, a unidirectional heat dissipation flow path can be formed within the third channel body 35, which helps to increase the flow rate of the cooling medium and thus improve the heat dissipation performance of the semiconductor structure.

[0063] In some embodiments, there may be two first flow channel bodies 33; and / or, there may be two second flow channel bodies 34.

[0064] In some embodiments, there may be two first flow channel bodies 33. The two first flow channel bodies 33 may be located at two opposite edge regions 51 of the 3D stacked chip 2, and the two first flow channel bodies 33 connect the two ends of the same sub-flow channel. For example, the two first flow channel bodies 33 connect the two ends of a first sub-flow channel. In some embodiments, there may be two second flow channel bodies 34. The two second flow channel bodies 34 may be located at two opposite edge regions 51 of the 3D stacked chip 2, and the two second flow channel bodies 34 connect the two ends of the same sub-flow channel. For example, the two first flow channel bodies 33 connect the two ends of a last sub-flow channel. In this way, the cooling medium can flow into the third flow channel body 35 from both ends of one sub-flow channel and flow out of the third flow channel body 35 from both ends of the other sub-flow channel, thereby effectively improving the flow efficiency of the cooling medium.

[0065] In some embodiments, at least two sub-channels may include a first sub-channel 36 and a second sub-channel 37, which are connected by a channel via 38. Thus, the first channel body 33 may be located in at least one edge region 51 of the 3D stacked chip 2 in a second direction, and the first channel body 33 may connect to the end of the first sub-channel 36. The second channel body 34 may be located in at least one edge region 51 of the 3D stacked chip 2 in a third direction, and the second channel body 34 may connect to the end of the second sub-channel 37.

[0066] Understandably, the first flow channel body 33 and the second flow channel body 34 can be respectively disposed in the edge regions 51 of the 3D stacked chip 2 in the second and third directions. In this way, the first flow channel body 33 and the second flow channel body 34 are distributed in different edge regions 51, which can significantly enhance the compatibility of the first flow channel body 33 and the second flow channel body 34 at the layout level, while effectively reducing the difficulty of their fabrication process.

[0067] In some embodiments, there may be two first flow channel bodies 33. The two first flow channel bodies 33 may be located at two edge regions 51 of the 3D stacked chip 2 in the second direction, and both first flow channel bodies 33 simultaneously connect to the two ends of the first sub-flow channel 36 in the second direction. There may also be two second flow channel bodies 34. The two second flow channel bodies 34 may be located at two edge regions 51 of the 3D stacked chip 2 in the third direction, and both second flow channel bodies 34 simultaneously connect to the two ends of the second sub-flow channel 37 in the third direction. Thus, the cooling medium can flow into the third flow channel body 35 from both ends of the first sub-flow channel 36 and out of the third flow channel body 35 from both ends of the second sub-flow channel 37, thereby effectively improving the flow efficiency of the cooling medium.

[0068] In some embodiments, the end cross-sectional shape of the sub-channel communicating with the first flow channel body 33 and the second flow channel body 34 may be straight, broken, or curved, and this application embodiment does not limit this. Here, the cross-section may be a plane parallel to the first direction.

[0069] Understandably, by setting different end cross-sectional shapes, it is possible to help the sub-channels better connect with the first channel body 33 and the second channel body 34. In some embodiments, by setting different end cross-sectional shapes, two sub-channels connected to the same channel body can be connected, thereby balancing the heat dissipation performance of the two sub-channels.

[0070] For example, the end cross-sectional shape of the second sub-channel 37 connected to the second flow channel body 34 can be L-shaped, forming an L-shaped end. The L-shaped end includes a vertical side and a horizontal side. The horizontal side can be exposed on the surface of the 3D stacked chip 2. When both second sub-channels 37 in two adjacent 3D stacked chips 2 form L-shaped ends, the horizontal sides of the two L-shaped ends can be joined together vertically to achieve the function of cooling medium convergence.

[0071] In some embodiments, the 3D stacked chip 2 may include a first metal layer and a second metal layer. The first metal layer and the second metal layer may be located on opposite sides of the 3D stacked chip 2 in a first direction. Each of the first and second metal layers may have a third flow channel body 35 disposed therein, and the third flow channel body 35 in the first metal layer and the third flow channel body 35 in the second metal layer are disposed opposite to each other.

[0072] Understandably, there can be multiple metal layers 25 in the 3D stacked chip 2. The first metal layer and the second metal layer 25 can be two of the multiple metal layers, with the first metal layer and the second metal layer located on opposite sides of the 3D stacked chip 2 in the first direction, respectively. By providing a third flow channel body 35 in at least the first metal layer and the second metal layer, the heat dissipation performance at least at both ends of the semiconductor structure along the first direction can be improved.

[0073] In some embodiments, the first metal layer and the second metal layer may be disposed opposite to each other, and the third flow channel body 35 in the first metal layer and the third flow channel body 35 in the second metal layer may be disposed opposite to each other.

[0074] In some embodiments, the first flow channel body 33 may have a reduced shape that gradually decreases in diameter as it approaches the inner diameter of the heat sink 1.

[0075] Understandably, the first flow channel body 33 is used to provide cooling medium to a plurality of third flow channel bodies 35, which have different heights along the first direction. The closer the first flow channel body 33 is to the heat sink 1, the fewer third flow channel bodies 35 need to be supplied with cooling medium. Thus, the first flow channel body 33 can have a tapered shape that gradually decreases in diameter as it approaches the heat sink 1, in order to balance the flow rate of cooling medium flowing into each third flow channel body 35.

[0076] In some embodiments, when there are multiple second flow channel bodies 34, the flow channel outlet 32 ​​can be a multi-pass structure, in which each liquid inlet is connected to a second flow channel body 34.

[0077] Understandably, when multiple second flow channel bodies 34 are configured, the flow channel outlet 32 ​​adopts a multi-pass structure design, with multiple liquid inlets and one liquid outlet. Each liquid inlet is connected to one second flow channel body 34, thereby collecting the cooling medium from multiple flow paths to a single outlet, realizing centralized management of the cooling medium after decentralized heat exchange.

[0078] In some embodiments, at least two 3D stacked chips 2 may include a top-layer chip 23, a middle-layer chip 22, and a bottom-layer chip 21 stacked along a first direction. The top-layer chip 23 may be a chip directly facing an external interface or sensor module, and the bottom-layer chip 21 may be connected to a heat sink 1. The middle-layer chip 22 is located between the top-layer chip 23 and the bottom-layer chip 21.

[0079] In some embodiments, at least two 3D stacked chips 2 may include a top chip 23 and a bottom chip 21 stacked along a first direction. The top chip 23 may be a chip that directly faces an external interface or sensor module, and the bottom chip 21 may be connected to a heat sink 1.

[0080] In some embodiments, any one of the top-layer chip 23, the middle-layer chip 22, and the bottom-layer chip 21 may include at least one sub-chip 26. Each of the at least one sub-chip 26 may include a device layer 24 and an interconnect layer connected to a metal layer 25. In some embodiments, a sub-chip 26 may be a chip including a single device layer. In some embodiments, a sub-chip 26 may be a chip including multiple device layers.

[0081] In some embodiments, when any one of the top chip 23, the middle chip 22 and the bottom chip 21 includes at least two sub-chips 26, the at least two sub-chips 26 may be stacked along a first direction using three-dimensional monolithic integration technology, and each sub-chip 26 may include a device layer formed by three-dimensional stacking technology (such as F3D technology).

[0082] Secondly, embodiments of this application provide a method for preparing a semiconductor structure. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. See also... Figure 2 As shown, the method for preparing the semiconductor structure in the embodiments of this application may include steps 201 to 203.

[0083] Step 201: Obtain a heat dissipation carrier plate, wherein a flow channel outlet is formed on the heat dissipation carrier plate.

[0084] Step 202: Prepare at least two chips. The preparation process of each chip includes: preparing an upper device layer and an upper metal layer connected to the upper device layer on a substrate; preparing a lower device layer and a lower metal layer connected to the lower device layer; preparing a third flow channel body in the upper metal layer and / or the lower metal layer; and preparing a first flow channel body portion and a second flow channel body portion connected to the third flow channel body in at least one edge region of the chip.

[0085] Step 203: Along the first direction, at least two chips are bonded together in pairs, and at least two chips are bonded together with a heat sink. After bonding, the first channel body portion of the at least two chips forms a first channel body, and the first channel body has a channel inlet at the end away from the heat sink; the second channel body portion of the at least two chips forms a second channel body, and the second channel body is connected to the channel outlet.

[0086] In the embodiments of this application, the semiconductor structure is prepared as described in any embodiment of the first aspect. The specific structure of the semiconductor structure can be found in the description of any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0087] The fabrication process of each 3D stacked chip may include, according to semiconductor standard fabrication processes, forming an upper device layer and an upper metal layer connected to the upper device layer on a substrate, and forming a lower device layer and a lower metal layer connected to the lower device layer according to semiconductor standard fabrication processes. Simultaneously, during the fabrication of the upper metal layer and / or the lower metal layer, a third flow channel body can be formed in the metal layer through processes such as etching and deposition. Furthermore, through-holes extending along a first direction are etched in at least one edge region of the 3D stacked chip using an etching process. These through-holes may connect a first flow channel body portion and a second flow channel body portion to the third flow channel body.

[0088] In some embodiments, after bonding multiple 3D stacked chips pairwise, the first channel body portions of two adjacent 3D stacked chips are aligned together until all the first channel body portions of at least two 3D stacked chips constitute a first channel body. The second channel body portions of two adjacent 3D stacked chips are aligned together until all the second channel body portions of at least two 3D stacked chips constitute a second channel body. After at least two 3D stacked chips are bonded to a heat sink, the second channel body communicates with the channel outlet on the heat sink. Therefore, in the embodiments of this application, a double-sided heat dissipation channel can be formed in the semiconductor structure, effectively reducing the risk of thermal runaway caused by heat accumulation inside the 3D stacked chips and improving the reliability of the semiconductor structure.

[0089] In some embodiments, the upper device layer and the lower device layer may be flip-chip stacked. Fabricating the upper and lower device layers according to standard semiconductor fabrication processes may include: forming a fin-like structure on a substrate, wherein the fin-like structure may include a first portion and a second portion, the first portion being closer to the substrate than the second portion; then forming the upper device layer and an upper interconnect layer connected to the upper device layer based on the first portion; then flipping and removing the substrate; then forming the lower device layer and a lower interconnect layer connected to the lower device layer based on the second portion.

[0090] In some embodiments, the upper device layer and the lower device layer may be arranged in a non-flip-chip stacked configuration. Fabricating the upper and lower device layers according to standard semiconductor fabrication processes may include: fabricating the lower device layer and a lower interconnect layer connected to the lower device layer on a substrate; bonding the lower device layer to a carrier wafer; and fabricating the upper device layer and the upper interconnect layer connected to the upper device layer on the carrier wafer.

[0091] In some embodiments, the device layer may include devices, such as CMOS logic transistors, memory cell transistors, etc., but this application does not limit this.

[0092] In some embodiments, fabricating the third flow channel body may include etching the dielectric structure of the metal layer using an etching process to form the third flow channel body within the metal layer. Here, the third flow channel body is not connected to the metal lines within the metal layer.

[0093] In some embodiments, the inner wall of the microchannel can be coated with a protective material. This protective material can form an anti-corrosion coating, prepared from materials such as silicon nitride and alumina. Alternatively, the protective material can form a heat-enhancing coating, prepared from materials such as graphene and carbon nanotubes. In some embodiments, the inner wall of the microchannel can also be treated using a hydrophilic / hydrophobic modification process.

[0094] In some embodiments, step 202 may include: forming at least two sub-channels and a flow channel via located between any two sub-channels. The at least two sub-channels include a first sub-channel and / or a second sub-channel. The first sub-channel extends along a second direction, and the second sub-channel extends along a third direction.

[0095] Understandably, the third flow channel body can include sub-flow channels along different directions. By etching sub-flow channels along different directions in different layers of the metal layer, and etching through-holes connecting any two sub-flow channels, the third flow channel body can be formed in the metal layer.

[0096] In some embodiments, step 202 may include: forming a second sub-channel between a lower metal layer and a higher metal layer in the metal layer, and forming a first sub-channel and a via connecting the first and second sub-channels in the higher metal layer. A first channel body portion connecting the second sub-channel is formed in at least one edge region of the 3D stacked chip in a second direction, and a second channel body portion connecting the second sub-channel is formed in at least one edge region of the 3D stacked chip in a third direction.

[0097] In the embodiments of this application, the terms "lower metal layer" and "higher metal layer" are relative concepts. The lower metal layer refers to the metal layer that is closer to the transistor than the higher metal layer, while the higher metal layer refers to the metal layer that is farther away from the transistor than the lower metal layer.

[0098] For example, assuming there are ten metal layers in total, when the lower metal layers include metals M0 to M3, the higher metal layers may include metals M4 to M9. When the lower metal layers include metals M0 to M6, the higher metal layers may include metals M7 to M9.

[0099] In some embodiments, forming a second sub-channel may include: forming a groove on the surface of the lower metal layer toward the upper metal layer, forming a groove on the surface of the upper metal layer toward the lower metal layer, or simultaneously forming grooves on the surface of the lower metal layer toward the upper metal layer and the surface of the upper metal layer toward the lower metal layer.

[0100] In some embodiments, the lower metal layer and the higher metal layer are formed on different carrier wafers. After the lower metal layer and the higher metal layer are bonded, the grooves on the surfaces of the lower metal layer and / or the higher metal layer are closed to form a second sub-channel. The lower metal layer is the metal layer closer to the transistor relative to the second sub-channel; the higher metal layer is the metal layer farther away from the transistor relative to the second sub-channel.

[0101] In the embodiments of this application, a groove is formed by etching the surface of the lower metal layer and / or the higher metal layer, which can form a second sub-channel after the lower metal layer and the higher metal layer are bonded.

[0102] In this embodiment of the application, forming the first sub-channel includes: forming a groove on the surface of the high layer facing the wafer, forming a groove on the surface of the wafer facing the high layer, or simultaneously forming grooves on both the surface of the high layer facing the wafer and the surface of the wafer facing the high layer.

[0103] In some embodiments, the formation of the grooves can be configured according to actual needs, and this application embodiment does not limit this. For example, the cross-section of the groove can be rectangular, square, semi-circular, etc. In some embodiments, there can be multiple grooves, each groove forming a horizontal microchannel, or two grooves can be combined to form a sub-channel.

[0104] The semiconductor structure and its fabrication method in this application are described below with specific embodiments.

[0105] Figures 3 to 10 This is a schematic diagram of a first fabrication process for a semiconductor structure provided in an embodiment of this application. A cross-sectional view of the semiconductor structure is shown. Figures 3 to 10 (The direction from left to right in the middle is the third direction). See also Figures 3 to 10 As shown, the first method for fabricating the semiconductor structure in this application embodiment may include:

[0106] The first step involves completing the logic circuit (i.e., the upper device layer 41) and the lower signal traces (i.e., the lower metal layer 42 within the upper metal layer) on the front side of the silicon wafer 40. A groove is formed in the reserved space within the lower signal trace; this groove is the second sub-channel 37 within the third channel body 35, resulting in… Figure 3 The structure shown.

[0107] Here, completing the logic circuits and low-level signal traces on the front side of the silicon wafer 40 may include: providing a silicon wafer 40, etching the upper portion of the silicon wafer 40 to form a fin structure, and retaining the lower portion of the silicon wafer 40 to form a substrate. Here, the fin structure includes a first portion and a second portion. The first portion is farther from the substrate than the second portion. Then, based on the first portion of the fin structure, an upper device layer 41 and a lower metal layer 42 in the upper metal layer are sequentially formed.

[0108] In some embodiments, the groove formed in the first step extends along a third direction.

[0109] The second step involves sequentially fabricating a sacrificial layer 44 and high-level signal traces (i.e., a high-level metal layer 43 in the upper metal layer) using a carrier wafer 45, and then bonding the high-level metal layer 43 in the upper metal layer to the low-level metal layer 42 in the upper metal layer to obtain... Figure 4 The structure shown.

[0110] Here, after bonding, the second sub-channel 37 is located between the upper metal layer 43 and the lower metal layer 42 in the upper metal layer.

[0111] The third step involves removing the sacrificial layer 44 to separate the carrier wafer 45 from the upper metal layer. Afterwards, vias are etched into the reserved spaces in the high-layer signal traces to form a connection to the second sub-channel 37. These vias are the channel vias 38 in the main body of the third channel, resulting in... Figure 5 The structure shown.

[0112] Fourth step: A groove is formed in the reserved space of the upper metal layer 43 in the upper metal layer. This groove is the first sub-channel 36 in the main body of the third flow channel, thus obtaining... Figure 6 The structure shown.

[0113] In some embodiments, the groove formed in the fourth step extends along the second direction. The first sub-channel 36 and the second sub-channel 37 extend in different directions, and the flow channel through-hole 38 may be located at the overlap of the first sub-channel 36 and the second sub-channel 37.

[0114] For example, Figure 11 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 2 . Figure 11 (a) in the middle is Figure 6 A top view of the structure shown. Wherein, Figure 11 (b) and (c) in the text are respectively along Figure 11 Schematic diagrams of the C1-C2 and C3-C4 cross sections in (a) are shown (metal traces and transistors are omitted; only the microchannel structure is displayed). See also Figure 11As shown, the first sub-channel 36 and the second sub-channel 37 can be connected through the channel through hole 38.

[0115] Step 5: Flip the structure obtained in Step 4 and remove the silicon wafer 40. Then, bond the upper metal layer to the heat sink 1, and according to the shape of the flow channel outlet 32 ​​in the heat sink 1, etch the dielectric structure in the 3D stacked chip 2 on both sides of the upper device layer and the upper metal layer along a third direction to form the second flow channel body 341, resulting in... Figure 7 The structure shown.

[0116] Here, the heat sink 1 integrates a flow channel outlet 32, which can be a multi-pass structure. The multiple liquid inlets of the multi-pass structure are respectively connected to multiple second flow channel main body parts 341.

[0117] For example, Figure 12 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 3 . Figure 12 (a) and (b) in the text are respectively along Figure 10 Schematic diagrams of the C1-C2 and C3-C4 cross sections in (a) are shown (metal traces and transistors are omitted; only the microchannel structure is displayed). See also Figure 12 As shown, one end of the second flow channel main body 341 can be connected to the second sub-flow channel 37, and the other end can be connected to the flow channel outlet 32.

[0118] In some embodiments, Figures 13 to 15 This is a schematic diagram of a fabrication process for a heat dissipation carrier provided in an embodiment of this application. Figures 13 to 15 (a) shows a top view of the heat sink 1. Figures 13 to 15 Image (b) shows a side view of heat sink 1. (See reference) Figures 13 to 15 As shown, firstly, trenches 46 are etched into the surface of an initial substrate using an etching process, which can obtain... Figure 13 The first substrate shown; then, through an etching process, through-hole 47 is etched into another initial substrate to obtain... Figure 14 The second carrier shown; finally, the first and second carriers are bonded together to obtain heat dissipation carrier 1, which can obtain Figure 15 The heat dissipation carrier 1 is shown. Here, the grooves 46 on the first carrier and the through holes 47 on the second carrier are bonded together to form the flow channel outlet 32.

[0119] Step 6: Based on the second part of the fin structure, the lower device layer 48 is formed using the same steps as the upper device layer, and the lower metal layer is formed using the same steps as the upper metal layer, to obtain... Figure 8 The structure shown.

[0120] Here, a third flow channel body 35 is also integrated in the lower metal layer. The third flow channel body 35 includes a second sub-flow channel 37 extending in a third direction, a first sub-flow channel 36 extending in a second direction, and a flow channel through-hole 38 connecting the first sub-flow channel 36 and the second sub-flow channel 37.

[0121] Step 7: Etch the dielectric structure in the 3D stacked chip 2 on both sides of the lower metal layer and the lower device layer along a third direction to form the second flow channel body portion 341, resulting in... Figure 9 The structure shown.

[0122] For example, Figure 16 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 4 . Figure 16 (a) in the middle is Figure 9 A top view of the structure shown. Wherein, Figure 16 (b) and (c) in the text are respectively along Figure 16 A schematic diagram of sections B3-B4 and B5-B6 in (a) of the diagram. Figure 16 (Metal traces and transistors are omitted; only the microchannel structure is shown.) See also: Figure 16 As shown, one end of the second flow channel main body 341 is connected to the second sub-flow channel 37 corresponding to the upper device layer and the second sub-flow channel 37 corresponding to the lower device layer, and the other end is connected to the flow channel outlet 32.

[0123] Step 8: Etch the dielectric structure in the 3D stacked chip 2 on both sides of the upper and lower metal layers and the upper and lower device layers along the second direction to form the first flow channel body portion 331, resulting in... Figure 10 The structure shown.

[0124] For example, Figure 17 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 5 . Figure 17 (a) in the middle is Figure 10 A top view of the structure shown. Wherein, Figure 17 (b) and (c) in the text are respectively along Figure 17 A schematic diagram of sections B3-B4 and B5-B6 in (a) of the diagram. Figure 17 (Metal traces and transistors are omitted; only the microchannel structure is shown.) See also: Figure 17 As shown, the first flow channel body 331 connects one end to the first sub-flow channel 36 corresponding to the upper device layer and the first sub-flow channel 36 corresponding to the lower device layer, and the other end has an opening that connects to other 3D stacked chips 2. This opening is used for the cooling medium to flow in from the previous 3D stacked chip 2.

[0125] At this point, the fabrication of the bottom layer chip 21 in at least two 3D stacked chips 2 is complete.

[0126] In the ninth step, using a process similar to steps one through eight, other 3D stacked chips 2 (such as top-layer chip 23 and middle-layer chip 22) are fabricated to obtain... Figure 1 The structure shown.

[0127] Here, when multiple 3D stacked chips 2 are bonded, only the heat sink 1 connected to the bottom chip 21 is retained. The first flow channel body portion 331 in the top chip 23, middle chip 22, and bottom chip 21 are connected end to end, forming the first flow channel body 33. The second flow channel body portion 341 in the top chip 23, middle chip 22, and bottom chip 21 are connected end to end, forming the second flow channel body 34. The end of the first flow channel body portion 33 on the top chip 23 can be the flow channel inlet 31.

[0128] Here, the top-layer chip 23, the middle-layer chip 22, and the bottom-layer chip 21 can all be bonded together with more chips within their respective layers and share the same heat dissipation channel (i.e., the third flow channel body 35), such as Figure 1 The middle-layer chip 22 includes two sub-chips. In addition, any chip can be stacked using M3D technology, such as... Figure 2 The top-layer chip 23 is shown in the diagram. Understandably, the cooling medium can flow in from the top of the semiconductor structure and out from the bottom.

[0129] This completes the fabrication of the semiconductor structure.

[0130] In some embodiments, Figures 18 to 24 This is a schematic diagram of a second fabrication process for a semiconductor structure provided in an embodiment of this application. A cross-sectional view of the semiconductor structure is shown. Figures 18 to 24 (The direction from left to right in the middle is the third direction). See also Figures 18 to 24 As shown, a second method for fabricating the semiconductor structure in this application embodiment may include:

[0131] The first step, following standard processes, is to complete the logic circuits (i.e., the upper device layer 41) and signal traces (i.e., the upper metal layer) on the front side of silicon wafer 40, resulting in... Figure 18 The structure shown.

[0132] The second step involves flipping the structure obtained in the first step and removing the silicon wafer 40. Then, the upper metal layer is bonded to the carrier wafer 45, resulting in the structure shown below. Figure 19 The structure shown.

[0133] The third step involves etching the dielectric structure in the 3D stacked chip 2 on both sides of the upper device layer and the upper metal layer along a third direction to form the second flow channel body portion 341, resulting in... Figure 20 The structure shown.

[0134] Fourth step: The lower device layer 48 is formed using the same steps as the upper device layer, and the lower metal layer is formed using the same steps as the upper metal layer. Then, the dielectric structure in the 3D stacked chip 2 is etched on both sides of the lower metal layer and the lower device layer along a third direction to form the second flow channel body portion 341. Furthermore, the dielectric structure in the 3D stacked chip 2 is etched on both sides of the upper and lower metal layers and the upper and lower device layers along a second direction to form the first flow channel body portion 331, resulting in... Figure 21 The structure shown.

[0135] Here, a third flow channel body 35 is integrated in the lower metal layer. The third flow channel body 35 includes a second sub-flow channel 37 extending in a third direction, a first sub-flow channel 36 extending in a second direction, and a flow channel through-hole 38 connecting the first sub-flow channel 36 and the second sub-flow channel 37.

[0136] For example, Figure 25 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 6 . Figure 25 (a) in the middle is Figure 21 A top view of the structure shown. Wherein, Figure 25 (b) and (c) in the text are respectively along Figure 25 A schematic diagram of the Z1-Z2 and Z3-Z4 sections in (a) of the diagram. Figure 25 (Metal traces and transistors are omitted; only the microchannel structure is shown.) See also: Figure 25 As shown, the second flow channel main body 341 extends along the stacking direction and connects to the second sub-flow channel 37 corresponding to the lower device layer. The second flow channel main body 341 has openings at both ends communicating with other 3D stacked chips 2, allowing the cooling medium after heat exchange to flow in from the previous 3D stacked chip 2 and out to the next 3D stacked chip 2. The first flow channel main body 331 extends along the stacking direction and connects to the first sub-flow channel 36 corresponding to the lower device layer. The first flow channel main body 331 has openings at both ends communicating with other 3D stacked chips 2, allowing the cooling medium to flow in from the previous 3D stacked chip 2 and out to the next 3D stacked chip 2.

[0137] Thus, the fabrication of one of the sub-chips in the middle layer chip 22 is completed through steps one through four.

[0138] The fifth step involves using steps one through five of the first fabrication method, followed by forming the lower device layer 48 using the same steps as for the upper device layer, and forming the lower metal layer using the same steps as for the upper metal layer, resulting in... Figure 22 The structure shown.

[0139] Here, the difference from the first preparation method is that the upper metal layer is not bonded to the heat dissipation carrier 1, but can be bonded to the carrier wafer 45.

[0140] Here, the lower metal layer may not be integrated with the third flow channel body 35.

[0141] Step 6: Etch the dielectric structure in the 3D stacked chip 2 on both sides of the lower metal layer and the lower device layer along the third direction to form the second flow channel body portion 341; and etch the dielectric structure in the 3D stacked chip 2 on both sides of the upper and lower metal layers and the upper and lower device layers along the second direction to form the first flow channel body portion 331, resulting in... Figure 23 The structure shown.

[0142] For example, Figure 26 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 7 . Figure 26 (a) in the middle is Figure 23 A top view of the structure shown. Wherein, Figure 26 (b) and (c) in the text are respectively along Figure 26 A schematic diagram of the Z9-Z10 and Z11-Z12 sections in (a) of the diagram. Figure 26 (Metal traces and transistors are omitted; only the microchannel structure is shown.) See also: Figure 26 As shown, the second flow channel main body 341 extends along the stacking direction and connects to the second sub-flow channel 37 corresponding to the upper device layer. The second flow channel main body 341 has openings at both ends communicating with other 3D stacked chips 2, allowing the cooling medium after heat exchange to flow in from the previous 3D stacked chip 2 and out to the next 3D stacked chip 2. The first flow channel main body 331 extends along the stacking direction and connects to the first sub-flow channel 36 corresponding to the upper device layer. The first flow channel main body 331 has openings at both ends communicating with other 3D stacked chips 2, allowing the cooling medium to flow in from the previous 3D stacked chip 2 and out to the next 3D stacked chip 2.

[0143] Thus, the fabrication of another sub-chip in the middle layer chip 22 is completed through steps five and six.

[0144] Step 7: Bond the sub-chip obtained in step 4 to the sub-chip obtained in step 6 to obtain the following... Figure 24 The structure shown.

[0145] In some embodiments, the lower metal layer of the sub-chip obtained in step four can be bonded to a new carrier wafer, and the carrier wafer originally connected to the upper metal layer can be removed. Then, the new carrier wafer is flipped to obtain a bottom sub-chip. Next, the sub-chip obtained in step six is ​​flipped, and the carrier wafer in the sub-chip obtained in step six is ​​removed to obtain a top sub-chip. Finally, the bottom sub-chip and the top sub-chip are bonded together to obtain... Figure 24 The structure shown.

[0146] Thus, the fabrication of the middle layer chip 22 in at least two 3D stacked chips 2 is completed using the second method for fabricating semiconductor structures.

[0147] In some embodiments, Figures 27 to 28 This is a schematic diagram of a third fabrication process for a semiconductor structure provided in an embodiment of this application. A cross-sectional view of the semiconductor structure is shown. Figures 27 to 28 (The direction from left to right in the middle is the third direction). See also Figures 27 to 28 As shown, the third method for fabricating the semiconductor structure in this application embodiment may include:

[0148] The first step involves using the same preparation processes as steps one through seven of the first preparation method to form microchannels, resulting in the following: Figure 27 The structure shown.

[0149] Here, unlike the first fabrication method, the third fabrication method integrates a transistor (which can be called an M3D transistor) on both the front and back sides of the silicon wafer using M3D technology. Furthermore, in order to form the third flow channel body 35, this step only needs to fabricate up to the low-layer metal layer that forms the lower M3D transistor.

[0150] The second step involves fabricating a higher metal layer above the lower metal layer of the lower M3D transistor, resulting in a layer as shown in the image. Figure 28 The structure shown.

[0151] Here, during the fabrication of the upper metal layer of the lower M3D transistor, a third flow channel body 35 is formed on the surface of the lower metal layer through an etching process. The third flow channel body 35 includes a second sub-flow channel 37 extending along a third direction, a first sub-flow channel 36 extending along a second direction, and a flow channel via 38 connecting the first sub-flow channel 36 and the second sub-flow channel 37. Thus, the fabrication of the top layer chip 23 in at least two 3D stacked chips 2 is completed using this third method for fabricating semiconductor structures.

[0152] In some embodiments, there is an implementation where the cooling medium outflow channels are combined. Figures 29 to 31 This is a schematic diagram of a fourth fabrication process for a semiconductor structure provided in an embodiment of this application. A cross-sectional view of the semiconductor structure is shown. Figures 29 to 31 (The direction from left to right in the middle is the third direction). See also Figures 29 to 31 As shown, the fourth method for fabricating the semiconductor structure in this application embodiment may include:

[0153] Step 1: Similar to the first preparation method, complete the second sub-channel 37 extending along the third direction, the channel via 38, and the first sub-channel 36 extending along the second direction in the upper metal layer, to obtain the following... Figure 29 The structure shown.

[0154] The second step involves etching L-shaped bends 50 at both ends of the second sub-channel 37 in the reserved area using a vertical etching process followed by a series of horizontal etching processes, resulting in the following... Figure 30 The structure shown.

[0155] For example, Figure 32 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application. See also... Figure 32 As shown, the L-shaped bend 50 is located at both ends of the second sub-channel 37 along the third direction.

[0156] The third step involves forming L-shaped bends in the second sub-channels of different metal layers using the same processing technique as in the second step, resulting in... Figure 31 The structure shown.

[0157] Understandably, the L-shaped bends between adjacent chips or metal layers can form a shared cooling medium outflow channel, thereby improving the uniformity of system heat dissipation. In other words, considering the significant differences in power consumption among different types of chips, a shared cooling medium outflow channel can help the cooling medium mix in advance, reducing uneven heat distribution.

[0158] In this embodiment, a heat dissipation network based on F3D is realized through multi-axis heat dissipation microchannels, which helps reduce the risk of chip thermal runaway. The multi-directional microchannel heat dissipation scheme can ensure effective heat dissipation of each chip in the F3D system, solve the heat dissipation problems of chip stacking and its wiring, and improve system lifespan and reliability.

[0159] This application's embodiments are also applicable to transistor structures adapted to FFET technology, such as GAA FETs, CFETs, and planar transistors. This application's embodiments are also applicable to structures where the metal trace layers are power supply networks, hybrid signal-power supply networks, and clock networks. This application's embodiments are also applicable to FFET structures where memory devices are flip-chip bonded to each other, or logic devices are flip-chip bonded to memory devices. Based on the F3D packaging background, this application's embodiments provide an efficient thermal management solution. Its successful application will directly unleash the enormous potential of 3D integration, paving the way for the creation of higher-density, more powerful logic chips, with broad application prospects.

[0160] The embedded microchannel structure proposed in this application has extremely high physical visibility, and its features can be obtained through standard semiconductor reverse engineering methods. For the packaged logic chip, longitudinal slicing using focused ion beam (FIB) combined with high-resolution scanning electron microscopy (SEM) or transmission electron microscopy (TEM) can clearly observe whether specific horizontal microchannel cavities and vertical via arrays exist in the transistor's vicinity (such as deep in the substrate or between back-end interconnect layers). In addition, the inner walls of the microchannels usually involve special protective materials or hydrophilic / hydrophobic modification processes, which can be identified through energy dispersive spectroscopy (EELS).

[0161] Prior to costly destructive physical analysis, the embodiments of this application also possess significant non-destructive features. Since microchannel heat dissipation acts directly on the vicinity of the heat source in the logic device, its heat conduction path differs fundamentally from that of traditional air-cooled or liquid-cooled heat sinks (cold plates). During chip operation, high-precision infrared thermal imaging (lock-in thermography) or transient thermal resistance testing techniques can capture the chip's specific temperature gradient distribution, exhibiting a lower thermal resistance coefficient and a more uniform heat distribution profile. Simultaneously, X-ray micro-CT technology allows visualization of the internal structure without damaging the chip package, effectively identifying the layout structure of the microchannel network.

[0162] For example, see TEM images. Figure 1 As shown, in Figure 1 The top view shown in (a) contains symmetrical radiator inlets. Figure 1 In the cross-sectional view B1-B2 shown in (b), there are horizontal microchannels in the X and Y directions in the bonding area of ​​multiple chips. Similar biaxial microchannels exist at the top and bottom of the system. Multiple interconnected vertical through-holes on both sides of the system serve as heat dissipation channels. Figure 1 The A1-A2 cross-sectional view shown in (c) contains multiple interconnected vertical through holes serving as inlets for the heat sink. Figure 1 The vertical through hole in the A3-A4 cross-sectional view shown in (d) corresponds to Figure 1 The heat dissipation channels on both sides are shown in the B1-B2 cross section diagram (c).

[0163] Thirdly, embodiments of this application provide an electronic device. It includes a circuit board and a semiconductor structure as described in the above embodiments, the semiconductor structure being disposed on the circuit board. The specific structure of the semiconductor structure can be found in the description of any embodiment of the first aspect; for the sake of brevity, it will not be repeated here.

[0164] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Heat sink; At least two chips are located above the heat sink and stacked along a first direction; each chip includes a device layer formed by three-dimensional stacking technology and a metal layer connected to the device layer; the first direction is the same as the stacking direction of the device layer; A microchannel, comprising a channel inlet, a channel outlet, and a channel body, wherein the channel inlet is located on one of the at least two chips, away from the heat sink, and the channel outlet is located on the heat sink; the channel body comprises a first channel body, a second channel body, and a plurality of third channel bodies, wherein the first channel body and the second channel body both extend along a first direction and are located in at least one edge region of the chip; each third channel body is located in a metal layer of the chip; One end of the first flow channel body is connected to the flow channel inlet, the other end of the first flow channel body is connected to one end of each of the third flow channel bodies, the other end of each of the third flow channel bodies is connected to one end of the second flow channel body, and the other end of the second flow channel body is connected to the flow channel outlet.

2. The semiconductor structure according to claim 1, characterized in that, Each third flow channel body includes: at least two sub-flow channels and a flow channel through hole located between any two sub-flow channels; the flow channel through hole is used to connect the any two sub-flow channels; Wherein, the at least two sub-channels include: a first sub-channel and / or a second sub-channel; the first sub-channel extends along a second direction, and the second sub-channel extends along a third direction; the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction.

3. The semiconductor structure according to claim 2, characterized in that, The first flow channel body is connected to one of the at least two sub-flow channels, and the second flow channel body is connected to the other sub-flow channel among the at least two sub-flow channels; The end cross-sectional shape of the sub-channels that are connected to the first flow channel body and the second flow channel body is straight, broken, or curved.

4. The semiconductor structure according to claim 2, characterized in that, The at least two sub-channels include: a first sub-channel and a second sub-channel; Wherein, the first flow channel body is located in at least one edge region of the chip in the second direction, and the first flow channel body connects to the end of the first sub-flow channel; the second flow channel body is located in at least one edge region of the chip in the third direction, and the second flow channel body connects to the end of the second sub-flow channel.

5. The semiconductor structure according to claim 1, characterized in that, The chip includes a first metal layer and a second metal layer; the first metal layer and the second metal layer are respectively located on both sides of the chip in the first direction; The first metal layer and the second metal layer each have a third flow channel body, and the third flow channel body in the first metal layer and the third flow channel body in the second metal layer are arranged opposite to each other.

6. The semiconductor structure according to claim 1, characterized in that, The at least two chips include: a top-layer chip, a middle-layer chip, and a bottom-layer chip stacked along the first direction, wherein the bottom-layer chip is connected to the heat sink. Wherein, when any one of the top-layer chip, the middle-layer chip, and the bottom-layer chip includes at least two sub-chips, the at least two sub-chips are stacked along the first direction using three-dimensional monolithic integration technology, and each sub-chip includes a device layer formed by three-dimensional stacking technology.

7. The semiconductor structure according to claim 2, characterized in that, The first flow channel body has a tapered shape that gradually decreases in diameter as it approaches the heat sink plate.

8. The semiconductor structure according to claim 1, characterized in that, When there are multiple second flow channel bodies, the flow channel outlet is a multi-pass structure, and each liquid inlet in the multi-pass structure is connected to one second flow channel body.

9. A method for fabricating a semiconductor structure, characterized in that, For preparing the semiconductor structure as described in any one of claims 1 to 8, comprising: A heat dissipation carrier is obtained, wherein a flow channel outlet is formed on the heat dissipation carrier; Prepare at least two chips; Along a first direction, the chips of the at least two chips are bonded together in pairs, and the at least two chips and the heat sink are bonded together; The fabrication process of each chip includes: fabricating an upper device layer and an upper metal layer connected to the upper device layer; fabricating a lower device layer and a lower metal layer connected to the lower device layer; forming a third flow channel body in the upper metal layer and / or the lower metal layer; and forming a first flow channel body portion and a second flow channel body portion that communicate with the third flow channel body in at least one edge region of the chip. After bonding, the first channel body portion of at least two chips forms a first channel body, and the first channel body has a channel inlet at the end away from the heat sink; the second channel body portion of at least two chips forms a second channel body, and the second channel body is connected to the channel outlet.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor structure as described in claim 9.

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