Interposer including inductor device

Abstract

In one aspect, the interposer includes: a substrate; a first metallization layer located on the substrate and having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first metallization layer and the second metallization layer and having a plurality of vias. At least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both may be configured to form a first inductor device and a second inductor device. The first inductor device may be electrically coupled between a first power node and a second power node of the interposer. The second inductor device may be electrically coupled between a first power node and a third power node of the interposer.

Description

Technical Field

[0001] This disclosure generally relates to an interposer, and more specifically, to an interposer for an integrated circuit (IC) package and including an inductor device coupled between two power nodes of the interposer. Background Technology

[0002] IC technology has made significant progress in improving computing power through the miniaturization of electronic components. An IC chip or IC die may include a set of circuits integrated thereon. In some specific embodiments, an IC device can be formed by incorporating and protecting one or more IC dies in an IC package, wherein various power and signal nodes of the one or more IC dies can be electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in one or more package substrates of the IC package. Unless otherwise stated, the term "substrate" in this disclosure refers to a package substrate used to encapsulate one or more IC dies, which is different from the semiconductor substrate used to form the IC dies.

[0003] Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) ICs, and so on. Advanced packaging and processing technologies enable complex devices such as multi-die devices and system-on-a-chip (SoC) devices, which may include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), etc.

[0004] For example, in a 3D IC (3DIC) packaging scheme, an interposer can be used within the IC package, on which one or more IC dies can be mounted, and the interposer can be further mounted on another IC die. The IC package can then be mounted on a circuit board (e.g., a printed circuit board, or PCB). In some examples, a power management integrated circuit (PMIC) (e.g., in the form of another IC package) can be mounted on the PCB and configured to manage one or more power distribution networks (PDNs) for supplying power to the IC dies within the IC package.

[0005] In some examples, multiple circuit blocks within an IC die may share the same PDN. However, in other examples, multiple circuit blocks on a single PDN can present design performance issues or risks, such as power supply noise caused by switching noise from one circuit block potentially coupling to another circuit block via the shared PDN. This could reduce the speed and signal integrity of the circuit blocks (affecting both analog and digital circuits). Furthermore, as the industry shifts towards 3DIC-based IC die packaging, the need for power sharing may increase as circuit density increases.

[0006] Therefore, it may be necessary to design a shared PDN that meets the power specifications of the circuit blocks on the shared PDN, so that the circuit blocks can share sensitive power supplies while having the necessary noise isolation from each other. Summary of the Invention

[0007] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0008] In one aspect, the interposer includes a substrate; a first metallization layer located on the substrate, the first metallization layer having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first metallization layer and the second metallization layer, the via layer having a plurality of vias, wherein at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, and the second inductor device being electrically coupled between a first power node and a third power node of the interposer.

[0009] In one aspect, a method of manufacturing an interposer includes forming a first metallization layer on a substrate, the first metallization layer having a first plurality of conductive patterns; forming a second metallization layer having a second plurality of conductive patterns; and forming a via layer disposed between the first metallization layer and the second metallization layer, the via layer having a plurality of vias, wherein at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, and the second inductor device being electrically coupled between a first power node and a third power node of the interposer.

[0010] In one aspect, an integrated circuit (IC) package includes an interposer comprising: a substrate; a first metallization layer located on the substrate and having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first and second metallization layers and having a plurality of vias, wherein a first IC die is mounted on the interposer, the first IC die including a first circuit block and a second circuit block, wherein at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, the second inductor device being electrically coupled between a first power node and a third power node of the interposer, the first circuit block including a first power terminal electrically coupled to the second power node of the interposer, and the second circuit block including a second power node electrically coupled to the third power node of the interposer.

[0011] In one aspect, an electronic device includes an integrated circuit (IC) package comprising: an interposer including: a substrate; a first metallization layer located on the substrate and having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first and second metallization layers and having a plurality of vias, wherein a first IC die is mounted on the interposer, the first IC die including a first circuit block and a second circuit block, wherein at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, the second inductor device being electrically coupled between a first power node and a third power node of the interposer, the first circuit block including a first power terminal electrically coupled to a second power node of the interposer, and the second circuit block including a second power node electrically coupled to a third power node of the interposer.

[0012] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0013] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided for illustrative purposes only and not to limit the aspects.

[0014] Figure 1 This is a cross-sectional view of a circuit board assembly according to various aspects of this disclosure.

[0015] Figure 2This is a cross-sectional view of an integrated circuit (IC) package according to various aspects of this disclosure.

[0016] Figures 3A to 3E The structure of the various stages of manufacturing the intermediate layer according to various aspects of this disclosure is illustrated.

[0017] Figure 4 Methods for creating an intermediary layer according to various aspects of this disclosure are illustrated.

[0018] Figure 5 Mobile devices according to various aspects of this disclosure are illustrated.

[0019] Figure 6 Various electronic devices that can be incorporated into IC packages including intermediaries as described herein are illustrated according to various aspects of this disclosure.

[0020] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0021] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0022] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0023] In some of the described example implementations, instances are identified where the various component structures and operational parts are derived from known conventional techniques and subsequently arranged according to one or more aspects. In such instances, the internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary aspects disclosed herein.

[0024] The terminology used herein is for descriptive purposes only and is not intended to be limiting. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the term “comprising,” as used herein, indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, terms such as approximate and general indicate that the examples provided are not intended to be limited to precise numerical values ​​or geometries and include normal variations due to manufacturing tolerances and variations, material variations, and other design considerations.

[0025] As mentioned above, various aspects generally involve fabricating an interposer layer that includes embedded inductor devices coupled between two power nodes in a shared power distribution network (PDN) for the same potential. In some aspects, the interposer layer may also include embedded inductor devices between power nodes in a shared PDN for different potentials.

[0026] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, switching noise coupled from one circuit block to a power node in a shared PDN can be blocked by an embedded inductor device without affecting another power node in the shared PDN that uses the same potential. In some examples, an embedded capacitor device can increase the stability of the voltage level at the power node for different potentials in a shared PDN with different circuit blocks.

[0027] Figure 1 This is a cross-sectional view of a portion of a circuit board assembly 100 according to various aspects of this disclosure. In some aspects, Figure 1 This is a simplified cross-sectional view of the circuit board assembly 100, and some details and components of the circuit board assembly 100 can be seen in... Figure 1 Simplified or omitted.

[0028] like Figure 1 As shown, the circuit board assembly 100 may include a printed circuit board (PCB) 110, an IC package 120 mounted on the PCB 110, and a power management integrated circuit (PMIC) 180 (in the form of another IC package) mounted on the PCB 110. In some aspects, the PCB 110 may include a conductive pattern layer (not shown) formed therein. In some aspects, the IC package 120 may be mounted on the PCB 110 via a terminal structure 122 (e.g., solder bumps based on the controlled collapse chip connection (C4) mounting method, also referred to as C4 bumps). In some aspects, the PMIC 180 may be mounted on the PCB 110 via a terminal structure 182 (e.g., C4 bumps).

[0029] In some aspects, the IC package 120 may include a package substrate 124, a first IC die 130, an interposer 140, and a second IC die 180. In some aspects, the first IC die 130 may be mounted on the interposer 140 via a terminal structure 132 (e.g., solder bumps or copper pillar bumps). In some aspects, the interposer 140 may be mounted on the second IC die 160 via a terminal structure 142 (e.g., solder bumps or copper pillar bumps). In some aspects, the second IC die 160 may be mounted on the package substrate 124 via a terminal structure 162 (e.g., solder bumps or copper pillar bumps).

[0030] In some aspects, the first IC die 130 may include a first circuit block 134 and a second circuit block 136. In some aspects, the first circuit block 134 and the second circuit block 136 may each be configured based on a corresponding intellectual property (IP) circuit block. In some aspects, the first circuit block 134 and / or the second circuit block 136 may include one or more analog circuit blocks, one or more digital circuit blocks, and / or one or more mixed-mode circuit blocks.

[0031] In some aspects, the interposer 140 may include conductive patterns (not shown) configured to define at least power nodes 144, 145, 146, 148, and 149. In some aspects, the interposer 140 may include conductive patterns (not shown) configured to form a first inductor device 152 and a second inductor device 154. In some aspects, the first inductor device 152 may be electrically coupled between power nodes 144 and 145 of the interposer 140. In some aspects, the second inductor device 154 may be electrically coupled between power nodes 144 and 146 of the interposer 140. In some aspects, the first circuit block 134 may include a first power terminal (e.g., represented by terminal structure 132a of terminal structure 132) electrically coupled to power nodes 145 of the interposer 140. In some aspects, the second circuit block 136 may have a second power terminal (e.g., represented by terminal structure 132b of terminal structure 132) electrically coupled to power nodes 146 of the interposer 140.

[0032] In some aspects, the interposer 140 may further include a first capacitor device 156 and a second capacitor device 158. In some aspects, the first capacitor device 156 may be electrically coupled between power nodes 145 and 148 of the interposer 140. In some aspects, the second capacitor device 158 may be electrically coupled between power nodes 146 and 149 of the interposer 140. In some aspects, the first circuit block 134 may include a third power terminal (e.g., represented by terminal structure 132c of terminal structure 132) electrically coupled to power node 148 of the interposer 140. In some aspects, the second circuit block 136 may have a fourth power terminal (e.g., represented by terminal structure 132d of terminal structure 132) electrically coupled to power node 149 of the interposer 140.

[0033] In some aspects, the second die 160 may include through-substrate vias (TSVs) 164a, 164b and 164c electrically coupled to power nodes 144, 148 and 149 via corresponding terminal structures in terminal structure 142.

[0034] In some aspects, PMIC 180 can be configured to supply a first supply voltage at terminal structure 182a of terminal structure 182. Power node 144 can be connected via conductive paths 112 formed by various conductive patterns in PCB 110, terminal structure 122a of terminal structure 122, conductive paths 126a formed by various conductive patterns in package substrate 124, and terminal structures of terminal structure 162 (e.g., Figure 2 The terminal structures of terminal structure 162a, TSV 164a, and terminal structure 142 (e.g., Figure 2 Terminal structure 142a) is electrically coupled to terminal structure 182a. Therefore, power node 144 can be configured to carry a first supply voltage from PMIC 180. In some respects, power nodes 144, 145, and 146 can be configured for the same direct current (DC) potential.

[0035] In some aspects, PMIC 180 can be configured to supply a second supply voltage different from the first voltage at terminal structure 182b of terminal structure 182, or to supply a ground voltage. Power node 148 can be connected via conductive paths 114 formed by various conductive patterns in PCB 110, terminal structures 122b in terminal structure 122, conductive paths 126b formed by various conductive patterns in package substrate 124, and terminal structures in terminal structure 162 (e.g., Figure 2 Terminal structures 162b, TSV 164b, and 142 (e.g., terminal structures in terminal structure 162b, TSV 164b, and terminal structure 142) Figure 2Terminal structure 142b) is electrically coupled to terminal structure 182b. Power node 149 can be electrically coupled through conductive path 114 of PCB 110, terminal structure 122c in terminal structure 122, conductive path 126c formed by various conductive patterns in package substrate 124, and terminal structure in terminal structure 162 (e.g., Figure 2 Terminal structures in terminal structure 162c, TSV 164c, and terminal structure 142 (e.g., Figure 2 Terminal structure 142c) is electrically coupled to terminal structure 182b. Therefore, power nodes 148 and 149 can be configured to carry a second supply voltage or ground voltage from PMIC 180.

[0036] In some respects, the second supply voltage may be lower than the first supply voltage. In some respects, the ground voltage may be lower than the first supply voltage.

[0037] Figure 2 IC packages (such as) according to various aspects of this disclosure Figure 1 A cross-sectional view of a portion of the IC package 120. Figure 2 Zhongyu Figure 1 Components that are identical or similar to those in the figures are given the same reference numerals, and therefore their detailed descriptions may be simplified or omitted.

[0038] like Figure 2 As shown, the interposer 140 may include a substrate 210, a first metallization layer 220 on the substrate 210, a second metallization layer 230, and a via layer 240 disposed between the first metallization layer 220 and the second metallization layer 230. In some aspects, the substrate 210 may include a dielectric layer 212 and TSVs 216a, 216b, and 216c extending through the dielectric layer 212. In some aspects, the substrate 210 may include an etch stop layer 214 below the dielectric layer 212, and may include conductive pads 217a, 217b, and 217c connected to the TSVs 216a, 216b, and 216c. In some aspects, the substrate 210 may also include a passivation layer 218 located below the etch stop layer 214 and surrounding the conductive pads 217a, 217b, and 217c. In some respects, conductive pads 217a, 217b and 217c can be connected to terminal structures 142a, 142b and 142c.

[0039] In some aspects, the first metallization layer 220 may include a first plurality of conductive patterns, including conductive patterns 222, 224a, 224b, 224c, and 224d. In some aspects, the first metallization layer 220 may include an interlayer dielectric layer 226 surrounding the first plurality of conductive patterns, and an etch stop layer 228 beneath the interlayer dielectric layer 226. In some aspects, the second metallization layer 230 may include a second plurality of conductive patterns, including conductive patterns 232, 234a, 234b, 234c, and 234d. In some aspects, the second metallization layer 230 may include an interlayer dielectric layer 236 surrounding the second plurality of conductive patterns, and an etch stop layer 238 beneath the interlayer dielectric layer 236. Furthermore, in some aspects, the via layer 240 may include a plurality of vias 242, 244a, 244b, 244c, and 244d. In some aspects, the via layer 240 may include an interlayer dielectric layer 246 surrounding a plurality of vias, and an etch stop layer 248 beneath the interlayer dielectric layer 246.

[0040] In some aspects, the interposer 140 may further include an etch stop layer 252 on the second metallization layer 230, a passivation layer 254 on the etch stop layer 252, and a dielectric layer 256 on the passivation layer 254. In some aspects, the interposer 140 may include bump under-metallization structures 262a, 262b, 262c, and 262d that pass through the etch stop layer 252, the passivation layer 254, and the dielectric layer 256 and are respectively connected to the conductive patterns 234a, 234b, 234c, and 234d. Furthermore, another passivation layer 258 may be disposed on the dielectric layer 256 and partially cover the bump under-metallization structures 262a, 262b, 262c, and 262d. Furthermore, the interposer layer 140 may include conductive pads 264a, 264b, 264c, and 264d located on and connected to the under-bump metallization structures 262a, 262b, 262c, and 262d. In some aspects, the conductive pads 264a, 264b, 264c, and 264d may be connected to the terminal structures 132a, 132b, 132c, and 132d.

[0041] In some aspects, dielectric layers 212, 226, 246, and 256 may comprise silicon dioxide (SiO2), tetraethyl orthosilicate (TEOS), or fluorinated tetraethyl orthosilicate (FTEOS). In some aspects, etch stop layers 214, 228, 248, and 252 may comprise silicon nitride (SiN). In some aspects, passivation layers 218, 254, and 258 may comprise polyimide.

[0042] In some aspects, conductive pads 217a, TSV 216a, conductive pattern 222, via 242, and conductive pattern 232 can constitute a set of conductive structures electrically coupled together, and can correspond to Figure 1 The power node 144 in the middle. In some aspects, conductive pattern 224a, via 244a, conductive pattern 234a, under-bump metallization structure 262a and conductive pad 264a can constitute a set of conductive structures electrically coupled together, and can correspond to Figure 1 The power node 145 in the middle. In some aspects, the conductive pattern 224b, via 244b, conductive pattern 234b, under-bump metallization structure 262b and conductive pad 264b can form a set of conductive structures electrically coupled together, and can correspond to Figure 1 Power node 146 in the middle.

[0043] In some aspects, conductive pads 217b, TSV 216b, conductive pattern 224c, via 244c, conductive pattern 234c, under-bump metallization structure 262c, and conductive pads 264c can constitute a set of conductive structures electrically coupled together, and can correspond to Figure 1 Power node 148 in the middle. In some aspects, conductive pads 217c, TSVs 216c, conductive patterns 224d, vias 244d, conductive patterns 234d, under-bump metallization structures 262d, and conductive pads 264d can constitute a set of conductive structures electrically coupled together, and can correspond to Figure 1 Power node 149 in the middle.

[0044] In addition, such as Figure 2 As shown, given Figure 1 At least a portion of the plurality of conductive patterns of the first metallization layer 220, a portion of the plurality of conductive patterns of the second metallization layer 230, or both, may be configured to form a first inductor device 152 and a second inductor device 154. In some aspects, the first inductor device 152 may be electrically coupled between power nodes 144 and 145 of the interposer layer 140. In some aspects, the second inductor device 154 may be electrically coupled between power nodes 144 and 146 of the interposer layer 140.

[0045] In some aspects, the first inductor device 152 may be a helical structure formed in the first metallization layer 220 or the second metallization layer 230. In some aspects, the first inductor device 152 may be a first solenoid structure formed in the first metallization layer 220, the via layer 240, and the second metallization layer 230, wherein the first solenoid structure may have a corresponding conductive pattern in the first metallization layer, a corresponding via in the via layer, and a corresponding conductive pattern in the second metallization layer connecting the coil windings of the first solenoid structure. In some aspects, the second inductor device 154 may be a second helical structure formed in the first metallization layer 220 or the second metallization layer 230. In some aspects, the second inductor device 154 may be a second solenoid structure formed in the first metallization layer 220, the via layer 240, and the second metallization layer 230, wherein the second solenoid structure may have a corresponding conductive pattern in the first metallization layer, a corresponding via in the via layer, and a corresponding conductive pattern in the second metallization layer connecting the coil windings of the second solenoid structure.

[0046] In some respects, the structures and manufacturing methods of the first helical structure, the second helical structure, the first solenoid structure, and / or the second solenoid structure are described in this disclosure as non-limiting examples and may be any suitable structure and / or method known in the field of semiconductor manufacturing.

[0047] In some aspects, each of inductor devices 152 and 154 may be a bimetallic stacked spiral inductor with a center tap, having a size of 60 micrometers (μm) × 60 μm. In some aspects, each of inductor devices 152 and 154 according to this example structure may have an inductance value of 100 pH (or an inductance value of 200 pH between power nodes 145 and 146 when the two inductor devices 152 and 154 are connected in series).

[0048] In addition, such as Figure 2 As shown, given Figure 1 The interposer 140 may include a first capacitor device 156 and a second capacitor device 158 formed in the substrate 210, the first metallization layer 220, the via layer 240, the second metallization layer 230, or a combination thereof. In some aspects, the first capacitor device 156 may be electrically coupled between power nodes 145 and 148 of the interposer 140. In some aspects, the second capacitor device 158 may be electrically coupled between power nodes 146 and 149 of the interposer 140.

[0049] In some aspects, the first capacitor device 156 may be a first metal-insulator-metal structure formed in the first metallization layer 220 and the via layer 240. In some aspects, the first capacitor device 156 may be a first metal-oxide-metal structure formed in the first metallization layer 220, the second metallization layer 230, or both. In some aspects, the first capacitor device 156 may be a first deep trench capacitor structure formed in the first metallization layer 220 and the substrate 210. In some aspects, the second capacitor device 158 may be a second metal-insulator-metal structure formed in the first metallization layer 220 and the via layer 240. In some aspects, the second capacitor device 158 may be a second metal-oxide-metal structure formed in the first metallization layer 220, the second metallization layer 230, or both. In some aspects, the second capacitor device 158 may be a second deep trench capacitor structure formed in the first metallization layer 220 and the substrate 210. In some aspects, the structures and manufacturing methods of the first metal-oxide-metal structure, the second metal-oxide-metal structure, the first metal-insulator-metal structure, the second metal-insulator-metal structure, the first deep trench capacitor structure and / or the second deep trench capacitor structure are described in this disclosure as non-limiting examples and may be any suitable structure and / or method known in the field of semiconductor manufacturing.

[0050] Therefore, as Figure 1 and Figure 2 As shown, the interposer layer 140 between the two IC dies 130 and 160 can increase the stability of the voltage levels supplied to the different circuit blocks (for different potentials) by including embedded capacitor devices (e.g., capacitor devices 156 and 158), and can isolate switching noise between the different circuit blocks by including embedded inductor devices (e.g., inductor devices 152 and 154). For example, switching noise of circuit block 134 coupled to power node 145 can be stopped or filtered by inductor devices 152 and 154, and therefore can remain unaffected by power node 146 (which is configured to supply a first supply voltage to circuit block 136 or is configured for the same potential).

[0051] Figures 3A to 3E Examples of manufacturing, such as, according to various aspects of this disclosure Figure 1 and Figure 2 The structure of each stage of the intermediate layer 140 in the middle layer. Figures 3A to 3E exemplified with Figure 1 and Figure 2 Components that are the same as or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0052] like Figure 3AAs shown, structure 300A can be formed by forming TSVs 216a, 216b, and 216c in substrate 310. At this stage, TSVs 216a, 216b, and 216c have not yet completely penetrated substrate 310. In some aspects, the lower portion of substrate 310 can be removed to expose the lower surfaces of TSVs 216a, 216b, and 216c (e.g., Figure 3E In some respects, TSV 216a, 216b and 216c can be formed by first forming an opening in substrate 310 and then filling the opening with a conductive material (e.g., copper, aluminum, tungsten or a combination thereof).

[0053] Furthermore, structure 300A may be further formed by fully or partially forming a first capacitor device 156 (e.g., portion 322a) and a second capacitor device 158 (e.g., portion 322b). In some aspects, the first capacitor device 156 and the second capacitor device 158 may comprise deep trench capacitor structures, and portions 322a and 322b may be formed by: forming trenches in substrate 310; forming a first metal portion of each of the deep trench capacitor structures in the trenches and extending the first metal portion to the upper surface of substrate 310; forming an insulating portion of each of the deep trench capacitor structures in the trenches and on the corresponding first metal portions; and / or forming a second metal portion of each of the deep trench capacitor structures in the trenches and on the insulating portions. In some aspects, the first metal portion, the insulating portion, and the second metal portion are at least partially in a first metallization layer (e.g., first metallization layer 220) and partially in the substrate.

[0054] In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a metal-oxide-metal structure or a metal-insulator-metal structure, and may not form portions 322a and 322b.

[0055] like Figure 3B As shown, structure 300B can be formed based on structure 300A by forming a first metallization layer 220 on substrate 310. In some aspects, the first metallization layer 220 can be formed by first forming an etch stop layer 228 on substrate 310, forming an interlayer dielectric layer 226 on the etch stop layer 228, etching the interlayer dielectric layer 226 and the etch stop layer 228 to define an opening, and filling the opening with a conductive material (e.g., copper, aluminum, tungsten, or a combination thereof) to form a first plurality of conductive patterns. In some aspects, the first plurality of conductive patterns may include conductive patterns 222, 224a, 224b, 224c, and 224d.

[0056] In some aspects, structure 300B may include portion 324a of the first capacitor device 156 and portion 324b of the second capacitor device 158. In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a deep trench capacitor structure, and portions 324a and 324b may be extensions of portions 322a and 322b as described above.

[0057] In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a metal-insulator-metal structure, and portions 324a and 324b may be formed by forming a first metal portion of each of the metal-insulator-metal structures. In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a metal-oxide-metal structure formed in a first metallization layer 220, and portions 324a and 324b may be formed by forming a first metal portion and a second metal portion of each of the metal-oxide-metal structures, wherein an insulating portion of each of the metal-oxide-metal structures separates a respective first metal portion and a respective second metal portion.

[0058] In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a metal-oxide-metal structure formed in a metallization layer other than the first metallization layer 220, and may not form portions 322a and 322b.

[0059] In some aspects, structure 300B may further include a portion 332a of the first inductor device 152 and a portion 332b of the second inductor device 154. In some aspects, the first inductor device 152 and the second inductor device 154 may include conductive patterns in portions 332a and 332b, the conductive patterns being configured as corresponding helical structures in the first metallization layer 220. In some aspects, the first inductor device 152 and the second inductor device 154 may include solenoid structures, and portions 332a and 332b may include conductive patterns of first lateral winding segments of coil windings configured as corresponding solenoid structures.

[0060] like Figure 3C As shown, structure 300C can be formed based on structure 300C by forming a via layer 240 on the first metallization layer 220. In some aspects, the via layer 240 can be formed by first forming an etch stop layer 248 on the first metallization layer 220, forming an interlayer dielectric layer 246 on the etch stop layer 248, etching the interlayer dielectric layer 246 and the etch stop layer 248 to define an opening, and filling the opening with a conductive material (e.g., copper, aluminum, tungsten, or a combination thereof) to form a plurality of vias. In some aspects, the plurality of vias may include vias 242, 244a, 244b, 244c, and 244d.

[0061] In some aspects, structure 300C may include portion 326a of the first capacitor device 156 and portion 326b of the second capacitor device 158. In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a deep trench capacitor structure and may not form portions 326a and 326b.

[0062] In some aspects, the first capacitor device 156 and the second capacitor device 158 may include metal-insulator-metal structures, and portions 326a and 326b may be formed by forming an insulating portion of each of the metal-insulator-metal structures on a respective first metal portion and forming a second metal portion on a respective insulating portion. In some aspects, the first capacitor device 156 and the second capacitor device 158 may include metal-oxide-metal structures formed in a first metallization layer 220 or another metallization layer, and portions 326a and 326b may include vias for electrically connecting the respective metal-oxide-metal structures.

[0063] In some aspects, structure 300C may further include a portion 334a of the first inductor device 152 and a portion 334b ​​of the second inductor device 154. In some aspects, the first inductor device 152 and the second inductor device 154 may include conductive patterns configured as respective helical structures in the first metallization layer 220 or another metallization layer, and portions 334a and 334b ​​may include vias for electrically connecting the respective helical structures. In some aspects, the first inductor device 152 and the second inductor device 154 may include solenoid structures, and portions 334a and 334b ​​may include conductive patterns of vertical winding segments of coil windings configured as corresponding solenoid structures.

[0064] like Figure 3D As shown, structure 300D can be formed based on structure 300C by forming a second metallization layer 230 on the via layer 240. In some aspects, the second metallization layer 230 can be formed by first forming an etch stop layer 238 on the via layer 240, forming an interlayer dielectric layer 236 on the etch stop layer 238, etching the interlayer dielectric layer 236 and the etch stop layer 238 to define an opening, and filling the opening with a conductive material (e.g., copper, aluminum, tungsten, or a combination thereof) to form a second plurality of conductive patterns. In some aspects, the second plurality of conductive patterns may include conductive patterns 232, 234a, 234b, 234c, and 234d.

[0065] In some aspects, structure 300D may include portion 328a of the first capacitor device 156 and portion 328b of the second capacitor device 158. In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a deep trench capacitor structure or a metal-insulator-metal structure, and portions 328a and 328b may be omitted.

[0066] In some aspects, the first capacitor device 156 and the second capacitor device 158 may include metal-oxide-metal structures formed in the second metallization layer 230, and portions 328a and 328b may be formed by forming a first metal portion of each of the metal-oxide-metal structures, a second metal portion of each of the metal-oxide-metal structures, and an insulating portion separating the respective first metal portion and the respective second metal portion.

[0067] In some aspects, the first capacitor device 156 and the second capacitor device 158 may include a metal-oxide-metal structure formed in a metallization layer other than the second metallization layer 230, and may not form portions 328a and 328b.

[0068] In some aspects, structure 300D may further include a portion 336a of the first inductor device 152 and a portion 336b of the second inductor device 154. In some aspects, the first inductor device 152 and the second inductor device 154 may include conductive patterns in portions 336a and 336b, the conductive patterns being configured as corresponding helical structures in the second metallization layer 230. In some aspects, the first inductor device 152 and the second inductor device 154 may include solenoid structures, and portions 336a and 336b may include conductive patterns of second lateral winding segments of coil windings configured as corresponding solenoid structures.

[0069] like Figure 3EAs shown, a structure 300E corresponding to the interposer layer 140 can be formed. In some aspects, the structure 300E can be formed based on the structure 300D by forming an etch stop layer 252 on the second metallization layer 230, a passivation layer 254 on the etch stop layer 252, and a dielectric layer 256 on the passivation layer 254. In some aspects, the structure 300E can be formed by forming openings in the etch stop layer 252 and the dielectric layer 256, and forming bump under-metallization structures 262a, 262b, 262c, and 262d in the openings and on the dielectric layer 256. In some respects, structure 300E may also be formed by forming another passivation layer 258 on dielectric layer 256 and partially covering under-bump metallization structures 262a, 262b, 262c and 262d, and then forming conductive pads 264a, 264b, 264c and 264d on under-bump metallization structures 262a, 262b, 262c and 262d and connecting them to these under-bump metallization structures.

[0070] Furthermore, in some aspects, structure 300E can be formed by removing the lower portion of substrate 310 (thus becoming substrate 210) to expose the lower surfaces of TSVs 216a, 216b, and 216c. In some aspects, structure 300E can be formed by: forming an etch stop layer 214 below dielectric layer 212; forming conductive pads 217a, 217b, and 217c connected to TSVs 216a, 216b, and 216c; and forming a passivation layer 218 below the etch stop layer 214 and around the conductive pads 217a, 217b, and 217c. In some aspects, structure 300E can also be formed by forming terminal structures 142a, 142b, and 142c below the conductive pads 217a, 217b, and 217c (e.g., in...). Figure 3E The process is described as forming solder balls before the interposer 140 is mounted on the IC die 160.

[0071] Figure 4 Examples of methods for manufacturing intermediate layers (such as) according to various aspects of this disclosure are illustrated. Figure 1 and 2 Intermediate layer 140 and / or Figure 3E Method 400 (structure 300E) in the structure. In some respects, Figures 3A to 3E Intermediate layers can be depicted according to different manufacturing stages of method 400.

[0072] At operation 410, a first metallization layer (e.g., first metallization layer 220) may be formed on a substrate (e.g., substrate 310 or substrate 210 after trimming substrate 310). In some aspects, the first metallization layer may have a first plurality of conductive patterns (e.g., conductive patterns 222, 224a, 224b, 224c, and 224d). In some aspects, prior to operation 410, portions of the first capacitor device 156 (e.g., portion 322a) and the second capacitor device 158 (portion 322b) may be formed together with the substrate 310. In some aspects, at operation 410, portions of the first capacitor device 156 (e.g., portion 324a) and the second capacitor device 158 (portion 324b) may be formed. In some aspects, at operation 410, portions of the first inductor device 152 (e.g., portion 332a) and the second inductor device 154 (portion 332b) may be formed.

[0073] At operation 420, a second metallization layer (e.g., second metallization layer 230) may be formed. In some aspects, the second metallization layer may have a second plurality of conductive patterns (e.g., conductive patterns 232, 234a, 234b, 234c, and 234d). In some aspects, at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device (e.g., first inductor device 152) and a second inductor device (e.g., second inductor device 154). In some aspects, the first inductor device may be electrically coupled between a first power node (e.g., power node 144) and a second power node (e.g., power node 145) of the intermediate layer. In some aspects, the second inductor device may be electrically coupled between a first power node (e.g., power node 144) and a third power node (e.g., power node 146) of the intermediate layer.

[0074] In some aspects, at operation 420, a portion of the first capacitor device 156 (e.g., portion 328a) and a portion of the second capacitor device 158 (part 328b) may be formed. In some aspects, at operation 420, a portion of the first inductor device 152 (e.g., portion 336a) and a portion of the second inductor device 154 (part 336b) may be formed.

[0075] In operation 430, a via layer (e.g., layer 240) may be provided between the first metallization layer and the second metallization layer. In some aspects, the via layer may have multiple vias (e.g., vias 242, 244a, 244b, 244c, and 244d). In some aspects, operation 430 may be performed after operation 410 but before operation 420. In some aspects, at operation 430, a portion of the first capacitor device 156 (e.g., portion 326a) and a portion of the second capacitor device 158 (portion 326b) may be formed. In some aspects, at operation 430, a portion of the first inductor device 152 (e.g., portion 334a) and a portion of the second inductor device 154 (portion 334b) may be formed.

[0076] In some aspects, the first capacitor device and the second capacitor device may be formed in a substrate, a first metallization layer, a via layer, a second metallization layer, or a combination thereof. In some aspects, the first capacitor device may be electrically coupled between a second power node (e.g., power node 145) and a fourth power node (e.g., power node 148) in the interposer. In some aspects, the second capacitor device may be electrically coupled between a third power node (e.g., power node 146) and a fifth power node (e.g., power node 149) in the interposer.

[0077] In some aspects, the first power node may be configured to carry a first supply voltage. In some aspects, the fourth and fifth power nodes may be configured to carry a second supply voltage different from the first supply voltage or to carry a ground voltage. In some aspects, the first, second, and third power nodes may be configured to use the same DC potential.

[0078] In some aspects, the first inductor device may include a first helical structure formed in a first metallization layer or a second metallization layer. In some aspects, the first inductor device may include a first solenoid structure formed in a first metallization layer, a via layer, and a second metallization layer, wherein the first solenoid structure may have a corresponding conductive pattern in the first metallization layer, a corresponding via in the via layer, and a corresponding conductive pattern in the second metallization layer, connecting coil windings of the first solenoid structure. In some aspects, the second inductor device may include a second helical structure formed in a first metallization layer or a second metallization layer. In some aspects, the second inductor device may include a second solenoid structure formed in a first metallization layer, a via layer, and a second metallization layer, wherein the second solenoid structure may have a corresponding conductive pattern in the first metallization layer, a corresponding via in the via layer, and a corresponding conductive pattern in the second metallization layer, connecting coil windings of the second solenoid structure.

[0079] In some aspects, the first capacitor device may include a first metal-insulator-metal structure formed in a first metallization layer and a via layer. In such scenarios, forming the first metallization layer may include forming a first metal portion of the first metal-insulator-metal structure, and forming the via layer includes forming an insulating portion of the first metal-insulator-metal structure on the first metal portion and forming a second metal portion on the insulating portion of the first metal-insulator-metal structure. In some aspects, the second capacitor device may include a second metal-insulator-metal structure formed in a first metallization layer and a via layer. In such scenarios, forming the first metallization layer may include forming a first metal portion of the second metal-insulator-metal structure, and forming the via layer includes forming an insulating portion of the second metal-insulator-metal structure on the first metal portion and forming a second metal portion on the insulating portion of the second metal-insulator-metal structure.

[0080] In some aspects, the first capacitor device may include a first metal-oxide-metal structure formed in a first metallization layer, a second metallization layer, or both. In such scenarios according to some examples, forming the first metallization layer may include a first metal portion forming the first metal-oxide-metal structure, a second metal portion forming the first metal-oxide-metal structure, and a first insulating portion separating the first metal portion and the second metal portion of the first metal-oxide-metal structure. In such scenarios according to some examples, forming the second metallization layer may include a third metal portion forming the first metal-oxide-metal structure, a fourth metal portion forming the first metal-oxide-metal structure, and a second insulating portion separating the third and fourth metal portions of the first metal-oxide-metal structure.

[0081] In some aspects, the second capacitor device may include a second metal-oxide-metal structure formed in a first metallization layer, a second metallization layer, or both. In such scenarios according to some examples, forming the first metallization layer may include a first metal portion forming the second metal-oxide-metal structure, a second metal portion forming the second metal-oxide-metal structure, and a first insulating portion separating the first metal portion and the second metal portion of the second metal-oxide-metal structure. In such scenarios according to some examples, forming the second metallization layer may include a third metal portion forming the second metal-oxide-metal structure, a fourth metal portion forming the second metal-oxide-metal structure, and a second insulating portion separating the third metal portion and the fourth metal portion of the second metal-oxide-metal structure.

[0082] In some aspects, the first capacitor device may include a first deep trench capacitor structure formed in a first metallization layer and a substrate. In some aspects, method 400 may further include: forming a first trench in the substrate; forming a first metal portion of the first deep trench capacitor structure in the first trench and extending the first metal portion to an upper surface of the substrate; forming an insulating portion of the first deep trench capacitor structure in the first trench and on the first metal portion; and forming a second metal portion of the first deep trench capacitor structure in the first trench and on the insulating portion. In some aspects, the first metal portion, the insulating portion, and the second metal portion of the first deep trench capacitor structure may be at least partially in the first metallization layer and partially in the substrate.

[0083] In some aspects, the second capacitor device may include a second deep trench capacitor structure formed in the first metallization layer and the substrate. In some aspects, method 400 may further include: forming a second trench in the substrate; forming a first metal portion of the second deep trench capacitor structure in the second trench and extending the first metal portion to an upper surface of the substrate; forming an insulating portion of the second deep trench capacitor structure in the second trench and on the first metal portion; and forming a second metal portion of the second deep trench capacitor structure in the second trench and on the insulating portion. In some aspects, the first metal portion, the insulating portion, and the second metal portion of the second deep trench capacitor structure may be at least partially in the first metallization layer and partially in the substrate.

[0084] The technical advantage of method 400 corresponds to the fabrication of an interposer layer comprising an embedded inductor device coupled between two power nodes in a shared PDN for the same potential, such that switching noise from one circuit block coupled to a power node in the shared PDN can be blocked by the embedded inductor device without affecting the other power node in the shared PDN. Another technical advantage of method 400 corresponds to an interposer layer including an embedded capacitor device, which can increase the stability of the voltage level at the power node for different potentials in the shared PDN across different circuit blocks.

[0085] Figure 5 A mobile device 500 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 500 may be implemented by including one or more IC devices that include an intermediary layer as disclosed herein.

[0086] In some aspects, the mobile device 500 can be configured as a wireless communication device. As shown, the mobile device 500 includes a processor 501. The processor 501 is communicatively coupled to a memory 532 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 500 also includes a display 528 and a display controller 526, wherein the display controller 526 is coupled to the processor 501 and the display 528. The mobile device 500 may include an input device 530 (e.g., a physical or virtual keyboard), a power source 544 (e.g., a battery), a speaker 536, a microphone 538, and a wireless antenna 542. In some aspects, the power source 544 may directly or indirectly provide power supply voltage for some or all of the components of the mobile device 500.

[0087] In some respects, Figure 5 It may include a decoder / decoder (codec) 534 (e.g., an audio and / or voice codec) coupled to processor 501; a speaker 536 and a microphone 538 coupled to codec 534; and a wireless circuit 540 (which may include a modem, RF circuitry, filters, etc.) coupled to wireless antenna 542 and to processor 501.

[0088] In some aspects, one or more of the processor 501 (e.g., SOC, application processor (AP)), display controller 526, memory 532, codec 534, and wireless circuit 540 (e.g., baseband interface) include an IC device packaged as an IC package and include an intermediary layer according to the various aspects described in this disclosure.

[0089] It should be noted that, although Figure 5 Mobile device 500 is described, but similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0090] Figure 6 Various electronic devices 610, 620 and 630 that can be incorporated with IC devices 612, 622 and 632 according to aspects of this disclosure are illustrated, and these IC devices can be packaged as IC packages including an interposer as described herein.

[0091] For example, mobile phone device 610, laptop computer device 620, and fixed-location terminal device 630 can each generally be considered as user equipment (UE) and may include one or more ICs (such as ICs 612, 622, and 632) and a power supply for providing a supply voltage to power the ICs. IC devices 612, 622, and 632 may, for example, correspond to IC devices packaged as IC packages having, based on the above references... Figure 2 and Figures 3A to 3E The example described is an intermediate layer manufactured.

[0092] Figure 6 The devices 610, 620, and 630 illustrated herein are merely non-limiting examples. Other electronic devices may also feature ICs including semiconductor structures as described in this disclosure, including, but not limited to, a group of devices (e.g., electronic devices): mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, laptop computers, access points, base stations, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0093] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0094] Figures 1 to 6 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some specific embodiments, Figures 1 to 6 The corresponding descriptions can be used to manufacture, create, provide, and / or produce integrated devices. In some specific implementations, the devices may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-a-chip (SoC), and stacked-package (PoP) devices, etc.

[0095] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0096] Specific implementation examples are described in the following numbered clauses.

[0097] Clause 1. An interposer comprising: a substrate; a first metallization layer located on the substrate, the first metallization layer having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first metallization layer and the second metallization layer, the via layer having a plurality of vias, wherein: at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer layer, and the second inductor device being electrically coupled between the first power node and a third power node of the interposer layer.

[0098] Clause 2. The interposer layer as described in Clause 1, wherein: the first inductor device comprises: a first helical structure formed in the first metallization layer or the second metallization layer; or a first solenoid structure formed in the first metallization layer, the via layer, and the second metallization layer; and the second inductor device comprises: a second helical structure formed in the first metallization layer or the second metallization layer; or a second solenoid structure formed in the first metallization layer, the via layer, and the second metallization layer.

[0099] Clause 3. The interposer layer according to any one of Clauses 1 to 2, the interposer layer further comprising: a first capacitor device and a second capacitor device, the first capacitor device and the second capacitor device being formed in the substrate, the first metallization layer, the via layer, the second metallization layer or a combination thereof, the first capacitor device being electrically coupled between a second power node and a fourth power node of the interposer layer, and the second capacitor device being electrically coupled between a third power node and a fifth power node of the interposer layer.

[0100] Clause 4. The interposer as described in Clause 3, wherein: the first capacitor device comprises: a first metal-insulator-metal structure formed in the first metallization layer and the via layer; a first metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both; or a first deep trench capacitor structure formed in the first metallization layer and the substrate; and the second capacitor device comprises: a second metal-insulator-metal structure formed in the first metallization layer and the via layer; a second metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both; or a second deep trench capacitor structure formed in the first metallization layer and the substrate.

[0101] Clause 5. An intermediary layer according to any one of Clauses 3 to 4, wherein: the first power node is configured to carry a first supply voltage; and the fourth power node and the fifth power node are configured to carry a second supply voltage different from the first supply voltage or to carry a ground voltage.

[0102] Clause 6. An intermediary layer according to any one of Clauses 1 to 5, wherein: the first power node, the second power node and the third power node are configured for the same direct current (DC) potential.

[0103] Clause 7. A method of manufacturing an interposer, the method comprising: forming a first metallization layer on a substrate, the first metallization layer having a first plurality of conductive patterns; forming a second metallization layer having a second plurality of conductive patterns; and forming a via layer disposed between the first metallization layer and the second metallization layer, the via layer having a plurality of vias, wherein: at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, and the second inductor device being electrically coupled between the first power node and a third power node of the interposer.

[0104] Clause 8. The method according to Clause 7, wherein: the first inductor device comprises: a first helical structure formed in the first metallization layer or the second metallization layer; or a first solenoid structure formed in the first metallization layer, the via layer and the second metallization layer, and the second inductor device comprises: a second helical structure formed in the first metallization layer or the second metallization layer; or a second solenoid structure formed in the first metallization layer, the via layer and the second metallization layer.

[0105] Clause 9. The method according to any one of Clauses 7 to 8, wherein: a first capacitor device and a second capacitor device are formed in the substrate, the first metallization layer, the via layer, the second metallization layer, or a combination thereof, the first capacitor device is electrically coupled between the second power node and the fourth power node of the intermediate layer, and the second capacitor device is electrically coupled between the third power node and the fifth power node of the intermediate layer.

[0106] Clause 10. The method according to Clause 9, wherein: the first capacitor device includes a first metal-insulator-metal structure formed in the first metallization layer and the via layer, forming the first metallization layer includes forming a first metal portion of the first metal-insulator-metal structure, and forming the via layer includes forming an insulating portion of the first metal-insulator-metal structure on the first metal portion and forming a second metal portion on the insulating portion.

[0107] Clause 11. The method according to Clause 9, wherein: the first capacitor device includes a first metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both, and one or both of the following are true: forming the first metallization layer includes forming a first metal portion of the first metal-oxide-metal structure, a second metal portion of the first metal-oxide-metal structure, and a first insulating portion separating the first metal portion and the second metal portion; or forming the second metallization layer includes forming a third metal portion of the first metal-oxide-metal structure, a fourth metal portion of the first metal-oxide-metal structure, and a second insulating portion separating the third metal portion and the fourth metal portion.

[0108] Clause 12. The method according to Clause 9, wherein: the first capacitor device includes a first deep trench capacitor structure formed in the first metallization layer and the substrate, the method further comprising: forming a trench in the substrate; forming a first metal portion of the first deep trench capacitor structure in the trench, the first metal portion extending to an upper surface of the substrate; forming an insulating portion of the first deep trench capacitor structure in the trench and on the first metal portion; forming a second metal portion of the first deep trench capacitor structure in the trench and on the insulating portion, the first metal portion, the insulating portion, and the second metal portion being at least partially in the first metallization layer and partially in the substrate.

[0109] Clause 13. The method according to any one of Clauses 9 to 12, wherein: the first power node is configured to carry a first supply voltage; and the fourth power node and the fifth power node are configured to carry a second supply voltage different from the first supply voltage or to carry a ground voltage.

[0110] Clause 14. The method according to any one of Clauses 7 to 13, wherein: the first power node, the second power node and the third power node are configured for the same direct current (DC) potential.

[0111] Clause 15. An integrated circuit (IC) package comprising: an interposer including: a substrate; a first metallization layer located on the substrate, the first metallization layer having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first metallization layer and the second metallization layer, the via layer having a plurality of vias, a first IC die mounted on the interposer, the first IC die including a first circuit block and a second circuit block, wherein at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, the second inductor device being electrically coupled between the first power node and a third power node of the interposer, the first circuit block including a first power terminal electrically coupled to the second power node of the interposer, and the second circuit block including a second power node electrically coupled to the third power node of the interposer.

[0112] Clause 16. The IC package according to Clause 15, wherein: the first inductor device comprises: a first spiral inductor having a first spiral structure formed in the first metallization layer or the second metallization layer; or a first solenoid structure having a first conductive pattern in the first metallization layer, a first via in the via layer, and a second conductive pattern in the second metallization layer connected to a coil winding of the first solenoid structure; and the second inductor device comprises: a second spiral inductor having a second spiral structure formed in the first metallization layer or the second metallization layer; or a second solenoid structure having a third conductive pattern in the first metallization layer, a second via in the via layer, and a fourth conductive pattern in the second metallization layer connected to a coil winding of the second solenoid structure.

[0113] Clause 17. An IC package according to any one of Clauses 15 to 16, wherein: a first capacitor device and a second capacitor device are formed in the substrate, the first metallization layer, the via layer, the second metallization layer, or a combination thereof in the interposer layer; the first capacitor device is electrically coupled between a second power node and a fourth power node in the interposer layer; the second capacitor device is electrically coupled between a third power node and a fifth power node in the interposer layer; the first circuit block includes a third power terminal electrically coupled to the fourth power node in the interposer layer; and the second circuit block includes a fourth power node electrically coupled to the fifth power node in the interposer layer.

[0114] Clause 18. The IC package according to Clause 17, wherein: the first capacitor device includes: a first metal-insulator-metal structure formed in the first metallization layer and the via layer; a first metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both; or a first deep trench capacitor structure formed in the first metallization layer and the substrate; and the second capacitor device includes: a second metal-insulator-metal structure formed in the first metallization layer and the via layer; a second metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both; or a second deep trench capacitor structure formed in the first metallization layer and the substrate.

[0115] Clause 19. An IC package according to any one of Clauses 17 to 18, wherein: the first power node is configured to carry a first supply voltage; and the fourth power node and the fifth power node are configured to carry a second supply voltage different from the first supply voltage or to carry a ground voltage.

[0116] Clause 20. An IC package according to any one of Clauses 17 to 19, the IC package further comprising: a second IC die, the interposer being mounted on the second IC die, wherein: the interposer includes a first set of conductive structures forming the first power node, a second set of conductive structures forming the fourth power node, and a third set of conductive structures forming the fifth power node, and the second IC die includes: a first through-substrate via (TSV) electrically coupled to the first set of conductive structures; a second TSV electrically coupled to the second set of conductive structures; and a third TSV electrically coupled to the third set of conductive structures.

[0117] Clause 21. An IC package according to any one of Clauses 15 to 20, wherein: the first power node, the second power node and the third power node are configured for the same direct current (DC) potential.

[0118] Clause 22. An electronic device comprising: an integrated circuit (IC) package, the IC package including: an interposer including: a substrate; a first metallization layer located on the substrate, the first metallization layer having a first plurality of conductive patterns; a second metallization layer having a second plurality of conductive patterns; and a via layer disposed between the first metallization layer and the second metallization layer, the via layer having a plurality of vias, a first IC die mounted on the interposer, the first IC die including a first circuit block and a second circuit block, wherein at least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device, the first inductor device being electrically coupled between a first power node and a second power node of the interposer, the second inductor device being electrically coupled between the first power node and a third power node of the interposer, the first circuit block including a first power terminal electrically coupled to the second power node of the interposer, and the second circuit block including a second power node electrically coupled to the third power node of the interposer.

[0119] Clause 23. The electronic device according to Clause 22, wherein: the first inductor device comprises: a first helical inductor having a first helical structure formed in the first metallization layer or the second metallization layer; or a first solenoid structure having a first conductive pattern in the first metallization layer, a first via in the via layer, and a second conductive pattern in the second metallization layer connected to a coil winding of the first solenoid structure; and the second inductor device comprises: a second helical inductor having a second helical structure formed in the first metallization layer or the second metallization layer; or a second solenoid structure having a third conductive pattern in the first metallization layer, a second via in the via layer, and a fourth conductive pattern in the second metallization layer connected to a coil winding of the second solenoid structure.

[0120] Clause 24. An electronic device according to any one of Clauses 22 to 23, wherein: a first capacitor device and a second capacitor device are formed in the substrate, the first metallization layer, the via layer, the second metallization layer, or a combination thereof, of the interposer layer; the first capacitor device is electrically coupled between a second power node and a fourth power node of the interposer layer; the second capacitor device is electrically coupled between a third power node and a fifth power node of the interposer layer; the first circuit block has a third power terminal electrically coupled to the fourth power node of the interposer layer; and the second circuit block has a fourth power node electrically coupled to the fifth power node of the interposer layer.

[0121] Clause 25. The electronic device according to Clause 24, wherein: the first capacitor device comprises: a first metal-insulator-metal structure formed in the first metallization layer and the via layer; a first metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both; or a first deep trench capacitor structure formed in the first metallization layer and the substrate; and the second capacitor device comprises: a second metal-insulator-metal structure formed in the first metallization layer and the via layer; a second metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both; or a second deep trench capacitor structure formed in the first metallization layer and the substrate.

[0122] Clause 26. An electronic device according to any one of Clauses 24 to 25, wherein: the first power node is configured to carry a first supply voltage; and the fourth power node and the fifth power node are configured to carry a second supply voltage different from the first supply voltage or to carry a ground voltage.

[0123] Clause 27. An electronic device according to any one of Clauses 24 to 26, wherein the IC package further comprises: a second IC die, the interposer being mounted on the second IC die, wherein: the interposer includes a first set of conductive structures forming the first power node, a second set of conductive structures forming the fourth power node, and a third set of conductive structures forming the fifth power node, and the second IC die includes: a first through-substrate via (TSV) electrically coupled to the first set of conductive structures; a second TSV electrically coupled to the second set of conductive structures; and a third TSV electrically coupled to the third set of conductive structures.

[0124] Clause 28. An electronic device according to any one of Clauses 22 to 27, wherein: the first power node, the second power node and the third power node are configured for the same direct current (DC) potential.

[0125] Clause 29. An electronic device pursuant to any one of Clauses 22 to 28, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

[0126] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0127] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0128] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic elements, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0129] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0130] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0131] Furthermore, as used herein, the terms “set,” “group,” etc., are intended to include one or more of the elements. Additionally, as used herein, the terms “having,” “comprising,” “including,” etc., do not exclude the presence of one or more additional elements (e.g., element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Moreover, as used herein, the term “or” is intended to be open-ended when used in a series and may be used interchangeably with “and / or” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one”), or these alternatives are mutually exclusive (e.g., “one or more” should not be interpreted as “one and more”). Furthermore, although components, functions, actions, and instructions may be described or claimed in the singular form, the plural form may also be considered unless explicitly stated as limited to the singular. Therefore, as used herein, the articles “a,” “an,” “the,” and “the” are intended to include one or more of the elements. Additionally, as used herein, the terms “at least one” and “one or more” include performing or being able to perform “one” component, function, action or instruction of the described or claimed functionality, and also include performing or being able to perform “two or more” components, functions, actions or instructions of the described or claimed functionality in combination.

[0132] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, no component, function, action, or instruction described or claimed herein should be construed as critical or essential unless expressly stated otherwise.

Claims

1. An intermediary layer, the intermediary layer comprising: substrate; A first metallization layer is located on the substrate and has a first plurality of conductive patterns. A second metallization layer having a second plurality of conductive patterns; and A via layer is disposed between the first metallization layer and the second metallization layer, and the via layer has a plurality of vias. in: At least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device. The first inductor device is electrically coupled between the first power node and the second power node of the interposer layer, and The second inductor device is electrically coupled between the first power node and the third power node of the interposer layer.

2. The intermediary layer according to claim 1, wherein: The first inductor device includes: A first helical structure is formed in the first metallization layer or the second metallization layer; or A first solenoid structure is formed in the first metallization layer, the via layer, and the second metallization layer, and The second inductor device includes: A second helical structure is formed in the first metallization layer or the second metallization layer; or A second solenoid structure is formed in the first metallization layer, the via layer, and the second metallization layer.

3. The intermediary layer according to claim 1, further comprising: A first capacitor device and a second capacitor device are formed in the substrate, the first metallization layer, the via layer, the second metallization layer, or a combination thereof. The first capacitor device is electrically coupled between the second and fourth power nodes of the intermediate layer, and The second capacitor device is electrically coupled between the third power node and the fifth power node in the intermediate layer.

4. The intermediary layer according to claim 3, wherein: The first capacitor device includes: A first metal-insulator-metal structure is formed in the first metallization layer and the via layer; A first metal-oxide-metal structure is formed in the first metallization layer, the second metallization layer, or both; or A first deep trench capacitor structure is formed in the first metallization layer and the substrate; and The second capacitor device includes: A second metal-insulator-metal structure is formed in the first metallization layer and the via layer; A second metal-oxide-metal structure is formed in the first metallization layer, the second metallization layer, or both; or A second deep trench capacitor structure is formed in the first metallization layer and the substrate.

5. The intermediary layer according to claim 3, wherein: The first power node is configured to carry a first supply voltage; and The fourth power node and the fifth power node are configured to carry a second power supply voltage that is different from the first power supply voltage or to carry a ground voltage.

6. The intermediary layer according to claim 1, wherein: The first power node, the second power node, and the third power node are configured for the same direct current (DC) potential.

7. A method for manufacturing an intermediary layer, the method comprising: A first metallization layer is formed on a substrate, the first metallization layer having a first plurality of conductive patterns; A second metallization layer is formed, the second metallization layer having a second plurality of conductive patterns; as well as A via layer is formed, wherein the via layer is disposed between the first metallization layer and the second metallization layer, and the via layer has a plurality of vias. in: At least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device. The first inductor device is electrically coupled between the first power node and the second power node of the interposer layer, and The second inductor device is electrically coupled between the first power node and the third power node of the interposer layer.

8. The method according to claim 7, wherein: The first inductor device includes: A first helical structure is formed in the first metallization layer or the second metallization layer; or A first solenoid structure is formed in the first metallization layer, the via layer, and the second metallization layer, and The second inductor device includes: A second helical structure is formed in the first metallization layer or the second metallization layer; or A second solenoid structure is formed in the first metallization layer, the via layer, and the second metallization layer.

9. The method according to claim 7, wherein: A first capacitor device and a second capacitor device are formed in the substrate, the first metallization layer, the via layer, the second metallization layer, or a combination thereof. The first capacitor device is electrically coupled between the second and fourth power nodes of the intermediate layer, and The second capacitor device is electrically coupled between the third power node and the fifth power node in the intermediate layer.

10. The method according to claim 9, wherein: The first capacitor device includes a first metal-insulator-metal structure formed in the first metallization layer and the via layer. Forming the first metallization layer includes forming a first metal portion of the first metal-insulator-metal structure, and Forming the via layer includes forming an insulating portion of the first metal-insulator-metal structure on the first metal portion and forming a second metal portion on the insulating portion.

11. The method of claim 9, wherein: The first capacitor device includes a first metal-oxide-metal structure formed in the first metallization layer, the second metallization layer, or both, and One or both of the following are true: Forming the first metallization layer includes forming a first metal portion of the first metal-oxide-metal structure, a second metal portion of the first metal-oxide-metal structure, and a first insulating portion separating the first metal portion and the second metal portion, or Forming the second metallization layer includes forming a third metal portion of the first metal-oxide-metal structure, a fourth metal portion of the first metal-oxide-metal structure, and a second insulating portion separating the third metal portion and the fourth metal portion.

12. The method according to claim 9, wherein: The first capacitor device includes a first deep trench capacitor structure formed in the first metallization layer and the substrate. The method further includes: Trenches are formed in the substrate; A first metal portion of the first deep trench capacitor structure is formed in the trench, and the first metal portion extends to the upper surface of the substrate; An insulating portion of the first deep trench capacitor structure is formed in the trench and on the first metal portion; A second metal portion of the first deep trench capacitor structure is formed in the trench and on the insulating portion. The first metal portion, the insulating portion, and the second metal portion are at least partially in the first metallization layer and partially in the substrate.

13. The method according to claim 9, wherein: The first power node is configured to carry a first supply voltage; and The fourth power node and the fifth power node are configured to carry a second power supply voltage that is different from the first power supply voltage or to carry a ground voltage.

14. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: Intermediary layer, the intermediary layer comprising: substrate; A first metallization layer is located on the substrate and has a first plurality of conductive patterns. A second metallization layer having a second plurality of conductive patterns; and A via layer is disposed between the first metallization layer and the second metallization layer, and the via layer has a plurality of vias. The first IC die is mounted on the interposer layer and includes a first circuit block and a second circuit block. in At least a portion of the first plurality of conductive patterns, a portion of the second plurality of conductive patterns, or both are configured to form a first inductor device and a second inductor device. The first inductor device is electrically coupled between the first power node and the second power node of the interposer layer. The second inductor device is electrically coupled between the first power node and the third power node of the interposer layer. The first circuit block includes a first power terminal electrically coupled to the second power node of the intermediate layer, and The second circuit block includes a second power node electrically coupled to the third power node of the intermediate layer.

15. The IC package according to claim 14, wherein: The first inductor device includes: A first spiral inductor, the first spiral inductor having a first spiral structure formed in the first metallization layer or the second metallization layer; or A first solenoid structure has a first conductive pattern in a first metallization layer connected to a coil winding of the first solenoid structure, a first via in the via layer, and a second conductive pattern in a second metallization layer. The second inductor device includes: A second spiral inductor, the second spiral inductor having a second spiral structure formed in the first metallization layer or the second metallization layer; or The second solenoid structure has a third conductive pattern in the first metallization layer connected to the coil winding of the second solenoid structure, a second via in the via layer, and a fourth conductive pattern in the second metallization layer.

16. The IC package according to claim 14, wherein: A first capacitor device and a second capacitor device are formed in the substrate of the intermediate layer, the first metallization layer, the via layer, the second metallization layer, or a combination thereof. The first capacitor device is electrically coupled between the second power node and the fourth power node of the intermediate layer. The second capacitor device is electrically coupled between the third and fifth power nodes of the intermediate layer. The first circuit block includes a third power terminal electrically coupled to the fourth power node of the intermediate layer, and The second circuit block includes a fourth power node electrically coupled to the fifth power node of the intermediate layer.

17. The IC package according to claim 16, wherein: The first capacitor device includes: A first metal-insulator-metal structure is formed in the first metallization layer and the via layer; A first metal-oxide-metal structure is formed in the first metallization layer, the second metallization layer, or both; or A first deep trench capacitor structure is formed in the first metallization layer and the substrate; and The second capacitor device includes: A second metal-insulator-metal structure is formed in the first metallization layer and the via layer; A second metal-oxide-metal structure is formed in the first metallization layer, the second metallization layer, or both; or A second deep trench capacitor structure is formed in the first metallization layer and the substrate.

18. The IC package of claim 16, wherein: The first power node is configured to carry a first supply voltage; and The fourth power node and the fifth power node are configured to carry a second power supply voltage that is different from the first power supply voltage or to carry a ground voltage.

19. The IC package according to claim 16, further comprising: The second IC die, wherein the interposer layer is mounted on the second IC die. in: The intermediate layer includes a first set of conductive structures forming the first power node, a second set of conductive structures forming the fourth power node, and a third set of conductive structures forming the fifth power node. The second IC die includes: A first through-substrate via (TSV) is electrically coupled to the first set of conductive structures; The second TSV is electrically coupled to the second set of conductive structures; and The third TSV is electrically coupled to the third set of conductive structures.

20. The IC package according to claim 14, wherein: The first power node, the second power node, and the third power node are configured for the same direct current (DC) potential.

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