An output current noise characterization method considering load-side parasitic parameters
By constructing equivalent models and small-signal equivalent models of load-side parasitic parameters, the problem of difficult characterization of DBSHPA load-side output current noise is solved, achieving high-precision output current noise analysis and improving the design accuracy and predictability of motor drive systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NORTHEAST FORESTRY UNIV
- Filing Date
- 2026-04-30
- Publication Date
- 2026-07-03
AI Technical Summary
In the prior art, it is difficult to accurately model and quantitatively characterize the output current noise on the load side of the dual buck symmetrical half-bridge power amplifier (DBSHPA). Especially under high-frequency switching conditions, the influence of parasitic parameters on the load side is not fully considered, resulting in increased output current noise and waveform distortion.
An equivalent model of the parasitic parameters on the load side is constructed. Combined with the parasitic parameters on the bridge arm side, a unified small-signal equivalent model is established. The expression for the output current is derived, revealing the mechanism of voltage oscillation at the switching node being conducted to the output side. The output current characteristics are analyzed through theoretical simulation.
This method enables accurate characterization of the output current noise propagation path and mechanism without increasing the switching frequency or introducing additional hardware, improving the accuracy and predictability of power amplifier output current analysis and providing theoretical support for noise optimization design of high-precision motor drive systems.
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Abstract
Description
Technical Field
[0001] This invention relates to a method for characterizing output current noise considering load-side parasitic parameters, belonging to the field of power supply and motor drive technology. Background Technology
[0002] In the field of high-precision power supplies and motor drives, dual buck symmetrical half-bridge power amplifiers (DBSHPAs) are widely used in ultra-precision motor drives and precision positioning systems due to their excellent low-distortion output characteristics and absence of dead-time effects. With the introduction of wide-bandgap power devices, such as GaN HEMTs, the switching frequency of power amplifiers has been significantly increased, effectively improving the system's dynamic response speed and power density. However, as the switching frequency increases to hundreds of kHz or even higher frequencies, high-frequency transient oscillations inevitably occur during device switching, causing the switching node voltage to deviate from the ideal rectangular wave, thus becoming one of the important factors affecting the system's output performance.
[0003] Existing research on modeling switching transient processes primarily focuses on the power devices on the bridge arm side and their parasitic parameters, such as parasitic inductance, parasitic capacitance, and drive circuit characteristics. The load-side filter inductor is typically treated as an ideal inductor or a constant current source to simplify the analysis model. However, in real-world systems, the filter inductor and motor windings inevitably introduce parasitic capacitance due to their structural distribution characteristics and coupling effects, resulting in a non-ideal parametric structure on the load side containing parasitic capacitance. Under high-frequency switching conditions, this equivalent parametric structure exhibits significant frequency-dependent impedance characteristics, making it easier for high-frequency oscillations of switching transients to propagate to the load side and form noise current components at the output, thus increasing high-frequency noise in the output current and exacerbating waveform distortion. Summary of the Invention
[0004] The purpose of this invention is to solve the problem that the output current noise on the load side of the dual buck symmetrical half-bridge power amplifier (DBSHPA) is difficult to accurately model and quantitatively characterize, and to provide a method for characterizing output current noise that takes into account load-side parasitic parameters.
[0005] The objective of this invention is achieved through the following technical solution:
[0006] A method for characterizing output current noise considering load-side parasitic parameters includes the following steps:
[0007] Step 1: Construct an equivalent model of the parasitic capacitance of the filter inductor and the motor inductor to characterize the non-ideal impedance characteristics of the load side under high-frequency conditions;
[0008] Step 2: Establish a unified small-signal equivalent model that includes parasitic parameters on the bridge arm side and parasitic parameters on the load side. Combine the parasitic capacitance equivalent model in Step 1 to derive the output current expression. Reveal the intrinsic mechanism by which voltage oscillations at the switching node are conducted to the output side through the parasitic capacitance network and introduce current noise from the mechanism level.
[0009] Step 3: Analyze the influence of theoretical simulation on the output current characteristics.
[0010] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0011] The innovative approach of this invention considers the modeling errors caused by parasitic parameters on the motor load side, thereby avoiding the modeling errors caused by treating the load side as an ideal component in traditional methods. Without increasing the switching frequency or introducing additional hardware, it achieves accurate characterization of the noise propagation path and mechanism of the output current, improving the accuracy and predictability of the power amplifier output current analysis, and providing theoretical basis and methodological support for the noise optimization design of high-precision motor drive systems. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the parasitic capacitance between the winding and the magnetic core.
[0013] Figure 2 This is a schematic diagram of the parasitic capacitance between windings.
[0014] Figure 3 This is a schematic diagram of the DBSHPA high-frequency equivalent circuit model; where:
[0015] Figure 3 (a) is the equivalent circuit diagram of the DBSHPA during the turn-on oscillation phase;
[0016] Figure 3 (b) is the equivalent circuit diagram of the DBSHPA during the turn-off oscillation stage.
[0017] Figure 4 The diagram shows the equivalent circuit models of bridge arm I and bridge arm II; where:
[0018] Figure 4 (a) Bridge arm I A schematic diagram illustrating the opening phase;
[0019] Figure 4 (b) Bridge Arm II A schematic diagram of the opening phase.
[0020] Figure 5 The diagram shows the equivalent circuit model of the turn-off of bridge arm I and bridge arm II; where:
[0021] Figure 5(a) Schematic diagram of the equivalent circuit model of bridge arm I being turned off;
[0022] Figure 5 (b) Schematic diagram of the equivalent circuit model of bridge arm II being turned off.
[0023] Figure 6 This is a schematic diagram illustrating the change in output current amplitude under varying parasitic parameters; where:
[0024] Figure 6 (a) is a schematic diagram showing the changes in parasitic capacitance and parasitic inductance on the load side;
[0025] Figure 6 (b) is a schematic diagram of the parasitic capacitance changes of GaN HEMT and diode.
[0026] Figure 7 This is a schematic diagram of the voltage waveform at the switching node of bridge arm I; where:
[0027] Figure 7 (a) is off node voltage Waveform diagram;
[0028] Figure 7 (b) for activation node voltage Waveform diagram.
[0029] Figure 8 Parasitic capacitance on the load side A schematic diagram of the changing output current.
[0030] Figure 9 For the change of parasitic capacitance on the load side Amplitude comparison diagram.
[0031] Figure 10 To consider inductor parasitic capacitance A schematic diagram of the switch-off voltage waveform; where:
[0032] Figure 10 (a) is Turn-off voltage during change Waveform diagram;
[0033] Figure 10 (b) is Turn-off voltage during change Waveform diagram.
[0034] Figure 11 To disregard inductance parasitic capacitance A schematic diagram of the switch-off voltage waveform; where:
[0035] Figure 11 (a) is Turn-off voltage during change Waveform diagram;
[0036] Figure 11 (b) is Turn-off voltage during change Waveform diagram. Detailed Implementation
[0037] The present invention will be further described in detail below with reference to the accompanying drawings: This embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation methods are given, but the protection scope of the present invention is not limited to the following embodiments.
[0038] like Figures 1 to 11 As shown, the output current noise characterization method considering load-side parasitic parameters involved in this embodiment includes the following steps:
[0039] 1. Modeling of parasitic parameters on the load side
[0040] In DBSHPA, although the functions of filter inductors and motor inductors differ, both are composed of conductive windings and magnetic cores, and their parasitic capacitance formation principles are the same. Therefore, under high-frequency conditions, the load-side inductance can be reduced to the parasitic capacitance between the winding and the magnetic core, as well as between the turns of the winding. Thus, simplifying both types of inductors to the same parasitic capacitance equivalent model, the parasitic capacitance of their load-side inductance can generally be divided into the capacitance between the winding and the magnetic core. Parasitic capacitance between windings .
[0041] Assuming all conductors in the winding have the same potential and are at the same distance from the core, then the capacitance between the winding and the core is... ,like Figure 1 As shown, this is equivalent to a lumped-parameter capacitor. Its value depends on the dielectric constant of the insulating material, the relative areas of the winding and the core, and the distance between them.
[0042] Under the above assumptions, the capacitance between the winding and the core... The capacitance can be approximated as that of a parallel plate capacitor, as shown in equation (1).
[0043]
[0044]
[0045] in, The vacuum permittivity, The relative permittivity of the insulating material, This represents the equivalent interaction area between the winding and the magnetic core. This is the equivalent spacing between the winding and the magnetic core. This indicates the distance between the bare copper layers of the two windings. and These are the conductor diameters before and after the winding insulation, respectively. The distance between the bare copper of two turns of the winding. This refers to the winding insulation thickness.
[0046] like Figure 2 As shown, This refers to the diameter of the conductor under winding insulation conditions. The diameter of the bare copper. The calculation in the text divides the spacing between adjacent windings into the distance between the bare copper of two turns of winding and the bare copper of the winding itself. .
[0047] Parasitic capacitance inevitably forms between two adjacent windings due to the coupling effect of the electric field. Since the windings are continuously distributed along the axis, the parasitic capacitance between the windings... It can be equivalent to multiple capacitors connected in series, such as Figure 2 As shown, The above-mentioned multiple capacitors are represented as parasitic capacitances between adjacent windings, with adjacent capacitors connected in series. To simplify the model, they are unified as follows: express.
[0048] Overall, the parasitic capacitance between windings is much smaller than that between the windings and the core. Therefore, the inter-winding capacitance is not modeled in detail during the modeling and analysis process.
[0049] 2. Mechanism Analysis of DBSHPA Switch Transient Oscillation on Load Output Characteristics
[0050] A high-frequency switching transient model based on DBSHPA is presented, which comprehensively considers the motor load model and the parasitic parameters of devices and circuits. The equivalent circuit during the turn-on and turn-off transient processes is shown below. Figure 3 As shown. The model includes the DC bus voltage. and Gate drive voltage Parasitic capacitance of switching devices ( Diode junction capacitance PCB parasitic capacitance Parasitic inductance ( and gate resistor It also includes inductance and load-related variables. Indicates parasitic resistance. This represents the load resistance. To simplify high-frequency transient analysis, the filter inductance and motor inductance are considered equivalent to parasitic capacitance. The analysis focuses on the parasitic capacitance coupling introduced by the filter inductor and motor inductance under high-frequency switching conditions. This type of parasitic parameter actively participates in the transient process and causes voltage oscillations at the switching node. During the analysis, the switching devices... and It remains in a conductive state at all times, while and Synchronous switch.
[0051] The switching node voltage is mainly determined by the parasitic parameters in the corresponding bridge arm branch. The following section discusses the switching node voltage. and The analysis only considers parasitic elements within each bridge arm branch. Based on Figure 3 (a) shows the opening-through oscillation model, from which equivalent models of bridge arm I and bridge arm II are obtained, as follows: Figure 4 As shown.
[0052] In switching devices Drain-source capacitance before the oscillation phase Discharge is completed at both ends, therefore only the gate circuit and the switching device are present. The on-resistance of the switching device The oscillation phase, such as Figure 4 (a) Equivalent impedance at this stage As shown in equation (3).
[0053]
[0054] in, The on-resistance of the switching device. For switch The drive on-resistance, Switching devices The resonant frequency of the oscillation. For switch Gate parasitic inductance, For switch Input capacitance;
[0055] Due to switching devices The switching device is always in the conducting phase, therefore Equivalent impedance during the oscillation phase As shown in equation (4), The resonant frequency is given by equation (5):
[0056]
[0057]
[0058] in, This is the diode junction capacitance. Parasitic capacitance, For parasitic inductance, For switch The drive on-resistance, Switching devices The resonant frequency of the oscillation. For switch Gate parasitic inductance, For switch Input capacitance;
[0059] When switching devices In conduction and diode When shut down, Figure 4 The loop shown in (a) can be approximated as a second-order oscillating network. Energy exchange occurs between the parasitic inductance of the loop and the node capacitance. KVL and KCL equations are written for this network along the closed path, and the switching node voltage during the opening process of bridge arm I is derived. The time-domain expression is shown in equation (6).
[0060]
[0061] in, For parasitic inductance, for Resonance time, for The voltage across the terminals rises to time; The abbreviations used to reduce the length of formula (6) have no practical significance;
[0062] Similarly, due to switching devices It has been in the conduction phase, such as Figure 4 (b), therefore switching devices Equivalent impedance during the oscillation phase For equation (7), For equation (8):
[0063]
[0064]
[0065] in, For switch The drive on-resistance, Switching devices The resonant frequency of the oscillation. For switch Gate parasitic inductance, For switch Input capacitance, For switch The drive on-resistance, For switch Gate parasitic inductance, For switch Input capacitance;
[0066] Switching node voltage during the opening process of bridge arm II The time-domain expression is shown in equation (9).
[0067]
[0068] in, For parasitic inductance, This is the diode junction capacitance. The equivalent resistance for oscillation of bridge arm II is set. Node voltage in the on state time, for Opening time; The abbreviations used to reduce the length of formula (9) have no practical significance;
[0069] according to Figure 5 (a) Obtaining the equivalent model of the turn-off process for the switching device of bridge arm I. Equivalent impedance during the turn-off oscillation phase For example, equation (10). Equation (11) is given, and the turn-off resonant frequency is given by Equation (12).
[0070]
[0071]
[0072]
[0073] Obtain the switching node voltage during the turn-off phase of bridge arm I. As in equation (13).
[0074]
[0075]
[0076] in, The equivalent resistance for the turn-off oscillation of bridge arm I. The abbreviations used to reduce the length of formula (13) have no practical significance. for Time, For switch Shutdown time;
[0077] switch High-frequency equivalent models such as Figure 5 (b) Equivalent impedance during the turn-off oscillation phase and Equation (15).
[0078]
[0079] Switching node voltage during the turn-off phase of bridge arm II As in equation (16).
[0080]
[0081] in, The equivalent resistance for the turn-off oscillation of bridge arm II. for Time; The abbreviations used to reduce the length of formula (16) have no practical significance;
[0082] The switching node voltage is obtained from formulas (6) and (13). The expression is as shown in equation (17):
[0083]
[0084] The switching node voltage is obtained from formulas (9) and (16). The expression is as shown in equation (18):
[0085]
[0086] Combining formulas (1), (17), and (18), the mathematical expression for the output current under small-signal conditions considering parasitic parameters on the bridge arm side and load side is derived as shown in formula (19), as follows:
[0087]
[0088] in, For containing Parameter-dependent high-order polynomials in the complex frequency domain, This is the equivalent parasitic capacitance. The equivalent impedance of loop I in the small-signal model. This is the equivalent impedance of loop II in the small-signal model. For filtering inductors, For load resistance, For load inductance, This is the representation method in the complex frequency domain.
[0089] 3. Analysis of the impact of DBSHPA load-side parasitic parameters on output and transient characteristics
[0090] (1) The influence of load-side parasitic parameters on the output characteristics of dual buck power amplifiers
[0091] like Figure 6 As shown in (a), increasing parasitic inductance This will increase the energy storage capacity of each bridge arm branch, exacerbating the oscillation amplitude of the output current. It will also increase parasitic capacitance. This provides a path for the transmission of switching transient oscillations to the output, causing the noise in the output current to vary. It increases as it increases. Figure 6 (b) Demonstrating the parasitic capacitance of GaN HEMT With diode junction capacitance The effect of changes on the output current amplitude and Both indirectly affect the output current by influencing the oscillation frequency of the switching node voltage.
[0092] By changing the parasitic capacitance To simulate the switching node voltage under different operating conditions, such as Figure 7 As shown, the output current varies with the parasitic capacitance. like Figure 8 As shown. Increase parasitic capacitance. Switching node voltages during turn-on and turn-off phases All of these increase accordingly. During the activation phase, compared to the initial overshoot, The overshoot increased by approximately 12% during the shutdown phase. The overshoot increases by approximately 8%. The overshoot of the output current changes by approximately 1.3%, while the theoretically calculated overshoot of the output current is 2.8%. The difference between the two is small, and their trends are consistent.
[0093] Switching oscillation current Frequency domain waveforms under different parasitic capacitances on the load side are as follows: Figure 9 As shown. With the parasitic capacitance of the motor... As the frequency increases, the bridge arm resonant frequency shifts to the left, decreasing from 30MHz to 28MHz, and the amplitude of the switching oscillation current near the resonant frequency increases.
[0094] (2) The influence of load-side parasitic parameters on the transient state of GaN HEMT switching
[0095] Figure 10 To take parasitic capacitance into account At that time, the parasitic inductance of bridge arm I and GaN HEMT switches The effect of turn-off voltage. Parasitic inductance. When the voltage at the switching node changes, The overshoot increase is approximately 1.6%. Parasitic inductance. When the voltage at the switching node changes, The overshoot increase is approximately 4%. If the parasitic capacitance of the load inductance is ignored... Switching node voltage The overshoot increase was 1.6% for all cases. Figure 11 As shown. Therefore, when optimizing parasitic parameters, the parasitic inductance that forms a resonant circuit with the load capacitance should be optimized first.
[0096] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method of output current noise characterization considering load side parasitic parameters, comprising: Includes the following steps: Step 1: Construct an equivalent model of the parasitic capacitance of the filter inductor and the motor inductor to characterize the non-ideal impedance characteristics of the load side under high-frequency conditions; Step 2: Establish a unified small-signal equivalent model that includes parasitic parameters on the bridge arm side and parasitic parameters on the load side. Combine the parasitic capacitance equivalent model in Step 1 to derive the output current expression. Reveal the intrinsic mechanism by which voltage oscillations at the switching node are conducted to the output side through the parasitic capacitance network and introduce current noise from the mechanism level. Step 3: Analyze the influence of theoretical simulation on the output current characteristics.
2. The output current noise characterization method considering load side parasitic parameters according to claim 1, wherein, The specific method for constructing the parasitic capacitance equivalent model of the filter inductor and the motor inductor in step one is as follows: Both filter inductors and motor inductors consist of conductive windings and magnetic cores. Under high-frequency conditions, filter inductors and motor inductors can be simplified to the same parasitic capacitance equivalent model, where the parasitic capacitance of the load-side inductor is the capacitance between the windings and the magnetic core. Assuming all conductors in the winding have the same potential and are at the same distance from the core, the capacitance between the winding and the core... The capacitance can be approximated as that of a parallel-plate capacitor as shown in equation (1). in, The vacuum permittivity, The relative permittivity of the insulating material, This represents the equivalent interaction area between the winding and the magnetic core. This is the equivalent spacing between the winding and the magnetic core. This indicates the distance between the bare copper layers of the two windings. This refers to the diameter of the conductor under winding insulation conditions. The distance between the bare copper of two turns of the winding. This refers to the winding insulation thickness.
3. The method for characterizing output current noise considering load-side parasitic parameters according to claim 2, characterized in that, The specific steps for establishing a unified small-signal equivalent model, including parasitic parameters on the bridge arm side and parasitic parameters on the load side, in step two are as follows: A high-frequency switching transient model based on DBSHPA, the model including DC bus voltage and Gate drive voltage Parasitic capacitance of switching devices Diode junction capacitance PCB parasitic capacitance Parasitic inductance and gate resistor It also includes inductance and load-related variables, among which, Indicates parasitic resistance. The load resistance, filter inductance, and motor inductance are considered equivalent to parasitic capacitance. This paper analyzes the parasitic capacitance coupling effect introduced by the filter inductor and the motor inductor under high-frequency switching conditions. This parasitic parameter actively participates in the transient process and causes voltage oscillation at the switching node. During the analysis, the switching devices... and It remains in a conductive state at all times, while and Synchronous switch; For switching node voltage and The analysis only considers the parasitic elements inside each bridge arm branch. Based on the opening process oscillation model, the equivalent models of bridge arm I and bridge arm II are obtained. In switching devices Drain-source capacitance before the oscillation phase Discharge is completed at both ends, therefore only the gate circuit and the switching device are present. The on-resistance of the switching device During the oscillation phase, the equivalent impedance in this phase As shown in equation (3); in, The on-resistance of the switching device. For switch The drive on-resistance, Switching devices The resonant frequency of the oscillation. For switch Gate parasitic inductance, For switch Input capacitance; Due to switching devices The switching device is always in the conducting phase, therefore Equivalent impedance during the oscillation phase As shown in equation (4), The resonant frequency is given by equation (5): in, This is the diode junction capacitance. Parasitic capacitance, For parasitic inductance, For switch The drive on-resistance, Switching devices The resonant frequency of the oscillation. For switch Gate parasitic inductance, For switch Input capacitance; When switching devices In conduction and diode When turned off, the loop of bridge arm I approximates a second-order oscillating network. Energy exchange occurs between the parasitic inductance of the loop and the node capacitance. KVL and KCL equations are written for this network along the closed path, deriving the switching node voltage during the turn-on process of bridge arm I. The time-domain expression is shown in equation (6); in, For parasitic inductance, for Resonance time, for The voltage across the terminals rises to time; Similarly, due to switching devices The switching device is always in the conducting phase, therefore Equivalent impedance during the oscillation phase For equation (7), For equation (8): in, For switch The drive on-resistance, Switching devices The resonant frequency of the oscillation. For switch Gate parasitic inductance, For switch Input capacitance, For switch The drive on-resistance, For switch Gate parasitic inductance, For switch Input capacitance; Switching node voltage during the opening process of bridge arm II The time-domain expression is shown in equation (9); in, For parasitic inductance, This is the diode junction capacitance. The equivalent resistance for oscillation of bridge arm II is set. Node voltage in the on state time, for Opening time; The switching devices of bridge arm I are obtained based on the equivalent model of the turn-off process. Equivalent impedance during the turn-off oscillation phase For example, equation (10). Equation (11) is given, and the turn-off resonant frequency is given by equation (12). Obtain the switching node voltage during the turn-off phase of bridge arm I. As in equation (13); in, The equivalent resistance for the turn-off oscillation of bridge arm I. for Time, For switch Shutdown time; switch Equivalent impedance during the turn-off oscillation phase of the high-frequency equivalent model and For example, equation (15); Switching node voltage during the turn-off phase of bridge arm II As in equation (16); in, The equivalent resistance for the turn-off oscillation of bridge arm II. for Time; The switching node voltage is obtained from formulas (6) and (13). The expression is as shown in equation (17): The switching node voltage is obtained from formulas (9) and (16). The expression is as shown in equation (18): 。 4. The method for characterizing output current noise considering load-side parasitic parameters according to claim 3, characterized in that, The expression for the output current in step two is as follows: in, For containing Parameter-dependent high-order polynomials in the complex frequency domain, This is the equivalent parasitic capacitance. The equivalent impedance of loop I in the small-signal model. This is the equivalent impedance of loop II in the small-signal model. For filtering inductors, For load resistance, For load inductance, This is the representation method in the complex frequency domain.
5. The method for characterizing output current noise considering load-side parasitic parameters according to claim 4, characterized in that, The specific method for analyzing the influence of output current characteristics using theoretical simulation in step three is as follows: (1) The influence of load-side parasitic parameters on the output characteristics of dual buck power amplifiers Increase parasitic inductance This will increase the energy storage capacity of each bridge arm branch, exacerbate the oscillation amplitude of the output current, and increase parasitic capacitance. This provides a path for the transmission of switching transient oscillations to the output, causing the noise in the output current to vary. The parasitic capacitance of GaN HEMT increases with the increase of [something]. With diode junction capacitance Both indirectly affect the output current by influencing the oscillation frequency of the switching node voltage; Increase parasitic capacitance Switching node voltages during turn-on and turn-off phases All of them increase accordingly; Switching oscillation current With the parasitic capacitance of the motor As the frequency of the bridge arm increases, the resonant frequency decreases, and the amplitude of the switching oscillation current near the resonant frequency increases. (2) The influence of load-side parasitic parameters on the transient state of GaN HEMT switching Consider parasitic capacitance At that time, the parasitic inductance of bridge arm I and GaN HEMT switches The influence of the turn-off voltage increases. Therefore, when optimizing parasitic parameters, the parasitic inductance that forms a resonant circuit with the load capacitance should be optimized first.