A simulation test method for surface metal interconnection layer resistance of a power MOSFET chip

Abstract

This application discloses a simulation test method for the surface metal interconnect layer resistance of a power MOSFET chip. The method involves fabricating an unsealed device, obtaining the simulated target resistance value of the unsealed device, constructing an actual device model, and obtaining the measured on-state resistance and chip conductivity parameters based on the actual device model. Based on the chip conductivity parameters, the on-state resistance value of the chip excluding the top metal layer is calculated. Finally, based on the measured on-state resistance value, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer, the surface metal interconnect layer resistance value of the power MOSFET chip is calculated. This method provides a reliable and novel characterization and calculation method for the surface metal interconnect layer resistance value, which is of great significance for optimizing metal bonding and reducing the overall device resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device simulation technology, and in particular to a simulation test method for the resistance of the surface metal interconnect layer of a power MOSFET chip. Background Technology

[0002] For traditional vertical structure power metal-oxide-semiconductor field-effect transistor (MOSFET) devices, a metal layer with a thickness of a few micrometers needs to be placed on the chip surface during the design process. It is usually an aluminum-silicon-copper alloy. This part serves as the metal bonding area of ​​the chip, used to connect the external bonding lines and the internal unit cell, as well as the interconnection between unit cells.

[0003] For low-voltage, low-on-resistance MOSFETs, the resistance introduced by the drift region, channel, and other areas of the device is relatively small, on the order of magnitude, which is comparable to that of the surface metal interconnect layer. As a result, the resistance introduced by the metal interconnect layer accounts for an important proportion of the overall resistance of the device.

[0004] However, the resistance introduced by the surface metal interconnect layer is strongly correlated with the size and shape of the MOSFET chip, current density distribution, bond wire specifications, and solder joint size and location, and this resistance is difficult to measure accurately. Therefore, how to reliably measure the resistance of the surface metal interconnect layer of a power MOSFET chip is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application aims to at least solve the technical problems existing in the prior art. To this end, the first aspect of this application proposes a simulation test method for the resistance of the surface metal interconnect layer of a power MOSFET chip, the method comprising: An empty-seal device is fabricated, and the simulated value of the target resistance of the empty-seal device is obtained; Construct an actual device model, and obtain the measured value of the device's on-state resistance and the chip's conductivity parameters based on the actual device model; Based on the chip conductivity parameters, the on-state resistance of the chip, excluding the top metal layer, is calculated. Based on the measured on-state resistance of the device, the simulated target resistance of the open-seal device, and the on-state resistance of the chip excluding the top metal layer, the surface metal interconnect layer resistance of the power MOSFET chip is calculated.

[0006] In one possible implementation, the process of fabricating an empty-seal device and obtaining the simulated target resistance value of the empty-seal device includes: An empty-seal device is fabricated, and the measured resistance value of the empty-seal device is obtained; Construct the empty-seal device model corresponding to the empty-seal device, and obtain the initial resistance simulation value; The material parameters of the empty-seal device model are calibrated so that the simulated resistance value of the empty-seal device matches the measured resistance value, thereby obtaining the target simulated resistance value of the empty-seal device.

[0007] In one possible implementation, the process of fabricating an empty-seal device and obtaining the measured resistance value of the empty-seal device includes: An aluminum block matching the size of the power MOSFET chip is prepared and bonded to the packaging frame; wherein the aluminum block is a low-resistance aluminum block, and the resistance of the aluminum block is one or more orders of magnitude lower than the packaging resistance formed by the packaging frame, adhesive layer and bonding wire. The empty-encapsulated device is fabricated according to the actual packaging process of the power MOSFET device. The drain-source resistance of the open-cell device was measured using the Kelvin method to obtain the measured resistance value of the open-cell device.

[0008] In one possible implementation, the step of constructing an actual device model and obtaining the measured values ​​of the device's on-state resistance and chip conductivity parameters based on the actual device model includes: A simulation model of a cuboid chip with the surface metal removed is constructed, and the conductivity along the chip plane is set to zero, while the conductivity along the chip thickness is set to an undetermined parameter. Construct an actual device model corresponding to the actual device, which includes a packaging framework, an adhesive layer, the chip model, a top metal layer, and wire bonding portions; The measured on-state resistance of the actual device is measured, and the same boundary conditions as the measured resistance are set for the actual device model for simulation calculation. The conductivity along the chip thickness direction is adjusted so that the simulated resistance value of the actual device is consistent with the measured resistance value. The undetermined parameter is then obtained as the chip conductivity parameter.

[0009] In one possible implementation, constructing the cuboid chip simulation model after removing the surface metal includes: Obtain the on-state resistance model of the MOSFET active region; Based on the on-state resistance model of the MOSFET active region, a cuboid structure is used as the chip shape. The cuboid structure is used to simulate the target MOSFET chip after the surface metal is removed, and the cuboid chip simulation model is obtained. The dimensions of the cuboid structure are completely matched with the active region dimensions of the target MOSFET chip.

[0010] In one possible implementation, the boundary conditions include at least the test temperature, current input point, current output point, and excitation current amplitude.

[0011] In one possible implementation, calculating the on-state resistance of the chip, excluding the top metal layer, based on the chip conductivity parameters includes: Obtain the chip thickness and the area of ​​the active region planar region; Based on the chip conductivity parameters, chip thickness, and active region planar area, the on-state resistance of the chip, excluding the top metal layer, is calculated.

[0012] In one possible implementation, calculating the surface metal interconnect layer resistance of the power MOSFET chip based on the measured on-state resistance of the device, the simulated target resistance of the unsealed device, and the on-state resistance of the chip excluding the top metal layer includes: The surface metal interconnect layer resistance value of the power MOSFET chip is calculated by subtracting the simulated target resistance value of the unsealed device and the on-state resistance value of the chip excluding the top metal from the measured on-state resistance value of the device.

[0013] A second aspect of this application provides a simulation testing device for the resistance of the surface metal interconnect layer of a power MOSFET chip, characterized in that the device comprises: The acquisition module is used to fabricate an empty-seal device and acquire the simulated target resistance value of the empty-seal device; The construction module is used to build an actual device model and obtain the measured value of the device's on-state resistance and chip conductivity parameters based on the actual device model. The first calculation module is used to calculate the on-state resistance value of the chip excluding the top metal, based on the chip's conductivity parameters. The second calculation module is used to calculate the surface metal interconnect layer resistance value of the power MOSFET chip based on the measured on-state resistance value of the device, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer.

[0014] The embodiments of this application have the following beneficial effects: This application provides a simulation test method for the surface metal interconnect layer resistance of a power MOSFET chip. The method involves fabricating an unsealed device, obtaining the simulated target resistance value of the unsealed device, constructing an actual device model, and obtaining the measured on-state resistance value and chip conductivity parameters based on the actual device model. Based on the chip conductivity parameters, the on-state resistance value of the chip excluding the top metal layer is calculated. Finally, based on the measured on-state resistance value, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer, the surface metal interconnect layer resistance value of the power MOSFET chip is calculated. This method provides a reliable and novel characterization and calculation method for the surface metal interconnect layer resistance value, which is of great significance for optimizing metal bonding and reducing the overall device resistance. Attached Figure Description

[0015] Figure 1 A flowchart illustrating the steps of a simulation test method for the resistance of a surface metal interconnect layer on a power MOSFET chip, provided in an embodiment of this application; Figure 2 A schematic diagram of a MOSFET active region on-state resistance model provided in an embodiment of this application; Figure 3 A flowchart illustrating the steps for obtaining the simulated target resistance value of an unsealed device, as provided in this application embodiment; Figure 4 A flowchart illustrating the steps for obtaining the measured resistance value of an unsealed device, as provided in this application embodiment; Figure 5 A flowchart illustrating the steps for obtaining the measured value of the on-state resistance of a device and the conductivity parameters of a chip, as provided in this application embodiment; Figure 6 A flowchart illustrating the steps for obtaining the measured value of the on-state resistance of a device and the chip conductivity parameters, provided in this application embodiment; Figure 7 This is a schematic diagram of a cuboid chip simulation model provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0017] For traditional vertical structure power metal-oxide-semiconductor field-effect transistor (MOSFET) devices, a metal layer with a thickness of a few micrometers needs to be placed on the chip surface during the design process. This layer is usually an aluminum-silicon-copper alloy. This part serves as the metal bonding area of ​​the chip, used to connect the external bonding lines and the internal unit cells, as well as the interconnections between unit cells.

[0018] For low-voltage, low-on-resistance MOSFETs, the resistance introduced by the drift region and channel is relatively small, on the order of magnitude of the surface metal interconnect layer. Therefore, the resistance introduced by this metal interconnect layer accounts for a significant portion of the overall device resistance. When a MOSFET is turned on, the current flows independently in each cell region, i.e., the path from substrate-epitaxy-channel-source-metal contact-surface metal interconnect layer. The resistance introduced by the surface metal layer is strongly correlated with the MOSFET chip's size and shape, current density distribution, bond wire specifications, and solder joint size and location, and this resistance is difficult to measure precisely.

[0019] In view of this, this application proposes a simulation test method for the surface metal interconnect layer resistance of a power MOSFET chip. This method involves fabricating an unsealed device, obtaining the simulated target resistance value of the unsealed device, constructing an actual device model, and obtaining the measured on-state resistance value and chip conductivity parameters based on the actual device model. Based on the chip conductivity parameters, the on-state resistance value of the chip excluding the top metal layer is calculated. Based on the measured on-state resistance value, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer, the surface metal interconnect layer resistance value of the power MOSFET chip is finally calculated. This method provides a reliable and novel characterization and calculation method for the surface metal interconnect layer resistance value, which is of great significance for optimizing metal bonding and reducing the overall device resistance.

[0020] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0021] like Figure 1 As shown, Figure 1 A flowchart illustrating the steps of a simulation test method for the surface metal interconnect layer resistance of a power MOSFET chip, provided in this application embodiment, includes: Step 102: Fabricate an empty-seal device and obtain the simulated target resistance value of the empty-seal device.

[0022] First, the on-state resistance of the MOSFET active region and the resistance of the metal layer can be modeled, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of a MOSFET active region on-state resistance model provided in an embodiment of this application. Assume R... Cell1 Equal to R Cell2 …equals R CellN Here, the model ignores the influence of cell uniformity, and since N is infinite, the influence of cell spacing is also ignored. According to the numerical calculation principles of subsequent simulation software, this is equivalent to replacing the discrete distribution of current density on the XOY plane of the wafer with a continuous linear interpolation function. Furthermore, Figure 2 In the diagram, Al layer1…Al layerN represent the corresponding surface metal layers, and wire bond represents the bonding wire.

[0023] Next, an empty-seal device can be fabricated and its resistance measured, in some alternative embodiments, such as Figure 3 As shown, Figure 3 A flowchart illustrating the steps for obtaining the simulated target resistance value of an unsealed device, as provided in this application embodiment, includes: Step 302: Fabricate an empty sealed device and obtain the measured resistance value of the empty sealed device.

[0024] Step 304: Construct the empty-seal device model corresponding to the empty-seal device and obtain the initial resistance simulation value.

[0025] Step 306: Calibrate the material parameters of the empty-seal device model so that the simulated resistance value of the empty-seal device matches the measured resistance value, and obtain the target simulated resistance value of the empty-seal device.

[0026] In some optional embodiments, such as Figure 4 As shown, Figure 4 A flowchart illustrating the steps for obtaining the measured resistance value of an unsealed device, as provided in this application embodiment, includes: Step 402: Prepare an aluminum block that matches the size of the power MOSFET chip and attach it to the packaging frame.

[0027] Step 404: Fabricate an empty-encapsulated device according to the actual packaging process of the power MOSFET device.

[0028] Step 406: Measure the drain-source resistance of the unsealed device using the Kelvin method to obtain the measured resistance value of the unsealed device.

[0029] The aluminum block is a low-resistance aluminum block, and its resistance is one or more orders of magnitude lower than the package resistance formed by the package frame, adhesive layer, and bonding wires. This allows an aluminum block of the same size as the chip to be bonded to the package frame. Furthermore, the aluminum block has a large surface area and a short length, making its resistance negligible compared to the package resistance.

[0030] Next, an empty-seal device can be fabricated according to the actual packaging process of the power MOSFET device, and the drain-source resistance of the empty-seal device can be measured using the Kelvin method to obtain the final measured resistance value of the empty-seal device.

[0031] Therefore, the empty-seal device model corresponding to the above-mentioned empty-seal device can be established in the numerical simulation software. The reconstruction of the empty-seal device model includes several parts such as the packaging frame, adhesive layer, aluminum block, and bonding wire, and boundary conditions that match the actual situation are added, so that the simulation can obtain the initial resistance simulation value.

[0032] Next, the material parameters of the empty-seal device model can be calibrated by referring to the measured resistance value of the empty-seal device, so that the simulated resistance value of the empty-seal device matches the measured resistance value, and finally the accurate simulated target resistance value of the empty-seal device can be obtained.

[0033] Step 104: Construct an actual device model and obtain the measured values ​​of the device's on-state resistance and chip conductivity parameters based on the actual device model.

[0034] In some optional embodiments, such as Figure 5 As shown, Figure 5 A flowchart illustrating the steps for obtaining measured values ​​of device on-state resistance and chip conductivity parameters, as provided in this application embodiment, includes: Step 502: Construct a simulation model of the cuboid chip after removing the surface metal, and set the conductivity along the chip plane to zero and the conductivity along the chip thickness to be determined.

[0035] Step 504: Construct an actual device model corresponding to the actual device, including the packaging framework, adhesive layer, chip model, top metal layer, and wire bonding section.

[0036] Step 506: Measure the actual on-state resistance of the actual device, and perform simulation calculations with the same boundary conditions as the actual measurement on the actual device model. Adjust the conductivity along the chip thickness direction so that the simulated resistance value of the actual device is consistent with the measured resistance value, and determine the undetermined parameter as the chip conductivity parameter.

[0037] In some optional embodiments, such as Figure 6 As shown, Figure 6 A flowchart illustrating the steps for obtaining measured values ​​of device on-state resistance and chip conductivity parameters, as provided in this application embodiment, includes: Step 602: Obtain the on-state resistance model of the MOSFET active region.

[0038] Step 604: Based on the MOSFET active region on-state resistance model, a cuboid structure is used as the chip outline. The cuboid structure is used to simulate the target MOSFET chip after removing the surface metal, and a cuboid chip simulation model is obtained.

[0039] Among them, the on-state resistance model of the MOSFET active region is as follows: Figure 2 As shown, this model can be used as a reference. Without considering the resistance of the metal layer, a cuboid block is used as the chip shape. The cuboid structure is used to simulate the target MOSFET chip after the surface metal is removed, thus obtaining a cuboid chip simulation model. The size of the cuboid structure is completely matched with the active area size of the target MOSFET chip.

[0040] like Figure 7 As shown, Figure 7 This is a schematic diagram of a cuboid chip simulation model provided in an embodiment of this application, wherein the X and Y directions are along the chip plane, and the Z direction is along the chip thickness direction. The conductivity along the chip plane can be set to zero, and the conductivity along the chip thickness direction can be set as an undetermined parameter.

[0041] Next, a real-world device model can be constructed, including the packaging framework, adhesive layer, chip model, top metal layer, and wire bonding section. The actual device is then tested to obtain the measured on-state resistance. Simulation calculations are then performed on the actual device model with the same boundary conditions as the measured values, i.e., current flows from the drain pin to the source pin. The conductivity along the chip thickness direction is adjusted to ensure the simulated resistance value matches the measured value. The final undetermined parameter is extracted as the chip conductivity parameter, i.e., the chip conductivity parameter in the Z-direction.

[0042] Optionally, the boundary conditions include at least the test temperature, current input point, current output point, and excitation current amplitude. Of course, other types of boundary conditions may also be included, but this application embodiment does not specifically limit them.

[0043] Step 106: Based on the chip conductivity parameters, calculate the on-state resistance of the chip excluding the top metal.

[0044] In calculating the on-state resistance, the chip thickness and active area can be obtained first. Then, based on the chip conductivity parameters, chip thickness, and active area, the on-state resistance of the chip, excluding the top metal, can be calculated.

[0045] Optionally, the chip thickness and the active region area of ​​the chip can be obtained based on the determined conductivity along the chip thickness direction. The chip thickness is used as the current path length and the active region area is used as the current flow cross-sectional area. The on-state resistance of the chip, excluding the top metal, can be calculated by dividing the chip thickness by the product of the conductivity along the thickness direction and the active region area.

[0046] Step 108: Based on the measured on-state resistance of the device, the simulated target resistance of the unsealed device, and the on-state resistance of the chip excluding the top metal layer, calculate the surface metal interconnect layer resistance of the power MOSFET chip.

[0047] The measured on-state resistance of the device can be subtracted sequentially from the simulated target resistance of the unsealed device and the on-state resistance of the chip excluding the top metal, thereby calculating the surface metal interconnect layer resistance value introduced by the top metal of the power MOSFET chip after specific metal bonding.

[0048] By changing the size of the bonding wires and the solder joints, or the chip size, the resistance value of the surface metal interconnect layer will change according to the above factors, thereby allowing the search for the optimal metal bonding method or the optimization of the surface metal layer thickness based on the feasibility of the process.

[0049] This application proposes a simulation test method for the surface metal interconnect layer resistance of a power MOSFET chip. The method involves fabricating an unsealed device, obtaining the simulated target resistance value of the unsealed device, constructing an actual device model, and obtaining the measured on-state resistance and chip conductivity parameters based on the actual device model. Based on the chip conductivity parameters, the on-state resistance value of the chip excluding the top metal layer is calculated. Finally, based on the measured on-state resistance value, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer, the surface metal interconnect layer resistance value of the power MOSFET chip is calculated. This method provides a reliable and novel characterization and calculation method for the surface metal interconnect layer resistance value, which is of great significance for optimizing metal bonding and reducing the overall device resistance.

[0050] This application embodiment also provides a simulation testing device for the resistance of the surface metal interconnect layer of a power MOSFET chip, the device comprising: The acquisition module is used to fabricate an empty-seal device and obtain the simulated target resistance value of the empty-seal device; The module is used to build a model of the actual device and obtain the measured value of the device's on-state resistance and the chip's conductivity parameters based on the actual device model. The first calculation module is used to calculate the on-state resistance of the chip, excluding the top metal, based on the chip's conductivity parameters. The second calculation module is used to calculate the surface metal interconnect layer resistance value of the power MOSFET chip based on the measured on-state resistance value of the device, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal.

[0051] The specific implementation process and beneficial effects of the simulation test device for the surface metal interconnect layer resistance of the power MOSFET chip can be referred to the above method embodiments, and will not be repeated here.

[0052] It is readily understood that, based on the several embodiments provided in this application, those skilled in the art can combine, split, or reorganize the embodiments of this application to obtain other embodiments, none of which exceed the protection scope of this application.

[0053] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A simulation test method for surface metal interconnection layer resistance of a power MOSFET chip, characterized in that, The method includes: An empty-seal device is fabricated, and the simulated value of the target resistance of the empty-seal device is obtained; Construct an actual device model, and obtain the measured value of the device's on-state resistance and the chip's conductivity parameters based on the actual device model; Based on the chip conductivity parameters, the on-state resistance of the chip, excluding the top metal layer, is calculated. Based on the measured on-state resistance of the device, the simulated target resistance of the open-seal device, and the on-state resistance of the chip excluding the top metal layer, the surface metal interconnect layer resistance of the power MOSFET chip is calculated.

2. The method of claim 1, wherein, The process of fabricating an empty-seal device and obtaining the simulated target resistance value of the empty-seal device includes: An empty-seal device is fabricated, and the measured resistance value of the empty-seal device is obtained; Construct the empty-seal device model corresponding to the empty-seal device, and obtain the initial resistance simulation value; The material parameters of the empty-seal device model are calibrated so that the simulated resistance value of the empty-seal device matches the measured resistance value, thereby obtaining the target simulated resistance value of the empty-seal device.

3. The method of claim 2, wherein, The process of fabricating an empty-seal device and obtaining the measured resistance value of the empty-seal device includes: An aluminum block matching the size of the power MOSFET chip is prepared and bonded to the packaging frame; wherein the aluminum block is a low-resistance aluminum block, and the resistance of the aluminum block is one or more orders of magnitude lower than the packaging resistance formed by the packaging frame, adhesive layer and bonding wire. The empty-encapsulated device is fabricated according to the actual packaging process of the power MOSFET device. The drain-source resistance of the open-cell device was measured using the Kelvin method to obtain the measured resistance value of the open-cell device.

4. The method according to any one of claims 1 to 3, characterized in that, The construction of the actual device model, and the acquisition of the measured on-state resistance and chip conductivity parameters based on the actual device model, include: A simulation model of a cuboid chip with the surface metal removed is constructed, and the conductivity along the chip plane is set to zero, while the conductivity along the chip thickness is set to an undetermined parameter. Construct an actual device model corresponding to the actual device, which includes a packaging framework, an adhesive layer, the chip model, a top metal layer, and wire bonding portions; The measured on-state resistance of the actual device is measured, and the same boundary conditions as the measured resistance are set for the actual device model for simulation calculation. The conductivity along the chip thickness direction is adjusted so that the simulated resistance value of the actual device is consistent with the measured resistance value. The undetermined parameter is then obtained as the chip conductivity parameter.

5. The method of claim 4, wherein, The construction of the cuboid chip simulation model after removing the surface metal includes: Obtain the on-state resistance model of the MOSFET active region; Based on the on-state resistance model of the MOSFET active region, a cuboid structure is used as the chip shape. The cuboid structure is used to simulate the target MOSFET chip after the surface metal is removed, and the cuboid chip simulation model is obtained. The dimensions of the cuboid structure are completely matched with the active region dimensions of the target MOSFET chip.

6. The method according to claim 4 or 5, characterized in that, The boundary conditions include at least the test temperature, current input point, current output point, and excitation current amplitude.

7. The method according to any one of claims 1-3, characterized in that, The calculation of the on-state resistance of the chip, excluding the top metal layer, based on the chip's conductivity parameters includes: Obtain the chip thickness and the area of ​​the active region planar region; Based on the chip conductivity parameters, chip thickness, and active region planar area, the on-state resistance of the chip, excluding the top metal layer, is calculated.

8. The method according to claims 1-3, characterized in that, The calculation of the surface metal interconnect layer resistance value of the power MOSFET chip based on the measured on-state resistance value of the device, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer includes: The surface metal interconnect layer resistance value of the power MOSFET chip is calculated by subtracting the simulated target resistance value of the unsealed device and the on-state resistance value of the chip excluding the top metal from the measured on-state resistance value of the device.

9. A simulation and testing device for the resistance of the surface metal interconnect layer of a power MOSFET chip, characterized in that, The device includes: The acquisition module is used to fabricate an empty-seal device and acquire the simulated target resistance value of the empty-seal device; The construction module is used to build an actual device model and obtain the measured value of the device's on-state resistance and chip conductivity parameters based on the actual device model. The first calculation module is used to calculate the on-state resistance value of the chip excluding the top metal, based on the chip's conductivity parameters. The second calculation module is used to calculate the surface metal interconnect layer resistance value of the power MOSFET chip based on the measured on-state resistance value of the device, the simulated target resistance value of the unsealed device, and the on-state resistance value of the chip excluding the top metal layer.

Images