A three-dimensional integrated circuit layout optimization method, system and electronic device

Abstract

This invention relates to the field of semiconductor integrated circuit technology, and discloses a three-dimensional integrated circuit layout optimization method, system, and electronic device. The method first allocates module layers based on the number of through-silicon vias (TSVs) as the optimization target, decoupling and generating interconnection information for each layer. Then, it optimizes the two-dimensional layout of functional modules, inserting TSVs in the blank areas between modules to obtain initial position information. Finally, it optimizes the inter-layer joint temperature by iteratively exchanging the positions of functional modules, using the three-dimensional thermal aggregation index as the optimization target. This invention achieves coordinated optimization of TSV positions and functional module layout while ensuring computational efficiency, and effectively controls the thermal aggregation effect of the 3D-IC system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and specifically to a three-dimensional integrated circuit layout optimization method, system, and electronic device. Background Technology

[0002] Three-dimensional integrated circuits (3D-ICs) achieve vertical interconnection between chip layers through through-silicon vias (TSVs). Compared to traditional two-dimensional chips, this can improve data transmission rates, reduce package size, and overcome the integration bottleneck of Moore's Law. However, the high-density vertical integration of 3D-ICs also brings challenges. Interlayer thermal coupling effects lead to significant heat accumulation, affecting chip reliability. As a scarce interlayer communication resource, the placement of TSVs directly affects the global interconnect length and signal delay, thus determining the overall chip performance and manufacturing cost.

[0003] To address these issues, scholars both domestically and internationally have conducted extensive research. Existing methods mainly fall into two categories: one category treats TSVs and functional modules as equal optimization objects for joint solution, such as non-simulated annealing 3D layout algorithms and TSV-module co-planning methods. While these methods expand the coverage of optimization variables, the number of TSVs typically far exceeds the number of modules (e.g., the number of TSVs in the n300 dataset can reach over 1500), leading to an exponential expansion of the solution space, a significant reduction in computational efficiency, and difficulty in engineering applications. The other category employs a phased strategy of layering first and then optimizing, such as thermal sensing layout and TSV planning methods and the three-phase GA-SA algorithm, which reduces the complexity of a single optimization by decoupling layer allocation from intra-layer layout. However, these methods generally use temperature-line length joint indicators as the decision-making basis in the layering stage, failing to fully consider the characteristic that the solution space for temperature optimization is much larger than that for line length optimization, resulting in limited temperature control effectiveness; at the same time, TSVs are mostly passively inserted after layout is completed, failing to fully leverage their active role in optimizing line length.

[0004] Therefore, how to achieve coordinated optimization of TSV position and module layout while ensuring computational efficiency, and effectively control the thermal aggregation effect of 3D-IC system, has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a three-dimensional integrated circuit layout optimization method, system, and electronic device to solve the problem of how to achieve coordinated optimization of TSV position and module layout while ensuring computational efficiency, and effectively control the thermal accumulation effect of 3D-IC system.

[0006] In a first aspect, the present invention provides a three-dimensional integrated circuit layout optimization method, the method comprising:

[0007] With the number of through-silicon vias as the optimization target, functional modules are allocated to each layer of the 3D integrated circuit, and the interconnection information of functional modules and through-silicon vias in each layer is decoupled and generated. Based on the interconnection information of the functional modules and through-silicon vias, the two-dimensional layout optimization of the functional modules that have been assigned layers is performed, and through-silicon vias are inserted in the blank areas formed after the functional module layout optimization to obtain the initial position information of each functional module and each through-silicon via. Based on the initial position information of each functional module and each through-silicon via obtained, the three-dimensional thermal aggregation index is used as the optimization target. Interlayer joint temperature optimization is performed by iteratively exchanging the positions of functional modules to obtain the final layout. The three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

[0008] The above solution employs a phased collaborative optimization strategy to reduce process costs while simultaneously ensuring interconnect performance and thermal reliability. The first phase optimizes layer allocation by targeting the number of through-silicon vias (TSVs), reducing the number of TSVs required for cross-layer interconnects from the outset, thus lowering process complexity and manufacturing costs. The second phase leverages the size differences between functional modules and TSVs, optimizing module layout first and then inserting TSVs into blank areas. This avoids the space explosion problem caused by treating a large number of TSVs as independent optimization variables and fully utilizes the blank areas naturally formed after module layout, improving space utilization. The third phase optimizes temperature by targeting the three-dimensional thermal aggregation index, effectively reducing the degree of localized heat accumulation in the system and improving chip thermal reliability.

[0009] In one optional implementation, the allocation of functional modules to the layers of the three-dimensional integrated circuit with the optimization target of the number of through-silicon vias includes: With minimizing the number of through-silicon vias as the optimization objective, functional modules with strong interconnections are assigned to the same layer of the 3D integrated circuit based on the interconnection network relationship between functional modules.

[0010] The above solution distributes strongly connected functional modules to the same layer, reducing the number of TSVs from the source and lowering process complexity and manufacturing costs.

[0011] In one optional implementation, the two-dimensional layout optimization of the functional modules of each layer that have been assigned layers includes: By constructing an ordered binary tree to represent the layout structure of functional modules at each level, and using various perturbation operations to iteratively update the structure of the ordered binary tree, non-overlapping two-dimensional planar layout coordinates for each level are generated.

[0012] The above scheme uses an ordered binary tree to represent the layout, which can efficiently generate compact and non-overlapping two-dimensional layout coordinates, laying the foundation for subsequent TSV insertion.

[0013] In one optional implementation, the step of constructing an ordered binary tree to represent the layout structure of functional modules at each layer, iteratively updating the structure of the ordered binary tree using various perturbation operations, and generating non-overlapping two-dimensional planar layout coordinates for each layer includes: For each functional module that has been assigned to a layer, an ordered binary tree is constructed to represent the layout structure of each functional module in order to generate the initial layout coordinates. Within the framework of simulated annealing, various perturbation operations are performed on the ordered binary tree to update the binary tree structure; After each perturbation, the coordinates of each functional module are reconstructed based on the updated binary tree structure to generate a non-overlapping two-dimensional planar layout. Iteratively execute the above construction, perturbation and reconstruction steps until the preset termination condition is met, and output the optimized two-dimensional planar layout coordinates of each functional module.

[0014] The above scheme iteratively optimizes the layout under the simulated annealing framework, which can effectively avoid getting trapped in local optima and improve the quality of module layout.

[0015] In one optional implementation, inserting a through-silicon via in the blank area formed after the functional module layout includes: Based on the optimized two-dimensional planar layout coordinates of each layer of functional modules, the distribution characteristics of the blank areas formed after the layout of each layer of functional modules are obtained. Following the order from the lowest to the highest layer, based on the distribution characteristics of the blank areas formed after the functional modules of each layer are laid out, through-silicon vias are inserted layer by layer, and the position information of the through-silicon vias already inserted in the lower layer is used as a reference input for the layout optimization of the higher layer.

[0016] In the above scheme, when laying out TSVs in the high-rise layer, the wiring length needs to be calculated based on the location of TSVs in the low-rise layer as an optimization indicator. Therefore, TSVs can be inserted layer by layer, and the location information of the TSVs already inserted in the low-rise layer can be used as a reference input for optimizing the layout of the high-rise layer.

[0017] In one optional implementation, the step of inserting through-silicon vias (TSVs) layer by layer based on the distribution characteristics of the blank areas formed after the layout of the functional modules at each layer, and using the location information of the TSVs already inserted in the lower layers as a reference input for the layout optimization of the higher layers, includes: For the blank areas formed after the layout of the current layer functional modules, the insertion priority of each blank area is determined based on the distribution characteristics of the blank areas and the connection requirements of the through silicon vias to be inserted. Based on the priority, for a through-silicon via (TSV) that needs to be inserted in the current layer, the position that meets the connection constraints is selected from the blank area according to the position of the upper and lower functional modules connected by the TSV; After completing the insertion of through-silicon vias in the current layer, update the position information of the inserted through-silicon vias to the input file of the higher layer layout as a reference constraint for the layout optimization of the higher layer functional modules. The above insertion process is performed iteratively layer by layer until all layers have had through-silicon vias inserted.

[0018] The above solution inserts TSVs based on the distribution characteristics of blank areas and connection requirements, thereby achieving coordinated optimization of TSV positions and module layout and improving space utilization.

[0019] In an alternative implementation, prior to the interlayer joint temperature optimization via iterative swapping of functional module positions, the method further includes: Each layer is divided into several grid points, and the layer connection temperature index of each grid point is calculated. The layer connection temperature index is determined by the power consumption weighted value of the layer where the grid point is located and the power consumption coupling value between the grid point and the corresponding grid points in the adjacent layer.

[0020] The above scheme quantifies interlayer thermal coupling by using gridded temperature indices, providing a refined computational basis for temperature optimization.

[0021] In one optional implementation, the step of performing interlayer joint temperature optimization by iteratively exchanging the positions of functional modules to obtain the final layout includes: For each functional module, the sum of the layer temperature indices of all grid points covered by the functional module is calculated as the temperature index of the current functional module; Within the current layer, the target functional module with the highest temperature index is selected, and the matching coefficient between other functional modules in the current layer and the target functional module is calculated. The candidate functional module with the highest matching coefficient is selected for exchange attempt. The matching coefficient is determined based on the area difference and power consumption difference between functional modules. After swapping the positions of the functional modules, the three-dimensional heat zone aggregation index after the swap is calculated. If the three-dimensional heat zone aggregation index decreases, the swap is accepted; otherwise, the original layout is retained. Based on the results of the swaps and retentions, the final layout is obtained.

[0022] The above scheme uses module temperature index to screen hotspots and iteratively exchange them to achieve precise elimination of local heat accumulation and improve the overall heat distribution.

[0023] In a second aspect, the present invention provides a three-dimensional integrated circuit layout optimization system, comprising: The layer allocation module is used to allocate functional modules to each layer of the 3D integrated circuit with the number of through-silicon vias as the optimization target, and to decouple and generate interconnection information of functional modules and through-silicon vias for each layer. The in-layer layout optimization module is connected to the layer allocation module. It is used to perform two-dimensional layout optimization on the functional modules of each layer that have been allocated based on the interconnection information of each layer functional module and through silicon via, and to insert through silicon vias in the blank areas formed after the functional module layout, so as to obtain the initial position information of each layer functional module and each layer through silicon via. The temperature optimization module, connected to the in-layer layout optimization module, is used to perform inter-layer joint temperature optimization based on the obtained initial position information of each layer's functional modules and each layer's through-silicon vias, with the three-dimensional thermal aggregation index as the optimization target, by iteratively exchanging the positions of functional modules to obtain the final layout; the three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

[0024] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform a three-dimensional integrated circuit layout optimization method of the first aspect or any corresponding embodiment described above.

[0025] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute a three-dimensional integrated circuit layout optimization method according to the first aspect or any corresponding embodiment described above.

[0026] Fifthly, the present invention provides a computer program product, including computer instructions, which are used to cause a computer to execute a three-dimensional integrated circuit layout optimization method according to the first aspect or any corresponding embodiment described above.

[0027] The present invention has the following beneficial effects: The above solution employs a phased collaborative optimization strategy to reduce process costs while simultaneously ensuring interconnect performance and thermal reliability. The first phase optimizes layer allocation by targeting the number of through-silicon vias (TSVs), reducing the number of TSVs required for cross-layer interconnects from the outset, thus lowering process complexity and manufacturing costs. The second phase leverages the size differences between functional modules and TSVs, optimizing module layout first and then inserting TSVs into blank areas. This avoids the space explosion problem caused by treating a large number of TSVs as independent optimization variables and fully utilizes the blank areas naturally formed after module layout, improving space utilization. The third phase optimizes temperature by targeting the three-dimensional thermal aggregation index, effectively reducing the degree of localized heat accumulation in the system and improving chip thermal reliability. Attached Figure Description

[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional integrated circuit (3D-IC) stacked structure according to an embodiment of the present invention; Figure 2 This is a flowchart of a three-dimensional integrated circuit layout optimization method according to an embodiment of the present invention; Figure 3 This is a second flowchart of a three-dimensional integrated circuit layout optimization method according to an embodiment of the present invention; Figure 4 This is a comparative schematic diagram of the functional module and through-silicon via joint optimization and two-stage optimization according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the characteristics of the temperature index of the interlayer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of three-dimensional heat distribution according to an embodiment of the present invention; Figure 7 This is a third flowchart of a three-dimensional integrated circuit layout optimization method according to an embodiment of the present invention; Figure 8 This is a schematic diagram of temperature clouds under the N300 dataset-4 layer setting according to an embodiment of the present invention; Figure 9 This is a structural block diagram of a three-dimensional integrated circuit layout optimization system according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0032] As an optional application scenario of this invention, such as Figure 1 As shown, Figure 1 This diagram shows a cross-sectional view of a three-dimensional integrated circuit (3D-IC) stacked structure. The bottom layer is a printed circuit board (PCB), which serves as the substrate for the entire electronic system, providing electrical connections and mechanical support. Above the PCB is a substrate, and above that is an interposer. Redistribution layers (RDLs) are laid on the interposer to connect to the chip stacked structure above.

[0033] Above the interposer is a multi-layered stacked chip structure. Figure 1 The layers are labeled Layer-3 to Layer-0. These four layers are stacked vertically and form the core functional area of ​​the 3D IC. Within each layer, the modules circled in dashed lines are units that implement specific circuit functions, i.e., functional modules. Functional modules in different layers are electrically interconnected through vertical through-silicon vias (TSVs), significantly shortening the signal transmission path.

[0034] Above the topmost layer -0, the heat spreader and the topmost heat sink are connected by TIM adhesive (thermal interface material). This structure is used to conduct and dissipate the heat generated by the core chip into the environment.

[0035] The aforementioned three-dimensional integrated circuits (3D-ICs) achieve vertical interconnection between layers through through-silicon vias (TSVs), offering significant advantages over traditional two-dimensional chips, such as improved data transmission speed, reduced package size, and overcoming integration bottlenecks imposed by Moore's Law. However, the high-density integration of 3D-ICs also presents challenges such as heat accumulation, layout stability, and cost control. Firstly, most methods treat TSVs merely as passive components, neglecting to consider their positional optimization effect on line length. Secondly, joint optimization of TSVs and modules leads to solution space explosion and low computational efficiency. Thirdly, staged methods employ multi-objective coupling indicators during layer allocation, limiting temperature control effectiveness. Therefore, this invention proposes a three-dimensional integrated circuit layout optimization method, system, and electronic device. Through a staged collaborative optimization strategy, it reduces process costs while simultaneously ensuring interconnect performance and thermal reliability. The first stage optimizes layer allocation by targeting the number of through-silicon vias (TSVs), reducing the number of TSVs required for cross-layer interconnects from the source, thereby lowering process complexity and manufacturing costs. The second stage utilizes the size difference between functional modules and TSVs, first optimizing the module layout and then inserting TSVs into the blank areas. This avoids the solution space explosion problem caused by treating a large number of TSVs as independent optimization variables, and makes full use of the blank areas naturally formed after the module layout, improving space utilization. The third stage optimizes temperature by targeting the three-dimensional heat accumulation index, effectively reducing the degree of local heat accumulation in the system and improving the thermal reliability of the chip.

[0036] According to an embodiment of the present invention, a method for optimizing the layout of three-dimensional integrated circuits is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0037] This embodiment provides a three-dimensional integrated circuit layout optimization method. Figure 2 This is a flowchart of a three-dimensional integrated circuit layout optimization method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S201: Using the number of through-silicon vias as the optimization target, the functional modules are allocated to each layer of the three-dimensional integrated circuit, and the interconnection information of the functional modules and through-silicon vias of each layer is decoupled and generated.

[0038] Furthermore, this embodiment optimizes the number of through-silicon vias (TSVs) to allocate functional modules of the 3D integrated circuit to each layer of the 3D integrated circuit. A functional module refers to a circuit unit with a specific function in the chip (such as a processor core, memory unit, etc.), while a TSV is a vertical conductive channel passing through the silicon substrate, used to achieve electrical connections between functional modules in different layers. Optimizing the number of TSVs means prioritizing reducing the number of TSVs required for cross-layer interconnects during the layer allocation stage, allocating groups of functional modules with strong interconnections to the same layer, thereby reducing process complexity and manufacturing costs from the outset. After layer allocation, the original overall interconnect network data is decoupled into independent interconnect information for each layer, including the number, size, and power consumption of functional modules in each layer, as well as the TSV information that each layer needs to connect to. This decoupling operation breaks down global optimization into multiple local sub-optimizations, laying the foundation for subsequent independent optimization of each layer, while avoiding the solution space explosion problem caused by the number of TSVs far exceeding the number of modules.

[0039] Step S202: Based on the interconnection information of each layer of functional modules and through-silicon vias, perform two-dimensional layout optimization on each layer of functional modules that have completed layer allocation, and insert through-silicon vias in the blank areas formed after the functional modules are laid out, so as to obtain the initial position information of each layer of functional modules and each layer of through-silicon vias.

[0040] Furthermore, based on the interconnection information generated in step S201, this embodiment performs two-dimensional layout optimization on the functional modules of each layer that have completed layer allocation, and inserts through-silicon vias (TSVs) in the blank areas formed after the functional module layout. Two-dimensional layout optimization involves adjusting the relative positions of functional modules within the two-dimensional plane of each layer to achieve a compact, non-overlapping layout, thereby shortening the interconnect length between modules. After the functional module layout is completed, blank areas (whitespace) unoccupied by modules will naturally form within each layer. These blank areas can be used to insert TSVs. In this embodiment, the routing length needs to be calculated based on the positions of lower-layer TSVs during higher-layer TSV layout as an optimization indicator. Therefore, TSVs can be inserted layer by layer, and the position information of the lower-layer inserted TSVs can be used as a reference input for higher-layer layout optimization. This embodiment's strategy of optimizing functional modules first and then inserting TSVs fully utilizes the size difference between functional modules and TSVs (the area of ​​a functional module is typically tens to hundreds of times that of a TSV), thereby achieving coordinated optimization of TSV positions and module layout while ensuring computational efficiency.

[0041] Step S203: Based on the initial position information of each layer of functional modules and each layer of through-silicon vias, the three-dimensional thermal aggregation index is used as the optimization target. The interlayer joint temperature optimization is performed by iteratively exchanging the positions of functional modules to obtain the final layout. The three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

[0042] Furthermore, based on the initial position information of each layer of functional modules and each layer of through-silicon vias (TSVs) obtained in step S202, this embodiment uses the three-dimensional thermal clustering index as the optimization target. It iteratively swaps the positions of functional modules to perform inter-layer joint temperature optimization, obtaining the final layout. The three-dimensional thermal clustering index is a quantitative indicator constructed based on the electron potential energy model, used to characterize the overall thermal clustering situation of a three-dimensional integrated circuit. Its core idea is that functional modules that are closer together and have higher power consumption contribute more to the index. When high-power modules are stacked vertically or clustered horizontally, the index will increase significantly, reflecting the risk of local hot spots. This step analyzes the power consumption distribution and relative positions of functional modules in the current layout to identify key modules causing thermal clustering, and attempts to swap the positions of these modules within or between layers to reduce the three-dimensional thermal clustering index. By iteratively executing the above swapping operations, the clustered areas of high-power modules are gradually dispersed, making the heat distribution more uniform. Ultimately, while ensuring the optimization effect of line length and TSV number, a final layout with better thermal reliability is obtained.

[0043] In summary, this invention employs a phased collaborative optimization strategy to reduce process costs while simultaneously ensuring interconnect performance and thermal reliability. The first phase optimizes layer allocation by focusing on the number of through-silicon vias (TSVs), reducing the number of TSVs required for cross-layer interconnects from the outset, thus lowering process complexity and manufacturing costs. The second phase leverages the size differences between functional modules and TSVs, optimizing module layout before inserting TSVs into blank areas. This avoids the space explosion problem caused by treating a large number of TSVs as independent optimization variables and fully utilizes the blank areas naturally formed after module layout, improving space utilization. The third phase optimizes temperature by targeting the three-dimensional thermal aggregation index, effectively reducing localized heat accumulation in the system and improving chip thermal reliability.

[0044] This embodiment provides another method for optimizing the layout of three-dimensional integrated circuits. Figure 3 This is a second flowchart of a three-dimensional integrated circuit layout optimization method according to an embodiment of the present invention, as follows: Figure 3 As shown, the process includes the following steps: Step S301: With minimizing the number of through-silicon vias as the optimization objective, based on the interconnection network relationship between functional modules, the functional module group with strong interconnection relationship is assigned to the same layer of the three-dimensional integrated circuit, and the interconnection information of functional modules and through-silicon vias of each layer is decoupled and generated.

[0045] Furthermore, this embodiment aims to minimize the number of through-silicon vias (TSVs) and allocates layers based on the interconnection network relationships between functional modules. In 3D integrated circuits, the connection relationships between functional modules determine the signal transmission path. If a group of modules with strong connections is allocated to different layers, a large number of TSVs will be required for cross-layer interconnection, which not only increases process complexity but also leads to longer signal paths. Therefore, this embodiment allocates groups of functional modules with strong connections to the same layer of the 3D integrated circuit based on the interconnection network relationships between functional modules, reducing the number of TSVs required from the source. After the layer allocation is completed, the original overall interconnection network data is decoupled into independent interconnection information for each layer, including the number, size, and power consumption of functional modules in each layer, as well as the TSV information that each layer needs to connect. This decoupling operation breaks down the global optimization problem into multiple local sub-problems, laying the foundation for subsequent independent optimization of each layer.

[0046] In other words, the first stage (step S301) of this embodiment allocates functional module layers in the 3D integrated circuit based on the interconnection network relationship between functional modules, with the optimization target being the number of through-silicon vias (TSVs) in the system. Since the optimization space constraints for line length and temperature differ significantly, for multi-module systems, line length strongly depends on the connection relationship between functional modules. If highly interconnected modules are allocated to different layers, the resulting loss of connection resources is difficult to compensate for in subsequent optimizations. Temperature, on the other hand, has a larger optimization solution space (taking the n300-4layer dataset as an example, each layer has approximately 75 functional modules, providing ample space for exchange. The n300-4layer dataset refers to the n300 dataset in the GSRC benchmark test set selected in the experiment, set as a 4-layer stacked structure. n300 represents the number of functional modules contained in this test set as 300, with approximately 75 modules per layer in the 4-layer setting). Changes in the position of module layers within the same interconnection network directly lead to significant changes in the interconnection path length and the number of TSVs, playing a decisive role in the overall line length optimization result. Therefore, in the first stage, the number of TSVs is used as the optimization target to complete the layer allocation of all functional modules, and the original overall interconnect data information is decoupled into the number, size, power consumption and interconnect information of each layer's functional modules and through-silicon vias, so as to generate input files for the layer optimization in the second stage.

[0047] Step S302: Based on the interconnection information of each layer of functional modules and through-silicon vias, for each layer of functional modules that have completed layer allocation, an ordered binary tree is constructed to represent the layout structure of each layer of functional modules. The structure of the ordered binary tree is iteratively updated using various perturbation operations to generate non-overlapping two-dimensional planar layout coordinates for each layer.

[0048] Furthermore, based on the interconnection information generated in step S301, this embodiment constructs an ordered binary tree to represent the layout structure of each functional module for the completed layer allocation. The structure of the ordered binary tree is iteratively updated using various perturbation operations to generate non-overlapping two-dimensional planar layout coordinates for each layer. An ordered binary tree is an efficient layout representation method. Its root node corresponds to the functional module in the lower left corner, with coordinates (0,0). If node nj is the left child of node ni, then module bj is placed to the right and adjacent to module bi; if node nj is the right child of node ni, then module bj is placed above module bi with equal x-coordinates. Given a tree, the coordinates of all modules can be uniquely determined. By iteratively optimizing the binary tree structure, a compact and non-overlapping two-dimensional planar layout can be generated.

[0049] In one optional implementation, step S302 includes: For each functional module that has been assigned to a layer, an ordered binary tree is constructed to represent the layout structure of each functional module in order to generate the initial layout coordinates. Within the framework of simulated annealing, various perturbation operations are performed on the ordered binary tree to update its structure; After each perturbation, the coordinates of each functional module are reconstructed based on the updated binary tree structure to generate a non-overlapping two-dimensional planar layout. Iteratively execute the above construction, perturbation and reconstruction steps until the preset termination condition is met, and output the optimized two-dimensional planar layout coordinates of each functional module.

[0050] Furthermore, in this embodiment, for each functional module whose layer allocation has been completed, an ordered binary tree is constructed to represent the layout structure of each functional module, thereby generating initial layout coordinates. Under the simulated annealing framework, various perturbation operations are performed on the ordered binary tree to update its structure. The simulated annealing algorithm mimics the annealing principle in metallurgy, accepting deterioration with a higher probability at high temperatures to achieve global search; as the temperature decreases, the probability of accepting deterioration gradually decreases, enhancing local search capabilities. The perturbation operations include three types: rotation (simulating a 90-degree rotation of a module), swapping (exchanging the relative positions of two nodes), and transfer (removing a node from its current position and attaching it to another node), used to explore different layout possibilities. After each perturbation, the coordinates of each functional module are reconstructed based on the updated binary tree structure, generating a non-overlapping two-dimensional planar layout. The reconstruction function automatically calculates the compact coordinates of all modules based on the structural constraints of the binary tree, ensuring that the layout is non-overlapping. The process iteratively executes the above construction, perturbation, and reconstruction steps until a preset termination condition is met (such as the temperature dropping to a threshold, the number of iterations reaching an upper limit, or the layout quality converging), outputting the optimized two-dimensional planar layout coordinates of each layer's functional modules. This process effectively avoids layout congestion or excessively long interconnect paths caused by initial solution deviations.

[0051] Step S303: Based on the optimized two-dimensional planar layout coordinates of each functional module, obtain the distribution characteristics of the blank areas formed after the layout of each functional module.

[0052] Furthermore, this embodiment analyzes and extracts the distribution characteristics of blank areas formed after the functional modules are laid out, based on the optimized two-dimensional planar layout coordinates of each layer of functional modules output in step S302. Blank areas refer to the unoccupied spaces naturally formed after the functional modules are laid out; these areas are ideal locations for subsequent insertion of through-silicon vias (TSVs). Due to the significant difference in physical dimensions between functional modules and TSVs, the module area is typically tens to hundreds of times larger than the TSV area, inevitably resulting in a large number of irregularly distributed blank areas after module layout. This embodiment identifies the location, shape, and size of these blank areas to establish a distribution characteristic map of blank areas in each layer, providing a spatial basis for the reasonable insertion of subsequent TSVs. The strategy of first laying out modules and then identifying blank areas in this embodiment fully utilizes the space resources naturally formed after module layout, avoids disrupting the compact module layout to reserve TSV positions, and improves space utilization.

[0053] Step S304: Following the order from the lowest layer to the highest layer, based on the distribution characteristics of the blank areas formed after the functional modules of each layer are laid out, through-silicon vias are inserted layer by layer, and the position information of the through-silicon vias already inserted in the lower layer is used as the reference input for the layout optimization of the higher layer, so as to obtain the initial position information of each layer of functional modules and each layer of through-silicon vias.

[0054] Furthermore, in this embodiment, following the order from the lowest layer to the highest layer, based on the distribution characteristics of the blank areas of each layer obtained in step S303, through-silicon vias (TSVs) are inserted layer by layer. The position information of the TSVs already inserted in the lower layers is used as a reference input for the layout optimization of the higher layers, thereby obtaining the initial position information of each layer's functional modules and each layer's TSVs. This strategy of passing position information from the bottom layer upwards is because the position of the lower-layer TSVs directly determines the anchor points that the higher-layer modules need to reference for establishing connections.

[0055] In one optional implementation, step S304 includes: For the blank areas formed after the layout of the current layer functional modules, the insertion priority of each blank area is determined based on the distribution characteristics of the blank areas and the connection requirements of the through silicon vias to be inserted. For a through-silicon via (TSV) that needs to be inserted into the current layer, select a location in the blank area that satisfies the connection constraints based on the locations of the upper and lower functional modules connected to the TSV; After completing the insertion of through-silicon vias in the current layer, update the position information of the inserted through-silicon vias to the input file of the higher layer layout as a reference constraint for the layout optimization of the higher layer functional modules. The above insertion process is performed iteratively layer by layer until all layers have had through-silicon vias inserted.

[0056] Furthermore, in this embodiment, for the blank areas formed after the current layer functional module layout, the insertion priority of each blank area is determined based on the distribution characteristics of the blank areas and the connection requirements of the through-silicon vias (TSVs). The distribution characteristics of the blank areas include their position, shape, and size, while the connection requirements depend on the specific positions of the upper and lower layer functional modules that the TSV needs to connect to. For TSVs that need to be inserted in the current layer, positions that meet the connection constraints are selected from the blank areas for insertion based on the positions of the upper and lower layer functional modules that the TSV connects to. The connection constraints require that the position of the TSV can simultaneously establish effective electrical connections with the target modules of the upper and lower layers. After the insertion of the TSVs in the current layer is completed, the position information of the inserted TSVs is updated to the input file of the higher-level layout as a reference constraint for the layout optimization of the higher-level functional modules. This means that when the higher-level modules perform layout optimization, since they need to calculate the wiring length based on the position of the lower-level TSVs as an optimization indicator, they can insert TSVs layer by layer and use the position information of the lower-level inserted TSVs as a reference input for the higher-level layout optimization, that is, they need to refer to the position of the lower-level TSVs. The above insertion process is executed iteratively layer by layer until all layers of through-silicon vias are inserted, and finally the initial position information of each layer's functional modules and each layer's through-silicon vias is obtained.

[0057] In other words, the second stage (steps S302 to S304) of this embodiment takes into account the significant differences in physical dimensions between functional modules and through-silicon vias (TSVs) in the 3D integrated circuit system. Therefore, the layout of functional modules with larger footprints is optimized first. The positions of the functional modules are generated using a simulated annealing method. By simulating the temperature drop mechanism during physical annealing, the problem of getting trapped in local optima is effectively avoided, reducing layout congestion or excessively long interconnect paths caused by initial solution deviations. Subsequently, a centroid-based greedy algorithm is used to insert TSVs into the blank areas formed after the functional module layout, which can flexibly adapt to irregular spaces. Figure 4 The diagram illustrates a comparison between joint optimization of functional modules and through-silicon vias (TSVs) and two-stage optimization. The process starts from the lowest layer. After obtaining the location information of the functional modules and TSVs in the lower layers, this information is updated in the layout input file of the higher layers. This is because the TSVs in the lower layers connect the higher and lower layers, and their locations provide inspiration for the layout optimization of the higher layers. After the second stage, the location information of the functional modules and TSVs in each layer is obtained and used as the input file for the third stage of inter-layer joint optimization. Figure 4Figure 4a illustrates how, during joint optimization, through-silicon vias (TSVs) are treated as equivalent to functional modules for placement. These modules are distributed with rectangles of varying sizes (representing functional modules, such as M1 to M4) and numerous densely packed small squares (representing TSVs). Modules and TSVs are mixed together; TSVs are scattered between modules and even occupy space that could have been used for modules, resulting in a less compact module arrangement, blank areas being squeezed out by TSVs, and size differences leading to low area utilization. Figure 4 Figure 4b illustrates the two-stage optimization approach, which first considers the layout of functional modules. The modules are initially arranged, creating natural, irregular blank areas between them. Then, TSVs are inserted into these blank areas. The TSVs appear only in the blank spaces, without interfering with the compact layout of the modules. This not only reduces computational load but also provides sufficient blank space for through-silicon vias (TSVs), significantly improving space utilization.

[0058] Step S305: Based on the initial position information of each functional module and each through-silicon via obtained, the three-dimensional thermal aggregation index is used as the optimization target. The interlayer joint temperature optimization is performed by iteratively exchanging the positions of functional modules to obtain the final layout. The three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

[0059] Furthermore, based on the initial position information of each functional module and each through-silicon via obtained in step S304, this embodiment uses the three-dimensional thermal aggregation index as the optimization target, and performs inter-layer joint temperature optimization by iteratively exchanging the positions of functional modules to obtain the final layout. The three-dimensional thermal aggregation index is a quantitative index constructed based on the electron potential energy model, used to characterize the overall thermal aggregation of three-dimensional integrated circuits. Its core idea is that functional modules that are closer together and have higher power consumption contribute more to the index. When high-power modules are stacked in the vertical direction or aggregated in the horizontal direction, the index will increase significantly, reflecting the risk of local hot spots.

[0060] In an optional implementation, before performing interlayer joint temperature optimization by iteratively exchanging the positions of functional modules in step S305, this embodiment further divides each layer into several grid points and calculates the joint temperature index of each grid point; the joint temperature index is jointly determined by the power consumption weighted value of the layer where the grid point is located and the power consumption coupling value between the grid point and the corresponding grid points in the adjacent layer.

[0061] Furthermore, in this embodiment, each layer is divided into several grid points, and the interlayer temperature index of each grid point is calculated. A grid point is a virtual sampling point obtained by meshing a two-dimensional plane, used for discretization of the temperature field analysis. The interlayer temperature index is determined by two parts: first, the power consumption weighting value of the layer where the grid point is located, with layers farther from the heat sink having a larger weight because their heat is more difficult to dissipate; second, the power consumption coupling value between the grid point and the corresponding grid points in adjacent layers, used to characterize the degree of vertical heat accumulation.

[0062] In one alternative implementation, the interlayer joint temperature optimization, achieved by iteratively swapping the positions of functional modules to obtain the final layout, includes: For each functional module, the sum of the layer temperature indices of all grid points covered by that functional module is calculated and used as the temperature index of the current functional module. Within the current layer, the target functional module with the highest temperature index is selected, and the matching coefficient between other functional modules in the current layer and the target functional module is calculated. The candidate functional module with the highest matching coefficient is selected for exchange attempt. The matching coefficient is determined based on the area difference and power consumption difference between functional modules. After swapping the positions of the functional modules, calculate the three-dimensional heat zone aggregation index after the swap. If the three-dimensional heat zone aggregation index decreases, accept the swap; otherwise, retain the original layout. Based on the results of the swaps and retentions, the final layout is obtained.

[0063] Furthermore, in this embodiment, for each functional module, the sum of the layer temperature indices of all grid points covered by that functional module is calculated as the temperature index of the current functional module. Since each functional module typically covers multiple grid points, this index can comprehensively reflect the module's own heat generation and its thermal coupling effect with surrounding modules. The target functional module with the highest temperature index is selected within the current layer, and the matching coefficient between other functional modules in the current layer and the target functional module is calculated. The candidate functional module with the highest matching coefficient is selected for an exchange attempt. The matching coefficient is determined based on the area and power consumption differences between functional modules. Exchanging modules with similar areas and power consumption has less impact on the layout and makes thermal optimization easier. After exchanging the functional modules, the three-dimensional thermal clustering index is calculated. If the index decreases, the exchange is accepted; otherwise, the original layout is retained. By using the three-dimensional thermal clustering index as a criterion, it is ensured that each exchange is directed towards improving the overall heat distribution. Based on the exchange and retention results, the final layout is obtained. By iteratively executing the above screening, exchange, and judgment process, the high-power modules that are vertically clustered are gradually dismantled, making the heat distribution more uniform. Ultimately, while ensuring the optimization of line length and TSV number, a final layout with better thermal reliability is obtained.

[0064] In other words, since the first two stages only considered the optimization of through-silicon vias and line lengths, local overheating problems may occur in the system due to the clustering of high-power modules after the second stage. Therefore, the third stage (step S305) of this embodiment uses interlayer joint optimization for temperature control. This embodiment proposes the concept of a three-dimensional thermal clustering index based on the electronic potential energy model, using a potential energy-like model to characterize the overall thermal situation of the system, and taking this as the overall optimization target. C Obtain it using the following formula: ; in, P m The power density of functional module m, P n For functional modules n power density, x m , y m , z m For functional modules m The three-dimensional coordinates z Coordinates correspond to the layer position. x n , y n , z n For functional modules m The three-dimensional coordinates γ The weighting parameters are assigned to the layer differences.

[0065] Next, during the optimization process, a layer temperature index for each grid point is proposed to characterize the temperature and aggregation of each unit grid point. Layer Temperature Index H(i,j) Obtain it using the following formula: ; in, (i,j) For the coordinates of the calculated points, k For the number of floors, n The total number of layers in the system. P k (i,j) For the first k upper layer (i,j) Power density of functional modules at coordinate locations W k The weight parameters to be assigned to this layer itself.

[0066] Layer temperature index H(i,j) The first part of the formula represents the weighted sum of power consumption; the further away from the heatsink the layer is, the greater its power consumption weight, because its heat is more difficult to dissipate; the interlayer temperature index H(i,j) The latter part of the formula characterizes the vertical clustering degree of high-power modules by accumulating the power consumption products of adjacent layers. For each functional module, the sum of the layer temperature indices of its total occupied grid points is calculated as the temperature index of that module, which is used as the criterion for module movement. Functional Module m Module temperature index G m Obtain it using the following formula: ; in, A m For functional modulesm Area occupied, module temperature index G m The meaning is for functional modules m Area occupied A m All coordinate points within H Sum.

[0067] For each functional module with the highest temperature index in each layer, calculate the matching coefficient of the remaining modules in that layer, and attempt to swap it with the candidate module with the highest matching degree. After the swap, calculate the new three-dimensional thermal zone index as the iterative criterion. Matching coefficient L n Obtain it using the following formula: ; in, α To assign weighting parameters to the area differences, β Weighting parameters are assigned to the power density difference.

[0068] Please see Figure 5 The schematic diagram shown illustrates the characteristics of the interlayer temperature index, including the distance between the heat layer and the heat sink, and the interlayer distribution of the heat layer. Figure 5 In the red and green layered structure, red represents heat and green represents cold, visually demonstrating the impact of the distance between the heat layers and the radiator on heat distribution, as well as the impact of the distance between heat layers on heat distribution. Please see [link / reference]. Figure 6 The diagram shows a three-dimensional heat distribution, with a color gradient from blue (low temperature) to red (high temperature) representing power density. Different layers, L0, L1, L2, and L3, are labeled, along with the locations of the Lmax and Gmax modules. The left side shows the power distribution before optimization, and the right side shows the state after module swapping optimization. The power distribution at layer L3 shows a significant change, indicating that swapping modules with higher temperature performance effectively improved the vertical heat accumulation.

[0069] Please see Figure 7 The diagram illustrates a third flowchart of a three-dimensional integrated circuit layout optimization method. The left side shows the layout optimization path, and the right side shows the temperature evaluation iteration path. The layout optimization path begins with module layer allocation, with the explicit goal of minimizing the number of TSVs. Subsequently, sub-network decomposition is performed to decouple the overall problem. Next, single-layer layout optimization is performed on each sub-network, aiming to reduce the bus length of each layer. This stage includes two key sub-steps: module layout (fast annealing) and TSV layout (greedy algorithm). The right side shows the temperature control and iteration process. First, the configuration files for each layer are updated based on the layout results from the left side. Then, the evaluation loop is entered to calculate the overall three-dimensional thermal clustering index. C Longitudinal temperature index of grid points H and the temperature specifications of each module Gm These metrics characterize the overall heat accumulation and local temperature distribution of the system. Subsequently, iterative operations are performed based on the calculation results: calculating the matching value L of each layer module based on the Gmax module, and exchanging Gmax-Lmax modules. Finally, the entire process determines whether to terminate the iteration by judging whether the three-dimensional thermal aggregation index C meets the requirements, thereby obtaining the final layout.

[0070] In summary, this embodiment first considers the significant difference in physical dimensions between functional modules and TSVs in 3D integrated circuits. The area of ​​a functional module is typically tens to hundreds of times larger than that of a TSV, and their layout space requirements and constraints are fundamentally different. Based on this, this embodiment adopts a phased optimization strategy: first, the layout optimization of functional modules with larger space requirements is performed; after the positions of the functional modules are fixed, the layout optimization of TSVs is carried out using the naturally formed staggered blank areas between modules. This approach significantly improves optimization efficiency without affecting overall performance.

[0071] Secondly, this embodiment improves upon the traditional layer-by-layer optimization framework. Analysis of the constraint characteristics of different performance indicators reveals that the core influencing factor for line length is the connection relationship between functional modules, and this relationship is highly specific; changes in module position within the same interconnect network directly lead to significant changes in interconnect path length, making its optimization constraints irreplaceable. Conversely, the core influencing factor for temperature is the power consumption distribution of functional modules, and this power consumption distribution is highly adjustable during the layer allocation stage. Based on the above analysis, this embodiment temporarily disregards temperature factors during the layer allocation stage, thereby significantly reducing the computational burden of temperature field simulation and avoiding the problem of ambiguous optimization direction due to an excessively large temperature solution space. Furthermore, to further improve the heat dissipation performance of the three-dimensional integrated circuit, this embodiment introduces a potential energy-like model based on electron potential energy (i.e., a three-dimensional thermal clustering index) to perform secondary adjustments to the local layout, focusing on solving the local overheating problem caused by the clustering of high-power modules.

[0072] In the layout optimization process, this embodiment uses the simulated annealing algorithm as the basic optimization framework. The simulated annealing algorithm mimics the annealing principle in metallurgical processes, analogizing the optimization process to finding the lowest energy state of the system. At high temperatures, due to the strong perturbation ability of molecules, the algorithm has a high tolerance for poor states and can perform a global random search within a given state space, thus having a high probability of escaping local optima. As the temperature gradually decreases, the perturbation ability of molecules weakens, the tolerance for poor states decreases accordingly, the global random search ability decreases, and the local optima search ability increases accordingly, eventually converging to the vicinity of the optimal solution.

[0073] To efficiently represent the two-dimensional layout, this embodiment models the layout of functional modules by constructing an ordered binary tree. The root node of this ordered binary tree corresponds to the functional module in the lower left corner, with coordinates (0, 0). If node nj is the left child of node ni, then functional module bj is placed to the right of bi and adjacent to it, i.e., xj = xi + wi, where xi represents the lower left x-coordinate of functional module bi corresponding to node ni, xj represents the lower left x-coordinate of functional module bj corresponding to node nj, and wi represents the width of functional module bi corresponding to node ni. If node nj is the right child of node ni, then functional module bj is placed above bi, and the x-coordinate of bj is equal to the x-coordinate of bi, i.e., xj = xi. Therefore, given an ordered binary tree, the coordinates of all functional modules can be uniquely determined. The layout of the entire system can be fully characterized by a tree and the attributes of its nodes.

[0074] During simulated annealing, three perturbation operations can be applied to the structure of an ordered binary tree: rotation, swap, and transition. Rotation simulates rotating a functional module by 90 degrees; swapping involves exchanging the relative positions of two nodes; and transitioning involves removing a specified node from its current position in the tree and grafting it to the left or right of another node. After each perturbation, the tree structure or node properties change, and a completely new, compact, non-overlapping two-dimensional planar layout coordinate system can be calculated using the reconstruct function.

[0075] The above embodiments are further illustrated by the following simple examples: To verify the effectiveness of this embodiment, this example implements the overall optimization algorithm using the Python programming language and conducts experimental verification using the GSRC benchmark dataset. The core physical parameters are set as follows: the aspect ratio is set to 1:1, the blank area ratio is set to 15%, the through-silicon via (TSV) size is uniformly set to 3μm×3μm, and the ambient temperature is set to 293K. Experiments were conducted on three datasets (n100, n200, and n300) from the GSRC benchmark dataset, with two stacking structures of 3 and 4 layers respectively, for a total of 6 sets of experiments. The core evaluation indicators were system line length, number of TSVs, highest temperature, and lowest temperature. The line length was calculated using the half-perimeter between functional module locations, and the temperature was simulated using the thermal modeling and simulation tool Hotspot. Table 1 shows the optimization results of this embodiment under different datasets.

[0076] Table 1

[0077] Table 2 shows a comparison of the optimization results of this embodiment and related technologies on different datasets.

[0078] Table 2

[0079] As shown in Table 2, regarding the optimization effects on line length and the number of through-silicon vias (TSVs), the overall system line length and number of TSVs obtained in this embodiment are lower than those of related technologies in all test scenarios. Furthermore, the optimization advantage increases significantly with the increase in the number of functional modules and stacking layers. Taking the n300 dataset as an example, with a 3-layer stacking configuration, the line length obtained in this embodiment is reduced by 21.7% compared to related technologies, and the number of TSVs is reduced by 14.8%. With a 4-layer stacking configuration, the line length is reduced by 29.0% compared to related technologies, and the number of TSVs is reduced by 27.7%.

[0080] Please see Figure 8 The temperature cloud diagram shown illustrates the layout of the N300 dataset with a 4-layer configuration, demonstrating the final layout effect and intuitively presenting the system temperature distribution under the N300 dataset and a 4-layer stacking configuration. Figure 8 The structure comprises four two-dimensional grids, labeled Layer 0 to Layer 3, each covered with fine grid lines representing spatial coordinates or sampling points. Temperature is represented by a color gradient, with a color bar on the right serving as a temperature reference, ranging from approximately 25.4°C (blue) to 41.8°C (red). From Layer 0 to Layer 3, the temperature distribution pattern changes significantly. Layer 0 shows a relatively wide high-temperature region (red / orange), while the temperature distribution becomes more dispersed as the layer number increases. In particular, compared to before optimization, there is no obvious clustering of high-temperature regions vertically, demonstrating that the heat generated by the high-power modules can be dissipated more efficiently to the outside of the system, achieving effective temperature performance control. Regarding temperature control, this embodiment keeps the system temperature within an acceptable range. In most datasets, the achieved system maximum temperature is lower than that of related technologies; the minimum temperature is slightly higher. This is due to the introduction of vertical heat distribution considerations. Optimization of the three-dimensional heat zone clustering index makes the distribution of high-power modules more balanced, avoiding excessive concentration of local hot spots. Figure 8 It is evident that there is no high-temperature area accumulation in the vertical direction, and the heat generated by the high-power module can be dissipated to the external heat sink more efficiently, ultimately achieving effective control of temperature performance.

[0081] In summary, firstly, this embodiment employs a phased optimization strategy, addressing the problem of dimensional explosion in solution space caused by the significant size difference between TSVs and functional modules in related technologies by first laying out modules and then inserting TSVs. This embodiment first optimizes the layout of functional modules with high space requirements; after fixing their positions, it utilizes the naturally formed staggered blank areas between modules for TSV layout optimization. This not only reduces computational load but also provides sufficient staggered blank areas for TSV placement, greatly improving space utilization. Secondly, this embodiment allocates groups of strongly connected functional modules to the same layer based on the interconnection network relationships between functional modules, effectively minimizing the number of through-silicon vias (TSVs) and reducing chip area overhead. Simultaneously, by employing a simulated annealing algorithm combined with ordered binary tree modeling, and through perturbation operations such as rotation, swapping, and transition, it effectively avoids getting trapped in local optima, generating a compact, non-overlapping two-dimensional planar layout. Furthermore, this embodiment limits TSV insertion to starting from the lowest layer and uses position information as input for higher layers, achieving collaborative optimization of inter-layer connections. Finally, this embodiment introduces a three-dimensional thermal clustering index, using a potential energy-like model to characterize the overall thermal situation of the system. By calculating the layer temperature index and iteratively swapping the positions of high-power modules, the system avoids the accumulation of high-temperature areas in the vertical direction. This allows the heat generated by the high-power modules to be dissipated to the outside of the system more efficiently, ultimately achieving effective control of the system's temperature performance.

[0082] This embodiment also provides a three-dimensional integrated circuit layout optimization system, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0083] This embodiment provides a three-dimensional integrated circuit layout optimization system, such as Figure 9 As shown, it includes: The layer allocation module 901 is used to allocate functional modules to each layer of the three-dimensional integrated circuit with the number of through silicon vias as the optimization target, and to decouple and generate interconnection information of functional modules and through silicon vias in each layer. The in-layer layout optimization module 902 is connected to the layer allocation module 901. It is used to perform two-dimensional layout optimization on the functional modules of each layer that have been allocated based on the interconnection information of the functional modules and through-silicon vias, and to insert through-silicon vias in the blank areas formed after the functional modules are laid out, so as to obtain the initial position information of each functional module and each through-silicon via. Temperature optimization module 903, connected to layout optimization module 902 within the same layer, is used to perform interlayer joint temperature optimization based on the initial position information of the functional modules and through-silicon vias of each layer, with the three-dimensional thermal aggregation index as the optimization target, by iteratively exchanging the positions of functional modules to obtain the final layout; the three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

[0084] In some alternative implementations, the layer allocation module 901 is further configured to: With minimizing the number of through-silicon vias as the optimization objective, functional modules with strong interconnections are assigned to the same layer of the 3D integrated circuit based on the interconnection network relationship between functional modules.

[0085] In some optional implementations, the in-layer layout optimization module 902 is further configured to: For each functional module that has been assigned to a layer, an ordered binary tree is constructed to represent the layout structure of each functional module. The structure of the ordered binary tree is iteratively updated using various perturbation operations to generate the non-overlapping two-dimensional planar layout coordinates of each layer.

[0086] In some optional implementations, the in-layer layout optimization module 902 is further configured to: For each functional module that has been assigned to a layer, an ordered binary tree is constructed to represent the layout structure of each functional module in order to generate the initial layout coordinates. Within the framework of simulated annealing, various perturbation operations are performed on the ordered binary tree to update its structure; After each perturbation, the coordinates of each functional module are reconstructed based on the updated binary tree structure to generate a non-overlapping two-dimensional planar layout. Iteratively execute the above construction, perturbation and reconstruction steps until the preset termination condition is met, and output the optimized two-dimensional planar layout coordinates of each functional module.

[0087] In some optional implementations, the in-layer layout optimization module 902 is further configured to: Based on the optimized two-dimensional planar layout coordinates of each functional module, the distribution characteristics of the blank areas formed after the layout of each functional module are obtained. Following the order from the lowest to the highest layer, based on the distribution characteristics of the blank areas formed after the functional modules of each layer are laid out, through-silicon vias are inserted layer by layer, and the position information of the through-silicon vias already inserted in the lower layer is used as a reference input for the layout optimization of the higher layer.

[0088] In some optional implementations, the in-layer layout optimization module 902 is further configured to: For the blank areas formed after the layout of the current layer functional modules, the insertion priority of each blank area is determined based on the distribution characteristics of the blank areas and the connection requirements of the through silicon vias to be inserted. For a through-silicon via (TSV) that needs to be inserted into the current layer, select a location in the blank area that satisfies the connection constraints based on the locations of the upper and lower functional modules connected to the TSV; After completing the insertion of through-silicon vias in the current layer, update the position information of the inserted through-silicon vias to the input file of the higher layer layout as a reference constraint for the layout optimization of the higher layer functional modules. The above insertion process is performed iteratively layer by layer until all layers have had through-silicon vias inserted.

[0089] In some alternative implementations, the system is also used for: Before performing interlayer joint temperature optimization by iteratively exchanging the positions of functional modules, each layer is divided into several grid points, and the joint temperature index of each grid point is calculated. The joint temperature index is determined by the power consumption weighted value of the layer where the grid point is located and the power consumption coupling value between the grid point and the corresponding grid points in the adjacent layer.

[0090] In some alternative implementations, the temperature optimization module 903 is further configured to: For each functional module, the sum of the layer temperature indices of all grid points covered by that functional module is calculated and used as the temperature index of the current functional module. Within the current layer, the target functional module with the highest temperature index is selected, and the matching coefficient between other functional modules in the current layer and the target functional module is calculated. The candidate functional module with the highest matching coefficient is selected for exchange attempt. The matching coefficient is determined based on the area difference and power consumption difference between functional modules. After swapping the positions of the functional modules, calculate the three-dimensional heat zone aggregation index after the swap. If the three-dimensional heat zone aggregation index decreases, accept the swap; otherwise, retain the original layout. Based on the results of the swaps and retentions, the final layout is obtained.

[0091] Furthermore, the system may also include: The data acquisition module, connected to the layer allocation module 901, is used to acquire the interconnection network information, power consumption information and physical size information of the functional modules; And an output module, connected to the temperature optimization module 903, for outputting the final layout result.

[0092] Among them, the interconnection network information is used to determine the connection relationship between functional modules, thereby allocating strongly connected modules to the same layer; although the first stage does not use power consumption information as the optimization target, power consumption information needs to be passed to subsequent stages, such as temperature optimization; physical size information is the size of each layer of functional modules, so that it can be used for subsequent two-dimensional layout optimization.

[0093] The three-dimensional integrated circuit layout optimization system provided in this embodiment of the invention can execute the three-dimensional integrated circuit layout optimization method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method. Further functional descriptions of the various modules and units are the same as in the corresponding embodiments described above, and will not be repeated here.

[0094] In summary, firstly, this embodiment employs a phased optimization strategy, addressing the problem of dimensional explosion in solution space caused by the significant size difference between TSVs and functional modules in related technologies by first laying out modules and then inserting TSVs. This embodiment first optimizes the layout of functional modules with high space requirements; after fixing their positions, it utilizes the naturally formed staggered blank areas between modules for TSV layout optimization. This not only reduces computational load but also provides sufficient staggered blank areas for TSV placement, greatly improving space utilization. Secondly, this embodiment allocates groups of strongly connected functional modules to the same layer based on the interconnection network relationships between functional modules, effectively minimizing the number of through-silicon vias (TSVs) and reducing chip area overhead. Simultaneously, by employing a simulated annealing algorithm combined with ordered binary tree modeling, and through perturbation operations such as rotation, swapping, and transition, it effectively avoids getting trapped in local optima, generating a compact, non-overlapping two-dimensional planar layout. Furthermore, this embodiment limits TSV insertion to starting from the lowest layer and uses position information as input for higher layers, achieving collaborative optimization of inter-layer connections. Finally, this embodiment introduces a three-dimensional thermal clustering index, using a potential energy-like model to characterize the overall thermal situation of the system. By calculating the layer temperature index and iteratively swapping the positions of high-power modules, the system avoids the accumulation of high-temperature areas in the vertical direction. This allows the heat generated by the high-power modules to be dissipated to the outside of the system more efficiently, ultimately achieving effective control of the system's temperature performance.

[0095] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0096] The following is a detailed reference. Figure 10 This diagram illustrates a suitable structural schematic for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from memory 1008 into random access memory (RAM) 1003. The RAM 1003 also stores various programs and data required for the operation of the electronic device. The processor 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0097] Typically, the following devices can be connected to the I / O interface 1005: input devices 1006 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 1007 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; memory devices 1008 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows electronic devices to exchange data via wireless or wired communication with other devices. Although Figure 10 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0098] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 1009, or installed from a memory 1008, or installed from a ROM 1002. When the computer program is executed by the processor 1001, it performs the functions defined in the XX method of the embodiments of the present invention.

[0099] Figure 10 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0100] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, it implements the three-dimensional integrated circuit layout optimization method shown in the above embodiments.

[0101] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0102] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the invention.

Claims

1. A three-dimensional integrated circuit layout optimization method, characterized in that, The method includes: With the number of through-silicon vias as the optimization target, functional modules are allocated to each layer of the 3D integrated circuit, and the interconnection information of functional modules and through-silicon vias in each layer is decoupled and generated. Based on the interconnection information of the functional modules and through-silicon vias, the two-dimensional layout optimization of the functional modules that have been assigned layers is performed, and through-silicon vias are inserted in the blank areas formed after the functional module layout optimization to obtain the initial position information of each functional module and each through-silicon via. Based on the initial position information of each layer of functional modules and each layer of through-silicon vias, the three-dimensional thermal aggregation index is used as the optimization target. Interlayer joint temperature optimization is performed by iteratively exchanging the positions of functional modules to obtain the final layout. The three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

2. The method according to claim 1, characterized in that, The method of allocating functional modules to the layers of a three-dimensional integrated circuit, with the number of through-silicon vias as the optimization objective, includes: With minimizing the number of through-silicon vias as the optimization objective, functional modules with strong interconnections are assigned to the same layer of the 3D integrated circuit based on the interconnection network relationship between functional modules.

3. The method according to claim 1, characterized in that, The optimization of the two-dimensional layout of the functional modules of each layer that have been assigned layers includes: For each functional module that has been assigned to a layer, an ordered binary tree is constructed to represent the layout structure of each functional module. The structure of the ordered binary tree is iteratively updated using various perturbation operations to generate non-overlapping two-dimensional planar layout coordinates for each layer.

4. The method according to claim 3, characterized in that, The process involves constructing an ordered binary tree to represent the layout structure of functional modules at each layer, iteratively updating the structure of the ordered binary tree using various perturbation operations, and generating non-overlapping two-dimensional planar layout coordinates for each layer, including: An ordered binary tree is constructed to represent the layout structure of each functional module to generate initial layout coordinates; Within the framework of simulated annealing, various perturbation operations are performed on the ordered binary tree to update the binary tree structure; After each perturbation, the coordinates of each functional module are reconstructed based on the updated binary tree structure to generate a non-overlapping two-dimensional planar layout. Iteratively execute the above construction, perturbation and reconstruction steps until the preset termination condition is met, and output the optimized two-dimensional planar layout coordinates of each functional module.

5. The method according to claim 4, characterized in that, Inserting through-silicon vias in the blank areas formed after the functional module layout includes: Based on the optimized two-dimensional planar layout coordinates of each layer of functional modules, the distribution characteristics of the blank areas formed after the layout of each layer of functional modules are obtained. Following the order from the lowest to the highest layer, based on the distribution characteristics of the blank areas formed after the functional modules of each layer are laid out, through-silicon vias are inserted layer by layer, and the position information of the through-silicon vias already inserted in the lower layer is used as a reference input for the layout optimization of the higher layer.

6. The method according to claim 5, characterized in that, Based on the distribution characteristics of the blank areas formed after the layout of the functional modules at each layer, through-silicon vias (TSVs) are inserted layer by layer, and the position information of the TSVs already inserted in the lower layers is used as a reference input for the layout optimization of the higher layers, including: For the blank areas formed after the layout of the current layer functional modules, the insertion priority of each blank area is determined based on the distribution characteristics of the blank areas and the connection requirements of the through silicon vias to be inserted. Based on the insertion priority, for a through-silicon via (TSV) that needs to be inserted in the current layer, the position that satisfies the connection constraints is selected from the blank area according to the positions of the upper and lower functional modules connected by the TSV; After completing the insertion of through-silicon vias in the current layer, update the position information of the inserted through-silicon vias to the input file of the higher layer layout as a reference constraint for the layout optimization of the higher layer functional modules. The above insertion process is performed iteratively layer by layer until all layers have had through-silicon vias inserted.

7. The method according to any one of claims 1 to 6, characterized in that, Before performing interlayer joint temperature optimization by iteratively exchanging the positions of functional modules, the method further includes: Each layer is divided into several grid points, and the layer temperature index of each grid point is calculated. The layer temperature index is determined by the power consumption weighted value of the layer where the grid point is located and the power consumption coupling value between the grid point and the corresponding grid points in the adjacent layer. The step of optimizing the interlayer joint temperature by iteratively exchanging the positions of functional modules to obtain the final layout includes: For each functional module, the sum of the layer temperature indices of all grid points covered by the functional module is calculated as the temperature index of the current functional module; Within the current layer, the target functional module with the highest temperature index is selected, and the matching coefficient between other functional modules in the current layer and the target functional module is calculated. The candidate functional module with the highest matching coefficient is selected for exchange attempt. The matching coefficient is determined based on the area difference and power consumption difference between functional modules. After swapping the positions of the functional modules, the three-dimensional heat zone aggregation index after the swap is calculated. If the three-dimensional heat zone aggregation index decreases, the swap is accepted; otherwise, the original layout is retained. Based on the results of the swaps and retentions, the final layout is obtained.

8. A three-dimensional integrated circuit layout optimization system, characterized in that, include: The layer allocation module is used to allocate functional modules to each layer of the 3D integrated circuit with the number of through-silicon vias as the optimization target, and to decouple and generate interconnection information of functional modules and through-silicon vias for each layer. The in-layer layout optimization module is connected to the layer allocation module. It is used to perform two-dimensional layout optimization on the functional modules of each layer that have been allocated based on the interconnection information of each layer functional module and through silicon via, and to insert through silicon vias in the blank areas formed after the functional module layout, so as to obtain the initial position information of each layer functional module and each layer through silicon via. The temperature optimization module, connected to the in-layer layout optimization module, is used to perform inter-layer joint temperature optimization based on the obtained initial position information of each layer's functional modules and each layer's through-silicon vias, with the three-dimensional thermal zone aggregation index as the optimization target, by iteratively exchanging the positions of functional modules to obtain the final layout. The three-dimensional thermal aggregation index is used to characterize the overall thermal aggregation of the three-dimensional integrated circuit.

9. An electronic device, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the computer instructions to perform a three-dimensional integrated circuit layout optimization method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, include: The computer-readable storage medium stores computer instructions for causing a computer to execute a three-dimensional integrated circuit layout optimization method according to any one of claims 1 to 7.

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