Array substrate, driving method of pixel circuit, and display panel

Abstract

This invention relates to the field of display technology, and specifically discloses an array substrate, a driving method for pixel circuits, and a display panel. The array substrate includes at least one pixel circuit. The pixel circuit includes a first storage module connected between a first control terminal and a first terminal of a driving module; a second storage module connected between a second control terminal and the first terminal of the driving module; a writing module transmitting a data signal or a first power signal to the first control terminal of the driving module according to a first scan signal; a first initialization module turning on or off the connection between the second control terminal of the driving module and a first initialization signal line according to a first switch signal; and a second initialization module turning on or off the connection between the second terminal of the driving module and a second initialization signal line according to a second switch signal. The pixel circuit design on the above-mentioned array substrate uses a small number of transistors, enabling ultra-high PPI display arrangements when applied to display products.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, a driving method for pixel circuits, and a display panel. Background Technology

[0002] In recent years, VR (Virtual Reality) technology has been widely applied in various fields, and related products have gained popularity among consumers. Due to the limited layout space in VR product design, there is a technical requirement for display panels with ultra-high PPI (Pixels Per Inch). However, current mature pixel driving circuits use a large number of TFTs (Thin Film Transistors), making it impossible to achieve ultra-high PPI. Furthermore, conventional 2T1C circuit solutions suffer from display problems such as image retention and uneven display, thus failing to meet application requirements. Summary of the Invention

[0003] Therefore, it is necessary to address the problems existing in the current pixel driving circuit by providing an array substrate, a pixel circuit driving method, and a display panel.

[0004] An array substrate includes at least one pixel circuit, the pixel circuit comprising: A driving module, connected between the first power line and the light-emitting module, is used to output driving signals; the driving module includes a first control terminal and a second control terminal; A first storage module is connected between the first control terminal and the first terminal of the drive module, and is used to store voltage information between the first control terminal and the first terminal of the drive module; The second storage module is connected between the second control terminal and the first terminal of the drive module, and is used to store the voltage information between the second control terminal and the first terminal of the drive module; The writing module is connected to the first control terminal of the driving module and is used to transmit a data signal or a first power signal to the first control terminal of the driving module according to the first scan signal. The first initialization module is connected between the second control terminal of the drive module and the first initialization signal line, and is used to turn on or off the connection between the second control terminal of the drive module and the first initialization signal line according to the first switch signal; The second initialization module is connected between the second end of the drive module and the second initialization signal line, and is used to turn on or off the connection between the second end of the drive module and the second initialization signal line according to the second switch signal.

[0005] In one possible implementation, the driving module includes a first transistor, which is a dual-gate transistor. The first gate of the first transistor serves as a first control terminal of the driving module, the second gate of the first transistor serves as a second control terminal of the driving module, the first electrode of the first transistor serves as a first terminal of the driving module, and the second electrode of the first transistor serves as a second terminal of the driving module.

[0006] In one possible implementation, the first storage module includes a first capacitor, the first terminal of the first capacitor being connected to the first control terminal of the drive module as the first end of the first storage module, and the second terminal of the first capacitor being connected to the first end of the drive module as the second end of the first storage module.

[0007] In one possible implementation, the second storage module includes a second capacitor, with the first terminal of the second capacitor serving as the first end of the second storage module and connected to the second control terminal of the drive module, and the second terminal of the second capacitor serving as the second end of the second storage module and connected to the first end of the drive module.

[0008] In one possible implementation, the writing module includes a second transistor, the gate of the second transistor being connected to the first scan signal as the control terminal of the writing module, the first electrode of the second transistor being connected to the data signal or the first power signal as the first terminal of the writing module, and the second electrode of the second transistor being connected to the first control terminal of the driving module as the second terminal of the writing module.

[0009] In one possible implementation, the second transistor is a dual-gate transistor, the first gate of the second transistor is connected to the first scan signal as the control terminal of the write module, and the second gate of the second transistor is connected to the first power line or the first initialization signal line as the second control terminal of the write module.

[0010] In one possible implementation, the first initialization module includes a third transistor, the gate of which serves as the control terminal of the first initialization module and is connected to the first switch signal, the first electrode of which serves as the first terminal of the first initialization module and is connected to the first initialization signal line, and the second electrode of which serves as the second terminal of the first initialization module and is connected to the second control terminal of the drive module.

[0011] In one possible implementation, the third transistor is a dual-gate transistor, the first gate of the third transistor is connected to the first switch signal as the control terminal of the first initialization module, and the second gate of the third transistor is connected to the second control terminal of the first initialization module, which is connected to the first power line or the first initialization signal line or the second control terminal of the drive module.

[0012] In one possible implementation, the second initialization module includes a fourth transistor, the gate of which serves as the control terminal of the second initialization module and is connected to the second switch signal, the first terminal of which serves as the first terminal of the second initialization module and is connected to the second initialization signal line, and the second terminal of which serves as the second terminal of the second initialization module and is connected to the second terminal of the driving module.

[0013] In one possible implementation, the pixel circuit further includes: A light-emitting control module is connected between the first power line and the first end of the driving module, and is used to turn on or off the connection between the first power line and the first end of the driving module according to the light-emitting control signal.

[0014] In one possible implementation, the light-emitting control module includes a fifth transistor, the gate of which serves as the control terminal of the light-emitting control module and is connected to the light-emitting control signal, the first electrode of which serves as the first terminal of the light-emitting control module and is connected to the first power line, and the second electrode of which serves as the second terminal of the light-emitting control module and is connected to the first terminal of the driving module.

[0015] In one possible implementation, the pixel circuit further includes: The light-emitting module is connected between the second end of the driving module and the second power line, and is used to emit light according to the driving signal; the second power line is used to output a second power signal.

[0016] In one possible implementation, the first initialization signal line, the second initialization signal line, the first power line, and the second power line are all global signal lines.

[0017] In one possible implementation, the array substrate includes multiple pixel circuits, and the first power signal, the first switch signal, the second switch signal, the first initialization signal, the second initialization signal, the light emission control signal, and the second power signal connected to all the pixel circuits are global signals.

[0018] In one possible implementation, the pixel circuit includes at least one of a metal-oxide-semiconductor transistor and a low-temperature polysilicon transistor.

[0019] In one possible implementation, the pixel circuit includes at least one metal oxide transistor and at least one low-temperature polysilicon transistor.

[0020] In one possible implementation, the writing module and the first initialization module both include metal-oxide transistors, and the driving module, the second initialization module, and the light-emitting control module all include low-temperature polysilicon transistors.

[0021] In one possible implementation, the writing module and the first initialization module both include N-type transistors, and the driving module, the second initialization module, and the light-emitting control module all include P-type transistors.

[0022] In one possible implementation, the pixel circuit includes a write frame in an operating mode. The write frame includes at least a first initialization phase. In the first initialization phase, the write module transmits the first power signal to the first control terminal of the drive module according to the first scan signal. The first initialization module is turned on according to the first switch signal, and the second initialization module is turned on according to the second switch signal.

[0023] In one possible implementation, during the first initialization phase, the level of the first scan signal connected to all the pixel circuits is a conducting level, the level of the first switch signal connected to all the pixel circuits is a conducting level, and the level of the second switch signal connected to all the pixel circuits is a conducting level.

[0024] In one possible implementation, during the operation of a write frame, the pixel circuit includes a threshold compensation phase after the first initialization phase. In the threshold compensation phase, the write module is turned off according to the first scan signal, the drive module is turned on according to the voltage at the first control terminal and the second control terminal of the drive module, the first initialization module is turned on according to the first switch signal, the second initialization module is turned on according to the second switch signal, and the first terminal of the drive module charges the second initialization signal line to adjust the threshold voltage corresponding to the first gate of the drive module to the target value.

[0025] In one possible implementation, during the threshold compensation stage, the level of the first scan signal connected to all the pixel circuits is a cutoff level, the level of the first switch signal connected to all the pixel circuits is a conduction level, and the level of the second switch signal connected to all the pixel circuits is a conduction level.

[0026] In one possible implementation, during the operation of one write frame, the pixel circuit includes a data writing phase after the threshold compensation phase. In the data writing phase, the writing module transmits the data signal to the first control terminal of the driving module according to the first scan signal, the first initialization module is turned off according to the first switch signal, and the second initialization module is turned off according to the second switch signal.

[0027] In one possible implementation, the array substrate includes a plurality of pixel circuits arranged in n rows of pixel circuit groups, where n is an integer greater than 0. The n rows of pixel circuit groups are respectively connected to n first scan signals. The data writing stage of the same write frame includes at least n independent sub-stages. The i-th first scan signal sequentially provides a conduction level to the i-th row of pixel circuit groups in the i-th sub-stage, i=1,2,3,…,n.

[0028] In one possible implementation, during the data writing phase, the level of the first switch signal connected to all the pixel circuits is a cutoff level, and the level of the second switch signal connected to all the pixel circuits is a cutoff level.

[0029] In one possible implementation, during the operation of one write frame, the pixel circuit includes a second initialization phase after the data write phase. In the second initialization phase, the write module is turned off according to the first scan signal, the first initialization module is turned off according to the first switch signal, and the second initialization module is turned on according to the second switch signal.

[0030] In one possible implementation, during the second initialization phase, the level of the first scan signal connected to all the pixel circuits is a cutoff level, the level of the first switch signal connected to all the pixel circuits is a cutoff level, and the level of the second switch signal connected to all the pixel circuits is a conduction level.

[0031] In one possible implementation, during the operation of one write frame, the pixel circuit includes a first light emission stage after the second initialization stage. In the first light emission stage, the write module is turned off according to the first scan signal, the first initialization module is turned off according to the first switch signal, the second initialization module is turned off according to the second switch signal, and the drive module outputs a drive signal.

[0032] In one possible implementation, during the first light emission stage, the level of the first scan signal connected to all the pixel circuits is a cutoff level, the level of the first switch signal connected to all the pixel circuits is a cutoff level, and the level of the second switch signal connected to all the pixel circuits is a cutoff level.

[0033] In one possible implementation, during the first initialization phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the first level; during the threshold compensation phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the first level; during the data writing phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the first level; during the second initialization phase, the light-emitting control module is turned off according to the light-emitting control signal, and the level of the second power signal jumps from the first level to the second level; during the first light-emitting phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the second level; wherein, the second level is lower than the first level.

[0034] In one possible implementation, the second initialization signal line is used to transmit a second initialization signal. In the first initialization phase, the level of the second initialization signal is a third level; in the second initialization phase, the level of the second initialization signal is a fourth level, wherein the third level is different from the fourth level.

[0035] In one possible implementation, the fourth level is greater than the second level.

[0036] In one possible implementation, the pixel circuit includes a hold frame in an operating mode, the hold frame including at least a third initialization phase, during at least a portion of the time period in the third initialization phase, the level of the second switch signal is an on level.

[0037] In one possible implementation, the pixel circuit includes a second light-emitting phase after the third initialization phase during the operation of one of the holding frames, in which the level of the second switch signal is a cutoff level.

[0038] In one possible implementation, during the hold frame, the levels of the first scan signal and the first switch signal are maintained at the off level.

[0039] In one possible implementation, during the third initialization phase, when the level of the second switch signal is on, the level of the light emission control signal is on; when the level of the second switch signal is off, the level of the light emission control signal is off. During the second light-emitting stage, the level of the light-emitting control signal is the on level.

[0040] A driving method for a pixel circuit is provided for driving a pixel circuit in an array substrate as described in any of the above embodiments. The pixel circuit includes a write frame in one operating mode. During the operation of one write frame, the pixel circuit includes a first initialization stage, a threshold compensation stage, a data writing stage, a second initialization stage, and a first light emission stage. The driving method includes: During the first initialization phase, the level of the first scan signal is controlled to be on, the first power signal is transmitted to the first terminal of the writing module, the level of the first switch signal is controlled to be on, and the level of the second switch signal is controlled to be on. During the first initialization phase, the level of the first scan signal is controlled to be on, the first power signal is transmitted to the first terminal of the writing module, the level of the first switch signal is controlled to be on, and the level of the second switch signal is controlled to be on. During the threshold compensation stage, the level of the first scan signal is controlled to be off, the level of the first switch signal is controlled to be on, and the level of the second switch signal is controlled to be on. During the data writing phase, the level of the first scan signal is controlled to be on, and the data signal is transmitted to the first terminal of the writing module. The level of the first switch signal is controlled to be off, and the level of the second switch signal is controlled to be off. During the second initialization phase, the level of the first scan signal is controlled to be off, the level of the first switch signal is controlled to be off, and the level of the second switch signal is controlled to be on. During the first light emission stage, the level of the first scanning signal is controlled to be at the cutoff level, the level of the first switching signal is controlled to be at the cutoff level, and the level of the second switching signal is controlled to be at the cutoff level.

[0041] In one possible implementation, the array substrate includes a plurality of pixel circuits arranged in n rows of pixel circuit groups, where n is an integer greater than 0. The n rows of pixel circuit groups are respectively connected to n first scan signals. The data writing stage of the same write frame includes at least n independent sub-stages, and the i-th first scan signal is controlled to provide a conduction level to the i-th row of pixel circuit groups in the i-th sub-stage, i=1,2,3,…,n.

[0042] In one possible implementation, the pixel circuit further includes a light-emitting module connected between the second terminal of the driving module and the second power line; the second power line is used to output a second power signal, and the driving method further includes: During the first initialization phase, the level of the control signal for light emission is set to the on level, and the level of the control signal for the second power supply is set to the first level. During the threshold compensation stage, the level of the control signal for light emission is controlled to be at the cutoff level, and the level of the second power supply signal is controlled to be at the first level. During the data writing phase, the level of the control signal for light emission is set to the on level, and the level of the second power signal is set to the first level. During the second initialization phase, the level of the control signal for light emission is set to the cutoff level, and the level of the control signal for the second power supply is set to the first level. During the first light-emitting stage, the level of the light-emitting control signal is the on level, and the level of the second power supply signal is the second level; wherein the second level is lower than the first level.

[0043] In one possible implementation, the second initialization signal line is used to transmit a second initialization signal. During the first initialization phase, the level of the second initialization signal is controlled to be a third level; during the second initialization phase, the level of the second initialization phase is controlled to be a fourth level, wherein the third level and the fourth level are different.

[0044] In one possible implementation, the pixel circuit includes a holding frame in an operating mode, and the pixel circuit includes a third initialization phase and a second emission phase during the operation of the holding frame, the driving method comprising: During at least a portion of the third initialization phase, the level of the second switch signal is controlled to be at the on level; During the second light-emitting phase, the level of the second switching signal is controlled to be at the cutoff level.

[0045] In one possible implementation, during the hold frame, the levels of the first scan signal and the first switch signal are kept at the off level.

[0046] In one possible implementation, during the third initialization phase, when the level of the second switch signal is on, the level of the light emission control signal is controlled to be on; when the level of the second switch signal is off, the level of the light emission control signal is controlled to be off. During the second light-emitting stage, the level of the light-emitting control signal is set to the on level.

[0047] A display panel includes n array substrates as described in any of the above embodiments, each array substrate including at least one pixel circuit. The display panel further includes at least one multiplexer, each multiplexer being connected to a first terminal of a write module in one of the pixel circuits. The multiplexer is used to transmit a first power signal to the first terminal of the write module according to a first selection signal, or to transmit a data signal to the first terminal of the write module according to a second selection signal.

[0048] In one possible implementation, the multiplexer includes: A first switch module is connected between the first power line and the first end of the write module, and is used to turn on or off the connection between the first power line and the first end of the write module according to the first selection signal. The second switch module is connected between the data line and the first end of the write module, and is used to turn on or off the connection between the data line and the first end of the write module according to the second selection signal.

[0049] In one possible implementation, the first switching module includes a sixth transistor, the gate of which serves as the control terminal of the first switching module and is connected to the first selection signal, the first electrode of which serves as the first terminal of the first switching module and is connected to the first power line, and the second electrode of which serves as the second terminal of the first switching module and is connected to the first terminal of the write module.

[0050] In one possible implementation, the second switching module includes a seventh transistor, the gate of which serves as the control terminal of the second switching module and is connected to the second selection signal, the first terminal of which serves as the first terminal of the second switching module and is connected to the data line, and the second terminal of which serves as the second terminal of the second switching module and is connected to the first terminal of the write module.

[0051] In one possible implementation, the pixel circuit includes a write frame in an operating mode. During the operation of the write frame, the pixel circuit includes a first initialization phase. In the first initialization phase of the write frame, the first switch module is turned on according to the first selection signal, and the second switch module is turned off according to the second selection signal. In the data writing phase of the write frame, the first switch module is turned off according to the first selection signal, and the second switch module is turned on according to the second selection signal. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the structure of one of the array substrates provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of one pixel circuit provided in an embodiment of this application; Figure 3 A schematic diagram of the circuit structure of one type of pixel circuit provided in the embodiments of this application. Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application; Figure 5 A schematic diagram of another pixel circuit structure provided in an embodiment of this application; Figure 6 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in an embodiment of this application. Figure 7 This is a schematic diagram of the signal timing of a pixel circuit in a holding frame, provided in an embodiment of this application. Figure 8 A schematic flowchart illustrating one of the pixel circuit driving methods provided in an embodiment of this application; Figure 9 A schematic diagram illustrating the structural connection between a multiplexer and a pixel circuit, provided in an embodiment of this application; Figure 10 A schematic diagram of the circuit connection between a multiplexer and a pixel circuit provided in one embodiment of this application; Figure 11 This is a schematic diagram of the signal timing of a multiplexer provided in one embodiment of the present application when writing a frame or holding a frame. Detailed Implementation

[0054] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0056] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0057] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0058] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0059] With the continuous development of display technology, the application range of organic light-emitting diode (OLED) display panels is becoming more and more widespread, such as VR (Virtual Reality) and AR (Augmented Reality) display solutions, bringing users a brand-new visual experience.

[0060] However, existing OLED display panels suffer from large bezels, failing to meet the application requirements of AR / VR and other display solutions. While mature pixel driving circuits such as the 7T1C circuit offer comprehensive functionality, their large number of TFTs (Thin Film Transistors) limits the achievement of ultra-high PPI (Pixel Per Inch) due to process limitations. The conventional 2T1C circuit solution, with fewer TFT devices, can significantly improve PPI, but it lacks gate initialization, anode initialization, and other functions, or cannot achieve threshold voltage compensation within the pixel, thus failing to meet application requirements.

[0061] Based on this, this application provides an array substrate. Figure 1 This is a schematic diagram of the structure of one of the array substrates provided in the embodiments of this application. The array substrate 20 may include at least one pixel circuit 10. The pixel circuit 10 is designed to be suitable for high PPI display panels and can achieve higher pixel density to at least meet the display requirements of AR / VR devices.

[0062] Figure 2 This is a schematic diagram of the structure of one pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit 10 may include a driving module 100, a writing module 200, a first storage module 300, a second storage module 400, a first initialization module 500, and a second initialization module 600.

[0063] The driving module 100 can be connected between the first power line and the light-emitting module 800, and can be used to output a driving signal. The driving signal can be a driving current. The driving module 100 may include a first control terminal and a second control terminal. In some specific embodiments, the first terminal of the driving module 100 can be connected to a first voltage source, and the second terminal can be connected to the light-emitting module 800. The driving signal output by the driving module 100 is transmitted to the light-emitting module 800, which can control the light-emitting module 800 to emit light. The first power line can be used to transmit a first power signal VDD. Preferably, the first power signal VDD is a DC high-level signal. Further, the first power line can be a global signal line, and the first power signal VDD transmitted on the first power line can be a global signal. That is, when the array substrate 20 includes multiple pixel circuits 10, the timing waveform of the first power signal VDD connected to all pixel circuits 10 is the same.

[0064] The write module 200 can be connected to the first control terminal of the drive module 100. The write module 200 can be configured to transmit a data signal Vdata or a first power signal VDD to the first control terminal of the drive module 100 according to the first scan signal S1. The first terminal of the write module 200 can be used to receive the first power signal VDD or the data signal Vdata, the control terminal of the write module 200 can be used to receive the first scan signal S1, and the second terminal of the write module 200 can be connected to the first control terminal of the drive module 100. In some embodiments, the first terminal of the write module 200 can be connected to different signals in a time-division multiplexing manner by means of, for example, a variable voltage signal line or a multiplexer. The control terminal of the write module 200 can be connected to the first scan line to receive the first scan signal S1, so that the write module 200 can transmit the first initialization signal Vini or the data signal Vdata to the first control terminal of the drive module 100 according to the control of the first scan signal S1.

[0065] A first storage module 300 can be connected between the first control terminal and the first terminal of the drive module 100, and the first storage module 300 can store the voltage changes at the first control terminal and the first terminal of the drive module 100. A second storage module 400 can be connected between the second control terminal and the first terminal of the drive module 100, and the second storage module 400 stores the voltage changes at the second control terminal and the first terminal of the drive module 100.

[0066] The first initialization module 500 can be connected between the second control terminal of the drive module 100 and the first initialization signal line. The first initialization module 500 can be configured to turn on or off according to the first switch signal S2, thereby controlling the connection between the second control terminal of the drive module 100 and the first initialization signal line. The first initialization signal line can be used to transmit the first initialization signal Vini. In some embodiments, the control terminal of the first initialization module 500 can be connected to the first switch signal line, and the first switch signal line can output the first switch signal S2 to control the on or off state of the first initialization module 500.

[0067] The second initialization module 600 can be connected between the second terminal of the drive module 100 and the second initialization signal line. The second initialization module 600 can be configured to turn on or off according to the second switch signal S3 to control the connection between the second terminal of the drive module 100 and the second initialization signal line. The second initialization signal line can be used to transmit the second initialization signal Vref. In some embodiments, the control terminal of the second initialization module 600 can be connected to the second switch signal line, and the second switch signal line can output the second switch signal S3 to control the on or off state of the second initialization module 600.

[0068] Furthermore, when the pixel circuit 10 is operating in the threshold compensation stage, the first storage module 300, the second storage module 400 and the second initialization module 600 work together to adjust the threshold voltage of the driving module 100, so as to solve the influence of the threshold voltage deviation of the driving module 100 on the driving signal.

[0069] In one embodiment, the pixel circuit 10 may further include a light-emitting module 800, which can be connected between the second terminal of the driving module 100 and the second power line. Specifically, the first terminal of the light-emitting module 800 can be connected to the second terminal of the driving module 100, and the second terminal of the light-emitting module 800 can be connected to the second power line. The light-emitting module 800 may be an LED (Light-Emitting Diode), an OLED (Organic Electroluminescence Display), or other light-emitting devices. The second power line can provide a second power signal ACVSS to the second terminal of the light-emitting module 800. Preferably, the second power signal ACVSS is an AC signal.

[0070] This application proposes a display driving scheme capable of achieving high PPI. The pixel circuit 10 in the array substrate 20, through the coordination of the writing module 200, driving module 100, first storage module 300, second storage module 400, first initialization module 500, and second initialization module 600, and the timing of various input signals, can achieve functions such as reset and threshold compensation of the driving module 100. On one hand, reducing the number of transistors within the pixel circuit 10 effectively reduces its size. On the other hand, reducing the number of transistors in the pixel circuit 10 also reduces the number of scan signals connected to the transistors, thereby reducing the number of GIP (Gate In Panel) circuit groups. Fewer power signals connected to the circuit facilitate pixel size compression, simplify the circuit structure, and save layout space, thus effectively improving PPI. Saving layout space also reduces parasitic capacitance between circuit nodes, preventing parasitic capacitance from affecting brightness uniformity. The application of the pixel circuit 10 in the array substrate provided in this application can effectively reduce the bezel size and improve display uniformity and solve the image retention problem while achieving ultra-high PPI display layout.

[0071] In embodiments of this disclosure, a transistor can refer to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the first and second terminals of all or some transistors can be interchanged as needed.

[0072] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. Furthermore, the on-level and off-level in the embodiments of this invention are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0073] Figure 3 This is a schematic diagram of the circuit structure of one pixel circuit provided in an embodiment of this application. In one possible implementation, the driving module 100 may include a first transistor M1. The first transistor M1 may be a dual-gate transistor, including a first gate G and a second gate B. Preferably, the first gate G is a top gate and the second gate B is a bottom gate. The first gate G of the first transistor M1 can serve as a first control terminal of the driving module 100, the second gate B of the first transistor M1 can serve as a second control terminal of the driving module 100, the first electrode of the first transistor M1 can serve as a first terminal of the driving module 100, and the second electrode of the first transistor M1 can serve as a second terminal of the driving module 100.

[0074] In one possible implementation, the first storage module 300 may include a first capacitor C1. The first terminal of the first capacitor C1 can be connected to the first control terminal of the driving module 100 as the first terminal of the first storage module 300, and the second terminal of the first capacitor C1 can be connected to the first terminal of the driving module 100 as the second terminal of the first storage module 300. Specifically, the first terminal of the first capacitor C1 is connected to the first gate G of the first transistor M1, and the second terminal of the first capacitor C1 is connected to the first terminal of the first transistor M1.

[0075] In one possible implementation, the second storage module 400 may include a second capacitor C2. The first terminal of the second capacitor C2 can be connected to the second control terminal of the driving module 100 as the first terminal of the second storage module 400, and the second terminal of the second capacitor C2 can be connected to the first terminal of the driving module 100 as the second terminal of the second storage module 400. Specifically, the first terminal of the second capacitor C2 is connected to the second gate B of the first transistor M1, and the second terminal of the second capacitor C2 is connected to the first terminal of the first transistor M1.

[0076] In one possible implementation, the write module 200 may include a second transistor M2. The gate of the second transistor M2 can be used as the control terminal of the write module 200 to connect to the first scan signal S1. The first terminal of the second transistor M2 can be used as the first terminal of the write module 200 to connect to the data signal Vdata or the first power signal VDD. The second terminal of the second transistor M2 can be used as the second terminal of the write module 200 to connect to the first control terminal of the drive module 100. Specifically, the gate of the second transistor M2 can be connected to the first scan line to connect to the first scan signal S1. The first terminal of the second transistor M2 is connected to the data signal Vdata or the first initialization signal Vini. The second terminal of the second transistor M2 can be connected to the first gate G of the first transistor M1. Further, the first scan number S1 transmitted on the first scan line can be output by a shift register unit (Gate In Panel, GIP circuit) located in the non-display area (usually also called the bezel area) of the array substrate.

[0077] In one possible implementation, the first terminal of the write module 200 is connected to a MUX (Multiplexer) circuit to receive different signals. The first input terminal of the MUX circuit can be connected to a first power line to receive the first power signal VDD; the second input terminal of the MUX circuit can be connected to a data line to receive the data signal Vdata; and the output terminal of the MUX circuit can be connected to the first terminal of the write module 200. Using the MUX circuit, the first power signal VDD or the data signal Vdata can be output to the first terminal of the write module 200 in a time-division multiplexing manner.

[0078] In one possible implementation, the first initialization module 500 may include a third transistor M3. The gate of the third transistor M3 can be used as the control terminal of the first initialization module 500 and connected to the first switch signal S2. The first terminal of the third transistor M3 can be used as the first terminal of the first initialization module 500 and connected to the first initialization signal line. The second terminal of the third transistor M3 can be used as the second terminal of the first initialization module 500 and connected to the second control terminal of the driving module 100. Specifically, the gate of the third transistor M3 can be connected to the first switch signal S2, the first terminal of the third transistor M3 is connected to the first initialization signal line, and the second terminal of the third transistor M3 is connected to the second gate B of the first transistor M1. Further, the first initialization signal line can be a global signal line, and the first initialization signal Vini transmitted on the first initialization signal line can be a global signal. At the same time, the first switch signal S2 can also be a global signal. That is, when the array substrate 20 includes multiple pixel circuits 10, the timing waveforms of the first initialization signal Vini connected to all pixel circuits 10 are the same, and the timing waveforms of the first switch signal S2 connected to all pixel circuits 10 are the same.

[0079] In one possible implementation, the second initialization module 600 may include a fourth transistor M4. The gate of the fourth transistor M4 can be used as the control terminal of the second initialization module 600 and connected to the second switch signal S3. The first terminal of the fourth transistor M4 can be used as the first terminal of the second initialization module 600 and connected to the second initialization signal line. The second terminal of the fourth transistor M4 can be used as the second terminal of the first initialization module 500 and connected to the second terminal of the driving module 100. Specifically, the gate of the fourth transistor M4 can be connected to the first switch signal S2, the first terminal of the fourth transistor M4 is connected to the first initialization signal line, and the second terminal of the fourth transistor M4 is connected to the second terminal of the first transistor M1. Since the second terminal of the driving module 100 is connected to the first terminal of the light-emitting module 800, when the second initialization module 600 transmits the second initialization signal Vref to the second terminal of the driving module 100, it can initialize both the second terminal of the driving module 100 and the first terminal of the light-emitting module 800. Further, the second initialization signal line can be a global signal line, and the second initialization signal Vref transmitted on the second initialization signal line can be a global signal. Simultaneously, the second switch signal S3 can also be a global signal. That is, when the array substrate 20 includes multiple pixel circuits 10, the timing waveforms of the second initialization signal Vref connected to all pixel circuits 10 are the same, and the timing waveforms of the second switching signal S3 connected to all pixel circuits 10 are the same.

[0080] In one possible implementation, the light-emitting module 800 may include a light-emitting diode (OLED) D1. The OLED may include an anode and a cathode. The anode of the OLED D1, serving as the first terminal of the light-emitting module 600, can be connected to the second terminal of the driving module 100, and the cathode of the OLED D1, serving as the second terminal of the light-emitting module 600, can be connected to a second power supply line. When a driving signal output from the driving module 100 is transmitted to the OLED D1, the OLED D1 can emit light with a brightness corresponding to the driving signal. Further, the second power supply line can be a global signal line, and the second power signal ACVSS transmitted on the second power supply line can be a global signal. That is, when the array substrate 20 includes multiple pixel circuits 10, the timing waveform of the second power signal ACVSS connected to all pixel circuits 10 is the same.

[0081] In one possible implementation, each functional module in the pixel circuit 10 can be implemented using low-temperature polysilicon transistors (LTPS TFTs). LTPS TFTs are transistors that use low-temperature polysilicon as the active semiconductor layer; they can be P-type or N-type transistors.

[0082] In one possible implementation, the pixel circuit 10 may include at least one metal-oxide-semiconductor (MODS) transistor and at least one low-temperature polycrystalline silicon (LTS) transistor. The MODS transistor is a transistor based on a LTS material as the active semiconductor layer. The MODS material may be at least one of IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IZTO (Indium Zinc Tin Oxide). The MODS transistor may be an N-type transistor. The pixel circuit 10 provided in this application is preferably a circuit fabricated using LTPO (Low Temperature Poly Silicon-Oxide) technology. LTPO is a hybrid OLED backplane technology combining LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide). In one possible implementation, at least one of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 is a MODS transistor, and at least one is a LTS transistor.

[0083] In one possible implementation, both the first transistor M1 and the fourth transistor M4 are P-type low-temperature polysilicon transistors (LTPS). LTPS devices possess extremely high carrier mobility, resulting in powerful current driving capabilities and advantages such as strong driving power and good stability, enabling high brightness and high refresh rate driving. Simultaneously, due to the high mobility, individual transistors can be made smaller, contributing to increased pixel density and enabling narrow bezel designs.

[0084] In one possible implementation, the second transistor M2 and the third transistor M3 can be either N-type LTPS transistors or IGZO transistors. IGZO devices have extremely low off-state leakage current, so inter-pixel crosstalk caused by leakage current is negligible, while also significantly reducing power consumption. The pixel circuit 10 provided in this application utilizes LTPS devices for high-speed switching and driving, and IGZO devices for low-leakage switching. Combining the stable characteristics of the two materials, a more complex and precise internal compensation circuit can be designed to cope with TFT characteristic drift, improve display uniformity and image quality stability, and achieve dynamic refresh rate. Utilizing the low leakage current characteristic of IGZO, some circuit structures can be simplified, or a pixel circuit 10 that can resist power supply voltage fluctuations can be designed, further improving energy efficiency and display quality.

[0085] In one possible implementation, the second transistor M2 can be an N-type LTPS transistor or an IGZO transistor. When the second transistor M2 is an IGZO, it can be a three-terminal or a four-terminal device. When the second transistor M2 is a three-terminal device, its connection method is as described in the above embodiments and will not be repeated here.

[0086] When the second transistor M2 is a four-terminal device, the first gate of the second transistor M2 is connected to the first scan signal S1 as the control terminal of the write module 200, and the second gate of the second transistor M2 is connected to the first power line or the first initialization signal line as the second control terminal of the write module 200 to connect to the first power signal VDD or the first initialization signal Vini. The first terminal of the second transistor M2 is connected to the first power signal VDD or the data signal Vdata as the first terminal of the write module 200, and the second terminal of the second transistor M2 is connected to the first gate G of the first transistor M1 as the second terminal of the write module 200.

[0087] In one possible implementation, the third transistor M3 can be an N-type LTPS transistor or an IGZO transistor. When the third transistor M3 is an IGZO, it can be a three-terminal device or a four-terminal device. When the third transistor M3 is a three-terminal device, its connection method is as described in the above embodiments and will not be repeated here.

[0088] When the third transistor M3 is a four-terminal device, the first gate of the third transistor M3 serves as the control terminal of the first initialization module 500 and is connected to the first scan signal S1. The second gate of the third transistor M3 serves as the second control terminal of the first initialization module 500 and can be connected to the first power supply line or the first initialization signal line to connect to the first power supply signal VDD or the first initialization signal Vini. Alternatively, the second gate of the third transistor M3 can also be connected to the second gate B of the first transistor M1. The first terminal of the third transistor M3 serves as the first terminal of the first initialization module 500 and is connected to the first initialization signal line to connect to the first initialization signal Vini. The second terminal of the third transistor M3 serves as the second terminal of the first initialization module 500 and is connected to the second gate B of the first transistor M1.

[0089] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. In one possible implementation, the pixel circuit 10 may further include a light-emitting control module 700. The light-emitting control module 700 is connected between the first power line and the first end of the driving module 100. The light-emitting control module 700 can be configured to turn on or off the connection between the first power line and the first end of the driving module 100 according to the light-emitting control signal EM. Specifically, the first end of the light-emitting control module 700 can be connected to the first power line, and the second end of the light-emitting control module 700 can be connected to the first end of the driving module 100.

[0090] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. In one possible implementation, the light emission control module 700 may include a fifth transistor M5. The gate of the fifth transistor M5 can be used as the control terminal of the light emission control module 700 to connect to the light emission control signal EM. The first terminal of the fifth transistor M5 can be used as the first terminal of the light emission control module 700 and connected to the first power supply line. The second terminal of the fifth transistor M5 can be used as the second terminal of the light emission control module 700 and connected to the first terminal of the driving module 100. Specifically, the gate of the fifth transistor M5 can be connected to the light emission control signal line to connect to the light emission control signal EM. The first terminal of the fifth transistor M5 can be connected to the first power supply line, and the second terminal of the fifth transistor M5 can be connected to the first terminal of the first transistor M1. In one possible implementation, the fifth transistor M5 can be a P-type LTPS transistor. Further, the light emission control signal EM can be a global signal. That is, when the array substrate 20 includes multiple pixel circuits 10, the timing waveform of the light emission control signal EM connected to all pixel circuits 10 is the same.

[0091] like Figure 5The pixel circuit 10 provided in the illustrated embodiment has a 5T2C structure, wherein the first transistor M1 is a driving transistor (DTFT), the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are switching transistors (STFTs), and the second transistor M2 and the third transistor M3 are both IGZO TFTs, while the first transistor M1, the fourth transistor M4, and the fifth transistor M5 are all LTPS P-type TFTs. C1 and C2 are capacitors. The second transistor M2 and the third transistor M3 are four-terminal IGZO TFT devices.

[0092] The first terminal of the second transistor M2 is connected to either the data signal Vdata or the first power signal VDD. The first gate of the second transistor M2 is connected to the first scan signal S1. The second gate of the second transistor M2 is connected to either the first power line or the first initialization signal line to connect to either the first power signal VDD or the first initialization signal Vini. The second terminal of the second transistor M2 is connected to the first gate G of the first transistor M1 and the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the first terminal of the first transistor M1, the second terminal of the fifth transistor M5, and the second terminal of the second capacitor C2. The first terminal of the second capacitor C2 is connected to the second gate B of the first transistor M2 and the second terminal of the third transistor M3. The first terminal of the fifth transistor M5 is connected to the first power line. The gate of the fifth transistor M5 is connected to the light emission control signal EM. The first terminal of the third transistor M3 is connected to the first initialization signal Vini. The first gate of the third transistor M3 is connected to the first switch signal S2. The second gate of the third transistor M3 is connected to either the first initialization signal line, the first power line, or the second gate B of the first transistor M1. The second terminal of the first transistor M1 is connected to the second terminal of the fourth transistor M4 and the anode of the light-emitting diode D1, respectively. The first terminal of the fourth transistor M4 is connected to the second initialization signal line, and the gate of the fourth transistor M4 is connected to the second switching signal S3. The cathode of the light-emitting diode D1 is connected to the second power supply signal ACVSS.

[0093] Display devices operate in different modes, and the refresh rate may differ between these modes. For example, the refresh rate differs when displaying static images and when displaying dynamic game visuals. Sometimes, the display device switches refresh rates between different operating modes. In related technologies, a low refresh rate can be achieved by skipping frames on top of a high refresh rate. For instance, at a refresh rate of 120Hz, all 120 data frames can be write frames, updating pixel data in each write frame. At a refresh rate of 1Hz, based on 120Hz, one data frame is used as a write frame, while the others are used as hold frames. Data is written during the write frame, and the pixel data is not updated during the hold frame; only the current data is maintained. The combination of write and hold frames can achieve a dynamic refresh rate and reduce power consumption. The distinction between high and low refresh rates can be set according to different application requirements. For example, a refresh rate of 120Hz or higher is considered a high refresh rate, and a refresh rate below 120Hz is considered a low refresh rate.

[0094] Figure 6 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in one embodiment of this application. It can be applied to, for example... Figure 5 The pixel circuit 10 shown in this embodiment is combined with... Figure 5 and Figure 6 The working process of the pixel circuit 10 in one embodiment of this application during frame writing is described in detail, but it should not be construed as a limitation on the scope of the invention patent.

[0095] In one possible implementation, the pixel circuit 10 may include a write frame in an operating mode. The write frame may include at least a first initialization phase t11. In the first initialization phase t11, the levels of the first scan signal S1 connected to all pixel circuits 10 in the array substrate may all be on, the levels of the first switch signal S2 connected to all pixel circuits 10 may all be on, and the levels of the second switch signal S3 connected to all pixel circuits 10 may all be on. Simultaneously, in the first initialization phase t11, the signals connected to the first terminals of the write modules 200 in all pixel circuits 10 may all be the first power signal VDD. All write modules 200 in the pixel circuits 10 are turned on according to the first scan signal S1 and transmit the first power signal VDD to the first control terminal of the drive module 100. All first initialization modules 500 in the pixel circuits 10 are turned on according to the first switch signal S2, and all second initialization modules 600 in the pixel circuits 10 are turned on according to the second switch signal S3.

[0096] In the first initialization stage t11, the first gate G, second gate B, first electrode, second electrode, and anode of the driving transistor (i.e., the first transistor M1) and the light-emitting diode D1 in the pixel circuit 10 can be reset. When the array substrate includes multiple pixel circuits 10, all pixel circuits 10 can be reset simultaneously at each point.

[0097] Specifically, the second transistor M2 is turned on according to the first scan signal S1, transmitting the first power supply signal VDD to the first gate G of the first transistor M1. That is, the potential at the first gate G is VG=VDD, and the first power supply signal VDD can be used to reset the first gate G of the first transistor M1. The third transistor M3 is turned on according to the first switch signal S2, so the first initialization signal Vini transmitted on the first initialization signal line can be transmitted through the third transistor M3 to the second gate B of the first transistor M1. That is, the potential at the second gate B of the first transistor M1 is VB=Vini, and the first initialization signal Vini can be used to reset the second gate B of the first transistor M1. The fourth transistor M4 is turned on according to the second switch signal S3, so the second initialization signal Vref transmitted on the second initialization signal line can be transmitted through the fourth transistor M4 to the second terminal of the first transistor M1 and the anode of the light-emitting diode D1. That is, the potential at the second terminal of the first transistor M1 is VD=Vref, and the second initialization signal Vref can be used to reset the second terminal of the first transistor M1 and the anode of the light-emitting diode D1.

[0098] Furthermore, during the first initialization phase t11, the light emission control signal EM connected to all pixel circuits 10 in the array substrate can be at the on level. The fifth transistor M5 in all pixel circuits 10 is turned on according to the light emission control signal EM and transmits the first power supply signal VDD to the first terminal of the first transistor M1, thus resetting the first terminal of the first transistor M1 using the first power supply signal VDD. At this time, the voltage difference across the first capacitor C1 is VGS = VG - VS = 0V. During the initialization phase t1, the level of the second power supply signal ACVSS connected to all pixel circuits 10 is the first level VSSH, where the first level VSSH is high.

[0099] In one possible implementation, the pixel circuit 10 may further include a threshold compensation stage t12 after the first initialization stage t11 during the operation of a write frame. In the threshold compensation stage t12, the levels of the first scan signal S1 connected to all pixel circuits 10 in the array substrate can all be off, the levels of the first switch signal S2 connected to all pixel circuits 10 can all be on, and the levels of the second switch signal S3 connected to all pixel circuits 10 can all be on. The write modules 200 in all pixel circuits 10 are turned off according to the first scan signal S1, the first initialization modules 500 in all pixel circuits 10 are turned on according to the first switch signal S2, and the second initialization modules 600 in all pixel circuits 10 are turned on according to the second switch signal S3. The first terminal of the driving module 100 charges the second initialization signal line, adjusting the threshold voltage corresponding to the first gate of the driving module 100 to a target value. Preferably, the target value is 0.

[0100] In the threshold compensation stage t12, the threshold voltage Vth of the driving transistor (i.e., the first transistor M1) can be compensated. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously achieve threshold compensation for all driving transistors.

[0101] Specifically, the second transistor M2 is turned off according to the first scan signal S1. The third transistor M3 is turned on according to the first switch signal S2, and the fourth transistor M4 is turned on according to the second switch signal S3. The first initialization signal Vini is still transmitted to the second gate B of the first transistor M1 through the third transistor M3, and the connection between the second terminal of the first transistor M1 and the second initialization signal line is turned on. Furthermore, during the threshold compensation stage t12, the levels of the light emission control signal EM connected to all pixel circuits 10 in the array substrate can all be at the cutoff level, and the fifth transistor M5 in all pixel circuits 10 is cut off according to the light emission control signal EM. That is, the first gate G and source S of the first transistor M1 become floating, and the voltage difference between the first capacitor C1 remains at 0V. The first transistor M1 is turned on according to the potential at its control terminal, the source S of the first transistor M1 is floating, and the drain D is connected to a fixed low potential Vref, so the current flows from the source S to the drain D. The source S point of the first transistor M1 is charged to the second initialization signal line Vref through the first transistor M1 and the fourth transistor M4 respectively, that is, DTFT Vth compensation is performed. The potential of the source S point continues to decrease until the first transistor M1 is just at the pinch-off critical point, the channel charge is fully released, and the threshold voltage of the first gate G (top gate) is adjusted to Vth=0V.

[0102] The threshold voltage regulation process for the first transistor M1 continues until the DTFT is just turned off, for example, when the compensation current becomes about 1nA. At this time, the Vth of the top gate of the first transistor M1 is regulated to 0. The voltage difference across the first capacitor C1 remains at VGS=0, and the threshold information that the Vth of the top gate of the first transistor M1 is 0 is stored in the first capacitor C1. At the same time, the voltage difference VBS across the second capacitor C2 can be regarded as the regulation voltage VB1. After the regulation of the threshold voltage of the top gate of the first transistor M1 is completed, the regulation voltage VB1 can be stored in the second capacitor C2. This regulation voltage VB1 can ensure that the Vth of the top gate of the first transistor M1 remains at 0V in subsequent operation. It should be noted that since there may be deviations between the threshold voltages of different driving transistors, the regulation voltage VB1 corresponding to different first transistors M1 is different. Here, VB1 is an illustrative parameter. Meanwhile, in the threshold compensation stage t12, the level of the second power supply signal ACVSS connected to the cathode of the light-emitting diode D1 can be the first level VSSH, that is, at this time, the cathode of the light-emitting diode D1 is connected to a high level, so the voltage of the light-emitting diode D1 is reversed and it does not emit light.

[0103] By adjusting the top gate threshold voltage of the first transistor M1 to 0, the influence of the threshold voltage on the drive current can be reduced, thereby improving the uniformity of the output signals of each pixel circuit 10. Simultaneously, by separating the threshold compensation process from the data writing process, the threshold compensation time is not limited by the data writing time, and the threshold compensation stage t12 is adjustable. Therefore, it can be ensured that the first transistor M1 in each pixel circuit 10 within the display panel receives sufficient compensation, further guaranteeing the uniformity of the display panel.

[0104] In one possible implementation, the pixel circuit 10 may further include a data writing stage t13 after the threshold compensation stage t12 during the operation of a write frame. In the data writing stage t13, the levels of the first switch signal S2 connected to all pixel circuits 10 in the array substrate can all be off, and the levels of the second switch signal S3 connected to all pixel circuits 10 in the array substrate can all be on. In the data writing stage t13, the signals connected to the first terminals of the writing modules 200 in all pixel circuits 10 are data signals Vdata. When the writing module 200 is turned on according to the first scan signal S1, it transmits the data signal Vdata to the first gate G of the first transistor M1, and the first storage module 300 stores the data signal Vdata.

[0105] In the data writing stage t13, the data signal Vdata can be input to the pixel circuit 10, and the data signal Vdata can be stored. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can be arranged into n rows of pixel circuit groups. The first scan signal S1 connected to each row of pixel circuit groups is the same, and the n rows of pixel circuit groups are respectively connected to n first scan signals S1. The data writing stage t13 can include n independent sub-stages. The i-th first scan signal sequentially provides a conduction level to the i-th row of pixel circuit groups row by row in the i-th sub-stage, i=1,2,3,…,n. That is, each row of pixel circuit 10 corresponds to a corresponding sub-stage. The level of the first scan signal S1 in each row of pixel circuit 10 is a conduction level in the corresponding sub-stage, and a cutoff level at other times, so as to realize the row-by-row writing of the data signal Vdata. Please refer to Figure 6 When the array substrate includes n rows of pixel circuit groups, the n rows of pixel circuit groups are respectively connected to the first scan signal S1_1 to the first scan signal S1_n. The first scan signal S1_1 to the first scan signal S1_n each correspond to a corresponding sub-stage. The level of the first scan signal S1_1 to the first scan signal S1_n in the corresponding sub-stage is the on level, and the level at other times is the off level, so as to realize the row-by-row writing of the data signal Vdata.

[0106] Specifically, in each row of pixel circuit groups on the array substrate, the second transistor M2 is turned on row by row according to the corresponding first scan signal S1, and the data signal Vdata is transmitted row by row to the first gate G of the corresponding first transistor M1. In addition, during the data writing stage t13, the level of the light emission control signal EM connected to all pixel circuits 10 can be the on level. The fifth transistor M5 in all pixel circuits 10 is turned on according to the light emission control signal EM. The first power supply signal VDD is transmitted to the source S of the first transistor M1 through the fifth transistor M5, that is, the potential at point S is VS=VDD. At this time, the potential at the first gate G is VG=Vdata, and the potential at the first terminal is VS=VDD. The potential difference across the first capacitor C1 becomes Vdata-VDD. During this stage, the second capacitor C2 stores the data signal Vdata.

[0107] Meanwhile, during the data writing stage t13, the level of the second power supply signal ACVSS connected to the cathode of the light-emitting diode D1 in all pixel circuits 10 can be the first level VSSH, that is, at this time the cathode of the light-emitting diode D1 is connected to a high level, so the voltage of the light-emitting diode D1 is reversed and it does not emit light.

[0108] In one possible implementation, the pixel circuit 10 may further include a second initialization phase t14 after the data writing phase t13 during the operation of a write frame. In the second initialization phase t14, the levels of the first scan signal S1 connected to all pixel circuits 10 in the array substrate are all off, the levels of the first switch signal S2 connected to all pixel circuits 10 are all off, and the levels of the second switch signal S3 connected to all pixel circuits 10 are all on. The write modules 200 in all pixel circuits 10 are turned off according to the first scan signal S1, the first initialization modules 500 in all pixel circuits 10 are turned off according to the first switch signal S2, and the second initialization modules 600 in all pixel circuits 10 are turned on according to the second switch signal S3. Simultaneously, the second initialization modules 600 in all pixel circuits 10 reset the anode of the light-emitting module 800.

[0109] In the second light-emitting stage t14, the anode of the light-emitting module 800 can be reset. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously reset the anodes of all row light-emitting diodes D1.

[0110] Specifically, the second transistor M2 is turned off according to the first scan signal S1, the third transistor M3 is turned off according to the first switch signal S2, and the fourth transistor M4 is turned on according to the second switch signal S3. Simultaneously, during the second initialization phase t14, the level of the light emission control signal EM is at the off level, and the light emission control module 700 is turned off according to the light emission control signal EM. The second initialization signal Vref is transmitted through the fourth transistor M4 to the second electrode of the first transistor M1 and the anode of the light emission diode D1, thereby resetting the second electrode of the first transistor M1 and the anode of the light emission diode D1. Meanwhile, during the second initialization phase t14, the level of the second power supply signal ACVSS connected to the cathode of the light emission diode D1 can remain at the first level VSSH.

[0111] In one possible implementation, the second initialization signal line is used to transmit the second initialization signal Vref. In the first initialization phase t11, the level of the second initialization signal Vref is the third level vref1; in the second initialization phase t14, the level is the fourth level vref2, where the third level vref1 and the fourth level vref2 are different. Using the second switch signal S3, the second initialization signal Vref can be controlled to reset the anode of the light-emitting diode D1 twice, in the first initialization phase t11 and the second initialization phase t12. By setting the voltage Vanode at the anode of the light-emitting diode D1 to vref1 during the first reset and Vanode to vref2 during the second reset, and ensuring that the vref2 voltage is higher than the second level VSSL, the brightness of the first frame can be improved while maintaining contrast.

[0112] Additionally, during the threshold compensation phase, the level of the second initialization signal Vref can also be the third level vref1, and the third level vref1 is less than the first power supply VDD. This results in the source S potential of the first transistor M1 being higher than its drain potential, causing current to flow from the source S to the drain D. The source S point of the first transistor M1 charges the second initialization signal line Vref through both the first transistor M1 and the fourth transistor M4, thus performing DTFT Vth compensation.

[0113] In one possible implementation, the pixel circuit 10 may further include a first light-emitting stage t15 after the second initialization stage t14 during the operation of a write frame. In the first light-emitting stage t15, the levels of the first scan signal S1 connected to all pixel circuits 10 in the array substrate are all at cutoff levels, the levels of the first switch signal S2 connected to all pixel circuits 10 are all at cutoff levels, and the levels of the second switch signal S3 connected to all pixel circuits 10 are all at cutoff levels. The write modules 200 in all pixel circuits 10 are cut off according to the first scan signal S1, the first initialization modules 500 in all pixel circuits 10 are cut off according to the first switch signal S2, and the second initialization modules 600 in all pixel circuits 10 are cut off according to the second switch signal S3. The driving module 100 outputs a driving signal.

[0114] In the first light-emitting stage t14, the light-emitting diode D1 can be controlled to emit light. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously realize that all row light-emitting diodes D1 emit light at the same time.

[0115] Specifically, the second transistor M2 is turned off according to the first scan signal S1, the third transistor M3 is turned off according to the first switch signal S2, the fourth transistor M4 is turned off according to the second switch signal S3, and the first capacitor C1 and the second capacitor C2 discharge the first gate G and the second gate B of the first transistor M1 respectively. Meanwhile, in the first light-emitting stage t14, the electrical levels of the light-emitting control signals EM accessed by all pixel circuits 10 are all conduction levels, and the light-emitting control modules 700 (i.e., the fifth transistor M5) in all pixel circuits 10 are all turned on according to the light-emitting control signal EM. The first transistor M1 outputs a driving signal, and the level of the second power supply signal ACVSS is the second level VSSL, where the second level VSSL is less than the first level VSSH, and VSSL is a low-level signal. The driving signal is transmitted to the light-emitting diode D1, and the light-emitting diode D1 emits light according to the driving signal. At this time, the driving current I output by the first transistor M1 is controlled by the voltage of Vdata - VDD, and drives the light-emitting diode D1 to emit light. When the first transistor M1 operates in the saturation region, its driving current can be approximately written as: I = K * (Vdata - VDD) 2 where K is a proportionality factor. It can be seen that the above pixel circuit 10 can effectively compensate for the threshold voltage Vth of the driving transistor DTFT, prevent the drift of the DTFT threshold voltage (Vth) from affecting the driving effect, prevent the overall brightness attenuation or afterimage of the screen, improve the brightness consistency of different regions of the screen, and enhance the image quality accuracy.

[0116] In this embodiment, the first switch signal S2, the second switch signal S3, and the light-emitting control signal EM can be global signals used to control the first initialization module 500, the second initialization module 600, and the light-emitting control module 700 in all pixel circuits 10. The second power supply signal ACVSS can be a global AC signal, which can include two voltage values with different functions of the first level VSSH and the second level VSSL, and VSSL < VSSH. In an optional implementation manner, VSSL < 0V < VSSH. S1_1, S1_n can be GIP signals with the composite function of including the data signal Vdata for simultaneous reset and row-by-row shift writing. It can be seen that only one group of GIP signals is included in the pixel circuit 10 provided in this application.

[0117] Figure 7 This is a signal timing diagram of one of the pixel circuits provided in the embodiment of the present application during the holding frame, which can be applied to the pixel circuit 10 as shown in Figure 5 In this embodiment, combining Figure 5 and Figure 7The working process of the pixel circuit 10 in one embodiment of this application during frame writing is described in detail, but it should not be construed as a limitation on the scope of the invention patent.

[0118] In one possible implementation, the pixel circuit 10 may include a hold frame in an operating mode. The hold frame may include a third initialization phase t21, during at least a portion of the third initialization phase t21, during which the level of the second switch signal S3 connected to all pixel circuits 10 in the array substrate is at an on level. The second initialization module 600 is turned on or off according to the second switch signal S3. In the third initialization stage t21, the anode of the light-emitting diode D1 can be reset. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously reset the anodes of all row sub-pixels.

[0119] Specifically, the fourth transistor M4 is turned on when the second switch signal S3 is at the on level, so that the second initialization signal Vref transmitted on the second initialization signal line can be transmitted through the fourth transistor M4 to the second terminal of the first transistor M1 and the anode of the light-emitting diode D1; when the second switch signal S3 is at the off level, the fourth transistor M4 is turned off. That is, each time the fourth transistor M4 is turned on, the second initialization signal Vref can be used to reset the second terminal of the first transistor M1 and the anode of the light-emitting diode D1. Through the reset operation, the brightness of the first frame can be improved while maintaining contrast. In some specific embodiments, the second switch signal S3 and the light emission control signal EM can be kept in the same timing for holding the frame and writing the frame to improve low-frequency flicker.

[0120] Furthermore, in the third initialization phase t21, when the level of the second switch signal S3 is on, the level of the light-emitting control signal EM is also on; when the level of the second switch signal S3 is off, the level of the light-emitting control signal EM is also off. That is, the fifth transistor M5 and the fourth transistor M4 are synchronously turned on and off. When the fifth transistor M5 is turned on according to the light-emitting control signal EM, the first power supply signal VDD can be transmitted through the fifth transistor M5 to the first terminal of the first transistor M1, and the first terminal of the first transistor M1 is reset using the first power supply signal VDD. At the same time, in the third initialization phase t21, the level of the second power supply signal ACVSS connected to the cathode of the light-emitting diode D1 can be maintained at the first level VSSH, and the voltage of the light-emitting diode D1 is reversed and it does not emit light.

[0121] In one possible implementation, during the operation of a holding frame, the pixel circuit 10 may further include a second light-emitting stage t22 after the third initialization stage t21. In the second light-emitting stage t22, the level of the second switching signal S3 connected to all pixel circuits 10 in the array substrate is at a cutoff level, and the second initialization module 600 in all pixel circuits 10 is turned off according to the second switching signal S3.

[0122] Furthermore, during the third initialization phase t21, the light emission control signal EM connected to all pixel circuits 10 in the array substrate can be at the on level. The light emission control modules 700 in all pixel circuits 10 are turned on according to the light emission control signal EM, and the level of the second power supply signal ACVSS is the second level VSSL, where the second level VSSL is lower than the first level VSSH, and VSSL is a low-level signal. The driving signal is transmitted to the light-emitting diode D1, and the light-emitting diode D1 emits light according to the driving signal.

[0123] In one possible implementation, when the pixel circuit 10 operates in a hold frame, the levels of the first scan signal S1 and the first switch signal S2 can be maintained at off levels. During the hold frame, the write module 200 and the first initialization module 300 remain in an off state.

[0124] The pixel circuit 10 design used in the array substrate 20 provided in this application requires fewer TFTs and contains fewer GIP signals. Its driving timing includes functions such as simultaneous gate reset of all row driving transistors, simultaneous anode reset of all row driving transistors, threshold voltage Vth compensation for all driving transistors, writing of row-by-row data signals Vdata, and simultaneous emission of all rows. By adjusting the DTFT Vth to a fixed value (0V) during the threshold compensation stage t12, brightness uniformity can be effectively improved. Furthermore, the compensation time of the threshold compensation stage t12 is adjustable, broadening the application scenarios of the array substrate 20. Therefore, the aforementioned array substrate 20 can achieve high PPI spatial arrangement while also improving image retention, increasing first-frame brightness, and enhancing display uniformity.

[0125] This invention also provides a driving method for driving a pixel circuit as described in any of the above embodiments. The pixel circuit 10 may include a first initialization stage t11, a threshold compensation stage t12, a data writing stage t13, a second initialization stage t14, and a first light emission stage t15 during the operation of a write frame. Figure 8 This is a flowchart illustrating one of the pixel circuit driving methods provided in an embodiment of this application. In one possible implementation, the pixel circuit driving method may include the following steps S100 to S500.

[0126] Step S100: In the first initialization phase, control the level of the first scan signal to be on, transmit the first power signal to the first end of the write module, control the level of the first switch signal to be on, and control the level of the second switch signal to be on.

[0127] In the first initialization phase t11, the levels of the first scan signal S1, the first switch signal S2, and the second switch signal S3 can all be on. Simultaneously, during the first initialization phase t11, the signal connected to the first terminal of the write module 200 can be the first power signal VDD. The write module 200 is turned on according to the first scan signal S1, transmitting the first power signal VDD to the first control terminal of the drive module 100. The first initialization module 500 is turned on according to the first switch signal S2, and the second initialization module 600 is turned on according to the second switch signal S3.

[0128] Additionally, during the first initialization phase t11, the level of the light-emitting control signal EM can be a conduction level. The fifth transistor M5 is turned on according to the light-emitting control signal EM and transmits the first power supply signal VDD to the first terminal of the first transistor M1, thus resetting the first terminal of the first transistor M1 using the first power supply signal VDD. The level of the second power supply signal ACVSS is the first level VSSH, where the first level VSSH is high.

[0129] Step S200: During the threshold compensation stage, the level of the first scan signal is controlled to be cut off, the level of the first switch signal is controlled to be on, and the level of the second switch signal is controlled to be on.

[0130] During the threshold compensation stage t12, the level of the first scan signal S1 can be off, the level of the first switch signal S2 can be on, and the level of the second switch signal S3 can be on. The write module 200 is turned off according to the first scan signal S1, the first initialization module 500 is turned on according to the first switch signal S2, and the second initialization module 600 is turned on according to the second switch signal S3.

[0131] In the threshold compensation stage t12, the threshold voltage Vth of the driving transistor (i.e., the first transistor M1) can be compensated. When the above includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously achieve threshold compensation for all driving transistors.

[0132] During the threshold compensation stage t12, the level of the light emission control signal EM can be the cutoff level, and the fifth transistor M5 is turned off according to the light emission control signal EM. At the same time, the level of the second power supply signal ACVSS connected to the cathode of the light emission diode D1 can be the first level VSSH, that is, at this time the cathode of the light emission diode D1 is connected to a high level, so the voltage of the light emission diode D1 is reversed and it does not emit light.

[0133] Step S300: During the data writing stage, the level of the first scan signal is controlled to be on, the data signal is transmitted to the first end of the writing module, the level of the first switch signal is controlled to be off, and the level of the second switch signal is controlled to be off.

[0134] During the data writing phase t13, the level of the first scan signal S1 is either on or off. The level of the first switch signal S2 is also either off, while the level of the second switch signal S3 is on. During data writing phase t13, the signal connected to the first terminal of the writing module 200 is the data signal Vdata. The writing module 200 can be turned on according to the first scan signal S1, and then transmits the data signal Vdata to the first gate G of the first transistor M1. The first storage module 300 then stores the data signal Vdata.

[0135] During the data writing phase t13, the level of the light emission control signal EM can be the on level, and the fifth transistor M5 is turned on according to the light emission control signal EM. The level of the second power supply signal ACVSS connected to the cathode of LED D1 can still be the first level VSSH, that is, at this time the cathode of LED D1 is connected to a high level, so the voltage of LED D1 is reversed and it does not emit light.

[0136] Step S400: In the second initialization phase, the level of the first scan signal is controlled to be off level, the level of the first switch signal is controlled to be off level, and the level of the second switch signal is controlled to be on level.

[0137] In the second initialization phase t14, the level of the first scan signal S1 is at the off level, the level of the first switch signal S2 can be at the off level, and the level of the second switch signal S3 can be at the on level. The writing module 200 is turned off according to the first scan signal S1, the first initialization module 500 is turned off according to the first switch signal S2, and the second initialization module 600 is turned on according to the second switch signal S3. The second initialization module 600 resets the anode of the light-emitting module 800.

[0138] In the second light-emitting stage t14, the anode of the light-emitting module 800 can be reset. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously reset the anodes of all row light-emitting diodes D1.

[0139] During the second initialization phase t14, the level of the light emission control signal EM is at the cutoff level, and the light emission control module 700 is turned off according to the light emission control signal EM. The second initialization signal Vref is transmitted through the fourth transistor M4 to the second electrode of the first transistor M1 and the anode of the light emission diode D1, thereby resetting the second electrode of the first transistor M1 and the anode of the light emission diode D1. At the same time, during the second initialization phase t14, the level of the second power supply signal ACVSS connected to the cathode of the light emission diode D1 can still be the first level VSSH.

[0140] Step S500: In the first light emission stage, the level of the first scan signal is controlled to be cut off, the level of the first switch signal is controlled to be cut off, and the level of the second switch signal is controlled to be cut off.

[0141] During the first light-emitting stage t15, the level of the first scan signal S1 is at the cutoff level, the level of the first switch signal S2 can be at the cutoff level, and the level of the second switch signal S3 can be at the cutoff level. The writing module 200 is cut off according to the first scan signal S1, the first initialization module 500 is cut off according to the first switch signal S2, the second initialization module 600 is cut off according to the second switch signal S3, and the driving module 100 outputs a driving signal.

[0142] In the first light-emitting stage t14, the light-emitting diode D1 can be controlled to emit light. When the array substrate includes multiple pixel circuits 10, the multiple pixel circuits 10 can simultaneously enable all row light-emitting diodes D1 to emit light at the same time.

[0143] During the first light-emitting stage t14, the light-emitting control signal EM is at the on level, and the fifth transistor M5 is turned on according to the light-emitting control signal EM. The first transistor M1 outputs a drive signal, and the level of the second power supply signal ACVSS is the second level VSSL, where the second level VSSL is less than the first level VSSH, and VSSL is a low-level signal. The drive signal is transmitted to the light-emitting diode D1, and the light-emitting diode D1 emits light according to the drive signal.

[0144] The pixel circuit driving method provided in this application embodiment can be applied to the pixel circuit 10 in the array substrate 20 provided in this application embodiment. The driving scheme contains fewer GIP signals, and its driving timing includes functions such as simultaneous reset of the gates of all row driving transistors, simultaneous reset of all row anodes, writing of row-by-row data signals Vdata, threshold voltage Vth compensation for all driving transistors, and simultaneous emission of all rows. Therefore, the array substrate 20 can improve display effects such as image retention, first frame brightness, and display uniformity while achieving high PPI spatial arrangement.

[0145] Furthermore, the above driving method can also achieve driving control of the pixel circuit 10 in the holding frame. Specifically, during at least a portion of the third initialization phase t21 of the holding frame, the level of the second switch signal S3 is controlled to be on; during the second emission phase t22 of the holding frame, the level of the second switch signal S3 is controlled to be off. Simultaneously, during the third initialization phase, when the level of the second switch signal S3 is on, the level of the emission control signal EM is also controlled to be on; when the level of the second switch signal S3 is off, the level of the emission control signal EM is also controlled to be off; during the second emission phase t22, the level of the emission control signal is controlled to be on. Additionally, during the holding frame, the levels of the first scan signal S1 and the first switch signal S2 are kept at off levels.

[0146] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0147] This invention also provides a display panel, which can be the array substrate 20 as described in any of the above embodiments. The array substrate 20 may include one or more sets of pixel circuits 10. The pixel circuits 10 can be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. This display panel can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0148] A display panel includes multiple pixel circuits 10 arranged in n rows of pixel circuit groups, where n is an integer greater than 0. For example, the value of n can include, but is not limited to, 1, 2, 3, 5, 10, 100, 1000, 3000, etc. During the operation of one display frame, the display panel may include a data writing stage t3, which may include n independent sub-stages. In the data writing stage t3, the signal connected to the first terminal of the writing module 200 in each pixel circuit 10 is a data signal Vdata. Simultaneously, the writing modules 200 in the n rows of pixel circuit groups are respectively connected to n first scan signals S1_1 to S1_n, each of which corresponds to a specific sub-stage.

[0149] Specifically, the i-th first scan signal S1_i sequentially provides a conduction level to the i-th row pixel circuit group row by row in the i-th sub-stage, i=1,2,3,…,n. That is, in the i-th sub-stage, the writing module 200 of the i-th row pixel circuit group is turned on according to the i-th first scan signal S1_i to transmit the data signal Vdata to the first gate G of the first transistor M1. That is, the level of the i-th first scan signal S1_i is the conduction level in the corresponding i-th sub-stage, and the level is the cutoff level at other times, so as to realize the row-by-row writing of the data signal Vdata.

[0150] In one possible implementation, the display panel may further include a light-emitting stage (such as the first light-emitting stage t15 for writing the frame or the second light-emitting stage t22 for holding the frame) during the operation of a display frame. During the light-emitting stage, the driving module 100 of each pixel circuit 10 outputs a driving signal to the light-emitting module 800, and the light-emitting module 800 of each pixel circuit 10 emits light simultaneously according to the driving signal.

[0151] Furthermore, in the first initialization stage t11, threshold compensation stage t12, second initialization stage t14, first light emission stage t15, and holding frame, the first scan signals S1_1 to S1_n connected to each pixel circuit 10 are all the same. For example, the first scan signals S1_1 to S1_n are all on, or the first scan signals S1_1 to S1_n are all off. In the data writing stage t13 of the write frame, the first scan signals S1_1 to S1_n are turned on line by line to realize the line-by-line writing of the data signal Vdata of the n pixel circuits 10. The first switch signal S2, the second switch signal S3, and the light emission control EM connected to each pixel circuit 10 in the display panel are all the same. That is, during the operation of a display frame, each pixel circuit 10 simultaneously performs initialization, threshold compensation, and light emission operations in the first initialization stage t11, threshold compensation stage t12, second initialization stage t14, first light emission stage t15, and holding frame of the write frame; in the data writing stage t13 of the write frame, n first scan signals are used to write the data signals Vdata of n pixel circuits 10 line by line.

[0152] In one possible implementation, the display panel may also include at least one multiplexer 900. Figure 9 This is a schematic diagram of the structural connection between a multiplexer and a pixel circuit provided in one embodiment of this application. A multiplexer 900 is connected to the first end of the write module 200 in a pixel circuit 10. The multiplexer 900 is used to transmit the first power signal VDD to the first end of the write module 200 according to the first selection signal mux1, or to transmit the data signal Vdata to the first end of the write module 200 according to the second selection signal mux2.

[0153] In one possible implementation, Figure 10 This is a schematic diagram of the circuit connection between a multiplexer and a pixel circuit provided in one embodiment of this application. The multiplexer 900 may include a first switch module 910 and a second switch module 920.

[0154] The first switch module 910 can be connected between the first power line and the first terminal of the write module 200. The first switch module 910 can be used to turn on or off the connection between the first power line and the first terminal of the write module 200 according to the first selection signal mux1. When the first switch module 910 is turned on according to the first selection signal mux1, the signal accessed at the first terminal of the write module 200 can be the first power signal VDD transmitted on the first power line.

[0155] The second switch module 920 can be connected between the data line and the first terminal of the write module 200. The second switch module 920 can be used to turn on or off the connection between the data line and the first terminal of the write module 200 according to the second selection signal mux2. When the second switch module 920 is turned on according to the second selection signal mux2, the signal connected to the first terminal of the write module 200 can be the data signal Vdata transmitted on the data line.

[0156] Furthermore, when the first switch module 910 is turned on according to the first selection signal mux1, the second switch module 920 is turned off according to the second selection signal mux2; when the second switch module 920 is turned on according to the second selection signal mux2, the first switch module 910 is turned off according to the first selection signal mux1. That is, at any given time, only one of the first switch module 910 and the second switch module 920 is in the on state.

[0157] In one possible implementation, the first switch module 910 may include a sixth transistor M6. The gate of the sixth transistor M6 may be connected to the first selection signal mux1 as the control terminal of the first switch module 910. The first terminal of the sixth transistor M6 may be connected to the first power line as the first terminal of the first switch module 910. The second terminal of the sixth transistor M6 may be connected to the first terminal of the write module 200 as the second terminal of the first switch module 910.

[0158] In one possible implementation, the second switch module 920 may include a seventh transistor M7. The gate of the seventh transistor M7 may be used as the control terminal of the second switch module 920 and connected to the second selection signal mux2. The first terminal of the seventh transistor M7 may be used as the first terminal of the second switch module 920 and connected to the data line. The second terminal of the seventh transistor M7 may be used as the second terminal of the second switch module 920 and connected to the first terminal of the write module 200.

[0159] In one possible implementation, Figure 11 This is a schematic diagram of the signal timing of a multiplexer provided in one embodiment of the present application during the writing frame or holding frame. In the first initialization stage t11 of the writing frame, the first switch module 910 can be turned on according to the first selection signal mux1, and the second switch module 920 can be turned off according to the second selection signal mux2. In the data writing stage t13 of the writing frame, the first switch module 910 can be turned off according to the first selection signal mux1, and the second switch module 920 can be turned on according to the second selection signal mux2.

[0160] Specifically, in the first initialization phase t11 of the write frame, the level of the first selection signal mux1 is on, the level of the second selection signal mux2 is off, the sixth transistor M6 is on, and the seventh transistor M7 is off. The sixth transistor M6 transmits the first power signal VDD transmitted on the first power line to the first terminal of the write module 200 in the pixel circuit 10. In the data writing phase t13 of the write frame, the level of the first selection signal mux1 is off, the level of the second selection signal mux2 is on, the sixth transistor M6 is off, and the seventh transistor M7 is on. The seventh transistor M7 transmits the data signal Vdata transmitted on the data line to the first terminal of the write module 200 in the pixel circuit 10.

[0161] In one possible implementation, such as Figure 11 As shown, during the hold frame, the levels of the first selection signal mux1 and the second selection signal mux2 can be maintained at the off level. That is, during the hold frame, the first switch module 910 and the second switch module 920 can remain closed.

[0162] This invention also provides a display device, which may include the pixel circuit described in any of the above embodiments. The display device may include one or more sets of pixel circuits 10. The pixel circuits 10 may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. Similarly, this display device can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0163] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0164] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, Includes at least one pixel circuit, the pixel circuit comprising: A driving module, connected between the first power line and the light-emitting module, is used to output driving signals; the driving module includes a first control terminal and a second control terminal; A first storage module is connected between the first control terminal and the first terminal of the drive module, and is used to store voltage information between the first control terminal and the first terminal of the drive module; The second storage module is connected between the second control terminal and the first terminal of the drive module, and is used to store the voltage information between the second control terminal and the first terminal of the drive module; The writing module is connected to the first control terminal of the driving module and is used to transmit a data signal or a first power signal to the first control terminal of the driving module according to the first scan signal. The first initialization module is connected between the second control terminal of the drive module and the first initialization signal line, and is used to turn on or off the connection between the second control terminal of the drive module and the first initialization signal line according to the first switch signal; The second initialization module is connected between the second end of the drive module and the second initialization signal line, and is used to turn on or off the connection between the second end of the drive module and the second initialization signal line according to the second switch signal.

2. The array substrate according to claim 1, characterized in that, The driving module includes a first transistor, which is a dual-gate transistor. The first gate of the first transistor serves as the first control terminal of the driving module, the second gate of the first transistor serves as the second control terminal of the driving module, the first electrode of the first transistor serves as the first terminal of the driving module, and the second electrode of the first transistor serves as the second terminal of the driving module. Preferably, the first storage module includes a first capacitor, the first terminal of the first capacitor is connected to the first control terminal of the drive module as the first terminal of the first storage module, and the second terminal of the first capacitor is connected to the first terminal of the drive module as the second terminal of the first storage module. Preferably, the second storage module includes a second capacitor, the first terminal of the second capacitor is connected to the second control terminal of the drive module as the first terminal of the second storage module, and the second terminal of the second capacitor is connected to the first terminal of the drive module as the second terminal of the second storage module. Preferably, the writing module includes a second transistor, the gate of the second transistor is connected to the first scan signal as the control terminal of the writing module, the first electrode of the second transistor is connected to the data signal or the first power signal as the first terminal of the writing module, and the second electrode of the second transistor is connected to the first control terminal of the driving module as the second terminal of the writing module. Preferably, the second transistor is a dual-gate transistor, the first gate of the second transistor is connected to the first scan signal as the control terminal of the write module, and the second gate of the second transistor is connected to the first power line or the first initialization signal line as the second control terminal of the write module. Preferably, the first initialization module includes a third transistor, the gate of the third transistor is connected to the first switch signal as the control terminal of the first initialization module, the first electrode of the third transistor is connected to the first initialization signal line as the first terminal of the first initialization module, and the second electrode of the third transistor is connected to the second control terminal of the drive module as the second terminal of the first initialization module. Preferably, the third transistor is a dual-gate transistor, the first gate of the third transistor is connected to the first switch signal as the control terminal of the first initialization module, and the second gate of the third transistor is connected to the second control terminal of the first initialization module, which is connected to the first power line or the first initialization signal line or the second control terminal of the drive module. Preferably, the second initialization module includes a fourth transistor, the gate of the fourth transistor is connected to the second switch signal as the control terminal of the second initialization module, the first terminal of the fourth transistor is connected to the second initialization signal line as the first terminal of the second initialization module, and the second terminal of the fourth transistor is connected to the second terminal of the driving module as the second terminal of the second initialization module. Preferably, the pixel circuit further includes: A light-emitting control module is connected between the first power line and the first end of the driving module, and is used to turn on or off the connection between the first power line and the first end of the driving module according to the light-emitting control signal. Preferably, the light-emitting control module includes a fifth transistor, the gate of the fifth transistor serves as the control terminal of the light-emitting control module and is connected to the light-emitting control signal, the first electrode of the fifth transistor serves as the first terminal of the light-emitting control module and is connected to the first power line, and the second electrode of the fifth transistor serves as the second terminal of the light-emitting control module and is connected to the first terminal of the driving module. Preferably, the pixel circuit further includes: The light-emitting module is connected between the second end of the driving module and the second power line, and is used to emit light according to the driving signal; the second power line is used to output a second power signal.

3. The array substrate according to claim 1 or 2, characterized in that, The first initialization signal line, the second initialization signal line, the first power line, and the second power line are all global signal lines; Preferably, the array substrate includes multiple pixel circuits, and the first power signal, the first switch signal, the second switch signal, the first initialization signal, the second initialization signal, the light emission control signal, and the second power signal connected to all the pixel circuits are global signals.

4. The array substrate according to claim 1 or 2, characterized in that, The pixel circuit includes at least one of a metal oxide transistor and a low-temperature polysilicon transistor. Preferably, the pixel circuit includes at least one metal-oxide transistor and at least one low-temperature polysilicon transistor; Preferably, the writing module and the first initialization module both include metal-oxide transistors, and the driving module, the second initialization module and the light-emitting control module all include low-temperature polycrystalline silicon transistors; Preferably, the writing module and the first initialization module both include N-type transistors, and the driving module, the second initialization module and the light emission control module all include P-type transistors.

5. The array substrate according to claim 1 or 2, characterized in that, The pixel circuit includes a write frame in one working mode. The write frame includes at least a first initialization phase. In the first initialization phase, the write module transmits the first power signal to the first control terminal of the drive module according to the first scan signal. The first initialization module is turned on according to the first switch signal, and the second initialization module is turned on according to the second switch signal. Preferably, during the first initialization phase, the level of the first scan signal connected to all the pixel circuits is a conducting level, the level of the first switch signal connected to all the pixel circuits is a conducting level, and the level of the second switch signal connected to all the pixel circuits is a conducting level. Preferably, during the operation of a write frame, the pixel circuit includes a threshold compensation stage after the first initialization stage. In the threshold compensation stage, the write module is turned off according to the first scan signal, the drive module is turned on according to the voltage at the first control terminal and the second control terminal of the drive module, the first initialization module is turned on according to the first switch signal, the second initialization module is turned on according to the second switch signal, and the first terminal of the drive module charges the second initialization signal line to adjust the threshold voltage corresponding to the first gate of the drive module to the target value. Preferably, during the threshold compensation stage, the level of the first scan signal connected to all the pixel circuits is the cutoff level, the level of the first switch signal connected to all the pixel circuits is the on level, and the level of the second switch signal connected to all the pixel circuits is the on level. Preferably, during the operation of a write frame, the pixel circuit includes a data writing stage after the threshold compensation stage. In the data writing stage, the writing module transmits the data signal to the first control terminal of the driving module according to the first scan signal, the first initialization module is turned off according to the first switch signal, and the second initialization module is turned off according to the second switch signal. Preferably, the array substrate includes a plurality of pixel circuits, which are arranged in n rows of pixel circuit groups, where n is an integer greater than 0. The n rows of pixel circuit groups are respectively connected to n first scan signals. The data writing stage of the same write frame includes at least n independent sub-stages. The i-th first scan signal sequentially provides a conduction level to the i-th row of pixel circuit groups in the i-th sub-stage, i=1,2,3,…,n. Preferably, during the data writing stage, the level of the first switch signal connected to all the pixel circuits is the cutoff level, and the level of the second switch signal connected to all the pixel circuits is the cutoff level. Preferably, during the operation of a write frame, the pixel circuit includes a second initialization phase after the data writing phase. In the second initialization phase, the write module is turned off according to the first scan signal, the first initialization module is turned off according to the first switch signal, and the second initialization module is turned on according to the second switch signal. Preferably, during the second initialization phase, the level of the first scan signal connected to all the pixel circuits is a cutoff level, the level of the first switch signal connected to all the pixel circuits is a cutoff level, and the level of the second switch signal connected to all the pixel circuits is a conduction level. Preferably, during the operation of a write frame, the pixel circuit includes a first light-emitting stage after the second initialization stage. In the first light-emitting stage, the write module is turned off according to the first scan signal, the first initialization module is turned off according to the first switch signal, the second initialization module is turned off according to the second switch signal, and the drive module outputs a drive signal. Preferably, during the first light emission stage, the level of the first scan signal connected to all the pixel circuits is a cutoff level, the level of the first switch signal connected to all the pixel circuits is a cutoff level, and the level of the second switch signal connected to all the pixel circuits is a cutoff level. Preferably, in the first initialization phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the first level; in the threshold compensation phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the first level; in the data writing phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the first level; in the second initialization phase, the light-emitting control module is turned off according to the light-emitting control signal, and the level of the second power signal jumps from the first level to the second level; in the first light-emitting phase, the light-emitting control module is turned on according to the light-emitting control signal, and the level of the second power signal is the second level; wherein, the second level is lower than the first level; Preferably, the second initialization signal line is used to transmit a second initialization signal. In the first initialization phase, the level of the second initialization signal is a third level; in the second initialization phase, the level of the second initialization signal is a fourth level, wherein the third level is different from the fourth level. Preferably, the fourth level is greater than the second level.

6. The array substrate according to claim 5, characterized in that, The pixel circuit includes a hold frame in one operating mode, the hold frame including at least a third initialization phase, during at least a portion of the time period in the third initialization phase, the level of the second switch signal is an on level; Preferably, during the operation of one of the holding frames, the pixel circuit includes a second light-emitting stage after the third initialization stage, in which the level of the second switch signal is a cutoff level; Preferably, in the hold frame, the levels of the first scan signal and the first switch signal are maintained at the off level; Preferably, in the third initialization phase, when the level of the second switch signal is on, the level of the light emission control signal is on; when the level of the second switch signal is off, the level of the light emission control signal is off. During the second light-emitting stage, the level of the light-emitting control signal is the on level.

7. A driving method for a pixel circuit, characterized in that, For driving the pixel circuit in the array substrate as described in any one of claims 1 to 6, the pixel circuit including a write frame in an operating mode, the pixel circuit including a first initialization phase, a threshold compensation phase, a data writing phase, a second initialization phase, and a first emission phase during the operation of a write frame, the driving method includes: During the first initialization phase, the level of the first scan signal is controlled to be on, the first power signal is transmitted to the first terminal of the writing module, the level of the first switch signal is controlled to be on, and the level of the second switch signal is controlled to be on. During the threshold compensation stage, the level of the first scan signal is controlled to be off, the level of the first switch signal is controlled to be on, and the level of the second switch signal is controlled to be on. During the data writing phase, the level of the first scan signal is controlled to be on, and the data signal is transmitted to the first terminal of the writing module. The level of the first switch signal is controlled to be off, and the level of the second switch signal is controlled to be off. During the second initialization phase, the level of the first scan signal is controlled to be off, the level of the first switch signal is controlled to be off, and the level of the second switch signal is controlled to be on. During the first light emission stage, the level of the first scanning signal is controlled to be at the cutoff level, the level of the first switching signal is controlled to be at the cutoff level, and the level of the second switching signal is controlled to be at the cutoff level.

8. The driving method for the pixel circuit according to claim 7, characterized in that, The array substrate includes multiple pixel circuits, which are arranged in n rows of pixel circuit groups, where n is an integer greater than 0. The n rows of pixel circuit groups are respectively connected to n first scan signals. The data writing stage of the same write frame includes at least n independent sub-stages. The i-th first scan signal is controlled to provide a conduction level to the i-th row of pixel circuit groups in the i-th sub-stage, i=1,2,3,…,n. Preferably, the pixel circuit further includes a light-emitting module connected between the second terminal of the driving module and the second power line; the second power line is used to output a second power signal, and the driving method further includes: During the first initialization phase, the level of the control signal for light emission is set to the on level, and the level of the control signal for the second power supply is set to the first level. During the threshold compensation stage, the level of the control signal for light emission is controlled to be at the cutoff level, and the level of the second power supply signal is controlled to be at the first level. During the data writing phase, the level of the control signal for light emission is set to the on level, and the level of the second power signal is set to the first level. During the second initialization phase, the level of the control signal for light emission is set to the cutoff level, and the level of the control signal for the second power supply is set to the first level. During the first light-emitting stage, the level of the light-emitting control signal is the on level, and the level of the second power supply signal is the second level; wherein the second level is lower than the first level; Preferably, the second initialization signal line is used to transmit a second initialization signal. In the first initialization phase, the level of the second initialization signal is controlled to be a third level; in the second initialization phase, the level of the second initialization phase is controlled to be a fourth level, wherein the third level and the fourth level are different. Preferably, the pixel circuit includes a holding frame in one operating mode, and the pixel circuit includes a third initialization phase and a second emission phase during the operation of the holding frame, and the driving method includes: During at least a portion of the third initialization phase, the level of the second switch signal is controlled to be at the on level; During the second light-emitting phase, the level of the second switching signal is controlled to be at the cutoff level; Preferably, in the hold frame, the levels of the first scan signal and the first switch signal are kept at the off level; Preferably, in the third initialization phase, when the level of the second switch signal is on, the level of the light emission control signal is controlled to be on; when the level of the second switch signal is off, the level of the light emission control signal is controlled to be off. During the second light-emitting stage, the level of the light-emitting control signal is set to the on level.

9. A display panel, characterized in that, The array substrate includes any one of claims 1 to 9, the array substrate includes at least one pixel circuit, the display panel further includes at least one multiplexer, one of the multiplexers is connected to a first terminal of the write module in one of the pixel circuits, the multiplexer is used to transmit a first power signal to the first terminal of the write module according to a first selection signal, or to transmit the data signal to the first terminal of the write module according to a second selection signal.

10. The display panel according to claim 9, characterized in that, The multiplexer includes: A first switch module is connected between the first power line and the first end of the write module, and is used to turn on or off the connection between the first power line and the first end of the write module according to the first selection signal. The second switch module is connected between the data line and the first end of the write module, and is used to turn on or off the connection between the data line and the first end of the write module according to the second selection signal. Preferably, the first switching module includes a sixth transistor, the gate of the sixth transistor serves as the control terminal of the first switching module and is connected to the first selection signal, the first electrode of the sixth transistor serves as the first terminal of the first switching module and is connected to the first power line, and the second electrode of the sixth transistor serves as the second terminal of the first switching module and is connected to the first terminal of the writing module. Preferably, the second switching module includes a seventh transistor, the gate of the seventh transistor is connected to the second selection signal as the control terminal of the second switching module, the first terminal of the seventh transistor is connected to the data line as the first terminal of the second switching module, and the second terminal of the seventh transistor is connected to the first terminal of the write module as the second terminal of the second switching module. Preferably, the pixel circuit includes a write frame in one working mode, and the pixel circuit includes a first initialization phase in the working process of a write frame. In the first initialization phase of the write frame, the first switch module is turned on according to the first selection signal, and the second switch module is turned off according to the second selection signal. In the data writing phase of the write frame, the first switch module is turned off according to the first selection signal, and the second switch module is turned on according to the second selection signal.

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