A full-dimension mismatch self-correcting time-interleaved ADC system of a coherent acquisition platform

Abstract

This invention provides a coherent acquisition platform with a full-dimensional mismatch self-correction time-interleaved ADC system, belonging to the field of mismatch self-correction technology. The architecture includes an analog front-end conditioning module, a time-interleaved ADC sampling array, a clock synchronization distribution module, a full-dimensional mismatch self-correction module, and a high-speed data transmission module. The ADC sampling array employs an interleaved structure with multiple main channels and multiple sub-ADCs per channel, achieving ultra-high-speed synchronous acquisition of multiple coherent signals. The full-dimensional mismatch self-correction module pioneers a dual-mode detection mechanism of "calibration sequence injection + blind estimation," which can detect and correct four types of mismatches—gain, delay, bias, and bandwidth—between sub-ADCs in real time, balancing initial calibration accuracy with dynamic environmental adaptability. This invention has advantages such as high sampling rate, good synchronization, excellent mismatch suppression effect, and strong signal integrity, and can be directly used in coherent acquisition equipment with speeds of 100G and above, providing high-quality signals for subsequent digital demodulation.

Description

Technical Field

[0001] This invention relates to the field of mismatch self-correction technology, and in particular to a coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system. Background Technology

[0002] High-speed coherent optical communication systems (such as 100G PM-QPSK) require ultra-high-speed, high-precision synchronous acquisition of four analog signals with dual polarization I / Q channels, with a single-channel sampling rate of at least 80 GSps. Limited by the sampling rate bottleneck of a single-channel ADC, the time-interleaved ADC (TIADC) architecture has become the mainstream technology for achieving ultra-high-speed sampling. It achieves an equivalent high sampling rate by interleaving multiple low-speed sub-ADCs for sampling in time.

[0003] Currently, the time-interleaved ADC architecture used in coherent acquisition platforms mainly includes the following technical solutions: (1) Dual-channel time-interleaving architecture An 80GSps sampling rate is achieved by interleaving two 40GSps ADCs. This approach suffers from limited channel count, limited interleaving gain, and a lack of dedicated channel synchronization and mismatch correction hardware modules, resulting in severe inter-channel delay, gain, and bias mismatches. Actual measurements show that inter-channel delay mismatch can exceed 300 fs, gain mismatch is ≥5%, sampling signal distortion exceeds 2%, and the effective bit width (ENOB) is only 8.2 bits, significantly impacting subsequent demodulation accuracy.

[0004] (2) Multi-channel simple splicing architecture Some solutions use four or more low-speed ADCs for interleaving and splicing, but the hardware layout is not optimized for symmetry, there is a significant time delay deviation in clock distribution, the impedance matching between the analog front end and the ADC interface is poor, and reflection and crosstalk are easily generated during high-speed signal transmission, resulting in a significant drop in the effective number of bits (ENOB) to below 8 bits, which cannot meet the requirements of high-precision demodulation.

[0005] (3) Mismatch correction scheme Existing mismatch correction techniques are mainly divided into two categories: offline calibration and simple online compensation. Offline calibration cannot adapt to the dynamic mismatch caused by changes in temperature and voltage of ADC devices. When the operating temperature changes by 10°C, the mismatch parameter shift can reach more than 3%. Simple online compensation only targets a single mismatch type (such as only compensating for time delay mismatch) and does not achieve full-dimensional mismatch correction of gain, time delay, bias, and bandwidth. The correction effect is limited and it cannot suppress the effects of four types of mismatch at the same time.

[0006] Furthermore, the existing time-interleaved ADC architecture is not customized for the four-channel synchronous acquisition requirements of the 100G coherent acquisition platform. The sampling timing deviation between polarizations and between I / Q channels is large, reaching more than 100 fs in actual measurements. This cannot guarantee the acquisition synchronization of dual-polarization I / Q signals, which seriously affects the demodulation performance of PM-QPSK signals, resulting in the demodulation bit error rate failing to meet the requirements of the communication system.

[0007] In summary, existing time-interleaved ADC architectures have significant shortcomings in terms of channel mismatch suppression, four-channel synchronization, signal integrity, and dynamic mismatch adaptability. There is an urgent need for a time-interleaved ADC architecture that can achieve ultra-high speed, multi-channel synchronization, low mismatch, and high integration to meet the engineering application requirements of coherent acquisition platforms with speeds of 100G and above. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a coherent acquisition platform with a full-dimensional mismatch self-correction time-interleaved ADC system, which aims to solve the technical pain points of the existing 100G coherent acquisition platform time-interleaved ADC architecture, namely "large channel mismatch, poor four-channel synchronization, insufficient signal integrity, and poor dynamic mismatch adaptability". By designing a time-interleaved ADC architecture with multi-channel synchronization, full-dimensional mismatch self-correction, low distortion, and high integration, ultra-high-speed sampling is achieved, ensuring the synchronization and integrity of the acquisition of dual-polarization I / Q four-channel signals, providing high-quality digital signals for subsequent digital demodulation, and adapting to the engineering application requirements of coherent acquisition platforms with speeds of 100G and above.

[0009] To achieve the above objectives, this application proposes a coherent acquisition platform with full-dimensional mismatch self-correction time-interleaved ADC system, comprising: The analog front-end conditioning module is used to condition the multiple coherent analog signals input to the coherent receiver; The time-interleaved ADC sampling array includes multiple main channels, each of which includes multiple sub-ADCs. Each sub-ADC is spliced ​​together by time interleaving to achieve single-channel ultra-high-speed sampling, and the multiple main channels work synchronously to achieve synchronous acquisition of multiple coherent signals. The clock synchronization distribution module is used to provide a synchronization clock signal to each of the sub-ADCs in order to control the sampling timing of each sub-ADC; The full-dimensional mismatch self-correction module is used to detect and correct gain mismatch, delay mismatch, bias mismatch and bandwidth mismatch between each sub-ADC in real time; A high-speed data transmission module is used to transmit the corrected sampled data to the FPGA core processing unit; wherein, the FPGA core processing unit is used for subsequent digital demodulation.

[0010] As a further solution, in the time-interleaved ADC sampling array, the multiple main channels are 4, corresponding to the four signals X_I, X_Q, Y_I, and Y_Q of the PM-QPSK coherent signal respectively; each main channel includes 4 sub-ADCs, and each sub-ADC is spliced ​​together by time interleaving to achieve a single-channel sampling rate of 80GSps; wherein, the sub-ADC is a high-speed ADC chip of 20GSps@12bit, and the effective number of bits of a single sub-ADC is ≥10 bits.

[0011] As a further solution, the analog front-end conditioning module has a multi-channel symmetrical structure. Each conditioning unit includes a programmable gain amplifier, a low-pass filter, and an impedance matching network connected in series. The gain of the programmable gain amplifier is adjustable from 0 to 20 dB, the cutoff frequency of the low-pass filter is ≥ 25 GHz, and the impedance matching network is used to achieve 50 Ω impedance matching. Furthermore, the component parameter consistency error of the multi-channel conditioning circuit is ≤ 1%.

[0012] As a further solution, the clock synchronization distribution module includes a 10GHz ultra-low phase noise crystal oscillator as the clock source, and clock division and phase adjustment are achieved through phase-locked loop and delay phase-locked loop; the clock tree of the clock synchronization distribution module adopts symmetrical equal-length wiring, the clock delay deviation between channels is ≤10fs, and the sampling clock jitter output to the sub-ADC is ≤30fs.

[0013] As a further solution, the full-dimensional mismatch self-correction module obtains mismatch parameters through a dual-mode detection mechanism, wherein the dual modes include: The calibration sequence injection mode is used to calculate the initial mismatch parameters by injecting a known calibration signal into the analog front end during the initial stage of system power-on. Blind estimation mode is used to estimate dynamic mismatch parameters in real time based on the constant mode and orthogonality of the input coherent signal during normal system operation.

[0014] As a further solution, the full-dimensional mismatch self-correction module corrects for different mismatch types in the following ways: To address bias mismatch, correction is performed by subtracting the DC mean of the sub-ADC sampling data; Gain mismatch is corrected by multiplying by a gain correction factor; To address the time delay mismatch, a fractional delay filter is used to adjust and correct the timing of the sampled data. To address bandwidth mismatch, a frequency domain equalization filter is used to correct the amplitude-frequency characteristics of the sampled data.

[0015] As a further solution, the full-dimensional mismatch self-correction module updates the mismatch parameters every 100μs to dynamically track mismatches caused by environmental changes.

[0016] As a further solution, the high-speed data transmission module adopts the JESD204C high-speed serial interface, with a single-channel interface rate of 10Gbps. Each main channel uses eight parallel JESD204C interfaces. The high-speed data transmission module also integrates a FIFO buffer unit and a CRC check unit, with a data transmission error rate ≤10%. -12 .

[0017] As a further solution, it also includes a collaborative optimization design, which includes: a symmetrical partitioned hardware layout for the analog front-end conditioning module, the time-interleaved ADC sampling array, the clock synchronization distribution module, the full-dimensional mismatch self-correction module, and the high-speed data transmission module; providing independent power supplies for analog and digital circuits; and a thermal design using high thermal conductivity materials and heat sinks. The system operates in a temperature range of 0-70℃, and the sampling start time deviation of the four main channels is ≤20fs.

[0018] As a further solution, a mismatch self-correction method is implemented through the following steps: Step S1: After the system is powered on, it enters the initial calibration phase, injecting a calibration signal with known amplitude and phase into the analog front end through the calibration sequence injection mode; Step S2: Calculate the initial gain mismatch parameters, delay mismatch parameters, bias mismatch parameters, and bandwidth mismatch parameters based on the sampling results of each sub-ADC; Step S3: Load the initial correction coefficients and perform full-dimensional initial correction on the output of the time-interleaved ADC sampling array. Then the system enters normal operation and begins to acquire coherent signals. Step S4: During normal operation, switch to blind estimation mode and estimate dynamic mismatch parameters in real time based on the constant mode or orthogonal characteristics of the received signal. Step S5: At each preset update cycle, dynamically update the correction coefficients based on the real-time estimated dynamic mismatch parameters, and adjust the correction strategy; Step S6: Repeat steps S4 to S5 until the system is shut down, thereby achieving real-time self-correction of mismatch across all dimensions.

[0019] Compared with related technologies, the coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system provided by this invention has the following advantages: 1. This invention employs a time-interleaving architecture of "4 main channels × 4 sub-ADCs per channel" to achieve synchronous sampling of four channels at 80GSps, with an effective bit width (ENOB) ≥ 10.5 bits and a sampling signal distortion < 0.3%. Through equal-length clock tree distribution (delay deviation ≤ 10fs) and synchronous acquisition control, the sampling start time deviation of the four channels is ≤ 20fs. Compared with existing technologies (ENOB only 8.2 bits, distortion 2%, synchronization deviation ≥ 100fs), the effective bit width is increased by more than 2.3 bits, the distortion is reduced by approximately 85%, and the synchronization is improved by more than 5 times, fully meeting the stringent synchronous acquisition requirements of 100G PM-QPSK signals.

[0020] 2. This invention pioneers a dual-mode detection mechanism of "calibration sequence injection + blind estimation," combined with four types of correction units—bias, gain, delay, and bandwidth—to achieve real-time self-correction of mismatches across all dimensions. After correction, the gain mismatch is ≤0.5%, the delay mismatch is ≤20fs, the bias mismatch is ≤0.1mV, and the bandwidth mismatch is ≤1%, with a mismatch suppression effect more than 5 times better than existing technologies. The dynamic adaptive mechanism updates parameters every 100μs, with a tracking error of ≤0.1% within the 0-70℃ range, solving the technical problems of offline calibration being unable to adapt to environmental changes and simple online compensation being unable to cover mismatches across all dimensions.

[0021] 3. This invention integrates analog front-end conditioning (adjustable gain 0-20dB, cutoff frequency ≥25GHz, 50Ω impedance matching) and JESD204C high-speed transmission (10Gbps per channel, 8 parallel channels per channel, bit error rate ≤10%). -12 With hardware co-optimization (partitioned layout, independent power supply, thermal design), the signal-to-noise ratio is ≥60dB, the operating temperature is 0-70℃, and it can be directly integrated into 100G coherent acquisition cards and testers; by increasing the number of sub-ADCs or increasing the sub-ADC rate, it can be expanded to more than 160GSps, and is compatible with 200G / 400G coherent optical transmission systems. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0024] Figure 1 This invention provides a schematic diagram of a coherent acquisition platform with full-dimensional mismatch self-correction time-interleaved ADC system structure. Figure 2 The sampling timing diagram of the multi-channel time-interleaved ADC provided by this invention; Figure 3 This invention provides a flowchart of the full-dimensional mismatch self-correction process. The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Please see Figure 1 This embodiment provides a coherent acquisition platform with a full-dimensional mismatch self-correction time-interleaved ADC system, including: The analog front-end conditioning module is used to condition the multiple coherent analog signals input to the coherent receiver; The time-interleaved ADC sampling array includes multiple main channels, each of which includes multiple sub-ADCs. Each sub-ADC is spliced ​​together by time interleaving to achieve single-channel ultra-high-speed sampling, and the multiple main channels work synchronously to achieve synchronous acquisition of multiple coherent signals. The clock synchronization distribution module is used to provide a synchronization clock signal to each of the sub-ADCs in order to control the sampling timing of each sub-ADC; The full-dimensional mismatch self-correction module is used to detect and correct gain mismatch, delay mismatch, bias mismatch and bandwidth mismatch between each sub-ADC in real time; A high-speed data transmission module is used to transmit the corrected sampled data to the FPGA core processing unit; wherein, the FPGA core processing unit is used for subsequent digital demodulation.

[0027] It should be noted that the existing technology has the following technical drawbacks: 1. The number of channels interleaving is small (e.g., 2 channels), the interleaving gain is insufficient, and the hardware layout is asymmetrical and the clock distribution is uneven, resulting in a large mismatch between channels and severe distortion of the sampling signal; 2. It lacks a comprehensive mismatch correction mechanism, can only handle single-type mismatches, has poor adaptability to dynamic mismatches, and the correction effect decays over time and with changes in the environment. 3. Poor synchronization of the four channels, with large sampling timing deviations between polarization channels and between I / Q channels, which cannot meet the synchronous acquisition requirements of 100GPM-QPSK signals; 4. Impedance matching and signal conditioning design of the analog front-end and ADC interface are not perfect, resulting in severe crosstalk and reflection during high-speed signal transmission, low effective number of bits (ENOB), and poor signal integrity. 5. The architecture has low integration, with sampling, correction, and data transmission modules operating independently and lacking collaborative optimization. This results in high hardware resource consumption, large processing latency, and an inability to meet the real-time requirements of a 100G coherent acquisition platform.

[0028] Therefore, the time-interleaved ADC architecture of this invention is specifically designed for coherent acquisition platforms. Its core objective is to achieve multi-channel ultra-high-speed synchronous sampling, full-dimensional mismatch self-correction, and low-distortion signal acquisition. The overall architecture consists of five parts: an analog front-end conditioning module, a time-interleaved ADC sampling array, a clock synchronization distribution module, a full-dimensional mismatch self-correction module, and a high-speed data transmission module. These modules work together in a deep collaboration to form an integrated acquisition architecture.

[0029] This embodiment presents a hardware solution specifically designed for high-speed coherent optical acquisition systems. The architecture consists of five core modules working collaboratively: First, the analog front-end conditioning module amplifies, filters, and impedance-matches the multiple weak analog signals output from the coherent receiver, ensuring signal quality before entering the sampling stage. Then, the time-interleaved ADC sampling array adopts a "multiple main channels, multiple sub-ADCs per channel" structure, using multiple low-speed sub-ADCs to alternately sample and stitch together an ultra-high-speed sampling rate, achieving synchronous acquisition of multiple signals. During this process, the clock synchronization distribution module provides a low-jitter, equal-length path global clock for all sub-ADCs, precisely controlling the sampling time of each sub-ADC and reducing timing deviations between channels from the source.

[0030] Building upon this foundation, the architecture further introduces a full-dimensional mismatch self-correction module. This module can detect and dynamically correct gain mismatch, delay mismatch, bias mismatch, and bandwidth mismatch between the sub-ADCs in real time. Regardless of whether these mismatches are inherent at the factory or caused by dynamic drift due to environmental changes such as temperature and voltage, they can be automatically compensated, thereby ensuring the consistency of sampling data from each channel. Finally, the high-speed data transmission module transmits the corrected massive digital signals to subsequent digital processing units such as the FPGA with low latency and high reliability.

[0031] Overall, this embodiment systematically solves the technical problems of large channel mismatch, poor synchronization, and weak dynamic adaptability in the existing time-interleaved ADC architecture through the organic combination of the above five modules.

[0032] In a specific embodiment, the architecture block diagram is as follows: Figure 1As shown, this embodiment fully presents the five core modules of the architecture, clearly defining the signal flow and the collaborative relationships between modules. The input is the dual-polarization I / Q four-channel analog signal output from the coherent receiver, and the output is sent to the FPGA core processing unit, demonstrating the closed-loop design logic of clock synchronization and mismatch correction. The functions of each module are as follows: 1. Analog front-end conditioning module: Receives multiple analog electrical signals output from the coherent receiver, performs signal amplification, noise filtering, and impedance matching, and provides high-quality analog signals for ADC sampling; 2. Time-interleaved ADC sampling array: Each analog signal corresponds to a set of multi-sub-ADC time-interleaving units. Ultra-high-speed sampling is achieved by interleaving and splicing multiple low-speed sub-ADCs. Multiple sets of units work synchronously to ensure the synchronization of the acquisition of multiple signals. 3. Clock synchronization distribution module: Provides a low-jitter global synchronization clock, which is distributed to each sub-ADC through an equal-length clock tree to precisely control the sampling timing and minimize the clock deviation between channels; 4. Full-dimensional mismatch self-correction module: Real-time detection and correction of gain, delay, bias, and bandwidth mismatch between sub-ADCs, dynamically adapting to environmental changes and ensuring the consistency of sampling signals; 5. High-speed data transmission module: Transmits the corrected digital signal to the FPGA core processing unit through a high-speed parallel interface to achieve low-latency, high-bandwidth data interaction.

[0033] Furthermore, in the time-interleaved ADC sampling array, there are four main channels, corresponding to the four signals X_I, X_Q, Y_I, and Y_Q of the PM-QPSK coherent signal, respectively; each main channel includes four sub-ADCs, and each sub-ADC is spliced ​​together through time interleaving to achieve a single-channel sampling rate of 80GSps; wherein, the sub-ADC is a high-speed ADC chip of 20GSps@12bit, and the effective number of bits of a single sub-ADC is ≥10 bits.

[0034] Specifically, this embodiment further defines the specific channel configuration and sampling rate of the time-interleaved ADC sampling array to meet the acquisition requirements of 100G PM-QPSK coherent optical signals.

[0035] Specifically, the architecture features four main channels, corresponding to the four dual-polarization orthogonal signals X_I, X_Q, Y_I, and Y_Q output by the coherent receiver. Each main channel contains four sub-ADCs, and through time-interleaving splicing technology, the single-channel sampling rate reaches 80GSps. The "4×4" array structure not only solves the bottleneck of insufficient rate of a single ADC, but also ensures the synchronization between the polarization state and the IQ channels, providing a complete four-channel parallel sampling data stream for subsequent digital demodulation.

[0036] Furthermore, the sub-ADCs employ high-speed ADC chips with a sampling rate of 20GSps@12bit, meaning each chip has a sampling rate of 20GSps, a quantization bit width of 12 bits, and an effective bit width (ENOB) of at least 10 bits. This embodiment clearly defines the basic unit performance constituting the 80GSps interleaved sampling: four 20GSps sub-ADCs are precisely stitched together to achieve a total rate of 80GSps through time-interleaved sampling, while the 12-bit quantization depth and ≥10-bit ENOB ensure that the sampled signal has a sufficiently high signal-to-noise ratio and spurious-free dynamic range, thereby meeting the stringent signal fidelity requirements of high-order modulation formats (such as PM-QPSK).

[0037] In a more specific embodiment, the time-interleaved ADC sampling array adopts an interleaved architecture of "4 main channels × 4 sub-ADCs per channel", with a total sampling rate of 80 GSps / channel. The specific design is as follows: Sub-ADC selection: Use a 20GSps@12bit high-speed ADC chip with low noise and high linearity characteristics. The effective number of bits (ENOB) of a single sub-ADC is ≥10 bits. Interleaving timing control: The four sub-ADCs of each main channel sample alternately in time sequence, with the sampling phase shifted sequentially by T / 4 (T is the sub-ADC sampling period, 50ps). An 80GSps sampling rate is achieved through timing splicing. The sampling timing relationship is as follows: Sub-ADC1: Sampling times t=0, 4T, 8T,... Sub-ADC2: Sampling times t=T, 5T, 9T,... Sub-ADC3: Sampling times t=2T, 6T, 10T,... Sub-ADC4: Sampling times t=3T, 7T, 11T,... like Figure 2 As shown, the sampling phase offset rules are clearly defined, and the sampling period and phase offset are marked, intuitively demonstrating the core principle of achieving 80GSps sampling through time interleaving and splicing.

[0038] Four-channel synchronous design: Four groups of "4-sub-ADC interleaving units" share the same global synchronization clock, with a sampling start time deviation of ≤20fs, ensuring the synchronous acquisition of the four signals X_I, X_Q, Y_I, and Y_Q.

[0039] Furthermore, considering the weakness and high bandwidth characteristics of coherent signals, the analog front-end conditioning module adopts a multi-channel symmetrical conditioning architecture. Each conditioning unit consists of a programmable gain amplifier (PGA), a low-pass filter (LPF), and an impedance matching network, as specifically designed below: Programmable gain amplifier (PGA): The gain is adjustable from 0 to 20 dB, adapting to input signals of different amplitudes and ensuring the dynamic range of ADC sampling; Low-pass filter (LPF): Cutoff frequency 25GHz, filters out high-frequency noise and spurious signals, avoids sampling aliasing, and ensures signal integrity; Impedance matching network: Employs a microstrip line design to achieve 50Ω impedance matching, reducing signal reflection and crosstalk, and improving the quality of high-speed signal transmission; The multi-channel conditioning circuit has a completely symmetrical layout, and the component parameter consistency error is ≤1%, which reduces the inherent channel mismatch from the hardware level.

[0040] Furthermore, the clock is the core of the time-interleaved ADC architecture, directly affecting sampling timing accuracy and inter-channel synchronization. This module is designed as follows: Clock source: Employs a 10GHz ultra-low phase noise crystal oscillator with phase noise ≤-150dBc / Hz@1kHz, providing a highly stable clock reference for the system; Clock division and phase adjustment: The 10GHz clock is divided into 20GHz sub-ADC sampling clocks through phase-locked loop (PLL) and delay phase-locked loop (DLL), and fine phase adjustment is performed on each clock to ensure that the sampling phase of the four sub-ADCs is accurately offset by T / 4. Equal-length clock tree distribution: A symmetrical equal-length PCB routing design is adopted, with the transmission path length difference of the clock signal from the source to each sub-ADC ≤500μm and the clock delay deviation ≤10fs, minimizing the clock mismatch between channels; Clock jitter suppression: Integrated clock cleanup circuitry suppresses the effects of power supply noise and electromagnetic interference on the clock signal, resulting in a final sub-ADC sampling clock jitter of ≤30fs.

[0041] Furthermore, the full-dimensional mismatch self-correction module is the core innovation of this architecture. It realizes real-time self-correction of gain mismatch, delay mismatch, bias mismatch, and bandwidth mismatch among sub-ADCs, solving the problem that existing technologies cannot simultaneously ensure initial calibration accuracy and dynamic tracking capability. The specific design is as follows: Mismatch detection unit: Detects mismatch parameters through a dual-mode approach of "calibration sequence injection + blind estimation," balancing the accuracy of initial calibration with the real-time performance of the process. Calibration sequence injection: During the initial stage of system power-on, a high-precision calibration signal with known amplitude and phase is periodically injected into the analog front end. By comparing the sampling results of each sub-ADC, the initial mismatch parameters are quickly calculated with a convergence time of ≤1ms, ensuring the mismatch correction accuracy in the initial state. Blind estimation: During normal system operation, dynamic mismatch parameters are estimated in real time based on the constant mode and dual polarization orthogonal characteristics of PM-QPSK signals, without requiring additional transmission bandwidth or interrupting normal acquisition. Mismatch correction unit: Based on the detected mismatch parameters, it performs targeted correction on the sampled data of each sub-ADC. Bias mismatch correction: The bias bias is eliminated by subtracting the DC mean of the sub-ADC sampling data; Gain mismatch correction: By multiplying by a gain correction factor, the signal amplitudes of each sub-ADC are made consistent. The correction factor is calculated from the amplitude ratio of each sub-ADC. Delay mismatch correction: A fractional delay filter (FDF) is used to adjust the timing of the sampled data to achieve accurate compensation for non-integer multiple delays, with a compensation accuracy of up to 1 fs; Bandwidth mismatch correction: The frequency domain equalization filter compensates for the inconsistency in amplitude-frequency characteristics caused by the bandwidth difference of each sub-ADC, ensuring signal consistency at different frequencies; Dynamic adaptive mechanism: The mismatch parameters are updated every 100μs to track the dynamic mismatch of the ADC device caused by temperature and voltage changes in real time. Within the operating temperature range of 0-70℃, the tracking error of the mismatch parameters is ≤0.1%, ensuring the long-term stability of the correction effect.

[0042] Furthermore, to achieve low-latency transmission of 80GSps sampled data, the high-speed data transmission module adopts the JESD204C high-speed serial interface, with the specific design as follows: Data format: The sampling data of the four sub-ADCs of each main channel are concatenated in time sequence to form an 80GSps serial data stream, which is transmitted using a 12-bit width. Interface rate: The single-channel JESD204C interface rate is 10Gbps, and each main channel uses 8 parallel JESD204C interfaces, with a total transmission bandwidth of 80Gbps / channel, which meets the data transmission requirements of 4 main channels. Data caching and synchronization: An integrated FIFO cache unit with a cache depth of 1024×12 bits enables asynchronous cross-clock domain transmission of sampled data while ensuring synchronous output of four channels of data; Error detection: Integrated CRC check unit for real-time detection of data transmission errors, with an error rate ≤10%. -12 This ensures the reliability of data transmission.

[0043] In a more specific embodiment, the following collaborative optimizations are performed to further improve the architecture's sampling performance and engineering adaptability: Hardware layout optimization: The design adopts a "symmetrical layout + shielding and isolation" approach, with the analog front-end, ADC array, clock module, and digital module arranged in separate zones to reduce electromagnetic interference; high-speed signal lines adopt microstrip or stripline designs to control impedance matching and transmission delay. Power supply optimization: Multiple high-precision linear regulators (LDOs) are used for power supply, and the analog and digital sections are powered independently to reduce power supply noise coupling; the power distribution network (PDN) adopts a low impedance design to ensure power supply stability. Thermal design optimization: The ADC array and clock module are integrated with heat sinks, and the PCB uses high thermal conductivity materials (such as high thermal conductivity resin-based copper clad laminate, ceramic-based copper clad laminate, or metal-based copper clad laminate) to ensure that the device operating temperature is stable at 0-70℃ and avoid performance degradation caused by temperature changes.

[0044] Furthermore, a mismatch self-correction method is implemented through the following steps: Step S1: After the system is powered on, it enters the initial calibration phase, injecting a calibration signal with known amplitude and phase into the analog front end through the calibration sequence injection mode; Step S2: Calculate the initial gain mismatch parameters, delay mismatch parameters, bias mismatch parameters, and bandwidth mismatch parameters based on the sampling results of each sub-ADC; Step S3: Load the initial correction coefficients and perform full-dimensional initial correction on the output of the time-interleaved ADC sampling array. Then the system enters normal operation and begins to acquire coherent signals. Step S4: During normal operation, switch to blind estimation mode and estimate dynamic mismatch parameters in real time based on the constant mode or orthogonal characteristics of the received signal. Step S5: At each preset update cycle, dynamically update the correction coefficients based on the real-time estimated dynamic mismatch parameters, and adjust the correction strategy; Step S6: Repeat steps S4 to S5 until the system is shut down, thereby achieving real-time self-correction of mismatch across all dimensions.

[0045] Specifically, such as Figure 3 As shown, the core of this embodiment lies in achieving full-cycle mismatch compensation from startup to stable operation through a two-stage strategy of "initial calibration + dynamic tracking".

[0046] This method first injects a high-precision calibration signal with known characteristics into the analog front-end during the initial power-on phase (steps S1-S2), rapidly acquiring the responses of each sub-ADC and calculating the initial gain, delay, bias, and bandwidth mismatch parameters. Then, these parameters are immediately corrected across all dimensions, enabling the system to enter a low-mismatch, high-precision operating state from the outset. This process solves the problems of slow initial convergence and reliance on historical data in conventional calibration methods.

[0047] After entering the normal operation phase (steps S3-S4), the method switches to blind estimation mode, no longer relying on dedicated calibration signals, but directly using the statistical characteristics such as constant mode and orthogonality of the received coherent signals (such as PM-QPSK signals) to estimate the changes in mismatch parameters caused by factors such as temperature, voltage or device aging in real time and dynamically.

[0048] The system periodically updates these dynamic mismatch parameters at fixed short intervals (e.g., every 100 microseconds) and adjusts the correction coefficients accordingly, thus forming a closed-loop adaptive correction mechanism. The entire method combines the accuracy of initial calibration with the dynamic tracking capability of long-term operation, continuously suppressing the impact of the four types of mismatches on the quality of the sampled signal without interrupting normal data acquisition.

[0049] In summary, this invention designs a time-interleaving architecture with multiple main channels and multiple sub-ADCs per channel, which can be expanded to adapt to coherent acquisition requirements at different rates. For the 100GPM-QPSK scenario, a "4 main channels × 4 sub-ADCs per channel" architecture is adopted. By interleaving and splicing four 20GSps sub-ADCs, 80GSps sampling per channel is achieved, and four channels are acquired synchronously, which can adapt to the acquisition requirements of dual-polarization I / Q four-channel signals. In actual testing and use, this invention has the following technical advantages: Excellent sampling performance: It achieves simultaneous sampling of 80GSps across four channels, with a sub-ADC resolution of 12 bits, an effective number of bits (ENOB) ≥ 10.5 bits, and a sampling signal distortion of < 0.3%, which is far superior to the 8.2-bit ENOB and 2% distortion of the existing 2-channel interleaved architecture, providing a high-quality digital signal for subsequent demodulation; Comprehensive and accurate mismatch correction: The all-dimensional mismatch self-correction module can simultaneously handle four types of mismatch: gain, delay, bias, and bandwidth. Dual-mode detection takes into account both initial accuracy and dynamic tracking. After correction, the inter-channel gain mismatch is ≤0.5%, delay mismatch is ≤20fs, and bias mismatch is ≤0.1mV. The mismatch suppression effect is more than 5 times better than existing technologies. High synchronization of four channels: Through symmetrical architecture design, precise clock distribution and synchronous acquisition control, the sampling start time deviation of the four channels is ≤20fs, and the synchronization between polarization and between I / Q channels is improved by 5 times compared with the existing technology, which fully meets the synchronous acquisition requirements of 100GPM-QPSK signals. Strong signal integrity: The impedance matching and noise filtering design of the analog front end, combined with hardware layout and electromagnetic compatibility optimization, effectively suppresses crosstalk, reflection and electromagnetic interference. The signal-to-noise ratio of high-speed signal transmission is ≥60dB, and the signal integrity is better than existing technologies. Good engineering adaptability: The architecture has a high degree of integration, reasonable hardware resource consumption, low power consumption, and a wide operating temperature range. It can be directly integrated into engineering equipment such as 100G coherent acquisition cards and coherent optical testers without major modifications, which facilitates mass production and promotion. High scalability: By increasing the number of sub-ADCs or increasing the sub-ADC rate, it can be easily expanded to a 200G / 400G coherent acquisition platform. For example, by interleaving eight 20GSps sub-ADCs, 160GSps sampling can be achieved, which can be adapted to higher-speed coherent optical transmission systems.

[0050] The technical specifications of this invention are shown in Table 1: Table 1 Technical Indicator Comparison Table In summary, this invention employs an interleaved architecture with multiple main channels and multiple sub-ADCs per channel, enabling ultra-high-speed synchronous acquisition of multiple coherent signals. The core, all-dimensional mismatch self-correction module pioneers a dual-mode detection mechanism of "calibration sequence injection + blind estimation," simultaneously achieving real-time and accurate correction of four types of mismatches: gain, delay, bias, and bandwidth, while maintaining both initial calibration accuracy and adaptability to dynamic environments. This invention features high sampling rate, excellent synchronization, superior mismatch suppression, and strong signal integrity, making it directly applicable to coherent acquisition equipment at speeds of 100G and above, providing high-quality signals for subsequent digital demodulation and meeting the engineering requirements of coherent optical transmission systems.

[0051] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A coherent acquisition platform with full-dimensional mismatch self-correction time-interleaved ADC system, characterized in that, include: The analog front-end conditioning module is used to condition the multiple coherent analog signals input to the coherent receiver; The time-interleaved ADC sampling array includes multiple main channels, each of which includes multiple sub-ADCs. Each sub-ADC is spliced ​​together by time interleaving to achieve single-channel ultra-high-speed sampling, and the multiple main channels work synchronously to achieve synchronous acquisition of multiple coherent signals. The clock synchronization distribution module is used to provide a synchronization clock signal to each of the sub-ADCs in order to control the sampling timing of each sub-ADC; The full-dimensional mismatch self-correction module is used to detect and correct gain mismatch, delay mismatch, bias mismatch and bandwidth mismatch between each sub-ADC in real time; A high-speed data transmission module is used to transmit the corrected sampled data to the FPGA core processing unit; wherein, the FPGA core processing unit is used for subsequent digital demodulation.

2. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 1, characterized in that, In the time-interleaved ADC sampling array, there are four main channels, corresponding to the four signals X_I, X_Q, Y_I, and Y_Q of the PM-QPSK coherent signal, respectively. Each main channel includes four sub-ADCs, and each sub-ADC is spliced ​​together through time interleaving to achieve a sampling rate of 80GSps per channel. The sub-ADCs are high-speed ADC chips with a capacity of 20GSps@12bit, and the effective number of bits of a single sub-ADC is ≥10bit.

3. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 1, characterized in that, The analog front-end conditioning module has a multi-channel symmetrical structure. Each conditioning unit includes a programmable gain amplifier, a low-pass filter, and an impedance matching network connected in series. The gain of the programmable gain amplifier is adjustable from 0 to 20 dB. The cutoff frequency of the low-pass filter is ≥25 GHz. The impedance matching network is used to achieve 50 Ω impedance matching. The component parameter consistency error of the multi-channel conditioning circuit is ≤1%.

4. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 1, characterized in that, The clock synchronization distribution module includes a 10GHz ultra-low phase noise crystal oscillator as the clock source, and clock frequency division and phase adjustment are achieved through phase-locked loop and delay phase-locked loop; the clock tree of the clock synchronization distribution module adopts symmetrical equal-length wiring, the clock delay deviation between channels is ≤10fs, and the sampling clock jitter output to the sub-ADC is ≤30fs.

5. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 1, characterized in that, The full-dimensional mismatch self-correction module obtains mismatch parameters through a dual-mode detection mechanism, the dual modes including: The calibration sequence injection mode is used to calculate the initial mismatch parameters by injecting a known calibration signal into the analog front end during the initial stage of system power-on. Blind estimation mode is used to estimate dynamic mismatch parameters in real time based on the constant mode and orthogonality of the input coherent signal during normal system operation.

6. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 5, characterized in that, The full-dimensional mismatch self-correction module corrects different mismatch types in the following ways: To address bias mismatch, correction is performed by subtracting the DC mean of the sub-ADC sampling data; Gain mismatch is corrected by multiplying by a gain correction factor; To address the time delay mismatch, a fractional delay filter is used to adjust and correct the timing of the sampled data. To address bandwidth mismatch, a frequency domain equalization filter is used to correct the amplitude-frequency characteristics of the sampled data.

7. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 5, characterized in that, The full-dimensional mismatch self-correction module updates the mismatch parameters every 100μs to dynamically track mismatches caused by environmental changes.

8. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 1, characterized in that, The high-speed data transmission module adopts a JESD204C high-speed serial interface, and the single interface rate is 10 Gbps; the main channel of each channel adopts an 8-way parallel JESD204C interface; the high-speed data transmission module is further integrated with a FIFO buffer unit and a CRC check unit, and the data transmission error rate is ≤10 -12 .

9. The coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to claim 1, characterized in that, It also includes a collaborative optimization design, which includes: a symmetrical partitioned hardware layout for the analog front-end conditioning module, the time-interleaved ADC sampling array, the clock synchronization distribution module, the full-dimensional mismatch self-correction module, and the high-speed data transmission module; providing independent power supplies for analog and digital circuits; and a thermal design using high thermal conductivity materials and heat sinks. The system operates in a temperature range of 0-70℃, and the sampling start time deviation of the four main channels is ≤20fs.

10. A coherent acquisition platform full-dimensional mismatch self-correction time-interleaved ADC system according to any one of claims 1 to 9, characterized in that, The mismatch self-correction method is implemented through the following steps: Step S1: After the system is powered on, it enters the initial calibration phase, injecting a calibration signal with known amplitude and phase into the analog front end through the calibration sequence injection mode; Step S2: Calculate the initial gain mismatch parameters, delay mismatch parameters, bias mismatch parameters, and bandwidth mismatch parameters based on the sampling results of each sub-ADC; Step S3: Load the initial correction coefficients and perform full-dimensional initial correction on the output of the time-interleaved ADC sampling array. Then the system enters normal operation and begins to acquire coherent signals. Step S4: During normal operation, switch to blind estimation mode and estimate dynamic mismatch parameters in real time based on the constant mode or orthogonal characteristics of the received signal. Step S5: At each preset update cycle, dynamically update the correction coefficients based on the real-time estimated dynamic mismatch parameters, and adjust the correction strategy; Step S6: Repeat steps S4 to S5 until the system is shut down, thereby achieving real-time self-correction of mismatch across all dimensions.

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