Semiconductor structure and trimming method thereof

Abstract

This application provides a semiconductor structure and a method for modifying the same. The first semiconductor structure includes a substrate layer, a first film layer, and a second film layer stacked sequentially. A line structure in the second film layer has a first roughness. The first semiconductor structure is etched using a first etching process with an ion beam to obtain the second semiconductor structure. In the first etching process, the incident direction of the ion beam has a first angle with the sidewall of the line structure. The second semiconductor structure is then etched using a second etching process with an ion beam to obtain a third semiconductor structure. In the second etching process, the incident direction of the ion beam has a larger second angle with the sidewall of the line structure. In the third semiconductor structure, the line structure has a smaller third roughness. Through two plasma etching processes, fine adjustment of the linewidth roughness or line edge roughness can be achieved, and lattice damage to the sidewalls can be reduced, resulting in good repair of the sidewalls of the line structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a semiconductor structure and a method for modifying the same. Background Technology

[0002] With the continuous development of semiconductor devices, the critical dimension (CD) is gradually decreasing. The critical dimension can be understood as the minimum linewidth of a line on a semiconductor substrate. The phenomenon of a line varying along its length is called line width roughness (LWR). The phenomenon of a single edge meandering along its length is called line edge roughness (LER). After the gate length of transistors in CMOS circuits reaches the nanometer scale, LER / LWR is a significant component of the channel length variation that causes the short-channel effect, thus having a non-negligible impact on the threshold voltage Vth, leakage current Ioff, and transconductance K' of MOS transistors. LER / LWR is one of the key indicators affecting the electrical performance of semiconductor devices. When CD enters the range below 100nm, many problems caused by LER / LWR become apparent. Simultaneously, the linewidth and spacing between lines become increasingly smaller, shrinking the process window and significantly increasing the difficulty of process control during fabrication, becoming one of the bottlenecks severely restricting the continued development of integrated circuits. Therefore, how to improve LWR or LER has become an urgent technical problem to be solved. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a semiconductor structure and a method for trimming the same, enabling fine adjustment of linewidth roughness or line edge roughness, reducing lattice damage to sidewalls, and achieving good repair of the sidewalls of the line structure. The specific solution is as follows:

[0004] On the one hand, this application provides a method for modifying a semiconductor structure, including:

[0005] A first semiconductor structure is provided; the first semiconductor structure includes a substrate layer (100), a first film layer (101) and a second film layer (102) stacked sequentially; the second film layer (102) is a patterned film layer, the second film layer (102) includes a plurality of line structures (1021), the line structures (1021) have a first roughness, the first roughness being linewidth roughness and / or line edge roughness;

[0006] The first semiconductor structure is subjected to ion beam etching using a first etching process to obtain a second semiconductor structure; in the first etching process, the incident direction of the ion beam has a first angle with the sidewall of the line structure (1021); the first angle is less than a preset angle; in the second semiconductor structure, the line structure (1021) has a second roughness, the second roughness is less than the first roughness;

[0007] The second semiconductor structure is subjected to ion beam etching using a second etching process to obtain a third semiconductor structure; in the second etching process, the incident direction of the ion beam has a second angle with the sidewall of the line structure (1021); the second angle is greater than the first angle; in the third semiconductor structure, the line structure (1021) has a third roughness, which is less than the second roughness.

[0008] Optionally, the second semiconductor structure is subjected to ion beam etching using a second etching process to obtain a third semiconductor structure, comprising:

[0009] With the film normal of the second semiconductor structure as the axis, rotate the second semiconductor structure so that the angle between the incident direction of the ion beam and the sidewall of the line structure (1021) reaches the second angle.

[0010] The second semiconductor structure is subjected to ion beam etching using the second etching process to obtain the third semiconductor structure.

[0011] Optionally, in the first etching process, the incident angle of the ion beam is greater than or equal to 75°, where the incident angle is the angle between the incident direction of the ion beam and the normal of the film layer of the first semiconductor structure.

[0012] Optionally, the incident angle of the ion beam in the first etching process is equal to the incident angle of the ion beam in the second etching process.

[0013] Optionally, in the first etching process, the voltage of the first gate is greater than or equal to 800V.

[0014] Optionally, in the first etching process, the current of the first gate is greater than or equal to 0.1A and less than or equal to 1A.

[0015] Optionally, in the first semiconductor structure, a trench is formed between adjacent line structures (1021), the aspect ratio of the trench being less than or equal to 1:5.

[0016] Optionally, in the second etching process, the voltage of the first gate is greater than or equal to 50V and less than or equal to 400V.

[0017] Optionally, in the second etching process, the current of the first gate is greater than or equal to 0.07A and less than or equal to 0.5A.

[0018] Optionally, in the first etching process or the second etching process, the voltage of the second gate is greater than or equal to 200V and less than or equal to 1500V.

[0019] Optionally, the first semiconductor structure is a logic device or a memory device.

[0020] Optionally, the first roughness is the sidewall roughness of the first semiconductor structure in the front-end process or the back-end process.

[0021] Optionally, during the ion beam etching process, the etching gas includes at least one of an inert gas, a fluorine-based gas, and a chlorine-based gas.

[0022] Optionally, the inert gas includes at least one of He, Ne, Ar, Kr, and Xe.

[0023] Optionally, the fluorine-based gas includes C x F y The chlorine-based gas includes at least one of NF3, SF6, WF6, CHF3, and CH2F2, and the chlorine-based gas includes at least one of Cl2, BCl3, CCl4, and SiCl4.

[0024] Optionally, during ion beam etching, the chamber pressure is greater than or equal to 0.05 mT and less than or equal to 5 mT.

[0025] Optionally, during ion beam etching, the total gas flow rate is greater than or equal to 10 sccm and less than or equal to 100 sccm.

[0026] In another aspect, embodiments of this application also provide a semiconductor structure, including:

[0027] A third semiconductor structure; the third semiconductor structure includes a substrate layer (100), a first film layer (101) and a second film layer (102) stacked sequentially; the second film layer (102) is a patterned film layer, the second film layer (102) includes a plurality of line structures (1021), the line structures (1021) have a third roughness, the third roughness is line width roughness and / or line edge roughness, the third roughness is less than the first roughness, the first roughness is the roughness of the line structures (1021) before the third semiconductor structure is trimmed.

[0028] This application provides a semiconductor structure and a method for modifying the same. A first semiconductor structure is provided. The first semiconductor structure includes a substrate layer (100), a first film layer (101), and a second film layer (102) stacked sequentially. The second film layer (102) is a patterned film layer, comprising multiple line structures (1021). Each line structure (1021) has a first roughness, which is a linewidth roughness and / or a line edge roughness. The first semiconductor structure is subjected to ion beam etching using a first etching process to obtain a second semiconductor structure. In the first etching process, the incident direction of the ion beam has a first angle with the sidewall of the line structure (1021). The first angle is less than a preset angle, allowing the ion beam to etch the sidewall of the line structure (1021) almost parallel to achieve rough modification of the first roughness. In the second semiconductor structure, the line structure (1021) has a second roughness, which is less than the first roughness. Next, the second semiconductor structure is subjected to ion beam etching using a second etching process to obtain a third semiconductor structure. In the second etching process, the incident direction of the ion beam has a second angle with the sidewall of the line structure (1021). The second angle is greater than the first angle, so the ion beam can have a certain angle with the sidewall of the line structure (1021), and the ion beam can be incident on the sidewall surface more, which can refine the first roughness. In this way, in the third semiconductor structure, the line structure (1021) in the second film layer (102) has a third roughness, which is less than the second roughness. That is, through two plasma etching processes, the line width roughness or line edge roughness can be finely adjusted, and the lattice damage of the sidewall can be reduced, thus achieving good repair of the sidewall of the line structure (1021). Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic flowchart of a semiconductor structure trimming method provided in an embodiment of this application is shown;

[0031] Figure 2 A schematic diagram of an ion beam etching method provided in an embodiment of this application is shown;

[0032] Figure 3 This illustration shows a schematic diagram of the etching rate change during ion beam etching according to an embodiment of this application;

[0033] Figure 4 This illustration shows a schematic diagram of an ion beam etching process according to an embodiment of this application.

[0034] Figure 5-7 A schematic diagram of a semiconductor structure provided in an embodiment of this application is shown. Detailed Implementation

[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0036] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0037] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0038] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides an embodiment of a semiconductor structure and its modification method provided in this application.

[0039] refer to Figure 1 The diagram shown is a flowchart illustrating a method for modifying a semiconductor structure according to an embodiment of this application. The method may include the following steps.

[0040] S101 provides the first semiconductor structure.

[0041] The first semiconductor structure may include a substrate layer (100), a first film layer (101), and a second film layer (102) stacked sequentially. The substrate layer (100) may be, for example, a silicon wafer. The materials of the first film layer (101) and the second film layer (102) may be the same or different. The second film layer (102) is a patterned film layer, that is, the second film layer (102) has a pattern, such as a patterned photoresist layer. The patterned second film layer (102) can provide a mask for subsequent etching. The first film layer (101) covered by the second film layer (102) can be retained in the subsequent etching process, while the first film layer (101) not covered by the second film layer (102) will be etched away. This achieves the transfer of the pattern of the second film layer (102) into the first film layer (101).

[0042] The patterned second film layer (102) may specifically include multiple line structures (1021), that is, the pattern of the second film layer (102) may be composed of a large number of line structures (1021), with grooves between adjacent line structures (1021), the grooves being used to expose part of the surface of the first film layer (101).

[0043] In one possible implementation, a trench is formed between adjacent line structures (1021) in the first semiconductor structure. The aspect ratio of the trench can be less than or equal to 1:5, thereby achieving flatness modification of the trench sidewalls and meeting the trench process requirements. Of course, the aspect ratio can also be other values.

[0044] The line structure (1021) has a first roughness, which can be linewidth roughness and / or line edge roughness. That is, the first roughness can be linewidth roughness, line edge roughness, or both. Linewidth roughness describes the deviation of the linewidth of the line structure (1021) from the target value due to edge roughness, while line edge roughness describes the deviation between the edge of the line structure (1021) and a theoretically perfect smooth edge. In other words, in the first semiconductor structure, there exists a case where the sidewall roughness of the line structure (1021) is large, and the sidewalls exhibit significant undulations, requiring trimming.

[0045] In one possible implementation, the first roughness can be the sidewall roughness of the first semiconductor structure in either the front-end of line (FEOL) or back-end of line (BEOL) process. In the front-end process, it is mainly used to fabricate transistors, while in the back-end process, it is mainly used to realize metal interconnects. That is, regardless of whether a roughness exists on the sidewall of the line structure during transistor fabrication or metal interconnect layer fabrication, the method provided in this solution can be applied for smoothing, thus expanding the application scenarios of this solution.

[0046] Ion beam etching is an atomic-level high-precision surface processing technology. It utilizes a neutral ion beam with specific energy to bombard the wafer surface. By adjusting parameters such as the ion beam's energy, incident angle, and gas composition, the trajectory of the colliding particles can be controlled. Combined with interaction mechanisms such as sputtering, scattering, and chemical reactions, it achieves precise planar finishing at the atomic level. The most significant advantage of ion beam etching is its ability to provide directional etching with an angle, where the etching direction is related to the incident angle. This allows for high process flexibility and provides sophisticated pattern finishing solutions in specific applications.

[0047] In addition, the ion beam etching technology used in this application can be understood as an ion beam shaping (IBS) technology. IBS technology refers to modifying and shaping the structure by etching, thereby modifying the sidewall of the line structure (1021).

[0048] refer to Figure 2 The diagram shown is a schematic of an ion beam etching process provided in an embodiment of this application. Etching gas (Gas in) can be introduced into the chamber, and the etching gas is excited to form plasma. The plasma, i.e., neutral ions (Neutralizer), passes through a first grid, a second grid, and a deceleration grid to form a neutral beam. The neutral beam is incident on the sample surface at a certain angle θ to etch the sample. Here, the angle θ can be understood as the incident angle of the ion beam. The first grid can be a screen grid, and the second grid can be an acceleration grid.

[0049] Because the sample surface is not a smooth plane but has a certain degree of undulation, different locations on the sample have their own equivalent incident angles. The equivalent incident angle can be understood as the actual incident angle of the film surface at a specific location on the sample, given a certain incident angle of the ion beam; that is, the angle between the ion beam and the normal to the film at that location. Due to the undulation of the film surface, some locations are convex while others are concave. Therefore, at the same incident angle of the ion beam, the equivalent incident angles corresponding to convex and concave locations are different.

[0050] refer to Figure 3 As shown in (a), the same ion beam incident angle is applied to the film surface at different locations. Taking an inert gas as an example, the overall shape is nearly parabolic. The ion beams applied to the first and second locations are both vertically downward, with an incident angle of 0°. However, the equivalent incident angles at these two locations are different: S' at the first location and S at the second location. Furthermore, the incident angles of the ion beams at the third and fourth locations are the same, but the equivalent incident angle at the third location is L, and at the fourth location it is L'.

[0051] Furthermore, under the same ion beam incident angle, different locations on the film surface have corresponding equivalent incident angles. Different equivalent incident angles may result in different etching rates; that is, there is a certain correlation between the equivalent incident angle and the etching rate. (Reference) Figure 3Figure (b) illustrates the relationship between the equivalent incident angle and the etching rate. The etching rate corresponding to the equivalent incident angle S' at the first location point is greater than the etching rate corresponding to the equivalent incident angle S at the second location point, and the etching rate corresponding to the equivalent incident angle L' at the fourth location point is greater than the etching rate corresponding to the equivalent incident angle L at the third location point. In other words, the highest etching rate is distributed near the medium equivalent incident angle, and the etching rate is lowest at higher equivalent incident angles.

[0052] refer to Figure 4 As shown, (a) is a top view of ion beam etching, with a line structure (1021) 1021 on the wafer, and the ion beam can modify the line structure (1021). (b) is a front view of ion beam etching, with the ion beam incident on the surface of the structure at a certain angle, and the incident angle of the ion beam is not less than 75°.

[0053] The material of the second film layer (102) is not limited here. The second film layer (102) can be a single layer structure, such as photoresist, dielectric material, or metal material. It is not limited to single film layer structures such as photoresist (PR), spin on carbon (SOC), SOH, silicon nitride Si3N4, silicon oxynitride SiON, silicon oxide (SiO2), polysilicon, low temperature oxide (LTO), Ta, W, TiN, TaN, and Al. Among them, SOH refers to highly doped H element in SOC.

[0054] The second film layer (102) can also be a multilayer structure, such as a combination of photoresist, dielectric material and metal material, such as a combination of two or three materials, such as a double-layer structure such as Poly / SiO2, Si3N4 / SiO2, SOC / SiO2, SiO2 / Ta, SiO2 / W, Ta / W, etc., or a multilayer combination structure such as SiO2 / Si3N4 / W, SiO2 / W / TiN / HfO2.

[0055] S102, the first semiconductor structure is subjected to ion beam etching using the first etching process to obtain the second semiconductor structure.

[0056] Specifically, the first semiconductor structure can be ion-beam etched to obtain the second semiconductor structure, and the process parameters in this ion-beam etch process can be represented by the first etching process. In the first etching process, the incident direction of the ion beam has a first angle with the sidewall of the line structure (1021).

[0057] In other words, the ion beam etching process primarily etches the sidewalls of the line structure (1021) to improve their flatness. The angle between the incident direction of the ion beam and the sidewall surface of the line structure (1021) is denoted as the first angle. It is worth noting that although the sidewalls of the line structure (1021) are rough, with some protrusions and depressions, these minor variations can be disregarded when determining the first angle. The ideal flat sidewall surface of the line structure (1021) can be used as a reference, and the angle between the incident direction of the ion beam and this flat sidewall surface is denoted as the first angle. (Reference) Figure 4 (c) is a three-dimensional schematic diagram of ion beam etching. It can be seen that the ion beam is incident on the sidewall of the line structure (1021) and etches the sidewall.

[0058] The first angle can be smaller than a preset angle, which can be a pre-defined angle, such as 5° or 8°. If the first angle is smaller than the preset angle, it means that the first angle is relatively small, that is, the incident direction of the ion beam is closer to the sidewall of the line structure (1021), thereby flattening the protruding part on the sidewall, making the sidewall of the line structure (1021) smoother, reducing the roughness of the sidewall of the line structure (1021), and achieving rough finishing of the sidewall of the line structure (1021). In addition, the first angle can also be as close to 0° as possible, so that the incident direction of the ion beam is almost parallel to the sidewall of the line structure (1021), thereby improving the etching effect and further reducing the roughness of the sidewall.

[0059] In other words, the roughness of the line structure (1021) in the second semiconductor structure can be denoted as the second roughness. The second roughness is smaller than the first roughness, that is, the roughness is reduced and the sidewall of the line structure (1021) becomes flat.

[0060] refer to Figure 5 As shown, (a) is a cross-sectional view of the first semiconductor structure, (b) is a cross-sectional view of the second semiconductor structure, and (c) is a cross-sectional view of the third semiconductor structure. After the etching process of the first etching process, it can be found that the roughness of the sidewall of the line structure (1021) of the second semiconductor structure is significantly smaller and the edge of the sidewall is smoother compared with the first semiconductor structure.

[0061] In one possible implementation, in the first etching process, the incident angle of the ion beam can be greater than or equal to 75°, where the incident angle is the angle between the incident direction of the ion beam and the normal of the film layer of the first semiconductor structure.

[0062] In other words, during the first etching, the ion beam is etched in a grazing incidence manner, and the ion beam is closer to the surface of the film. For example, the incident angle of the ion beam can be 80° or 85°. With the help of this near parallel incident, the sidewall of the line structure (1021) can be modified by directly flattening the convex undulation area. The higher incident angle can effectively reduce the bombardment of the ion beam on the top of the second film layer (102) and the surface of the first film layer (101), reduce the damage to them, and achieve precise trimming of the sidewall of the line structure (1021).

[0063] In one possible implementation, the voltage BMV of the first gate in the first etching process can be greater than or equal to 800V. This avoids the situation where the voltage of the first gate is too low, resulting in a low initial kinetic energy of the ion beam and poor collimation. In this application, by selecting a higher voltage for the first gate, the ion beam has a higher initial kinetic energy, which in turn gives it better collimation. The higher energy is beneficial for efficiently smoothing the undulations on both sides of the line, enabling more precise trimming of the sidewalls of the line structure (1021) and further improving the smoothness of the sidewalls.

[0064] In one possible implementation, the current BMI of the first gate in the first etching process can be greater than or equal to 0.1A and less than or equal to 1A. BMI can affect the ion beam density. Selecting a relatively low BMI can achieve a lower ion density, reduce collisions between ion beams, enhance beam collimation, enable more precise trimming of the sidewalls of the line structure (1021), and increase the wafer per hour (WPH).

[0065] In this way, by using a high-energy, low-current ion beam for etching in the first etching process, it is possible to achieve roughing of the sidewall linewidth roughness and to achieve an initial improvement in LER / LWR.

[0066] S103, the second semiconductor structure is subjected to ion beam etching using the second etching process to obtain the third semiconductor structure.

[0067] To further reduce the roughness of the sidewalls of the line structure (1021), the second semiconductor structure can be further etched with an ion beam. The etched semiconductor structure is referred to as the third semiconductor structure. The process parameters in this ion beam etching process can be referred to as the second etching process. Compared with the first etching process, the second etching process mainly adjusts the angle between the incident direction of the ion beam and the sidewalls of the line structure (1021).

[0068] In the second etching process, the incident direction of the ion beam has a second angle with the sidewall of the line structure (1021), which is greater than the first angle. That is, compared with the first etching, the second etching increases the angle between the ion beam and the sidewall of the line structure (1021), making the incident direction of the ion beam more pointed towards the sidewall surface. As an example, the difference between the second angle and the first angle can be less than or equal to 10°, for example, less than or equal to 5°.

[0069] refer to Figure 4 (c) shows the angle change β, which is the difference between the first angle and the second angle. (d) is a top view of ion beam etching. The angle change β is less than or equal to 10°. During the first etching, the ion beam is almost parallel to the sidewall lines. During the second etching, the angle between the ion beam and the sidewall lines becomes larger.

[0070] It is worth noting that both the first angle and the second angle refer to the angle between the ion beam and the surface where the sidewall of the line structure (1021) is located, and do not involve the angle between the ion beam and the normal of the film layer. That is, the first angle or the second angle has no direct relationship with the angle between the ion beam and the normal of the film layer.

[0071] Specifically, in the third semiconductor structure, the roughness of the line structure (1021) can be denoted as the third roughness, which is less than the second roughness and also less than the first roughness. Compared to the first semiconductor structure, the roughness of the side surface of the line structure (1021) in the third semiconductor structure is significantly reduced, and the sidewalls are smoother. (Reference) Figure 5 As shown in (b) and (c), the roughness of the sidewalls of the line structure (1021) in the third semiconductor structure is significantly reduced and the sidewalls become smoother compared to the second semiconductor structure.

[0072] Furthermore, when comparing the first roughness, the second roughness, and the third roughness, the comparison is made under the same physical quantity. That is, these three roughnesses can all be line width roughness, or they can all be line edge roughness, or they can all be line width roughness and line edge roughness.

[0073] This increases the contact area between the ion beam and the sidewalls of the line structure (1021), allowing the ion beam to etch more locations on the sidewalls, achieving precise etching at each location, i.e., oblique incidence grazing of the sidewalls. The angle between the ion beam and the sidewalls of the line structure (1021) can couple the divergence angle of the ion beam, reducing the parallelism between the grazing incidence ion beam and the sidewalls of the line structure (1021), reducing sidewall damage. That is, it can repair the lattice damage to the sidewalls caused during the first etching, thereby further reducing the roughness of the sidewalls and achieving fine finishing of the sidewalls of the line structure (1021).

[0074] In summary, by performing two plasma etching processes, fine adjustment of linewidth roughness or line edge roughness can be achieved, and lattice damage to the sidewalls can be reduced, resulting in good repair of the sidewalls of the line structure (1021). Furthermore, it can reduce material loss on the top surface of the line structure (1021) and avoid over-etching of the first film layer (101), which is beneficial for improving device reliability, increasing device lifespan, facilitating subsequent process integration, enhancing device performance, and reducing costs. In conclusion, this application enables cross-wafer-level, in-situ global modification of the entire surface, not limited to a specific location of the trench in the semiconductor structure.

[0075] In one possible implementation, the first semiconductor structure can be a logic device or a memory device, wherein the memory device can be, for example, a 3D NAND memory, and the types of memory devices and logic devices will not be listed one by one.

[0076] Furthermore, measurements of the third semiconductor structure revealed that, compared to the first semiconductor structure, the CD loss of the third semiconductor structure is less than 2 nm, and the loss at the top of the line structure (1021) and the surface of the first film layer (101) is less than 1 nm, achieving an LER / LWR improvement of ≥20%.

[0077] In one possible implementation, the incident angle of the ion beam in the first etching process can be equal to the incident angle of the ion beam in the second etching process. That is, the incident angle of the ion beam can remain unchanged during the two etching processes, without the need to adjust the incident angle. Only the angle between the ion beam and the sidewall surface of the line structure (1021) needs to be adjusted, thereby reducing the number of process steps and improving etching efficiency.

[0078] In one possible implementation, S103 performs ion beam etching on the second semiconductor structure using a second etching process to obtain a third semiconductor structure, which may specifically include S1031-S1032.

[0079] S1031, with the film normal of the second semiconductor structure as the axis, rotate the second semiconductor structure so that the angle between the incident direction of the ion beam and the sidewall of the line structure (1021) reaches the second angle.

[0080] Specifically, the normal of the film layer of the second semiconductor structure can be used as the axis of rotation to rotate the second semiconductor structure, that is, to rotate the second semiconductor structure in its own plane, for example, clockwise or counterclockwise. Before and after the rotation, the plane on which the surface of the second semiconductor structure is located does not deflect.

[0081] By rotating the second semiconductor structure, the plane containing the sidewall of the line structure (1021) also rotates, thereby changing the angle between the sidewall and the ion beam from the original first angle to a larger second angle, so that the angle between the incident direction of the sub-beam and the sidewall of the line structure (1021) reaches the second angle.

[0082] In actual processes, the second semiconductor structure can be rotated clockwise (or counterclockwise) first to achieve a second angle between the ion beam incident direction and the sidewall. Then, the second semiconductor structure can be rotated counterclockwise (or clockwise) to achieve another second angle between the ion beam incident direction and the sidewall. In this way, both sidewalls of the same linear structure can be etched with ion beams at a large angle, thereby enabling fine finishing of both sidewalls and improving the flatness of the sidewalls.

[0083] S1032, the second semiconductor structure is subjected to ion beam etching using the second etching process to obtain the third semiconductor structure.

[0084] In this way, by rotating the second semiconductor structure to change the angle between the sidewall of the line structure (1021) and the incident direction of the ion beam, this adjustment method is easier to operate than adjusting the incident direction of the ion beam. It only requires controlling the stage on which the second semiconductor structure is placed to rotate, without the need for complex adjustments to the ion beam, which can greatly improve the adjustment rate and thus improve the etching rate.

[0085] In one possible implementation, during the second etching process, the voltage of the first gate can be greater than or equal to 50V and less than or equal to 400V. That is, a lower voltage for the first gate and a lower energy level can be used for the modification process to specifically remove residues. The lower energy level can reduce lattice damage to the sidewalls and further refine the linewidth sidewall roughness.

[0086] In one possible implementation, during the second etching process, the current of the first gate can be greater than or equal to 0.07A and less than or equal to 0.5A. Compared to the first etching process, the current of the first gate is generally smaller, resulting in a lower ion density, further reducing collisions between ion beams, enhancing beam collimation, and enabling fine finishing of various locations on the sidewalls.

[0087] In one possible implementation, during the first or second etching process, the voltage (ACV) of the second gate can be greater than or equal to 200V and less than or equal to 1500V. ACV can affect the beam divergence angle of the ion beam. By adjusting this parameter, different locations on the surface and edge regions of the semiconductor structure can have different ion beam irradiation capabilities. For wafer-level height differences, a suitable voltage can be selected within this voltage range to adaptively adjust the ion beam distribution and etching rate in the corresponding regions, balancing the differences in performance across regions and ultimately achieving global high-precision planarization.

[0088] The following explanation uses the first ion beam etching as an example. The first semiconductor structure may include a first region and a second region, where the distance between the first region and the center of the structure is less than the distance between the second region and the center of the structure. In other words, the first region is closer to the center of the first semiconductor structure, while the second region is farther away from the center. For example, the first region could be a central region, and the second region could be an edge region. It is understood that the first and second regions are defined relative to the center and are not limited to only these two regions; for example, the first semiconductor structure could be divided into three regions.

[0089] During ion beam etching, due to the relatively large surface area of ​​the first semiconductor structure, it is impossible to achieve completely equal etching rates at all locations. Different regions will have different etching rates, resulting in different heights of the line structures (1021) located in different regions. The height of the line structure (1021) located in the first region can be denoted as the first height, and the height of the line structure (1021) located in the second region can be denoted as the second height. The first height and the second height have some differences; that is, there is a height difference between the first height of the line structure (1021) located in the first region and the second height of the line structure (1021) located in the second region.

[0090] During the ion beam etching process, when the first height is greater than the second height, the voltage of the second grid is the first voltage; when the first height is less than or equal to the second height, the voltage of the second grid is the second voltage; the first voltage is greater than the second voltage.

[0091] Specifically, when the first height is greater than the second height, it indicates that the etching rate of the first region is lower and the etching rate of the second region is higher. This results in a higher height for the line structure (1021) in the first region and a lower height for the line structure (1021) in the second region. In other words, the etching of the central region is slower and the etching of the edge region is faster. At this time, a larger voltage for the second grid, i.e., the first voltage, can be selected. This can reduce the beam divergence angle of the ion beam, allowing more ion beams to be incident on the central region, increasing the etching rate of the central region. This makes the etching rates of the central region and the edge region consistent, and thus makes the trimming of the line structure (1021) in the central region and the edge region more consistent, i.e., achieving a global high-precision LER / LWR improvement.

[0092] When the first height is less than or equal to the second height, it indicates that the etching rate of the first region is higher than that of the second region. This results in a smaller height for the line structure (1021) in the first region and a larger height for the line structure (1021) in the second region. In other words, the etching rate is faster in the central region and slower in the edge region. At this time, a smaller voltage for the second grid can be selected, i.e., the second voltage. This can increase the beam divergence angle of the ion beam, allowing more ion beams to be incident on the edge region, thereby increasing the etching rate of the edge region. This makes the etching rates of the central region and the edge region consistent, resulting in more consistent trimming of the line structure (1021) in the central region and the edge region, thus achieving a global high-precision LER / LWR improvement.

[0093] In one possible implementation, during the ion beam etching process, the etching gas includes at least one of inert gas, fluorine-based gas, and chlorine-based gas. That is, in the first or second etching process, the etching gas used can be one or a combination of inert gas, fluorine-based gas, and chlorine-based gas, depending on the material difference between the second film layer (102) and the first film layer (101), and a suitable gas combination can be selected to reduce the generation of residues (polymer) and sidewall damage.

[0094] Specifically, the inert gas may include one or more combinations of He, Ne, Ar, Kr, Xe, and Rn. Using an inert gas for etching enables ion beam etching, thereby reducing process costs and improving the trimming effect on the sidewalls of the line structure (1021). In addition, it can also prevent the generation of new residues that adhere to the sidewalls of the line structure (1021).

[0095] Fluorine-based gases may include C x F yWhere x and y are positive integers, and can also be one or more combinations of NF3, SF6, WF6, CHF3, and CH2F2. Chlorine-based gases can include one or more combinations of Cl2, BCl3, CCl4, and SiCl4.

[0096] Fluorine-based or chlorine-based gases can chemically react with the film material, which is called reactive ion beam etching (RIBS). RIBS can also be understood as reactive ion beam shaping (RIBS) technology. It not only retains the physical etching capability of ion beams but also increases the chemical reactivity of ionized fluorine-based or chlorine-based gases with the sample, which can significantly improve the etching rate, etching quality, and the trimming effect on the sidewalls of the (1021) line structure. In addition, the residues generated by RIBS can be removed during the second etching process.

[0097] Furthermore, during ion beam etching, the chamber pressure is greater than or equal to 0.05 mT and less than or equal to 5 mT. The total gas flow rate during ion beam etching is greater than or equal to 10 sccm and less than or equal to 100 sccm. That is, during the first or second etching process, the chamber pressure range can be 0.05 mT to 5 mT, and the total gas flow rate can be 10 sccm to 100 sccm. Lower chamber pressure is beneficial for increasing the molecular free path, improving ion collimation, achieving better directional removal and high-uniformity process control, and enabling precise smoothing of the sidewalls of the (1021) line structure.

[0098] Next, we will take the first semiconductor structure as an example where the layers from top to bottom are SiON / SOH / SiON / Carbon. The substrate layer (100) is Carbon, the first film layer (101) is SiON, and the second film layer (102) is a stack of SiON and SOH.

[0099] After etching the SOH in the first semiconductor structure, the resulting sidewall roughness is poor, leading to the LWR (Low Roughness) problem. Utilizing the directional collimation characteristics of ion beam etching, a suitable etching gas and ion beam incident direction are selected for the first etching process. The ion beam incident direction is parallel to the trench, thus achieving roughing of uneven sidewalls. A second etching process is then used, employing an oblique incidence sweep mode to achieve fine-tuning of the sidewalls. This reduces sidewall damage and polymer removal, and also minimizes damage to the top material and substrate, thereby improving the LWR.

[0100] In the first etching process, the ion beam incident angle is 80°, and the voltage (BMV) of the first grid is 1000V. The higher initial kinetic energy provides better beam collimation while also achieving high removal efficiency, making it favorable for production capacity. The current (BMI) of the first grid is 0.1A, the voltage (ACV) of the second grid is 400V, Ar is used as the etching gas, the etching chamber pressure is 0.05mT, and the total gas flow rate is 12sccm.

[0101] In the second etching process, a grazing incidence sweep mode is adopted, with an ion beam incident angle of 80° and a semiconductor structure deflection of ±5° to achieve the second angle. The voltage BMV of the first gate is selected as 75V, the current BMI of the first gate is selected as 0.07A, the voltage ACV of the second gate is selected as 400V, Ar is used as the etching gas, the etching chamber pressure is 0.05mT, and the total gas flow rate is 12sccm.

[0102] refer to Figure 6 As shown, (a), (b), and (c) represent the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure, respectively. It can be observed that the sidewalls of the line structure (1021) gradually become flat and smooth.

[0103] After etching, measurements showed that the angle between the sidewall of the line structure (1021) and the surface of the first film layer (101) changed by less than 2°, the material loss of the top material of the line structure (1021) and the material loss of the first film layer (101) was less than 1 nm, the change in CD was less than 1 nm, and the LWR was improved by about 25%.

[0104] Next, we will take the first semiconductor structure as an example where the layers from top to bottom are PR / anti-reflection layer / SiON / SOH. The substrate layer (100) is SOH, the first film layer (101) is SiON and anti-reflection layer, and the second film layer (102) is PR layer.

[0105] During the first etching process, the incident angle of the ion beam is 80°, the voltage BMV of the first grid is 1200V, the current BMI of the first grid is 0.96A, the voltage ACV of the second grid is 1000V, the etching gas is Ar, the etching chamber pressure is 0.05mT, and the total gas flow rate is 18sccm, thus achieving rough finishing of the sidewall of the line structure (1021).

[0106] During the second etching process, the incident angle of the ion beam is 80°, the voltage BMV of the first grid is 75V, the current BMI of the first grid is 0.1A, the voltage ACV of the second grid is 400V, the etching gas is Ar, the etching chamber pressure is 0.05mT, and the total gas flow rate is 12sccm, thereby achieving fine finishing of the sidewall of the line structure (1021).

[0107] refer to Figure 7 As shown, (a), (b), and (c) represent the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure, respectively. It can be observed that the sidewalls of the line structure (1021) gradually become flat and smooth.

[0108] After etching, measurements showed that the angle between the sidewall of the line structure (1021) and the surface of the first film layer (101) changed by less than 3°, the material loss of the top material of the line structure (1021) and the material loss of the first film layer (101) was less than 1 nm, the change in CD was less than 2 nm, and the LWR was increased by more than 20%.

[0109] This application provides a method for trimming a semiconductor structure. By performing two plasma etching processes, the line width roughness or line edge roughness can be finely adjusted, and the lattice damage of the sidewalls can be reduced, thus achieving good repair of the sidewalls of the line structure (1021).

[0110] This application also provides a semiconductor structure, see reference. Figure 5 As shown in (c), the semiconductor structure is specifically a third semiconductor structure, which includes a substrate layer (100), a first film layer (101), and a second film layer (102) stacked sequentially. The second film layer (102) is a patterned film layer, which includes multiple line structures (1021). The line structures (1021) have a second roughness, which is the line width roughness and / or the line edge roughness. The second roughness is less than the first roughness, which is the roughness of the line structures (1021) before the third semiconductor structure is trimmed.

[0111] This application provides a semiconductor structure that, obtained through two plasma etching processes, enables fine adjustment of linewidth roughness or line edge roughness, reduces lattice damage to sidewalls, and achieves good repair of the sidewalls of the line structure (1021).

[0112] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0113] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method of trimming a semiconductor structure, characterized by, include: A first semiconductor structure is provided; the first semiconductor structure includes a substrate layer (100), a first film layer (101) and a second film layer (102) stacked sequentially; the second film layer (102) is a patterned film layer, the second film layer (102) includes a plurality of line structures (1021), the line structures (1021) have a first roughness, the first roughness being linewidth roughness and / or line edge roughness; The first semiconductor structure is subjected to ion beam etching using a first etching process to obtain a second semiconductor structure; in the first etching process, the incident direction of the ion beam has a first angle with the sidewall of the line structure (1021); the first angle is less than a preset angle; in the second semiconductor structure, the line structure (1021) has a second roughness, the second roughness is less than the first roughness; The second semiconductor structure is subjected to ion beam etching using a second etching process to obtain a third semiconductor structure; in the second etching process, the incident direction of the ion beam has a second angle with the sidewall of the line structure (1021); the second angle is greater than the first angle; in the third semiconductor structure, the line structure (1021) has a third roughness, which is less than the second roughness.

2. The method of claim 1, wherein, The second semiconductor structure is subjected to ion beam etching using a second etching process to obtain a third semiconductor structure, comprising: With the normal of the film layer of the second semiconductor structure as the axis, rotate the second semiconductor structure so that the angle between the incident direction of the ion beam and the sidewall of the line structure (1021) reaches the second angle. The second semiconductor structure is subjected to ion beam etching using the second etching process to obtain the third semiconductor structure.

3. The method of claim 1, wherein, In the first etching process, the incident angle of the ion beam is greater than or equal to 75°, and the incident angle is the angle between the incident direction of the ion beam and the normal of the film layer of the first semiconductor structure.

4. The method of claim 3, wherein, The incident angle of the ion beam in the first etching process is equal to the incident angle of the ion beam in the second etching process.

5. The method of claim 1, wherein, In the first etching process, the voltage of the first gate is greater than or equal to 800V.

6. The method according to claim 1, characterized in that, In the first etching process, the current of the first gate is greater than or equal to 0.1A and less than or equal to 1A.

7. The method according to claim 1, characterized in that, In the first semiconductor structure, a trench is formed between adjacent line structures (1021), and the aspect ratio of the trench is less than or equal to 1:

5.

8. The method according to claim 1, characterized in that, In the second etching process, the voltage of the first gate is greater than or equal to 50V and less than or equal to 400V.

9. The method according to claim 1, characterized in that, In the second etching process, the current of the first gate is greater than or equal to 0.07A and less than or equal to 0.5A.

10. The method according to claim 1, characterized in that, In either the first etching process or the second etching process, the voltage of the second gate is greater than or equal to 200V and less than or equal to 1500V.

11. The method according to claim 1, characterized in that, The first semiconductor structure is a logic device or a memory device.

12. The method according to claim 1, characterized in that, The first roughness is the sidewall roughness of the first semiconductor structure in the front-end process or back-end process.

13. The method according to claim 1, characterized in that, During the ion beam etching process, the etching gas includes at least one of inert gas, fluorine-based gas, and chlorine-based gas.

14. The method according to claim 13, characterized in that, The inert gas includes at least one of He, Ne, Ar, Kr and Xe.

15. The method according to claim 13, characterized in that, The fluorine-based gas includes C x F y The chlorine-based gas includes at least one of NF3, SF6, WF6, CHF3, and CH2F2, and the chlorine-based gas includes at least one of Cl2, BCl3, CCl4, and SiCl4.

16. The method according to claim 1, characterized in that, During ion beam etching, the chamber pressure is greater than or equal to 0.05 mT and less than or equal to 5 mT.

17. The method according to claim 1, characterized in that, During ion beam etching, the total gas flow rate is greater than or equal to 10 sccm and less than or equal to 100 sccm.

18. A semiconductor structure, characterized in that, include: A third semiconductor structure; the third semiconductor structure includes a substrate layer (100), a first film layer (101) and a second film layer (102) stacked sequentially; the second film layer (102) is a patterned film layer, the second film layer (102) includes a plurality of line structures (1021), the line structures (1021) have a third roughness, the third roughness is line width roughness and / or line edge roughness, the third roughness is less than the first roughness, the first roughness is the roughness of the line structures (1021) before the third semiconductor structure is trimmed.

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