Power supply for a transmitter of a medium-high speed interface circuit

Abstract

This invention discloses a power supply for a transmitter in a medium-to-high-speed interface circuit, comprising an LDO and its on-chip voltage regulator C, as well as a data change detector and a charge replenisher. The data change detector detects whether the data to be transmitted by the transmitter in the medium-to-high-speed interface circuit undergoes a reversal. If so, a trigger pulse with a pulse width of T0 is generated at the moment of the reversal. The charge replenisher is activated under the trigger pulse and replenishes the charge of the on-chip voltage regulator C of the LDO. This invention activates the charge replenisher by detecting the moment of reversal of the data to be transmitted and generating a corresponding trigger pulse. Since the pulse width T0 is the activation time of the charge replenisher, the charge replenisher replenishes the charge drawn from the on-chip voltage regulator C by the transmitter drive circuit due to the data reversal. This allows the power supply of the transmitter in the medium-to-high-speed interface circuit to adopt a capacitor-free LDO structure, while avoiding severe ripple in the power supply caused by data transmission.

Description

Technical Field

[0001] This invention belongs to the field of power supply circuit technology, specifically relating to a power supply for a transmitter used in a medium-to-high-speed interface circuit. Background Technology

[0002] In the medium-to-high-speed interface PHY (physical layer interface), the transmitter is responsible for sending data signals to the receiver. Every change in the data in the transmitter will cause the state of the drive circuit to change. The power supply / ground will either charge or discharge the parasitic capacitance and the driven capacitor, causing power fluctuations.

[0003] LDO (low dropout regulator) is a general-purpose technology commonly used to power transmitters. In chip design, it can be divided into capacitive LDO and capless LDO depending on whether an external capacitor is required. Figure 1 and Figure 2 The following are implementation diagrams of two LDOs applicable to different application scenarios, provided for existing technologies. Figure 1 The existing technology shown is still Figure 2 The existing technology shown, employing a capacitor-based LDO structure (i.e., capacitor C in the diagram is an external capacitor), can meet the power supply requirements for the transmitter circuit of medium-to-high-speed interfaces; however, its disadvantage is the need for external capacitors, increasing BOM (Bill of Materials) costs. Furthermore, regardless of... Figure 1 The existing technology shown is still Figure 2 The existing technologies shown can also meet the power supply requirements of the transmitting circuit of the medium and high speed interface if a capacitorless LDO structure is adopted (i.e., capacitor C in the figure is an on-chip capacitor); however, they all have the following problems: (1) a large on-chip capacitor is required to barely supply power to the transmitting circuit of the high speed interface. Due to the large power supply jitter, the quality of the transmitting signal of the high speed interface circuit is affected; (2) the bandwidth of the LDO needs to be made very large, and the transient response of the LDO needs to be fast enough to meet the transient response of the interface circuit.

[0004] However, in order to save on BOM costs, chip design currently tends to use capacitorless LDOs to power the transmitter. As mentioned above, because the on-chip capacitance of a capacitorless LDO is small, the bandwidth of the capacitorless LDO itself generally cannot keep up with the changes in high-speed signals, resulting in a large output voltage ripple of the capacitorless LDO, which leads to a deterioration in the signal quality transmitted by the transmitter. Summary of the Invention

[0005] This invention provides a power supply for transmitters in medium-to-high-speed interface circuits. When using a capacitorless LDO structure, it can reduce power supply ripple caused by data transmission. This invention is achieved through the following technical solution:

[0006] A power supply for a transmitter in a medium-to-high-speed interface circuit includes an LDO and its on-chip voltage regulator C; characterized in that it further includes a data change detector and a charge replenisher; the data change detector detects whether the data to be transmitted by the transmitter in the medium-to-high-speed interface circuit has reversed, and if so, generates a trigger pulse with a pulse width of T0 at the moment of change; the charge replenisher is activated under the trigger pulse and replenishes the charge of the on-chip voltage regulator C of the LDO.

[0007] As a preferred technical solution, the data change detector includes a differential positive signal rising edge detection circuit and a differential negative signal rising edge detection circuit, which respectively detect whether the logic differential signals DP_PRE and DM_PRE of the data to be transmitted by the transmitter of the medium- and high-speed interface circuit have rising edges. Each time the logic differential signal DP_PRE has a rising edge, a corresponding trigger pulse is generated in the output signal ENIC_DP of the differential positive signal rising edge detection circuit; each time the logic differential signal DM_PRE has a rising edge, a corresponding trigger pulse is generated in the output signal ENIC_DP of the differential negative signal rising edge detection circuit; the charge replenisher is turned on under the trigger of each trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

[0008] As a preferred technical solution, the differential positive signal rising edge detection circuit includes an inverter I1, a controllable delay chain I2, and an AND gate I3. The input of inverter I1 is connected to the logic differential signal DP_PRE, the output of inverter I1 is connected to the input of controllable delay chain I2, the output of controllable delay chain I2 is connected to one input of AND gate I3, the other input of AND gate I3 is connected to the logic differential signal DP_PRE, and the output of AND gate I3 is used to output the trigger pulse ENIC_DP. The differential negative signal rising edge detection circuit includes an inverter I4, a controllable delay chain I5, and an AND gate I6. The input of inverter I4 is connected to the logic differential signal DM_PRE, the output of inverter I4 is connected to the input of controllable delay chain I5, the output of controllable delay chain I5 is connected to one input of AND gate I6, the other input of AND gate I6 is connected to the logic differential signal DM_PRE, and the output of AND gate I6 is used to output the trigger pulse ENIC_DM.

[0009] As a preferred technical solution, for the above-mentioned data change detector including differential positive and negative signal rising edge detection circuits, the charge replenisher can adopt a non-constant current source structure; specifically, the charge replenisher includes PMOS transistors MP0, MP1, MP2 and NMOS transistors MN0, MN1, MN2; the gates of MP1 and MN1 are both connected to the trigger pulse ENIC_DM, and the gates of MP2 and MN2 are both connected to the trigger pulse ENIC_DP; the sources of MP1 and MP0 are both connected to the power supply VCC of the LDO, and the drain of MP1 is connected to the source of MP2; the source of MN1 is connected to the source of MN2 and ground, and the drain of MN1 is connected to the drain of MN2 and the source of MN0; the drain of MP2 is connected to the drain of MN0 and the gate of MP0; the gate of MN0 is connected to the output voltage of the LDO or a current-limiting resistor is used to replace MN0 and connected to the drain of MP2 and the drains of MN1 and MN2, and the drain of MP0 serves as the supplementary charge output terminal Icharge.

[0010] As a preferred technical solution, for the above-mentioned data change detector including differential positive and negative signal rising edge detection circuits, the charge replenisher can also adopt a constant current source structure; specifically, the charge replenisher includes PMOS transistors MP0, MP1, MP2, MP3, MP4 and a constant current source Iref; the positive terminal of the constant current source Iref is grounded, and the negative terminal is connected to the drain (D), gate (G), and gate (G) of MP3 and MP0; the drain (D) of MP4 is connected to the source (S) of MP3, and the sources (S) of MP4, MP1, and MP2 are all connected to an LDO. The power supply VCC is connected to the gate (G) of MP4, which is connected to the signal PDN, the inverted signal of the power-down signal PD; the drain (D) of MP1 is connected to the source (S) of MP0 and the drain (D) of MP2, and the drain of MP0 serves as the supplementary charge output terminal Icharge; the gate (G) of MP1 is connected to the signal ENICN_DP, the inverted signal of the trigger pulse signal ENIC_DP; the gate (G) of MP2 is connected to the signal ENICN_DM, the inverted signal of the trigger pulse ENIC_DM.

[0011] As a preferred technical solution, the data change detector includes a differential positive signal integrated detection circuit, which detects whether the logic differential signal DP_PRE of the data to be transmitted by the transmitter of the medium- and high-speed interface circuit has a rising edge and a falling edge. When a rising edge and a falling edge occur, a trigger pulse is generated in the output signal ENIC accordingly. The charge replenisher is turned on under the trigger of each trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

[0012] As a preferred technical solution, the differential positive signal comprehensive detection circuit includes a controllable delay chain I7 and an XOR gate I8. The input terminal of the controllable delay chain I7 is connected to the logic differential signal DP_PRE. The output terminal of the controllable delay chain I7 is connected to one input terminal of the XOR gate I8. The other input terminal of the XOR gate I8 is connected to the logic differential signal DP_PRE. The output terminal of the XOR gate I8 is used to output the trigger pulse ENIC.

[0013] As a preferred technical solution, for the above-mentioned data change detector that only includes the differential positive signal integrated detection circuit, the charge replenisher can adopt a non-constant current source structure; specifically, the charge replenisher includes PMOS transistors MP0 and MP1 and NMOS transistors MN0 and MN1; the gate (G) of MP1 and the gate (G) of MN1 are both connected to the trigger pulse ENIC, the source (S) of MP1 and the source (S) of MP0 are both connected to the power supply VCC of the LDO, and the drain (D) of MP1 is connected to the drain (D) of MN0; the source (S) of MN1 is grounded, and the drain (D) of MN1 is connected to the source (S) of MN0; the gate (G) of MN0 is connected to the output voltage of the LDO, or a current-limiting resistor can be used to replace MN0 and connect it to the drain (D) of MP1 and the drain (D) of MN1, and the drain (D) of MP0 serves as the supplementary charge output terminal Icharge.

[0014] As a preferred technical solution, for the above-mentioned data change detector that only includes one differential positive signal integrated detection circuit, the charge replenisher can also adopt a constant current source structure; specifically, the charge replenisher includes PMOS transistors MP0, MP1, MP3, MP4 and a constant current source Iref; the positive terminal of the constant current source Iref is grounded, and the negative terminal is connected to the drain (D), gate (G) of MP3, and gate (G) of MP0; the drain (D) of MP4 is connected to the source (S) of MP3, and the sources (S) of MP4 and MP1 are both connected to the power supply VCC of the LDO; the gate (G) of MP4 is connected to the signal PDN, which is the inverted signal of the power-down signal PD; the drain (D) of MP1 is connected to the source (S) of MP0, and the drain (D) of MP0 serves as the charge replenishment output terminal Icharge; the gate (G) of MP1 is connected to the signal ENICN, which is the inverted signal of the trigger pulse signal ENIC.

[0015] The power supply provided by this invention for a transmitter in a medium-to-high-speed interface circuit has the following advantages: A data change detector detects the inversion moment of the data to be transmitted. Whenever the data inversion detector detects an inversion, a trigger pulse is generated to activate the charge replenisher. Since the pulse width T0 is the activation time of the charge replenisher, it replenishes the charge drawn from the on-chip voltage regulator C of the LDO due to the data inversion, preventing a drop in the LDO voltage and replenishing the charge through the LDO loop. This allows the power supply of the medium-to-high-speed interface circuit transmitter to use a simple capacitor-free LDO structure while avoiding severe ripple caused by data transmission, greatly improving the stability of the power supply for the transmitter and thus ensuring the quality of the transmitted signal. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of an existing LDO.

[0018] Figure 2 This is a schematic diagram of another existing LDO structure.

[0019] Figure 3 This is a block diagram of the power supply structure for a transmitter used in a medium-to-high-speed interface circuit, provided in an embodiment of the present invention.

[0020] Figure 4 This is a circuit diagram of a data change detector, including differential positive and negative signal rising edge detection circuits, provided in the power supply of a transmitter for a medium-to-high-speed interface circuit according to an embodiment of the present invention.

[0021] Figure 5 This is a signal timing diagram of a data change detector, including differential positive and negative signal rising edge detection circuits, provided in the power supply of a transmitter for a medium-to-high-speed interface circuit according to an embodiment of the present invention.

[0022] Figure 6 This is a circuit diagram of a power supply for a transmitter in a medium-to-high-speed interface circuit provided by an embodiment of the present invention, in which the data change detector includes only one differential positive signal comprehensive detection circuit.

[0023] Figure 7This is a signal timing diagram of a data change detector that includes only one differential positive signal integrated detection circuit in the power supply of a transmitter for a medium-to-high-speed interface circuit provided in this embodiment of the invention.

[0024] Figure 8 This is a circuit diagram of a charge replenisher with a non-constant current source structure when the data change detector includes differential positive and negative signal rising edge detection circuits in the power supply of a medium-to-high-speed interface circuit transmitter provided by an embodiment of the present invention.

[0025] Figure 9 This is a circuit diagram of a charge replenisher using a constant current source structure when the data change detector includes differential positive and negative signal rising edge detection circuits in the power supply of a medium-to-high-speed interface circuit transmitter provided by an embodiment of the present invention.

[0026] Figure 10 This is a circuit diagram of a charge replenisher with a non-constant current source structure in a power supply for a transmitter of a medium-to-high-speed interface circuit provided by an embodiment of the present invention, where the data change detector only includes one differential positive signal comprehensive detection circuit.

[0027] Figure 11 This is a circuit diagram of a constant current source structure for a charge replenisher in a power supply for a transmitter of a medium-to-high-speed interface circuit provided in this embodiment of the invention, where the data change detector only includes one differential positive signal comprehensive detection circuit. Detailed Implementation

[0028] To make the technical solution of the present invention clearer and its technical advantages more apparent, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of the present invention.

[0029] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments without conflict.

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0032] Research and analysis reveal that the bandwidth of Capless LDOs often lags behind the speed of medium- and high-speed interface circuits. This results in a significant drop in the LDO's output voltage before it can replenish the charge of the voltage regulator capacitor C. Furthermore, once the interface output data changes and the drive circuit stops drawing current from the voltage regulator capacitor C, the LDO cannot promptly adjust the bias voltage of the output power transistor, leading to output voltage overshoot. It takes time for the output voltage to stabilize, resulting in large power supply ripple. Therefore, this invention aims to provide a power supply based on a Capless LDO structure that can be applied to transmitters in medium- and high-speed interface circuits, while simultaneously reducing power supply ripple caused by data transmission.

[0033] Combination Figure 3 As shown, a basic embodiment of the present invention provides a power supply for a transmitter applied to a medium-to-high-speed interface circuit, including an LDO and its on-chip voltage regulator C, as well as a data change checker and a charge replenisher. The implementation principle and scheme of the LDO and its on-chip voltage regulator C can be adopted using... Figure 1 or Figure 2 The technical solution shown. Furthermore... Figure 1 The technical solutions shown are Figure 2 Compared to the technical solutions shown, Figure 2 The technology shown is compared to Figure 1 The technology shown is better because Figure 2 The technology shown uses an NMOS transistor as the driver transistor. The gm (transconductance) of the NMOS transistor is larger than that of the PMOS transistor. Figure 2 The technology shown is better than Figure 1 The technology shown has a faster response. Therefore, the implementation principle and scheme of the LDO and its on-chip voltage regulator C in this embodiment are preferably selected. Figure 2 The technical solution shown is not the focus of this embodiment, nor is the specific structure of the LDO and its on-chip voltage regulator C limited.

[0034] The key feature of the above basic embodiment is that it also includes a data change detector and a charge replenisher. The data change detector detects whether the data to be transmitted by the transmitter of the medium-high speed interface circuit has reversed. If so, a trigger pulse with a pulse width of T0 is generated at the moment of change; otherwise, no trigger pulse is generated. The charge replenisher is turned on under the trigger of the trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO. The pulse width T0 is the turn-on time of the charge replenisher.

[0035] The power supply provided in the above basic embodiment for a transmitter in a medium-to-high-speed interface circuit detects the inversion moment of the data to be transmitted using a data change detector. Whenever a data change is detected, a trigger pulse is generated to activate the charge replenisher. Since the pulse width T0 is the activation time of the charge replenisher, it replenishes the charge drawn from the on-chip voltage regulator C of the LDO due to the data inversion, preventing a drop in the LDO voltage and replenishing the charge through the LDO loop. This allows the power supply of the medium-to-high-speed interface circuit transmitter to use a simple capacitor-free LDO structure while avoiding severe ripple caused by data transmission, greatly improving the stability of the power supply for the transmitter and thus ensuring the quality of the transmitted signal.

[0036] For details on the implementation of the data change detector, please refer to [link / reference]. Figure 4As shown, in one optional embodiment, the data change detector includes a differential positive signal rising edge detection circuit and a differential negative signal rising edge detection circuit, which respectively detect whether the logic differential signals DP_PRE and DM_PRE of the data to be transmitted by the transmitter of the medium-high speed interface circuit have rising edges; each time the logic differential signal DP_PRE has a rising edge, a corresponding trigger pulse is generated in the output signal ENIC_DP of the differential positive signal rising edge detection circuit; each time the logic differential signal DM_PRE has a rising edge, a corresponding trigger pulse is generated in the output signal ENIC_DP of the differential negative signal rising edge detection circuit; the charge replenisher is turned on under the trigger of each trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

[0037] See also Figure 4 As a more specific embodiment, the differential positive signal rising edge detection circuit includes an inverter I1, a controllable delay chain I2, and an AND gate I3. The input of inverter I1 is connected to the logic differential signal DP_PRE, the output of inverter I1 is connected to the input of controllable delay chain I2, the output of controllable delay chain I2 is connected to one input of AND gate I3, the other input of AND gate I3 is connected to the logic differential signal DP_PRE, and the output of AND gate I3 is used to output the trigger pulse ENIC_DP. The differential negative signal rising edge detection circuit includes an inverter I4, a controllable delay chain I5, and an AND gate I6. The input of inverter I4 is connected to the logic differential signal DM_PRE, the output of inverter I4 is connected to the input of controllable delay chain I5, the output of controllable delay chain I5 is connected to one input of AND gate I6, the other input of AND gate I6 is connected to the logic differential signal DM_PRE, and the output of AND gate I6 is used to output the trigger pulse ENIC_DM.

[0038] Combination Figure 4 and Figure 5 As shown, the differential positive signal rising edge detection circuit detects the rising edge of signal DP_PRE. When a rising edge of DP_PRE occurs, ENIC_DP generates a high-level pulse. Similarly, the differential negative signal rising edge detection circuit detects the rising edge of signal DM_PRE. When a rising edge of DM_PRE occurs, ENIC_DM generates a high-level pulse. The pulse width T0 is controlled by the controllable delay chain I2, and the delay is determined by the unit data time length and the total drive delay of the PHY.

[0039] For details on the implementation of the data change detector, please refer to [link / reference]. Figure 6As shown, as another optional specific embodiment, the data change detector includes a differential positive signal integrated detection circuit, which detects whether the logic differential signal DP_PRE of the data to be transmitted by the transmitter of the high-speed interface circuit has a rising edge and a falling edge. When a rising edge and a falling edge occur, a corresponding trigger pulse is generated in the output signal ENIC. The charge replenisher is turned on under the trigger of each trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

[0040] See also Figure 6 As a more specific embodiment, the differential positive signal comprehensive detection circuit includes a controllable delay chain I7 and an XOR gate I8. The input terminal of the controllable delay chain I7 is connected to the logic differential signal DP_PRE. The output terminal of the controllable delay chain I7 is connected to one input terminal of the XOR gate I8. The other input terminal of the XOR gate I8 is connected to the logic differential signal DP_PRE. The output terminal of the XOR gate I8 is used to output the trigger pulse ENIC.

[0041] Combination Figure 6 and Figure 7 As shown, the differential positive signal integrated detection circuit detects the rising and falling edges of DP_PRE. When DP_PRE has a rising or falling edge, a high-level trigger pulse is generated in the signal ENIC. The pulse width T0 is controlled by the controllable delay chain I7, and the delay is determined by the unit data time length and the total drive delay of the PHY.

[0042] Next, regarding the implementation of the charge replenisher, for the aforementioned data change detector, a scheme including differential positive and negative signal rising edge detection circuits (i.e. Figure 4 and Figure 5 (As shown in the diagram), the charge replenisher can adopt a non-constant current source structure; specifically, see... Figure 8 As shown, the charge replenisher includes PMOS transistors MP0, MP1, MP2 and NMOS transistors MN0, MN1, MN2; the gates (G) of MP1 and MN1 are connected to the trigger pulse ENIC_DM, and the gates (G) of MP2 and MN2 are connected to the trigger pulse ENIC_DP; the sources (S) of MP1 and MP0 are connected to VCC, where VCC represents the power supply of the LDO (also used to indicate the power supply line name); the drain (D) of MP1 is connected to the source (S) of MP2; the source (S) of MN1 is connected to the source (S) of MN2 and ground; the drain (D) of MN1 is connected to the drain (D) of MN2 and the source (S) of MN0; the drain (D) of MP2 is connected to the drain (D) of MN0 and the gate (G) of MP0; the gate (G) of MN0 is connected to the output voltage of the LDO, or a current-limiting resistor can be used to replace MN0 and connected to the drain (D) of MP2 and the drains (D) of MN1 and MN2; the drain (D) of MP0 serves as the charge replenishment output terminal Icharge.

[0043] Figure 8In the scheme shown, the charge added to the Zener capacitor C is determined by the size of MP0 (W / L) and the width T0 of the trigger pulse when ENIC_DM or ENIC_DP is turned on. MN0 is biased by the LDO output voltage to limit current, or it can be replaced by a current-limiting resistor to prevent excessive shoot-through current when MP1, MN2 or MP2, MN1 are turned on simultaneously, and to achieve the function of MP0 fast turn-off and slow turn-on.

[0044] Furthermore, regarding the implementation of the charge replenisher, the aforementioned data change detector includes a scheme with differential positive and negative signal rising edge detection circuits (i.e. Figure 4 and Figure 5 (As shown in the diagram), the charge replenisher can also employ a constant current source structure; specifically, see... Figure 9 As shown, the charge replenisher includes PMOS transistors MP0, MP1, MP2, MP3, and MP4, and a constant current source Iref. The positive terminal of the constant current source Iref is grounded, and the negative terminal is connected to the drain (D), gate (G), and gate (G) of MP3 and MP0. The drain of MP4 is connected to the source (S) of MP3. The sources of MP4, MP1, and MP2 are all connected to VCC, which represents the power supply of the LDO. The gate of MP4 is connected to the signal PDN, which is the inverted signal of the power-down signal PD. The drain of MP1 is connected to the source of MP0 and the drain of MP2. The drain of MP0 serves as the charge replenishment output terminal Icharge. The gate of MP1 is connected to the signal ENICN_DP, which is the inverted signal of the trigger pulse signal ENIC_DP. The gate of MP2 is connected to the signal ENICN_DM, which is the inverted signal of the trigger pulse ENIC_DM.

[0045] Figure 9 In the scheme shown, the charge added to the voltage regulator capacitor C is determined by the size of MP0 (W / L) and the width T0 of the trigger pulse for ENIC_DP to turn on. MN0 uses the LDO output voltage bias to limit the current, and can be replaced by a current-limiting resistor to achieve the function of MP0 fast-turn-off and slow-turn-on.

[0046] Furthermore, regarding the implementation of the charge replenisher, for the aforementioned data change detector, only the differential positive signal comprehensive detection circuit is included in the detection circuit scheme (i.e. Figure 6 and Figure 7 (As shown in the diagram), the charge replenisher can adopt a non-constant current source structure; specifically, such as... Figure 10As shown, the charge replenisher includes PMOS transistors MP0 and MP1, and NMOS transistors MN0 and MN1. The gate (G) of MP1 and the gate (G) of MN1 are both connected to the trigger pulse ENIC. The source (S) of MP1 and the source (S) of MP0 are both connected to VCC, where VCC represents the power supply of the LDO. The drain (D) of MP1 is connected to the drain (D) of MN0. The source (S) of MN1 is grounded, and the drain (D) of MN1 is connected to the source (S) of MN0. The gate (G) of MN0 is connected to the output voltage of the LDO, or a current-limiting resistor can be used to replace MN0 and connect it to the drain (D) of MP1 and the drain (D) of MN1. The drain (D) of MP0 serves as the charge replenishment output terminal Icharge.

[0047] Finally, regarding the implementation of the charge replenisher, the above-mentioned data change detector only includes one differential positive signal comprehensive detection circuit (i.e. Figure 6 and Figure 7 (As shown in the diagram), the charge replenisher can also adopt a constant current source structure; specifically, such as... Figure 11 As shown, the charge replenisher includes PMOS transistors MP0, MP1, MP3, and MP4, and a constant current source Iref. The positive terminal of the constant current source Iref is grounded, and the negative terminal is connected to the drain (D), gate (G), and gate (G) of MP3 and MP0. The drain of MP4 is connected to the source (S) of MP3, and the sources of MP4 and MP1 are connected to VCC, where VCC represents the power supply of the LDO. The gate of MP4 is connected to the signal PDN, which is the inverted signal of the power-down signal PD. The drain of MP1 is connected to the source of MP0, and the drain of MP0 serves as the charge replenishment output terminal Icharge. The gate of MP1 is connected to the signal ENICN, which is the inverted signal of the trigger pulse signal ENIC.

[0048] Figure 11 In the scheme shown, the switch of the charge replenisher adopts a source switch structure. MP1 is the pulse switch of the charge replenisher, MP4 is the mirror switch of MP1, and the control signal of MP4 is controlled by the inverted signal PDN of the power down signal PD.

[0049] The amount of charge replenished by the charge replenisher provided in the above embodiments is determined by the circuit structure, the device's own parameters, and preset parameters. Figure 11 Taking the illustrated scheme as an example, the calculation method for its supplementary charge is as follows: the reference current of the charge supplementer is Iref, and the W / L ratio of MP3 and MP0 is MP3:MP0=1:N, MP4:MP1=1:N; therefore, Icharge=Iref*N. The charge supplemented to the stabilizing capacitor C is determined by the constant current source Iref and the pulse width T0 and N of ENIC activation, i.e., Q=Iref*N*T0.

[0050] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made according to the specific implementation of the present invention are still within the scope of the present invention.

Claims

1. A power supply for a transmitter in a medium-to-high-speed interface circuit, comprising an LDO and an on-chip voltage regulator C; characterized in that, It also includes a data change detector and a charge replenisher; the data change detector detects whether the data to be transmitted by the transmitter of the medium-high speed interface circuit has reversed, and if so, it generates a trigger pulse with a pulse width of T0 at the moment of change. The charge replenisher is turned on under the trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

2. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 1, characterized in that: The data change detector includes a differential positive signal rising edge detection circuit and a differential negative signal rising edge detection circuit, which respectively detect whether the logic differential signals DP_PRE and DM_PRE of the data to be transmitted by the transmitter of the medium- and high-speed interface circuit have rising edges. Each time the logic differential signal DP_PRE has a rising edge, a corresponding trigger pulse is generated in the output signal ENIC_DP of the differential positive signal rising edge detection circuit; each time the logic differential signal DM_PRE has a rising edge, a corresponding trigger pulse is generated in the output signal ENIC_DP of the differential negative signal rising edge detection circuit; the charge replenisher is turned on under the trigger of each trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

3. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 2, characterized in that: The differential positive signal rising edge detection circuit includes an inverter I1, a controllable delay chain I2, and an AND gate I3. The input of inverter I1 is connected to the logic differential signal DP_PRE, the output of inverter I1 is connected to the input of controllable delay chain I2, the output of controllable delay chain I2 is connected to one input of AND gate I3, the other input of AND gate I3 is connected to the logic differential signal DP_PRE, and the output of AND gate I3 is used to output the trigger pulse ENIC_DP. The differential negative signal rising edge detection circuit includes an inverter I4, a controllable delay chain I5, and an AND gate I6. The input of inverter I4 is connected to the logic differential signal DM_PRE, the output of inverter I4 is connected to the input of controllable delay chain I5, the output of controllable delay chain I5 is connected to one input of AND gate I6, the other input of AND gate I6 is connected to the logic differential signal DM_PRE, and the output of AND gate I6 is used to output the trigger pulse ENIC_DM.

4. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 2 or 3, characterized in that: The charge replenisher includes PMOS transistors MP0, MP1, MP2 and NMOS transistors MN0, MN1, MN2; the gates (G) of MP1 and MN1 are connected to the trigger pulse ENIC_DM, and the gates (G) of MP2 and MN2 are connected to the trigger pulse ENIC_DP; the sources (S) of MP1 and MP0 are connected to the power supply VCC of the LDO, and the drain (D) of MP1 is connected to the source (S) of MP2; the source (S) of MN1 is connected to the source (S) of MN2 and ground, and the drain (D) of MN1 is connected to the drain (D) of MN2 and the source (S) of MN0; the drain (D) of MP2 is connected to the drain (D) of MN0 and the gate (G) of MP0; the gate (G) of MN0 is connected to the output voltage of the LDO, or a current-limiting resistor can be used to replace MN0 and connect it to the drain (D) of MP2 and the drains (D) of MN1 and MN2; the drain (D) of MP0 serves as the charge replenishment output terminal Icharge.

5. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 2 or 3, characterized in that: The charge replenisher includes PMOS transistors MP0, MP1, MP2, MP3, and MP4, and a constant current source Iref. The positive terminal of the constant current source Iref is grounded, and the negative terminal is connected to the drain (D), gate (G), and gate (G) of MP3 and MP0. The drain of MP4 is connected to the source (S) of MP3. The sources of MP4, MP1, and MP2 are all connected to the power supply VCC of the LDO. The gate of MP4 is connected to the signal PDN, which is the inverted signal of the power-down signal PD. The drain of MP1 is connected to the source of MP0 and the drain of MP2. The drain of MP0 serves as the charge replenishment output terminal Icharge. The gate of MP1 is connected to the signal ENICN_DP, which is the inverted signal of the trigger pulse signal ENIC_DP. The gate of MP2 is connected to the signal ENICN_DM, which is the inverted signal of the trigger pulse ENIC_DM.

6. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 1, characterized in that: The data change detector includes a differential positive signal integrated detection circuit, which detects whether the logic differential signal DP_PRE of the data to be transmitted by the transmitter of the medium- and high-speed interface circuit has a rising edge and a falling edge. When a rising edge and a falling edge occur, a corresponding trigger pulse is generated in the output signal ENIC. The charge replenisher is turned on under the trigger of each trigger pulse and replenishes the charge to the on-chip voltage regulator C of the LDO.

7. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 6, characterized in that: The differential positive signal comprehensive detection circuit includes a controllable delay chain I7 and an XOR gate I8. The input of the controllable delay chain I7 is connected to the logic differential signal DP_PRE. The output of the controllable delay chain I7 is connected to one input of the XOR gate I8. The other input of the XOR gate I8 is connected to the logic differential signal DP_PRE. The output of the XOR gate I8 is used to output the trigger pulse ENIC.

8. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 6 or 7, characterized in that: The charge replenisher includes PMOS transistors MP0 and MP1, and NMOS transistors MN0 and MN1. The gate (G) of MP1 and the gate (G) of MN1 are both connected to the trigger pulse ENIC. The source (S) of MP1 and the source (S) of MP0 are both connected to the power supply VCC of the LDO. The drain (D) of MP1 is connected to the drain (D) of MN0. The source (S) of MN1 is grounded, and the drain (D) of MN1 is connected to the source (S) of MN0. The gate (G) of MN0 is connected to the output voltage of the LDO, or a current-limiting resistor can be used to replace MN0 and connect it to the drain (D) of MP1 and the drain (D) of MN1. The drain (D) of MP0 serves as the charge replenishment output terminal Icharge.

9. The power supply for a transmitter used in a medium-to-high-speed interface circuit according to claim 6 or 7, characterized in that: The charge replenisher includes PMOS transistors MP0, MP1, MP3, and MP4, and a constant current source Iref. The positive terminal of the constant current source Iref is grounded, and the negative terminal is connected to the drain (D), gate (G), and gate (G) of MP3 and MP0. The drain of MP4 is connected to the source (S) of MP3. The sources of MP4 and MP1 are both connected to the power supply VCC of the LDO. The gate of MP4 is connected to the signal PDN, which is the inverted signal of the power-down signal PD. The drain of MP1 is connected to the source of MP0, and the drain of MP0 serves as the charge replenishment output terminal Icharge. The gate of MP1 is connected to the signal ENICN, which is the inverted signal of the trigger pulse signal ENIC.

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