Radio frequency differential system, radio frequency amplifier system, and method of solving common mode noise

Abstract

Embodiments of the present application disclose radio frequency (RF) differential systems, RF amplifier systems, and methods of addressing common mode noise in RF differential circuits. The RF differential system includes an RF differential circuit and a winding connected to the RF differential circuit. The winding has a center tap. A biasing terminal is configured to receive a biasing signal. A suppression network is connected between the center tap and the biasing terminal.

Description

Technical Field

[0001] Embodiments of this application relate to radio frequency differential systems, radio frequency amplifier systems, and methods for resolving common-mode noise. Background Technology

[0002] Radio frequency (RF) differential circuits have a pair of signal lines that ideally provide signals of equal and opposite polarity, allowing the circuit to effectively eliminate unwanted noise (common-mode noise) that occurs equally on both lines while amplifying the intended differential signal between them. For example, a differential amplifier circuit can be used to achieve amplification. RF differential circuits are used to improve noise reduction, linearity, and stability. For example, amplifier circuits are commonly used in RF circuits to amplify weak signals received by the antenna to a level suitable for subsequent circuit-level processing, while adding minimal noise and distortion. Summary of the Invention

[0003] According to one aspect of the present application, a radio frequency differential system is provided, comprising: an RF differential circuit; a winding connected to the RF differential circuit and including a center tap; a bias terminal; and a suppression network connected between the center tap and the bias terminal.

[0004] According to another aspect of the embodiments of this application, a radio frequency amplifier system is provided, comprising: a differential amplifier circuit including a first amplifier stage and a second amplifier stage; a transformer connected between the output terminal of the first amplifier stage and the input terminal of the second amplifier stage, the transformer including a first winding having a first center tap and a second winding having a second center tap; a first bias terminal; a second bias terminal; a first suppression network connected between the first center tap and the first bias terminal; and a second suppression network connected between the second center tap and the second bias terminal.

[0005] According to another aspect of the embodiments of this application, a method for resolving common-mode noise in a radio frequency differential circuit is provided, comprising: receiving an RF differential input signal through a first RF differential circuit; outputting a first RF differential output signal from the first RF differential circuit to the primary winding of a transformer; filtering the first RF differential output signal through a first suppression network connected between a first center tap and a first bias signal of the primary winding and a second suppression network connected between a second center tap and a second bias signal of the secondary winding of the transformer; receiving the first RF differential output signal from the secondary winding through a second RF differential circuit; and outputting a second RF differential output signal from the second RF differential circuit. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. Furthermore, the drawings are provided as examples of embodiments of the invention and are not intended to be limiting.

[0007] Figure 1 This is a block diagram illustrating various aspects of an example RF differential system according to some embodiments.

[0008] Figure 2 This is a block diagram illustrating aspects of another example RF differential system according to some embodiments.

[0009] Figure 3 This illustrates some embodiments. Figure 1 or Figure 2 The circuit diagram of an example amplifier circuit used in an RF differential system.

[0010] Figure 4 This illustrates some embodiments. Figure 1 or Figure 2 The circuit diagram of another example amplifier circuit used in the RF differential system.

[0011] Figure 5 This is a block diagram illustrating various aspects of a multi-stage RF differential system according to some embodiments.

[0012] Figure 6 This is a block diagram illustrating other aspects of a multi-stage RF differential system according to some embodiments.

[0013] Figure 7 This is a block diagram illustrating aspects of another example RF differential system according to some embodiments.

[0014] Figure 8 This is a circuit diagram illustrating an example suppression network circuit according to some embodiments.

[0015] Figure 9 This is a circuit diagram illustrating another example of a suppression network circuit according to some embodiments.

[0016] Figure 10 This is a circuit diagram illustrating another example of a suppression network circuit according to some embodiments.

[0017] Figure 11 This is a circuit diagram illustrating another example of a suppression network circuit according to some embodiments.

[0018] Figure 12 This is a flowchart illustrating an example of a method according to the disclosed embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0021] An RF differential circuit ideally receives equal and opposite differential input signals. This allows the circuit to effectively eliminate unwanted noise (common-mode noise) that occurs equally on both lines, while amplifying the intended differential signal between them. Ideally, the common-mode signal in a differential circuit should be zero; that is, the received differential input signals should be equal and opposite in polarity. However, due to mismatches in actual implementations, common-mode signals are often not completely eliminated. This can lead to common-mode noise, affecting the performance of the RF differential circuit.

[0022] In some RF circuit designs, such as RF differential amplifiers, impedance matching circuitry is provided between the input and output terminals of the amplifier stage. Such circuitry can include inductors or transformers. For example, an interstage transformer can be connected between the output terminal of one amplifier stage and the input terminal of the next. This maintains signal isolation while suppressing interstage common-mode noise. More specifically, the center tap of the transformer or inductor winding is designed to bypass common-mode signals to VDD and / or AC ground terminals and provide bias to the circuit. However, if common-mode noise is injected into the bias network, it can create feedback loops, and circuit stability can be compromised by unwanted common-mode noise. This is particularly problematic when the circuit operates at high frequencies containing significant harmonic effects.

[0023] This disclosure relates to common-mode rejection networks for RF differential circuits to reduce common-mode noise in the circuit. For example, some examples involve adding a rejection network between the center tap and bias point of a winding element to reduce common-mode noise. The winding element can be, for example, the winding of a transformer and / or inductor. Common-mode noise suppression networks can improve the stability, gain, and power efficiency of RF differential circuits. For example, this topology can be extended to single-stage or multi-stage amplifiers with differential structures, as well as LC-VCO circuits.

[0024] In some publicly available examples, a suppression network is added between the center tap of the winding element and the associated bias point. The suppression network can be constructed using any type of parallel / series combination. The bandpass response (R / L / C values) is designed based on the specific circuit application.

[0025] Some examples use passive components to implement suppression networks that suppress different types of noise. Different types of filter circuits can be employed, such as various low-pass suppression networks for suppressing high-frequency noise and / or band-pass suppression networks for suppressing both low-frequency and high-frequency noise. Further examples use notch suppression networks to suppress noise with notch frequencies.

[0026] In other embodiments, the network is implemented with active components such as operational amplifiers (operational amplifiers), active filters, transistors (BJTs, FETs, etc.), voltage regulators (linear and switching regulators), active noise cancellation circuits, phase-locked loops (PLLs), etc.

[0027] Suppression networks can be added to any type of RF differential circuit in an RF front-end design, such as single-stage or multi-stage amplifiers and LC-VCOs. Suppression networks can be applied to the center tap of winding elements (such as transformers or inductors) in any type of technology, including CMOS, III-V compound semiconductors, 3D integrated circuits (3DIC), integrated power devices (IPD), etc.

[0028] For example, a suppression network can be incorporated into a single-stage RF differential circuit where the winding element with a center tap is an inductor. A suppression network is added between the center tap of the inductor and the associated bias point.

[0029] In other embodiments, the suppression network is incorporated into a multi-stage RF differential circuit, wherein the winding element with a center tap is the primary and / or secondary winding of a transformer. A suppression network is added between the center tap of the primary winding of the transformer and a first bias point, and another suppression network is added between the center tap of the secondary winding of the transformer and a second bias point. Alternatively, the first bias point may be a VDD connection, and the second bias point may be a gate voltage VG2.

[0030] In other examples, the suppression network is incorporated into the LC-VCO RF differential circuit, where the winding element with a center tap is an inductor, and the suppression network is added between the center tap of the inductor and the associated bias point.

[0031] Figure 1 This is a block diagram illustrating various aspects of an RF differential system 100 (such as an RF amplifier system). System 100 includes an RF differential circuit 10. A winding 20 is connected to the RF differential circuit 10, and the winding 20 has a center tap 22. A suppression network 30 is connected between the center tap 22 and a bias terminal 40, such as a VDD or gate voltage VG terminal. As will be further described below, in some embodiments, the winding 20 is an inductor winding or a primary or secondary transformer winding. As will also be discussed below, the RF differential circuit can include any of several types of differential circuits, such as amplifier circuits, multistage amplifier circuits, voltage-controlled oscillator (VCO) circuits, etc.

[0032] Figure 2 Example system 101 is shown, where the RF differential circuitry is a differential amplifier 12, such as a power amplifier or a low-noise amplifier (LNA). Amplifier 12 is configured to receive and amplify the RF differential input signal and provide the amplified RF differential signal at differential RF output terminal 14. Inductor 21 provides a winding connected to the input of amplifier 12. Inductor 21 includes a center tap 22, and a common-mode noise suppression network 30 is connected between the center tap 22 and a bias terminal 40 (e.g., a VDD or VG terminal). The stability, gain, and power efficiency of differential amplifier 12 can be improved by the common-mode noise suppression network 30.

[0033] Figure 3 Example system 102 is shown, where amplifier 12 is a differential LNA 110. LNA circuit 110 is implemented using a complementary cascaded design in differential mode. LNA circuit 110 includes a pair of NMOS transistors M1A, M1B and a pair of PMOS transistors M2A, M2B arranged in a differential configuration. Positive and negative input terminals receive a differential input signal (RFin) and are connected to the gate terminals of transistors M1A and M2A, and the gate terminals of transistors M1B and M2B, respectively, such that the input signal RFI is received at the gate terminals of NMOS transistors M1A, M1B and PMOS transistors M2A, M2B.

[0034] The source terminals of M1A and M1B are connected to common ground. The drain terminals of M1A and M1B are coupled to the drain terminals of PMOS transistors M2A and M2B, which serve as active loads. The source terminals of PMOS transistors M2A and M2B are connected to the power supply voltage VDD. The drain terminals of PMOS transistors M2A and M2B and the drain terminals of NMOS transistors M1A and M1B are coupled to the differential output terminal RFout.

[0035] Bias resistors R1 and R2 can be connected between the gate and drain terminals of PMOS transistors M2A and M2B and NMOS transistors M1A and M1B to help set the DC operating point of PMOS transistors M2A and M2B, and to ensure that the gate voltage is biased to the correct level by creating a stable feedback path for PMOS transistors M2B and M2A. Inductor 21 is connected between the positive and negative input terminals RFin+ / RFin-, and suppression network 30 is connected between the center tap 22 of inductor 21 and the bias terminal 40.

[0036] The operation of an LNA is based on the transconductance (gm) of NMOS transistors M1A and M1B and the output resistance (rout) of PMOS transistors M2A and M2B. When an input signal is applied at RFin, the NMOS transistor amplifies the signal and controls the current through its gate-source voltage. The PMOS transistor acts as a load device, converting the amplified signal into an output voltage at RFout.

[0037] Figure 4 Another example of amplifier 12 including a differential common-source circuit is shown. For simplicity, only one side of the differential amplifier circuit is shown, where one of the RF signal inputs RFin+ is connected to inductor 21 and amplifier circuit 112. Common-source amplifier circuit 112 includes CMOS transistor M1, whose gate terminal receives the input signal RFin+ and whose drain terminal receives the output node RFout+. A mirror of circuit 112 will receive the differential input signal RFin and output an amplified RFout signal. Load resistor RD is connected between the drain terminal of transistor M1 and the VDD terminal. Transistor M1 converts the gate-source voltage change into a small-signal drain current, which passes through the resistive load RD and generates an amplified voltage across the load resistor RD. Inductor 21 is connected to the positive input terminal RFin+ and the negative input terminal RFin+, although as described above... Figure 4 (Not shown in the image). The suppression network 30 is connected between the center tap 22 and the bias terminal 40 of the inductor 21.

[0038] Figure 5 An example of incorporating multiple suppression networks into a multi-stage RF differential circuit is shown. The winding 20 with center tap 22 is the primary winding and / or secondary winding of transformer 122.

[0039] More specifically, Figure 5 The system 103 shown includes a differential amplifier circuit comprising a first amplifier stage 12-1 and a second amplifier stage 12-2. A transformer 122 is connected between the output terminal of the first amplifier stage 12-1 and the input terminal of the second amplifier stage 12-2. The transformer 122 has a primary or first winding 124 having a first center tap 126 and a secondary or second winding 128 having a second center tap 130. A first suppression network 301 is connected between the first center tap 126 and a first bias terminal 40-1, and a second suppression network 30-2 is connected between the second center tap 130 and the second bias terminal 40-2. As described above, the first and second amplifier circuits 12-1 and 12-2 can be power amplifiers or LNA circuits, such as... Figure 3 and Figure 4 The example shown.

[0040] Figure 6 It shows Figure 5 Other aspects of the multi-stage RF differential circuit 103 shown. The multi-stage RF differential circuit 103 includes a first amplifier stage 12-1, a second amplifier stage 12-2, and any number of N additional amplifier stages up to amplifier stages 12-N. A transformer 122 is connected between the output terminal of one amplifier stage and the input terminal of the subsequent amplifier stage. Therefore, in Figure 6 In the example, the first transformer 122-1 is connected between the output terminal of the first amplifier stage 12-1 and the input terminal of the second amplifier stage 12-2, and the second transformer 122-2 is connected between the output terminal of the second amplifier stage 12-2 and the input terminal of the next (i.e., the last) amplifier stage 12-N. Figure 6 The configuration of each transformer shown is similar to Figure 5 Transformer 122 is shown. Therefore, the first center tap 126 of the first transformer 122-1 is connected to the first suppression network 30-1, which is also connected to the first bias terminal 40-1. The second center tap 130 of the first transformer 122-1 is connected to the second suppression network 30-2, which is connected to the second bias terminal 40-2.

[0041] Similarly, the first center tap 126 of the second transformer 122-2 is connected to the third suppression network 30-3, which is connected to the second bias terminal 40-3. The second center tap 130 of the second transformer 122-2 is connected to the fourth suppression network 30-4, which is connected to the third bias terminal 40-4. Figure 6In the diagram, the first and third bias terminals 40-1 and 40-3 are VDD terminals, while the second and fourth bias terminals 40-2 and 40-4 are VG terminals.

[0042] Figure 7 Another example 104 is shown, where the differential circuit includes an inductor-capacitor (LC) voltage-controlled oscillator (VCO) circuit. System 104 includes an inductor 21 connected in parallel with a capacitor 52. The parallel connection of the inductor 21 and the capacitor 52 determines the oscillation frequency, which can be varied by an applied control voltage 50. A suppression network 30 is connected between the center tap 22 of the inductor 21 and a bias terminal 40, which can be either a VDD terminal or a VG terminal.

[0043] Return to reference Figure 6 The common-mode signal is composed of 1 / 2 (V in+ +V in- The common-mode signals are ideally equal and thus cancel each other out at the transformer center tap. However, since the common-mode signals are typically mismatched, noise can be generated and passed as noise to the bias network, which acts as the feedback loop. This can affect and degrade circuit performance.

[0044] Suppression network 30 is configured to reduce this common-mode noise. Suppression network 30 can be implemented using various circuit topologies, including passive and / or active elements. Figures 8-11 Various examples of circuits implementing the suppression network 30 using passive components are shown. Figure 8 An example suppression network 30 including a low-pass filter circuit 140 is shown. The RC low-pass filter circuit 140 is configured to suppress high-frequency noise and includes a resistor R connected to the center tap 22 of the inductor 21. A capacitor C is connected between the bias terminal 40 and ground, and the output is taken from both ends of the capacitor C. At low frequencies, the capacitor C has high reactance and therefore operates like an open circuit. Most of the input voltage appears across the capacitor, so the output voltage remains high. At high frequencies, the reactance of the capacitor C decreases, so it begins to operate like a short circuit, shunting the high-frequency signal to ground. This results in a lower output voltage.

[0045] Figure 9 Another example of a suppression network 30 including a bandpass filter circuit 141 is shown. The bandpass filter circuit 141 is configured to suppress low-frequency and high-frequency noise while allowing the desired frequency signal to pass. Two capacitors C1 and C2 are connected to a resistor R in a bandpass configuration. More specifically, the first capacitor C1 is connected between the center tap 22 and ground, and the second capacitor C2 is connected between the bias terminal 40 and ground. The resistor R is connected between the center tap 22 and the bias terminal 40. Figure 9The bandpass circuit 141 combines low-pass and high-pass filters to allow the desired intermediate frequency band to pass. At low frequencies, the reactance of capacitor C is high, so it blocks low-frequency signals. At high frequencies, the reactance of capacitor C is low, so it effectively short-circuits high-frequency signals to ground. At the intermediate frequency (i.e., the "passband"), the circuit allows signals to pass with minimal attenuation.

[0046] Figure 10 Another embodiment of the suppression network 30, including a low-pass filter circuit 142, is shown. The low-pass filter circuit 142 has two transmission lines Tlines connected in series between the center tap 22 and the device terminal 40. A capacitor C is connected between a node of the transmission lines and ground. Figure 8 Similar to the low-pass filter circuit 140 shown, the low-pass filter circuit 142 allows signals with frequencies below a specific cutoff frequency to pass through while attenuating signals with frequencies above that specific cutoff frequency. Transmission lines (Tlines) are essentially used as low-pass filters because their reactance varies with frequency, limiting the bandwidth of signals they can carry. Therefore, high-frequency signals will be rejected.

[0047] Figure 11 An example suppression network 30 employing a notch filter 143 is shown. The notch filter 143 includes an LC circuit having an inductor L connected in parallel with a capacitor C between a center tap 22 and a bias terminal 40. The LC notch filter 143 is configured to attenuate specific frequencies while allowing frequencies above and below it to pass through with minimal attenuation. The parallel inductor L and capacitor C are connected in series with the signal path. At the resonant frequency, the LC circuit presents high impedance, blocking the signal. Other frequencies show almost no attenuation.

[0048] The suppression network 30 can include various combinations of components connected in parallel or series. The bandpass response (R / L / C values) can be designed based on specific circuit applications.

[0049] In other examples, the suppression network 30 can be formed from active components or circuits, such as operational amplifiers (Op-Amp), active filters, transistors (BJTs and FETs), voltage regulators (linear and switching regulators), active noise cancellation circuits, phase-locked loops (PLLs), etc. Furthermore, the suppression network 30 can be added to other RF differential circuits besides those shown herein and is suitable for a variety of technologies, including CMOS, III-V compound semiconductors, three-dimensional integrated circuits (3DICs), integrated power devices (IPDs), etc.

[0050] Figure 12 This is a flowchart illustrating common noise reduction methods 200 in RF differential circuits (such as the various RF differential circuits discussed above). Reference Figure 12 and Figure 5In operation 210, the first RF differential circuit 12-1 receives the RF differential input signals RFin+ / RFin-. In operation 212, a first RF differential output signal is output from the first RF differential circuit 12-1 to the primary winding 124 of the transformer 122. In operation 214, the first RF differential output signal is filtered by a first suppression network 30-1 connected between the first center tap 126 and the first bias signal 40-1 of the primary winding 124, and a second suppression network 30-2 connected between the second center tap 130 and the second bias signal 40-2 of the secondary winding 128 of the transformer 122. In operation 216, the first RF differential output signal is received from the secondary winding 128 via the second RF differential circuit 12-2. In operation 218, a second RF differential output signal is output from the second RF differential circuit 12-2.

[0051] As described above, in some embodiments, the first RF differential circuit 12-1 and the second RF differential circuit 12-2 are amplifier circuits, such as LNAs. Therefore, the RF differential input signal is amplified to generate a first RF differential output signal, and the first RF differential output signal is amplified by the second RF differential circuit. In some examples, the first bias signal is a VDD signal and / or a VG signal.

[0052] Therefore, various aspects of this disclosure provide a common-mode rejection network for RF differential circuits to reduce common-mode noise in the circuit. Several embodiments are disclosed, applicable to various circuit topologies of RF differential circuits. The disclosed common-mode rejection topologies improve the stability, gain, noise performance, etc., of RF circuits.

[0053] According to an aspect of this disclosure, the RF system includes an RF differential circuit. A winding is connected to the RF differential circuit and includes a center tap. A bias terminal is configured to receive a bias signal, and a suppression network is connected between the center tap and the bias terminal.

[0054] In some embodiments, the RF system further includes an inductor, wherein the inductor includes a winding having a center tap.

[0055] In some embodiments, the RF differential circuit includes a differential amplifier circuit.

[0056] In some embodiments, the differential amplifier circuit is a multi-stage differential amplifier including a first amplifier stage and a second amplifier stage.

[0057] In some embodiments, the RF differential circuit includes a voltage-controlled oscillator (VCO) circuit.

[0058] In some embodiments, the bias terminal is one of the VDD terminal or the VG terminal.

[0059] In some embodiments, the suppression network includes a low-pass filter circuit.

[0060] In some embodiments, the suppression network includes a bandpass filter circuit.

[0061] In some embodiments, the suppression network includes a notch filter circuit.

[0062] According to a further aspect, the RF amplifier system includes a differential amplifier circuit having a first amplifier stage and a second amplifier stage. A transformer is connected between the output terminal of the first amplifier stage and the input terminal of the second amplifier stage, the transformer including a first winding with a first center tap and a second winding with a second center tap. Both the first bias terminal and the second bias terminal are configured to receive a bias signal. A first suppression network is connected between the first center tap and the first bias terminal, and a second suppression network is connected between the second center tap and the second bias terminal.

[0063] In some embodiments, both the first amplifier stage and the second amplifier stage include a common-source amplifier circuit.

[0064] In some embodiments, both the first amplifier stage and the second amplifier stage include cascaded amplifier circuitry.

[0065] In some embodiments, both the first suppression network and the second suppression network include filter circuits.

[0066] In some embodiments, the first suppression network and the second suppression network include active elements.

[0067] In some embodiments, the first bias terminal is a VDD terminal and the second bias terminal is a VG terminal.

[0068] In some embodiments, the differential amplifier circuit includes a third amplifier stage, and wherein the transformer is a first transformer. The system further includes: a second transformer connected between the output terminal of the second amplifier stage and the input terminal of the third amplifier stage, the second transformer including a third winding having a third center tap and a fourth winding having a fourth center tap; a third bias terminal; a fourth bias terminal; a third suppression network connected between the third center tap and the third bias terminal; and a fourth suppression network connected between the fourth center tap and the fourth bias terminal.

[0069] According to an additional aspect of this disclosure, a method for resolving common-mode noise in an RF differential circuit includes receiving an RF differential input signal through a first RF differential circuit; outputting a first RF differential output signal from the first RF differential circuit to the primary winding of a transformer; filtering the first RF differential output signal through a first suppression network connected between a first center tap and a first bias signal in the primary winding and a second suppression network connected between a second center tap and a second bias signal in the secondary winding of the transformer; receiving the first RF differential output signal from the secondary winding through a second RF differential circuit; and outputting a second RF differential output signal from the second RF differential circuit.

[0070] In some embodiments, the method further includes: amplifying the RF differential input signal through a first RF differential circuit; and amplifying the first RF differential output signal through a second RF differential circuit.

[0071] In some embodiments, the first bias signal is the VDD signal.

[0072] In some embodiments, the second bias signal is the VG signal.

[0073] This disclosure outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A radio frequency differential system, comprising: Radio frequency differential circuit; A winding, connected to the radio frequency differential circuit, and including a center tap; Bias terminal; as well as A suppression network is connected between the center tap and the bias terminal.

2. The radio frequency differential system of claim 1 further includes an inductor, wherein the inductor includes the winding having the center tap.

3. The radio frequency differential system of claim 1, wherein, The radio frequency differential circuit includes a differential amplifier circuit.

4. The radio frequency differential system of claim 1, wherein, The radio frequency differential circuit includes a voltage-controlled oscillator circuit.

5. The radio frequency differential system of claim 1, wherein, The suppression network includes a low-pass filter circuit.

6. The radio frequency differential system of claim 1, wherein, The suppression network includes a bandpass filter circuit.

7. The radio frequency differential system of claim 1, wherein, The suppression network includes a notch filter circuit.

8. A radio frequency amplifier system, comprising: A differential amplifier circuit includes a first amplifier stage and a second amplifier stage; A transformer is connected between the output terminal of the first amplifier stage and the input terminal of the second amplifier stage, the transformer including a first winding having a first center tap and a second winding having a second center tap; First bias terminal; Second bias terminal; A first suppression network is connected between the first center tap and the first bias terminal; as well as A second suppression network is connected between the second center tap and the second bias terminal.

9. The radio frequency amplifier system of claim 8, wherein, The differential amplifier circuit includes a third amplifier stage, and wherein the transformer is a first transformer. The RF amplifier system also includes: A second transformer is connected between the output terminal of the second amplifier stage and the input terminal of the third amplifier stage. The second transformer includes a third winding with a third center tap and a fourth winding with a fourth center tap. Third bias terminal; Fourth bias terminal; A third suppression network is connected between the third center tap and the third bias terminal; and A fourth suppression network is connected between the fourth center tap and the fourth bias terminal.

10. A method for solving common-mode noise in radio frequency differential circuits, comprising: The radio frequency differential input signal is received through the first radio frequency differential circuit; The first radio frequency differential output signal is output from the first radio frequency differential circuit to the primary winding of the transformer; The first radio frequency differential output signal is filtered by a first suppression network connected between the first center tap and the first bias signal of the primary winding and a second suppression network connected between the second center tap and the second bias signal of the secondary winding of the transformer. The first radio frequency differential output signal is received from the secondary winding via the second radio frequency differential circuit; and The second RF differential output signal is output from the second RF differential circuit.

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