Method for manufacturing a circuit board structure

Abstract

A method for manufacturing a circuit board structure is provided. The method includes providing a base substrate, wherein the base substrate includes a core layer and a first base circuit layer disposed on the core layer; patterning a plurality of conductive films to form a plurality of circuit layers, wherein the circuit layers include a first circuit layer and a second circuit layer; providing a plurality of dielectric layers, wherein the dielectric layers include a first dielectric layer and a second dielectric layer; sequentially stacking the first dielectric layer, the first circuit layer, the second dielectric layer and the second circuit layer on the first base circuit layer; and performing a lamination process to fix the first dielectric layer, the first circuit layer, the second dielectric layer and the second circuit layer on the first base circuit layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a circuit board structure, and more particularly to a method for manufacturing a circuit board structure by pressing multiple pre-fabricated circuit layers onto a base substrate in one step. Background Technology

[0002] Circuit board structures typically include a base substrate and add-on layers. Specifically, a dielectric film and a conductive film are sequentially stacked on the base substrate. Next, a patterning process is performed on the conductive film to transform it into a circuit pattern (or wiring layer) capable of performing a specific function. Finally, the add-on layer process is repeated until the entire circuit board structure has the required number of layers. However, as circuit board structures become increasingly complex and the number of layers gradually increases, this layer-by-layer stacking method becomes extremely time-consuming. Therefore, while existing circuit board fabrication methods have gradually met their intended uses, they are not perfect in every aspect. Thus, there is still a need to develop new circuit board fabrication methods. Summary of the Invention

[0003] According to some embodiments, a method for manufacturing a circuit board structure is provided. The method includes: providing a base substrate, wherein the base substrate includes a core layer and a first basic circuit layer disposed on the core layer; patterning a plurality of conductive thin films to form a plurality of circuit layers, wherein the circuit layers include a first circuit layer and a second circuit layer; providing a plurality of dielectric layers, wherein the dielectric layers include a first dielectric layer and a second dielectric layer; sequentially stacking the first dielectric layer, the first circuit layer, the second dielectric layer, and the second circuit layer on the first basic circuit layer; and performing a lamination process to fix the first dielectric layer, the first circuit layer, the second dielectric layer, and the second circuit layer onto the first basic circuit layer.

[0004] In some embodiments, after performing the lamination process, the process further includes performing a drilling process to cause the first circuit layer to include a first portion and a second portion that are disconnected from each other, and to cause the second circuit layer to include a third portion and a fourth portion that are disconnected from each other.

[0005] In some embodiments, the second portion surrounds the first portion, and the fourth portion surrounds the third portion.

[0006] In some embodiments, the base substrate further includes a second base circuit layer, and the second base circuit layer is disposed on the core layer relative to the first base circuit layer.

[0007] In some embodiments, the circuit layer includes a third circuit layer and a fourth circuit layer, the dielectric layer includes a third dielectric layer and a fourth dielectric layer, and the method of manufacturing the circuit board structure further includes: sequentially stacking the third dielectric layer, the third circuit layer, the fourth dielectric layer and the fourth circuit layer on the second base circuit layer; and performing a lamination process to fix the third dielectric layer, the third circuit layer, the fourth dielectric layer and the fourth circuit layer onto the second base circuit layer.

[0008] In some embodiments, after performing the lamination process, the process further includes performing a drilling process to cause the third circuit layer to include fifth and sixth portions that are disconnected from each other, and to cause the fourth circuit layer to include seventh and eighth portions that are disconnected from each other.

[0009] In some embodiments, the sixth portion surrounds the fifth portion, and the eighth portion surrounds the seventh portion.

[0010] In some embodiments, after patterning multiple conductive films, the circuit layer can be carried by multiple partitions to stack the circuit layer on a first base circuit layer.

[0011] In some embodiments, the process of patterning the conductive thin film includes a laser etching process.

[0012] In some embodiments, the laser etching process includes solid-state lasers.

[0013] The method for manufacturing the circuit board structure of the present invention can be applied to various types of circuit board structures. To make the components and advantages of the present invention more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0014] When with attachment Figure 1 The invention will be more fully understood from the following detailed description. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0015] Figure 1 , Figure 2A , Figure 3 , Figure 4 , Figure 5A and Figure 6 These are cross-sectional schematic diagrams showing the circuit board structure at different stages of the manufacturing process according to some embodiments of the present invention.

[0016] Figure 2B and Figure 5B These are top views illustrating different stages of the fabrication process of the circuit layer according to some embodiments of the present invention. Detailed Implementation

[0017] The apparatus of various embodiments of the present invention will be described in detail below. It should be understood that the following description provides many different embodiments for implementing various ways of some embodiments of the present invention. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are merely examples and not for limiting the present invention. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements in order to clearly describe the present invention. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present invention and does not represent any relationship between the different embodiments and / or structures discussed.

[0018] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number representing the (or plurality of) elements, nor to represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.

[0019] In some embodiments of the present invention, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding connection and bonding may also include cases where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0020] In this text, the terms "approximately," "about," and "substantially" typically indicate a value or range within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantities are approximate; that is, even without specific mention of "approximately," "about," or "substantially," their meaning is implied. The phrase "the range is between the first and second values" indicates that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%. If the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, then the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0021] It should be understood that, without departing from the spirit of the invention, components in the following embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of the invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of the invention.

[0023] In existing circuit board manufacturing methods, dielectric and conductive films are typically stacked sequentially on a base substrate, and the conductive films are patterned to form a build-up structure on the base substrate. This process is repeated until the circuit board structure reaches the required number of layers. However, while this method offers high precision, the overall process time increases with the number of build-up layers. In other words, this approach is not conducive to the development of new processes or materials that require rapid results. Therefore, this invention provides a circuit board manufacturing method that pre-fabricates multiple circuit layers and then laminates the overlapping circuit layers and dielectric layers onto a base substrate, thereby completing all the build-up structures in one step.

[0024] Reference Figure 1 , Figure 2A , Figure 3 , Figure 4 , Figure 5A and Figure 6 These are cross-sectional schematic diagrams showing the circuit board structure at different stages of the manufacturing process according to some embodiments of the present invention. In addition, see also... Figure 2B and Figure 5B These are top views illustrating different stages of the circuit layer fabrication method according to some embodiments of the present invention. It should be understood that, for clarity, some components of the circuit board structure are omitted in the drawings, and only some components are schematically shown. In some embodiments, additional components may be added to the circuit board structure described below. In other embodiments, some components of the circuit board structure described below may be replaced or omitted. It should be understood that, in some embodiments, additional operational steps may be provided before, during, and / or after the circuit board structure formation method. In some embodiments, some operational steps may be replaced or omitted, and the order of some operational steps is interchangeable.

[0025] like Figure 1 As shown, a base substrate 10 is provided, comprising a core layer 100, a first basic circuit layer 101, and a second basic circuit layer 102. Specifically, the core layer 100 is used to support components disposed thereon (e.g., the first basic circuit layer 101, the second basic circuit layer 102, and other components) during manufacturing. In some embodiments, the material of the core layer 100 may be a prepreg containing polymeric materials, fibrous materials, or other suitable materials, but the invention is not limited thereto. For example, polymeric materials may include epoxy resin, polyimide (PI), polypropylene (PP), other suitable polymeric materials, or combinations thereof, but the invention is not limited thereto. For example, fibrous materials may include carbon fiber, glass fiber, other suitable fibrous materials, or combinations thereof, but the invention is not limited thereto.

[0026] like Figure 1As shown, a first base circuit layer 101 is disposed on one side of the base layer 10, and a second base circuit layer 102 is disposed on the core layer 100 opposite to the first base circuit layer 101. Specifically, the first base circuit layer 101 and the second base circuit layer 102 are used to transmit signals, such as control signals, image signals, sound signals, other suitable signals, or combinations thereof, but the invention is not limited thereto. In some embodiments, the first base circuit layer 101 or the second base circuit layer 102 may include a conductive material. For example, the conductive material may be aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the invention is not limited thereto. In some embodiments, the conductive material may be copper foil. For example, the copper foil may include brass, phosphor bronze, beryllium copper alloy, or oxygen-free copper, but the invention is not limited thereto.

[0027] In some embodiments, the base substrate 10 may further include a first via 103, which passes through the core layer 100 and electrically connects to components on both sides of the core layer 100 (e.g., the first basic circuit layer 101 and the second basic circuit layer 102). In some embodiments, the first via 103 may include a conductive material.

[0028] In some embodiments, the first base circuit layer 101, the second base circuit layer 102, and the first via 103 may be formed by photolithography, plating, other suitable processes, or combinations thereof, but the invention is not limited thereto. For example, photolithography may include photoresist application (e.g., spin-on coating, lamination), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. For example, plating may include electroplating, electroless plating, other suitable plating techniques, and / or combinations thereof.

[0029] like Figure 2AAs shown, a plurality of conductive thin films (not shown) are provided and patterned to form a plurality of circuit layers 11. Specifically, the circuit layers 11 are used to transmit signals or perform specific functions. In some embodiments, the conductive thin films may include metal films, such as copper foil, but the invention is not limited thereto. In some embodiments, the thickness of the metal film may be between 12 μm and 18 μm, but the invention is not limited thereto. For example, the thickness of the metal film may be 12 μm, 14 μm, 16 μm, 18 μm, or any value or range between the above values.

[0030] In some embodiments, the process of patterning the conductive thin film may include a laser etching process, such as a solid-state laser, but the invention is not limited thereto. Compared to using a conventional laser, using a solid-state laser to pattern the conductive thin film avoids the formation of craters during the breakdown of the conductive film. Therefore, the circuit layer produced by a solid-state laser can have a certain degree of high precision and high flatness.

[0031] In some embodiments, the circuit layer 11 formed by the above process may include at least two circuit layers corresponding to one side of the base substrate 10. For example, the circuit layer 11 may include a first circuit layer 111 and a second circuit layer 112 corresponding to the first base circuit layer 101, and these two circuit layers will be sequentially stacked on the first base circuit layer 101 in subsequent steps. In other words, compared with the prior art approach of "first setting a conductive film on the base substrate or the add-on structure, then forming the conductive film into a circuit layer by a solid-state laser, and repeating the above steps", the present invention first forms at least two conductive films into at least two circuit layers by a solid-state laser before setting the conductive film on the base substrate or the add-on structure, and then laminates at least two circuit layers onto one side of the base substrate 10 in a subsequent process.

[0032] In some embodiments, the circuit layer 11 formed by the above process may further include at least two circuit layers corresponding to the other side of the base substrate 10. For example, the circuit layer 11 may further include a third circuit layer 113 and a fourth circuit layer 114 corresponding to the second base circuit layer 102, and these two circuit layers will be sequentially stacked on the second base circuit layer 102 in subsequent steps.

[0033] In some embodiments, line layer 11 may also include more line layers as needed, for example Figure 2A The fifth line layer 115 and the sixth line layer 116 are shown. The fifth line layer 115 may correspond to the first basic line layer 101, and the sixth line layer 116 may correspond to the second basic line layer 102.

[0034] In some embodiments, the material, thickness, shape, density, and other specifications (or parameters) of each of the plurality of circuit layers 11 may be the same or different. For example, the first circuit layer 111 and the second circuit layer 112 may be made of the same material, but have different shapes of circuit patterns. Alternatively, the number of circuit layers corresponding to both sides of the base substrate 10 may also be different. For example, the number of circuit layers in the first base circuit layer 101 corresponding to the base substrate 10 may be greater than or less than the number of circuit layers in the second base circuit layer 102 corresponding to the base substrate 10. In other words, asymmetrical (e.g., different numbers) circuit layers may be formed on both sides of the base substrate 10.

[0035] In some embodiments, to facilitate the extraction or transfer of the patterned conductive film (i.e., circuit layer 11), the lines in the patterned conductive film (i.e., circuit layer 11) may be interconnected. For example... Figure 2B As shown, a top view of the first circuit layer 111 is used for illustration. In some embodiments, the first circuit layer 111 includes multiple first portions 111A and second portions 111B. The multiple first portions 111A are elongated lines, and the second portions 111B are rectangular loop lines, with each first portion 111A connected to a second portion 111B. In other words, all lines of the first circuit layer 111 are physically connected to the second portions 111B, facilitating the extraction or transfer of the entire first circuit layer 111 at once. Of course, Figure 2B The quantity, shape, density, or relative position of the first portion 111A and the second portion 111B shown are merely examples, and the invention is not limited thereto. In other embodiments, the second portion 111B may also be a circular loop, a triangular loop, a polygonal loop, a loop with disconnected ends, or a loop with other suitable shapes.

[0036] In some embodiments, the second circuit layer 112 includes a plurality of third portions (not shown) and fourth portions (not shown), with the fourth portions surrounding the third portions. Similarly, the third circuit layer 113 includes a plurality of fifth portions (not shown) and sixth portions (not shown), with the sixth portions surrounding the fifth portions. Similarly, the fourth circuit layer 114 includes a plurality of seventh portions (not shown) and eighth portions (not shown), with the eighth portions surrounding the seventh portions. The relationship between two portions in each circuit layer may be similar to or the same as the relationship between two portions in the first circuit layer 111, and therefore will not be described further.

[0037] In some embodiments, each of the circuit layers 11 described above may be supported by a plurality of partitions (not shown) to facilitate the transfer and stacking of these circuit layers onto the first base circuit layer 101 and / or the second base circuit layer 102. In some embodiments, the partitions may include mylar, other suitable materials, or combinations thereof, but the invention is not limited thereto.

[0038] like Figure 2A As shown, following the steps described above, a plurality of dielectric layers 12 are provided. Specifically, the dielectric layers 12 will form a build-up structure together with the circuit layers 11, and the dielectric layers 12 can be used to isolate the two circuit layers located on their upper and lower sides. In some embodiments, the dielectric layers 12 may include epoxy resin, polyimide, Ajinomoto build-up film (ABF), other suitable polymer materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the thickness of each of the dielectric layers 12 is at least 35 μm to effectively achieve electrical isolation. For example, the thickness of the dielectric layers 12 may be 35 μm, 40 μm, 45 μm, 50 μm, 100 μm, or any value or range between the above values.

[0039] In some embodiments, dielectric layer 12 may include at least two dielectric layers corresponding to one side of the base substrate 10. For example, dielectric layer 12 may include a first dielectric layer 121 and a second dielectric layer 122 corresponding to the first base circuit layer 101, and these two dielectric layers will be sequentially stacked on the first base circuit layer 101 in a subsequent step. Similarly, dielectric layer 12 may also include at least two dielectric layers corresponding to the other side of the base substrate 10. For example, dielectric layer 12 may also include a third dielectric layer 123 and a fourth dielectric layer 124 of the second base circuit layer 102, and these two circuit layers will be sequentially stacked on the second base circuit layer 102 in a subsequent step.

[0040] In some embodiments, dielectric layer 12 may also include more circuit layers as needed, for example Figure 2A The fifth dielectric layer 125 and the sixth dielectric layer 126 are shown. The fifth dielectric layer 125 may correspond to the first base circuit layer 101, and the sixth dielectric layer 126 may correspond to the second base circuit layer 102.

[0041] In some embodiments, the material, thickness, shape, and other specifications (or parameters) of each of the plurality of dielectric layers 12 may be the same or different. For example, the materials of the first dielectric layer 121 and the second dielectric layer 122 may be different. Alternatively, the number of dielectric layers corresponding to both sides of the base substrate 10 may also be different. For example, the number of dielectric layers corresponding to the first base circuit layer 101 of the base substrate 10 may be greater than or less than the number of dielectric layers corresponding to the second base circuit layer 102 of the base substrate 10. In other words, asymmetrical (e.g., different numbers) dielectric layers may be formed on both sides of the base substrate 10.

[0042] like Figure 3 As shown, following the above steps, at least two dielectric layers and at least two circuit layers are stacked on one side of the base substrate 10. For example, a first dielectric layer 121, a first circuit layer 111, a second dielectric layer 122, and a second circuit layer 112 can be sequentially stacked on the first base circuit layer 101. The first dielectric layer 121 and the first circuit layer 111 can together form a build-up structure, and the second dielectric layer 122 and the second circuit layer 112 can together form another build-up structure. In this invention, a build-up structure may include at least one dielectric layer and at least one circuit layer.

[0043] However, the present invention is not limited thereto. In some embodiments, at least two dielectric layers and at least two circuit layers may be stacked on each side of the base substrate 10 in the same step. For example, in addition to forming two sets of add-on structures on the first base circuit layer 101, a third dielectric layer 123, a third circuit layer 113, a fourth dielectric layer 124, and a fourth circuit layer 114 may be sequentially stacked on the second base circuit layer 102. The third dielectric layer 123 and the third circuit layer 113 may together form one set of add-on structures, and the fourth dielectric layer 124 and the fourth circuit layer 114 may together form another set of add-on structures.

[0044] Of course, the stacking methods or number of added layers described above are merely examples. For instance, more dielectric and circuit layers, such as a fifth dielectric layer 125 and a fifth circuit layer 115, can be stacked on the second circuit layer 112. Similarly, more dielectric and circuit layers, such as a sixth dielectric layer 126 and a sixth circuit layer 116, can be stacked on the fourth circuit layer 114 in the same step.

[0045] like Figure 4As shown, following the above steps, a lamination process is performed to fix the first dielectric layer 121, the first circuit layer 111, the second dielectric layer 122, and the second circuit layer 112 onto the first base circuit layer 101. In other words, the present invention significantly reduces the total time required for the layer-addition process by laminating at least two or more sets of add-on structures in a single step. Similarly, in the same lamination process, the third dielectric layer 123, the third circuit layer 113, the fourth dielectric layer 124, and the fourth circuit layer 114 can be fixedly attached to the second base circuit layer 102.

[0046] It is worth noting that the stacking method and number of stacked layers in the above steps are merely examples and are not intended to limit the present invention. For those skilled in the art, the number of dielectric and circuit layers that can be stacked and laminated in a single process depends on the material type, design requirements, process capabilities, or other possible factors. For example, in some embodiments, m dielectric layers and n circuit layers can be laminated onto one side of the base substrate 10 in a single step. For example, m can be a positive integer between 2 and 10, n can be a positive integer between 2 and 10, and m can be greater than, equal to, or less than n. In some embodiments, x dielectric layers and y circuit layers can be laminated simultaneously onto both sides of the base substrate 10 in a single step. For example, x can be a positive integer between 3 and 20, y can be a positive integer between 3 and 20, and x can be greater than, equal to, or less than y.

[0047] In some embodiments, the above-described lamination process can achieve a fixed adhesion effect through specific temperature and pressure. In other words, the method for manufacturing the circuit board structure of the present invention can omit bonding agents such as copper paste and copper glue. Of course, those skilled in the art can also add bonding agents to the circuit board structure as needed, and are not limited to the above.

[0048] In some embodiments, to enable the circuit pattern to perform a specific function, the circuit pattern in each circuit layer can be further adjusted by drilling. For example... Figure 5AAs shown, after the lamination process, a drilling process can optionally be performed to form a first blind via 104A on one side of the base substrate 10. The first blind via 104A can pass through the first dielectric layer 121, the first circuit layer 111, the second dielectric layer 122, the second circuit layer 112, and other layers located thereon (e.g., the fifth dielectric layer 125, the fifth circuit layer 115, etc.). In some embodiments, the drilling process can also form a second blind via 105A on one side of the base substrate 10. The second blind via 105A can pass through the third dielectric layer 123, the third circuit layer 113, the fourth dielectric layer 124, the fourth circuit layer 114, and other layers located thereon (e.g., the sixth dielectric layer 126, the sixth circuit layer 116, etc.). In some embodiments, the drilling process can also form a through-hole 106A. The through-hole 106A penetrates the entire circuit board structure.

[0049] like Figure 5B The diagram shows a top view of the first circuit layer 111. In some embodiments, a first blind via 104A can be used to disconnect the first portion 111A and the second portion 111B of the first circuit layer 111 from each other. Additionally, the first blind via 104A can also disconnect the third and fourth portions of the second circuit layer 112 from each other. Similarly, the second blind via 105A can disconnect the fifth and sixth portions of the third circuit layer 113 from each other, and / or the seventh and eighth portions of the fourth circuit layer 114 from each other. This allows for further adjustment of the circuit patterns in each circuit layer and enables these circuit patterns to have predetermined functions.

[0050] In some embodiments, the drilling process may include mechanical drilling, chemical drilling, laser drilling, other suitable drilling techniques, or combinations thereof, but the invention is not limited thereto. In some embodiments, the number, size, location, or other parameters of the formed first blind hole 104A, second blind hole 105A, and through hole 106A may be determined as needed. In some embodiments, the first blind hole 104A, second blind hole 105A, and through hole 106A may be formed simultaneously or sequentially in the same or different drilling processes.

[0051] In some embodiments, to enable electrical connection between circuit patterns of different circuit layers, vias can be further formed by providing conductive material in blind vias or through-holes. For example... Figure 6 As shown, after the drilling process, a plating process may optionally be performed to fill or cover these blind holes or vias with a conductive material. This can cause the first blind hole 104A to form a second via 104B, the second blind hole 105A to form a third via 105B, and / or the through hole 106A to form a fourth via 106B. In some embodiments, the conductive material may include aluminum (Al), copper (Cu), alloys thereof, or compounds thereof, but the invention is not limited thereto.

[0052] Through the above steps, a circuit board structure can be obtained. In practice, the circuit accuracy of the circuit board structure formed by the above steps can reach 75μm±20% (i.e., 75μm±15μm), which is sufficient for verification in the development of new processes or new materials.

[0053] In summary, this invention provides a method for manufacturing a circuit board structure. Specifically, this invention pre-fabricates multiple circuit layers and then laminates the overlapping circuit layers and dielectric layers onto a base substrate, thereby completing multiple add-on structures in one step. In this way, this invention achieves a circuit board structure manufacturing method with extremely low time consumption, significantly reducing the verification time in the development of new processes or materials. This, in turn, can greatly increase the efficiency of new process or material development.

[0054] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0055] [Symbol Explanation]

[0056] 10: Base substrate

[0057] 100: Core Layer

[0058] 101: First Basic Circuit Layer

[0059] 102: Second Basic Line Layer

[0060] 103: First guide hole

[0061] 104A: First blind hole

[0062] 104B: Second guide hole

[0063] 105A: Second blind hole

[0064] 105B: Third guide hole

[0065] 106A: Through hole

[0066] 106B: Fourth guide hole

[0067] 11: Line Layer

[0068] 111: First Line Layer

[0069] 112: Second Line Layer

[0070] 113: Third Line Layer

[0071] 114: Fourth Line Layer

[0072] 115: Fifth Line Layer

[0073] 116: Sixth Line Layer

[0074] 12: Dielectric layer

[0075] 121: First dielectric layer

[0076] 122: Second dielectric layer

[0077] 123: Third dielectric layer

[0078] 124: Fourth dielectric layer

[0079] 125: Fifth dielectric layer

[0080] 126: Sixth dielectric layer.

Claims

1. A method for manufacturing a circuit board structure, characterized in that, include: A base substrate is provided, wherein the base substrate includes: Core layer; and The first basic circuit layer is set on the core layer; Multiple conductive thin films are patterned to form multiple circuit layers, wherein the multiple circuit layers include a first circuit layer and a second circuit layer; A plurality of dielectric layers are provided, wherein the plurality of dielectric layers include a first dielectric layer and a second dielectric layer; The first dielectric layer, the first circuit layer, the second dielectric layer, and the second circuit layer are sequentially stacked on the first base circuit layer; and A lamination process is performed to fix the first dielectric layer, the first circuit layer, the second dielectric layer, and the second circuit layer onto the first base circuit layer.

2. The method for manufacturing the circuit board structure according to claim 1, wherein, After performing the pressing process, the process further includes: A drilling process is performed to make the first circuit layer include a first portion and a second portion that are disconnected from each other, and to make the second circuit layer include a third portion and a fourth portion that are disconnected from each other.

3. The method for manufacturing a circuit board structure according to claim 2, wherein the second part surrounds the first part, and the fourth part surrounds the third part.

4. The method for manufacturing a circuit board structure according to claim 1, wherein the base substrate further includes a second base circuit layer, and the second base circuit layer is disposed on the core layer relative to the first base circuit layer.

5. The method for manufacturing a circuit board structure according to claim 4, wherein the plurality of circuit layers include a third circuit layer and a fourth circuit layer, the plurality of dielectric layers further include a third dielectric layer and a fourth dielectric layer, and the method for manufacturing the circuit board structure further includes: The third dielectric layer, the third circuit layer, the fourth dielectric layer, and the fourth circuit layer are stacked sequentially on the second base circuit layer; as well as The lamination process is performed to fix the third dielectric layer, the third circuit layer, the fourth dielectric layer, and the fourth circuit layer onto the second base circuit layer.

6. The method for manufacturing the circuit board structure according to claim 5, wherein, After performing the pressing process, the process further includes: A drilling process is performed to make the third circuit layer include a fifth and a sixth portion that are disconnected from each other, and to make the fourth circuit layer include a seventh and an eighth portion that are disconnected from each other.

7. The method for manufacturing a circuit board structure according to claim 6, wherein the sixth part surrounds the fifth part, and the eighth part surrounds the seventh part.

8. The method for manufacturing a circuit board structure according to claim 1, wherein after patterning the plurality of conductive films, the plurality of circuit layers can be carried by a plurality of partitions to stack the plurality of circuit layers on the first base circuit layer.

9. The method for manufacturing a circuit board structure according to claim 1, wherein the process of patterning the plurality of conductive thin films includes a laser etching process.

10. The method for manufacturing a circuit board structure according to claim 9, wherein the laser etching process includes solid-state laser.

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