Semiconductor structure and electronic device

Abstract

The present disclosure relates particularly to a semiconductor structure and an electronic device, wherein the semiconductor structure comprises: a first transistor array comprising a plurality of row control lines, a plurality of column control lines, and a plurality of first transistors defined by the row control lines and the column control lines crossing and arranged in an array, wherein each first transistor is coupled to a corresponding row control line and a column control line; a capacitor array comprising a plurality of capacitors corresponding to the plurality of first transistors one by one and arranged in an array, wherein a second source-drain electrode of the first transistor is coupled to a first electrode of a corresponding capacitor; a second transistor array comprising a plurality of input lines, a plurality of output lines, and a plurality of second transistors defined by the input lines and the output lines crossing and arranged in an array, and the plurality of second transistors corresponding to the plurality of capacitors one by one, wherein a gate of each second transistor is coupled to a second electrode of a corresponding capacitor, and each second transistor is coupled to a corresponding input line and an output line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor design, and in particular to a semiconductor structure and electronic device. Background Technology

[0002] As semiconductor manufacturing processes approach their physical limits, the performance gains from Moore's Law are gradually diminishing, and the cost-effectiveness of miniaturizing traditional chip manufacturing processes is decreasing, further exacerbating the computing power supply dilemma. The rapid development of large model technology has further amplified this contradiction. The parameter scale of large language models, represented by GPT (GPT series models), has grown from billions to hundreds of billions, resulting in an exponential increase in the demand for storage capacity and bandwidth.

[0003] It is against this backdrop that in-memory computing technology has emerged and become widely used. The core logic of in-memory computing is very simple: embedding computing units into storage units allows data to be computed directly within the embedded storage array.

[0004] For Dynamic Random Access Memory (DRAM), the computing power supply method and structure of DRAM urgently need to be optimized. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and electronic device. By proposing a simple and easy-to-implement in-memory computing architecture, a computing array structure is added without significantly changing the current memory array structure, thereby improving in-memory computing efficiency while reducing production costs.

[0006] This disclosure provides a semiconductor structure, comprising: a first transistor array including multiple row control lines, multiple column control lines, and a plurality of first transistors arranged in an array and defined by the intersection of the row control lines and the column control lines, wherein the gate of each first transistor is coupled to the corresponding row control line, and the first source-drain of each first transistor is coupled to the corresponding column control line; a capacitor array including a plurality of capacitors arranged in an array corresponding to the plurality of first transistors, wherein the second source-drain of each first transistor is coupled to the first electrode of the corresponding capacitor; and a second transistor array including multiple input lines, multiple output lines, and a plurality of second transistors arranged in an array and defined by the intersection of the input lines and the output lines, wherein the plurality of second transistors correspond to the plurality of capacitors, wherein the gate of each second transistor is coupled to the second electrode of the corresponding capacitor, the first source-drain of each second transistor is coupled to the corresponding input line, and the second source-drain of each second transistor is coupled to the corresponding output line.

[0007] Optionally, the input line extends in the same direction as the column control line, and the output line extends in the same direction as the row control line.

[0008] Optionally, the input line extends in the same direction as the row control line, and the output line extends in the same direction as the column control line.

[0009] Optionally, the semiconductor structure includes a first device layer, a second device layer, and a third device layer stacked sequentially along a vertical direction; wherein, the first device layer is configured to house the first transistor in the first transistor array; the second device layer is configured to house the capacitor in the capacitor array; and the third device layer is configured to house the second transistor in the second transistor array; each capacitor, its corresponding first transistor, and its corresponding second transistor are arranged along the vertical direction.

[0010] Optionally, the second transistor is configured as a channel-all-around structure with a horizontal channel, and the first transistor is configured as a gate-all-around structure with a vertical channel.

[0011] Optionally, the gate of the second transistor extends in the vertical direction and is electrically connected to the second electrode of the corresponding capacitor; the second source and drain of the first transistor extend in the vertical direction and are electrically connected to the first electrode of the corresponding capacitor.

[0012] Optionally, the third device layer includes a first metal layer, a second metal layer, and a semiconductor layer; the first metal layer is configured to provide the input line, which extends along a first direction and is spaced apart in a second direction, the first direction being perpendicular to the second direction; the second metal layer is configured to provide the output line, which extends along the second direction and is spaced apart in the first direction; the semiconductor layer is configured to provide a first source / drain, a second source / drain, and a channel region between the first and second source / drains of the second transistor, wherein the connection direction between the first and second source / drains of the second transistor is a third direction, which intersects both the first and second directions; the gate of the second transistor extends along a direction perpendicular to the semiconductor layer and at least penetrates the semiconductor layer; the intersection of the third direction and the first direction is used to provide a first interconnect structure, which electrically connects the first source / drain and the input line; the intersection of the third direction and the second direction is used to provide a second interconnect structure, which electrically connects the second source / drain and the output line.

[0013] Optionally, the first electrodes of the plurality of capacitors are independent of each other, and the second electrodes of the plurality of capacitors are independent of each other.

[0014] Optionally, the semiconductor structure further includes: an array of regulating resistors, comprising a plurality of regulating resistors corresponding one-to-one with the second transistor and arranged in an array; each of the regulating resistors is coupled to the corresponding second transistor.

[0015] Optionally, the first source and drain of each of the second transistors are coupled to the corresponding input line via a corresponding adjustment resistor.

[0016] This disclosure also provides an electronic device, an in-memory computing device, the in-memory computing device including the above-described semiconductor structure.

[0017] The technical solution provided in this disclosure has at least the following advantages: By adding a corresponding in-memory computing array to the memory array to form an in-memory computing structure, and by reusing DRAM technology and adding a computing array structure without changing the current memory array structure, a new low-cost and high-efficiency in-memory computing device can be launched, which improves in-memory computing efficiency while reducing production costs. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of the first transistor array provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram showing the connection relationship between the first transistor and the capacitors in the capacitor array provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the structure of the second transistor array provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram showing the connection relationship between the second transistor and the capacitors in the capacitor array provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a second transistor array with an adjustable resistor array provided in an embodiment of this disclosure; Figure 6This is a schematic diagram of the stacked first device layer, second device layer and third device layer in the semiconductor structure provided in the embodiments of this disclosure; Figure 7 This is a schematic diagram of the specific structure of the first semiconductor structure provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of a second semiconductor structure provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of a third semiconductor structure provided in an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the fourth semiconductor structure provided in the embodiments of this disclosure; Figure 11 This is a schematic cross-sectional view of the third device layer provided in an embodiment of the present disclosure; Figure 12 This is a top view of the third device layer provided in an embodiment of the present disclosure; Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached figures: A first transistor array 100, row control line 101, column control line 102, first transistor 103, capacitor 104, first electrode A, second electrode B, a second transistor array 200, input line 201, output line 202, second transistor 203, regulating resistor 204, semiconductor structure 300, first device layer 301, second device layer 302, third device layer 303, second terminal 401, second dielectric layer 402, second electrode 403, first terminal 430, first dielectric layer 420, first electrode 410, semiconductor layer 500, first metal layer 510, second metal layer 520, first source / drain of the second transistor 501, second source / drain of the second transistor 502, channel region 503, gate of the second transistor 504, processing device 801, storage device 802, and in-memory computing device 803. Detailed Implementation

[0021] As can be seen from the background technology, the computing power supply method and structure of DRAM urgently need to be optimized.

[0022] For example, DRAM computing power can be supplied in several ways: the DRAM array stores weights, which are then read out and processed by the CPU (Central Processing Unit), or a new computing architecture needs to be built to achieve in-memory computing functionality. The former has lower computing efficiency, while the latter has higher development costs.

[0023] To address or improve the aforementioned technical problems, this disclosure provides a semiconductor structure and proposes a simple and easy-to-implement in-memory computing architecture. It adds a computing array structure without significantly altering the existing memory array structure, thereby improving in-memory computing efficiency while reducing production costs. The semiconductor structure provided in this disclosure includes: a first transistor array comprising multiple row control lines, multiple column control lines, and multiple first transistors arranged in an array, defined by the intersection of the row and column control lines, wherein the gate of each first transistor is coupled to the corresponding row control line, and the first source-drain of each first transistor is coupled to the corresponding column control line; a capacitor array comprising multiple capacitors arranged in an array, each corresponding to one of the multiple first transistors, wherein the second source-drain of each first transistor is coupled to the first electrode of the corresponding capacitor; and a second transistor array comprising multiple input lines, multiple output lines, and multiple second transistors arranged in an array, defined by the intersection of the input and output lines, wherein each second transistor corresponds to one of the multiple capacitors, wherein the gate of each second transistor is coupled to the second electrode of the corresponding capacitor, the first source-drain of each second transistor is coupled to the corresponding input line, and the second source-drain of each second transistor is coupled to the corresponding output line.

[0024] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may, depending on the context in which the term is used, encompass both above and below orientations, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0028] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0029] In the description of embodiments of this disclosure, the terms "about," "approximately," "roughly," or "about" for a numerical value referring to a specific parameter include the numerical value, and those skilled in the art will understand that the deviation from the numerical value is within acceptable tolerances of the specific parameter. For example, "about" or "about" for a numerical value may include additional numerical values ​​that are in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0030] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. Furthermore, when a component is described as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a portion of the edge of the entire surface.

[0031] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when a component is described as being on the surface of another component, or a component is "directly" on another component, or another component is formed or disposed on the surface of a component, it indicates that there is no intermediate component between the two components. For simplicity and clarity, various components may be drawn at any scale. In the drawings, some components may be omitted for simplicity.

[0032] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. The aforementioned component may refer to a layer, film, region, portion, structure, or plate, etc.

[0033] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0034] Figure 1 This is a schematic diagram of the structure of the first transistor array provided in an embodiment of this disclosure. Figure 2 This diagram illustrates the connection relationship between the first transistor and the capacitors in the capacitor array, as provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of the structure of the second transistor array provided in an embodiment of this disclosure. Figure 4 This is a schematic diagram showing the connection relationship between the second transistor and the capacitors in the capacitor array provided in an embodiment of this disclosure.

[0035] refer to Figures 1-4The semiconductor structure includes: a first transistor array 100, a capacitor array (not shown), and a second transistor array 200.

[0036] refer to Figure 1 For the first transistor array 100, the first transistor array 100 includes: multiple row control lines 101, multiple column control lines 102, and multiple first transistors 103 defined by the intersection of the row control lines 101 and the column control lines 102 and arranged in an array. It should be noted that, in Figure 1 In the example, row control line 101 is indicated by a solid line and column control line 102 by a dashed line, which is only used by those skilled in the art to distinguish between row control line 101 and column control line 102, and does not constitute a limitation on whether row control line 101 or column control line 102 is solid or dashed; in addition, Figure 1 In the example, the number of row control lines 101 and column control lines 102 does not constitute a limitation on the embodiments of this disclosure.

[0037] For example, row control line 101 is a word line (WL) in memory, column control line 102 is a bit line (BL) in memory, and first transistor 103 is an access transistor in memory.

[0038] For the connection relationship between row control line 101, column control line 102 and first transistor 103, refer to Figure 1 and Figure 2 The gate of each first transistor 103 is coupled to the corresponding row control line 101, and the first source-drain of each first transistor 103 is coupled to the corresponding column control line 102. In addition, the capacitor array includes multiple capacitors 104 corresponding to the first transistors 103 and arranged in an array, and the second source-drain of the first transistor 103 is coupled to the first electrode A of the corresponding capacitor 104.

[0039] The capacitor array and the first transistor array 100 constitute the memory array in the memory.

[0040] For a storage array, when the corresponding row control line 101 and column control line 102 are activated, the row control line 101 will turn on the corresponding first transistor 103, and the capacitor 104 corresponding to the first transistor 103 will interact with the column control line 102 to realize data access.

[0041] For example, when data is transferred from column control line 102 to capacitor 104, it is a data storage process of the memory; when data is transferred from capacitor 104 to column control line 102, it is a data readout process of the memory.

[0042] It should be noted that, in the above description, one of the "first source-drain" and the "second source-drain" of the first transistor 103 corresponds to the source of the first transistor 103, and the other corresponds to the drain of the first transistor 103.

[0043] refer to Figure 3 For the second transistor array 200, the second transistor array 200 includes: multiple input lines 201, multiple output lines 202, and multiple second transistors 203 defined by the intersection of the input lines 201 and the output lines 202 and arranged in an array. It should be noted that in... Figure 3 In the example, the input line 201 is indicated by a dashed line and the output line 202 by a solid line, which is only used by those skilled in the art to distinguish between the input line 201 and the output line 202, and does not constitute a limitation on whether the input line 201 and the output line 202 are dashed or solid; in addition, Figure 3 In this example, the number of input lines 201 and output lines 202 does not constitute a limitation on the embodiments of this disclosure.

[0044] For the connection relationship of input line 201, output line 202, second transistor 203 and capacitor 104, refer to... Figures 2-4 Each of the multiple second transistors 203 corresponds to a multiple capacitors 104. The gate of each second transistor 203 is coupled to the second electrode B of the corresponding capacitor 104. The first source and drain of each second transistor 203 are coupled to the corresponding input line 201. The second source and drain of each second transistor 203 are coupled to the corresponding output line 202.

[0045] It should be noted that, in the above description, one of the "first source-drain" and the "second source-drain" of the second transistor 203 corresponds to the source of the second transistor 203, and the other corresponds to the drain of the second transistor 203.

[0046] The capacitor array and the second transistor array 200 constitute an in-memory array in the memory. The second transistor array 200 is configured to perform binary multiply-accumulate operations based on the data stored in the capacitor array.

[0047] For the memory array, after the memory completes data storage by storing data into the capacitor 104, the amount of charge stored in the capacitor 104 determines whether the second transistor 203 is turned on or off. When the second transistor 203 is turned on, the input voltage of the input line 201 will generate an output sub-current on the corresponding output line 202 through the second transistor 203. When the second transistor 203 is turned off, the input voltage of the input line 201 will not generate the corresponding output sub-current through the second transistor 203.

[0048] In one example, suppose capacitor 104 stores data at a positive voltage, and the second transistor 203 is configured as an NMOS. For instance, when the first transistor array 100 controls the storage of data "1" into the corresponding capacitor 104, the first electrode A of capacitor 104 accumulates positive charge and presents a positive potential. Correspondingly, the second electrode B of capacitor 104 accumulates negative charge and presents a negative potential, causing the gate of the second transistor 203, which is electrically connected to the second electrode B, to accumulate positive charge and present a positive potential. At this time, the second transistor 203, as an NMOS, is turned on, and the input voltage of input line 201 will generate an output sub-current on the corresponding output line 202 through the second transistor 203. Similarly, when the first transistor array 100 controls the storage of data "0" into the corresponding capacitor 104, the gate of the second transistor 203, which is electrically connected to the second electrode B, will accumulate negative charge and present a negative potential. The second transistor 203, as an NMOS, is turned off, and the input voltage of input line 201 will not generate the corresponding output sub-current through the second transistor 203.

[0049] In another example, capacitor 104 can also store data under a negative voltage, in which case the second transistor 203 is configured as a PMOS. For example, when the first transistor array 100 controls the storage of data "1" in the corresponding capacitor 104, the first electrode A of capacitor 104 accumulates negative charge and presents a negative potential. Correspondingly, the second electrode B of capacitor 104 accumulates positive charge and presents a positive potential, causing the gate of the second transistor 203, which is electrically connected to the second electrode B, to accumulate negative charge and present a negative potential. At this time, the second transistor 203, as a PMOS, is turned on, and the input voltage of input line 201 will generate an output sub-current on the corresponding output line 202 through the second transistor 203. Similarly, when the first transistor array 100 controls the storage of data "0" in the corresponding capacitor 104, the gate of the second transistor 203, which is electrically connected to the second electrode B, will accumulate positive charge and present a positive potential. The second transistor 203, as a PMOS, is turned off, and the input voltage of input line 201 will not generate the corresponding output sub-current through the second transistor 203.

[0050] The output sub-currents of all the second transistors 203 electrically connected to the output line 202 are summed and output as the output current of the output line 202. The output currents corresponding to multiple output lines 202 can be converted from analog to digital to obtain the matrix operation result of the memory array.

[0051] In some application scenarios, the second transistor 203 in the second transistor array 200 is turned on according to the corresponding capacitor 104. The input voltage corresponding to the input line 201 is output as a series of potentials (output current of the output line 202) after passing through the corresponding second transistor 203, which is used to complete the matrix operation required by AI (Artificial Intelligence).

[0052] The semiconductor structure provided in this disclosure sets up a corresponding in-memory computing array on the basis of the memory's storage array to form an in-memory computing integrated structure. Without changing the current storage array structure, it reuses DRAM technology and adds a computing array structure to introduce a new low-cost and high-efficiency in-memory computing integrated device, which improves in-memory computing efficiency while reducing production costs.

[0053] In one example, see reference Figure 3 The second transistor array 200 includes n input lines 201 and m output lines 202; the input voltages of the n input lines 201 are V1 to Vn, and the output currents of the m output lines 202 are I1 to Im, where m and n are any integers greater than or equal to 2.

[0054] In some embodiments, a plurality of second transistors 203 arranged along the extension direction of input line 201 are coupled to the same input line 201. The input line 201 is configured to receive and provide the same input voltage to the coupled plurality of second transistors 203. A plurality of second transistors 203 arranged along the extension direction of output line 202 are coupled to the same output line 202. The output line 202 is configured to receive the output sub-current generated by the coupled plurality of second transistors 203 according to the corresponding input voltage, and form and output the output current corresponding to the output line 202.

[0055] In one example, multiple input lines 201 receive the same input voltage. For instance, the input voltages V1 to Vn can be set to the same voltage value. In this case, the output currents I1 to Im are related to the number of corresponding conducting second transistors 203 on the output line 202. Assuming that the output sub-current of each second transistor 203 under the same input voltage is I, and the number of conducting second transistors 203 on the output line 202 is i, then the output current of the output line 202 is i × I (multiplied by the two). The analog-to-digital converter connected to the output line 202 can convert the output decimal "i" into binary data, where i is any integer.

[0056] In this example, computation is transferred to a second transistor array electrically connected to the DRAM array, which greatly improves computational efficiency. Moreover, information storage and retrieval are separated, and in extreme cases, they may be performed simultaneously.

[0057] refer to Figure 1 and Figure 3 It should be noted that, in Figure 1 and Figure 3In the example, the horizontal extension of row control line 101 and output line 202 does not indicate that their extension directions are the same; similarly, the vertical extension of column control line 102 and input line 201 does not indicate that their extension directions are the same. In some embodiments, the extension direction of input line 201 is the same as that of column control line 102, and the extension direction of output line 202 is the same as that of row control line 101. In this example, input line 201 corresponds to the bit line of memory, and output line 202 corresponds to the word line of memory. In some embodiments, the extension direction of input line 201 is the same as that of row control line 101, and the extension direction of output line 202 is the same as that of column control line 102. In this example, input line 201 corresponds to the word line of memory, and output line 202 corresponds to the bit line of memory.

[0058] Figure 5 This is a schematic diagram of the structure of a second transistor array with an adjustable resistor array provided in an embodiment of this disclosure.

[0059] refer to Figure 5 In some embodiments, the semiconductor structure further includes an array of regulating resistors, comprising a plurality of regulating resistors 204 that correspond one-to-one with the second transistor 203 and are arranged in an array, each regulating resistor 204 being coupled to the corresponding second transistor 203.

[0060] When the second transistor 203 is turned on, it can be considered as a resistor connected in series between the input line 201 and the output line 202. Due to differences in semiconductor fabrication processes, the equivalent resistance of the second transistors 203 arranged in the same column may be different after being turned on. This causes the output current of the second transistor array 200 to differ in different rows based on the same input voltage in the same column, which may lead to subsequent calculation errors.

[0061] For example, the adjusting resistor 204 is configured to adjust the equivalent resistance of the branch where the corresponding second transistor 203 is located, so as to keep the equivalent resistance of the branch where the multiple second transistors 203 coupled to the same input line 201 are located the same.

[0062] By configuring a corresponding regulating resistor 204 for each second transistor 203, the equivalent resistance of the branch where the second transistor 203 is located is changed by regulating the resistor 204, so that the equivalent resistance of the branch where the second transistor 203 in the same column is turned on is the same, thereby ensuring the consistency and accuracy of the output current output by the second transistor array 200.

[0063] The adjusting resistor 204 can be connected in series with the source-drain path of the second transistor 203 to change the equivalent resistance of the branch containing the second transistor 203. In this case, the equivalent resistance of the branch containing the second transistor 203 is the sum of the equivalent resistance of the second transistor 203 and the resistance of the adjusting resistor 204. By configuring the resistance difference of the adjusting resistor 204, the difference in equivalent resistance between the second transistors 203 is compensated, thereby ensuring the consistency of the equivalent resistance of the branch containing the second transistor 203.

[0064] In some embodiments, reference Figure 5 Each second transistor 203 has its first source and drain coupled to its corresponding input line 201 via a corresponding regulating resistor 204. For example, the first terminal of the regulating resistor 204 is coupled to the corresponding input line 201, and the second terminal of the regulating resistor 204 is coupled to the first source and drain of the corresponding second transistor 203. With this configuration, when the second transistor 203 is turned off, the regulating resistor 204 will not be connected to the output line 202, thus not affecting the magnitude of the output current on the output line 202, further ensuring the accuracy of the output current output by the second transistor array 200.

[0065] Figure 6 This is a schematic diagram of the stacked first device layer, second device layer, and third device layer in the semiconductor structure provided in the embodiments of this disclosure.

[0066] For the semiconductor structure 300 provided in the embodiments of this disclosure, refer to... Figure 6 In some embodiments, the semiconductor structure 300 includes a first device layer 301, a second device layer 302, and a third device layer 303 stacked sequentially along a vertical direction Z. The first device layer 301 is configured to house a first transistor 103 in a first transistor array; the second device layer 302 is configured to house a capacitor 104 in a capacitor array; and the third device layer 303 is configured to house a second transistor 203 in a second transistor array.

[0067] This configuration allows for direct bonding or formation of a second transistor array on the memory array, resulting in a simple and easy-to-implement structure that reduces production costs. Furthermore, the memory array retains its original read / write functionality, with the addition of a second transistor array forming an in-memory computing structure. By storing the computational weights in the capacitors of the memory array and controlling the switching on and off of the second transistors connected to it, the computational function is completed based on the multi-terminal input voltage, thus improving the memory's computational efficiency.

[0068] It should be noted that, Figure 6The example is only used to illustrate the positional relationship and effect between the first device layer 301, the second device layer 302 and the third device layer 303, and does not constitute a structural limitation on the first transistor 103 in the first device layer 301, the capacitor 104 in the second device layer 302 and the second transistor 203 in the third device layer 303.

[0069] In other embodiments, the positions of the first transistor array and the second transistor array can be replaced. In this case, the first device layer is configured to house the second transistor in the second transistor array; the second device layer is configured to house the capacitor in the capacitor array; and the third device layer is configured to house the first transistor in the first transistor array.

[0070] In some other embodiments, a capacitor array can also be provided through a first device layer or a third device layer. In this case, a longer interconnect structure is required to couple the capacitors to the corresponding first and second transistors.

[0071] Since the length of the conductive path in the interconnect structure determines the resistance of the wires between the capacitor, the first transistor, and the second transistor, to reduce the resistance of the wires between these components and thus optimize memory performance, the length of the conductive path in the interconnect structure needs to be minimized. Therefore, referring to... Figure 6 In some embodiments, each capacitor 104, its corresponding first transistor 103, and its corresponding second transistor 203 are arranged along the vertical direction Z. By vertically arranging the capacitor 104, the first transistor 103, and the second transistor 203, the spacing between the capacitor 104, the first transistor 103, and the second transistor 203 is greatly reduced, thereby reducing the conductive path length of the interconnect structure.

[0072] Figure 7 This is a schematic diagram of the specific structure of the first semiconductor structure provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of a second semiconductor structure provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of a third semiconductor structure provided in an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the fourth semiconductor structure provided in the embodiments of this disclosure.

[0073] To further reduce the conductive path length of the interconnect structure, thereby optimizing memory performance. (Reference) Figures 7-10In some embodiments, the first transistor 103 is configured as a gate-all-around (GAA) structure with a vertical channel, and the second transistor 203 is configured as a gate-all-around (CAA) structure with a horizontal channel. This configuration allows for a reduction in the distance between the second source / drain of the first transistor 103 and the first electrode A of the capacitor 104 via the second source / drain located at the top of the vertical channel. Similarly, the distance between the gate of the second transistor 203 and the second electrode B of the capacitor 104 can be reduced via the gate of the second transistor 203 arranged horizontally around the channel, thereby further reducing the conductive path length of the interconnect structure.

[0074] In a specific implementation, continue to refer to Figures 7-10 The gate of the second transistor 203 extends in the vertical direction Z and is electrically connected to the second electrode B of the corresponding capacitor 104; the second source and drain of the first transistor 103 extends in the vertical direction Z and is electrically connected to the first electrode A of the corresponding capacitor 104.

[0075] It should be noted that the term "electrical connection" mentioned in the above description refers to: a connection and conductive transmission between corresponding structures through direct contact, or an indirect connection and conductive transmission between corresponding structures via other conductive structures. For example, the gate of the second transistor 203 is electrically connected to the second electrode B of the capacitor 104. This connection can be a direct contact connection between the gate of the second transistor 203 and the second electrode B of the capacitor 104, or an indirect connection achieved through an interconnect structure. Similarly, the second source / drain of the first transistor 103 is electrically connected to the first electrode A of the capacitor 104. This connection can be a direct contact connection between the second source / drain of the first transistor 103 and the first electrode A of the capacitor 104, or an indirect connection achieved through an interconnect structure.

[0076] It should be noted that in a conventional DRAM structure, the capacitors in the memory array have a single interconnected and grounded electrode. However, in this embodiment, the first electrodes A of the multiple capacitors 104 are independent of each other, and the second electrodes B of the multiple capacitors 104 are also independent of each other. For each capacitor 104 in the capacitor array, since the second transistor 203 loads the capacitor 104 and conducts, matrix operations are performed based on the second transistor array; therefore, each capacitor 104 in the capacitor array is independent of each other.

[0077] For the multiple capacitors 104 in the capacitor array, the capacitors 104 may adopt the same structural configuration or different structural configurations, and the embodiments disclosed herein do not limit this.

[0078] In some embodiments, the capacitor 104 may be configured as an up-and-down structure, a left-and-right structure, a side-enclosed structure, a semi-enclosed structure, etc.

[0079] For capacitor 104 with an up-and-down structure, refer to... Figure 10 In the case of "upper and lower", the first electrode A and the second electrode B of capacitor 104 are arranged along the vertical direction Z. In this case, the horizontal dimensions of the first electrode A and the second electrode B determine the capacitance value of capacitor 104.

[0080] For capacitor 104 with a left-right structure, refer to Figure 9 In a capacitor 104 with a left-right structure, the first electrode A and the second electrode B are arranged in any direction within a plane perpendicular to the vertical direction Z. In this case, the height of the first electrode A and the second electrode B determines the capacitance value of the capacitor 104.

[0081] For capacitor 104 with a semi-enclosed structure, refer to Figure 7 and Figure 8 The semi-enclosed structure refers to the fact that one electrode of the capacitor 104 surrounds the other electrode from the side and the front / back, thereby increasing the plate area of ​​the capacitor 104.

[0082] In one example, refer to Figure 7 The capacitor 104 includes: a second electrode post 401 serving as a second electrode plate B; a second dielectric layer 402 surrounding the side of the second electrode post 401 and covering the bottom surface of the second electrode post 401; and a second electrode plate 403 surrounding the side of the second dielectric layer 402 and covering the bottom surface of the second dielectric layer 402, serving as a first electrode plate A.

[0083] In one example, refer to Figure 8 The capacitor 104 includes: a first electrode post 430 serving as the first electrode plate A; a first dielectric layer 420 surrounding the side of the first electrode post 430 and covering the top surface of the first electrode post 430; and a first electrode plate 410 surrounding the side of the first dielectric layer 420 and covering the top surface of the first dielectric layer 420, serving as the second electrode plate B.

[0084] For a side-surrounded capacitor 104, it means that one electrode of the capacitor 104 surrounds the other electrode from the side, which will not be described in detail in the embodiments of this disclosure.

[0085] Figure 11 This is a schematic cross-sectional view of the third device layer provided in an embodiment of this disclosure. Figure 12 This is a top view of the third device layer provided in an embodiment of this disclosure.

[0086] refer to Figure 11 and Figure 12In some embodiments, the third device layer includes a first metal layer 510, a second metal layer 520, and a semiconductor layer 500. The first metal layer 510 is configured to provide an input line 201 extending along a first direction X and spaced apart along a second direction Y, wherein the first direction X is perpendicular to the second direction. The second metal layer 520 is configured to provide an output line 202 extending along the second direction Y and spaced apart along the first direction X. The semiconductor layer 500 is configured to provide a first source / drain 501, a second source / drain 502, and a channel region 503 located between the first source / drain 501 and the second source / drain 502 of the second transistor. The connection direction between the first source / drain 501 and the second source / drain 502 of the second transistor is a third direction. The gate 504 of the second transistor is disposed around the channel region 503, and the third direction intersects both the first direction X and the second direction Y.

[0087] With this configuration, on the top view of the third device layer, the gate 504 of the second transistor can still be exposed after the input line 201 is set in the first metal layer 510 and the output line 202 is set in the second metal layer 520. The subsequent gate interconnection of the second transistor is not affected, thus optimizing the memory wiring.

[0088] In some embodiments, the gate 504 of the second transistor extends along a direction perpendicular to the semiconductor layer 500 and at least penetrates the semiconductor layer 500; the intersection of the third direction and the first direction X is used to set a first interconnect structure, the first interconnect structure electrically connecting the first source / drain 501 and the input line 201; the intersection of the third direction and the second direction Y is used to set a second interconnect structure, the second interconnect structure electrically connecting the second source / drain 502 and the output line 202.

[0089] In summary, the semiconductor structure provided in this disclosure provides a new low-cost and high-efficiency in-memory computing device by setting up a corresponding in-memory computing array on the basis of the memory's storage array to form an in-memory computing integrated structure. Without changing the current storage array structure, DRAM technology is reused to add a computing array structure, thereby improving in-memory computing efficiency while reducing production costs.

[0090] Accordingly, this disclosure also provides an electronic device including a memory computing device, which includes the semiconductor structure provided in the foregoing embodiments. Therefore, the content disclosed in the foregoing embodiments is also applicable to the embodiments of the following electronic devices.

[0091] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0092] In some embodiments, the electronic device includes a processing device 801 and a memory computing device 803 electrically connected to the processing device 801.

[0093] The processing device 801 described above may refer to one or more processors. For example, the processing device 801 may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or a neural network processor). When the processing device 801 includes multiple processors, these processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0094] Schematic, the processing device 801 may be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0095] The processing device 801 may integrate one or a combination of several of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem.

[0096] In some embodiments, the electronic device further includes a storage device 802, which is electrically connected to a processing device 801 and a storage-computing device 803.

[0097] The processing device 801 can send commands and / or addresses to the storage device 802, and the processing device 801 can also send data to the storage device 802 or receive data from the storage device 802; the storage device 802 can also transmit the data it stores, perform calculations through the second transistor array in the in-memory computing device 803, and thus output the corresponding matrix operation results.

[0098] In some embodiments, storage device 802 may be a storage device including volatile memory cells. For example, storage device 802 may include various dynamic random access memories (DRAMs), such as Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or Low Power Double Data Rate (LPDDR) SDRAM.

[0099] In some embodiments, storage device 802 may be a stacked storage device with stacked DRAM dies, such as a high-bandwidth memory. Storage device 802 may also be a storage module, such as a dual-inline-memory module (DIMM) or a single-inline-memory module (SIMM).

[0100] In other embodiments, the storage device 802 includes, in addition to volatile memory cells, non-volatile memory cells such as SRAM, NAND flash memory, NOR flash memory, RRAM, FRAM, PRAM, TRAM, or MRAM.

[0101] Electronic devices can include one or more of the following: smartphones, personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable media players (PMPs), mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices can be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices can be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted displays (HMDs).

[0102] In some embodiments, the electronic device can also be used in large servers, such as data centers or AI computers.

[0103] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The first transistor array includes multiple row control lines, multiple column control lines, and multiple first transistors defined by the intersection of the row control lines and the column control lines and arranged in an array, wherein the gate of each first transistor is coupled to the corresponding row control line, and the first source and drain of each first transistor are coupled to the corresponding column control line. A capacitor array includes multiple capacitors that correspond one-to-one with the plurality of first transistors and are arranged in an array, wherein the second source and drain of the first transistors are coupled to the first electrode of the corresponding capacitor. The second transistor array includes multiple input lines, multiple output lines, and multiple second transistors arranged in an array defined by the intersection of the input lines and the output lines. Each of the multiple second transistors corresponds to one of the multiple capacitors. The gate of each second transistor is coupled to the second electrode of the corresponding capacitor, the first source and drain of each second transistor are coupled to the corresponding input line, and the second source and drain of each second transistor are coupled to the corresponding output line.

2. The semiconductor structure according to claim 1, characterized in that, The input line extends in the same direction as the column control line, and the output line extends in the same direction as the row control line.

3. The semiconductor structure according to claim 1, characterized in that, The input line extends in the same direction as the row control line, and the output line extends in the same direction as the column control line.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a first device layer, a second device layer, and a third device layer stacked sequentially along a vertical direction; Wherein, the first device layer is configured to house the first transistor in the first transistor array; the second device layer is configured to house the capacitor in the capacitor array; and the third device layer is configured to house the second transistor in the second transistor array. Each of the capacitors, the corresponding first transistor, and the corresponding second transistor are arranged along the vertical direction.

5. The semiconductor structure according to claim 4, characterized in that, The second transistor is configured as a channel-all-around structure with a horizontal channel, and the first transistor is configured as a gate-all-around structure with a vertical channel.

6. The semiconductor structure according to claim 5, characterized in that, The gate of the second transistor extends in the vertical direction and is electrically connected to the second electrode of the corresponding capacitor; the second source and drain of the first transistor extend in the vertical direction and are electrically connected to the first electrode of the corresponding capacitor.

7. The semiconductor structure according to claim 5, characterized in that, The third device layer includes a first metal layer, a second metal layer, and a semiconductor layer; The first metal layer is configured to provide the input lines, which extend along a first direction and are spaced apart in a second direction, wherein the first direction is perpendicular to the second direction; The second metal layer is configured to provide the output lines, which extend along the second direction and are spaced apart in the first direction; The semiconductor layer is configured to provide a first source-drain, a second source-drain, and a channel region between the first source-drain and the second source-drain of the second transistor, wherein the connection direction between the first source-drain and the second source-drain of the second transistor is a third direction, which intersects both the first direction and the second direction. The gate of the second transistor extends in a direction perpendicular to the semiconductor layer and penetrates at least through the semiconductor layer; The intersection of the third direction and the first direction is used to set the first interconnect structure, which is electrically connected to the first source and drain and the input line. The intersection of the third direction and the second direction is used to set up a second interconnect structure, which electrically connects the second source / drain and the output line.

8. The semiconductor structure according to claim 1, characterized in that, The first electrodes of the plurality of capacitors are independent of each other, and the second electrodes of the plurality of capacitors are independent of each other.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: an array of regulating resistors, comprising a plurality of regulating resistors that correspond one-to-one with the second transistor and are arranged in an array; each of the regulating resistors is coupled to the corresponding second transistor.

10. The semiconductor structure according to claim 9, characterized in that, The first source and drain of each of the second transistors are coupled to the corresponding input line via a corresponding adjustment resistor.

11. An electronic device, characterized in that, The electronic device includes: an in-memory computing device, wherein the in-memory computing device includes the semiconductor structure according to any one of claims 1 to 10.

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