Semiconductor device

Abstract

Semiconductor devices are provided. The semiconductor devices include a stack structure including interlayer insulating layers and gate electrodes stacked along a first direction; an upper interconnection structure located below the stack structure; an upper bonding structure connected to the upper interconnection structure and bonded to the lower bonding structure; a channel structure; an etch stop structure located on the stack structure, the etch stop structure extending along a second direction perpendicular to the first direction within the first region and spaced apart along a third direction perpendicular to the first and second directions; a common source conductive layer located on the stack structure between the etch stop structures; and a buffer layer located on the common source conductive layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and data storage systems that include semiconductor devices. Background Technology

[0002] Semiconductor devices can be used to store large amounts of data in data storage systems. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0003] One or more example embodiments provide a semiconductor device with improved miniaturization and reliability.

[0004] One or more example embodiments also provide a data storage system including semiconductor devices with improved miniaturization and reliability.

[0005] According to one aspect of an example embodiment, a semiconductor device includes: a first semiconductor structure, the first semiconductor structure including a first substrate, circuit elements located on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure; and a second semiconductor structure located on the first semiconductor structure. The second semiconductor structure includes: a stacked structure comprising an interlayer insulating layer and a gate electrode stacked along a first direction and located in a first region and a second region; an upper interconnect structure located below the stacked structure; an upper bonding structure connected to the upper interconnect structure and bonded to the lower bonding structure; a channel structure comprising a first portion penetrating the stacked structure along the first direction and a second portion extending upward from the first portion and located in the first region; an etch stop structure located on the stacked structure, extending in the first region along a second direction perpendicular to the first direction and spaced along a third direction perpendicular to the first and second directions; a common source conductive layer located in the first region between the etch stop structures on the stacked structure and connected to the second portion of the channel structure; and a buffer layer located on the common source conductive layer.

[0006] According to another aspect of an example embodiment, a semiconductor device includes: a stacked structure including an interlayer insulating layer and a gate electrode stacked along a first direction and located in a first region and a second region; a separating region penetrating the stacked structure along the first direction in the first region and the second region, the separating region extending along a second direction perpendicular to the first direction and spaced apart along a third direction perpendicular to the first and second directions; a channel structure penetrating the stacked structure along the first direction in the first region; an etch-stop structure located on the stacked structure in the first region, the etch-stop structure extending along the second direction; a common source conductive layer located on the stacked structure between the etch-stop structures in the first region and connected to the channel layer of the channel structure; and a buffer layer located on the common source conductive layer and comprising an insulating material. The upper surface of the buffer layer is at the same horizontal height as the upper surface of the etch-stop structure.

[0007] According to another aspect of an example embodiment, a semiconductor device includes: a stacked structure including an interlayer insulating layer and a gate electrode stacked along a first direction, the stacked structure being located in a first region and a second region; a separating region penetrating the stacked structure along the first direction in the first region and the second region, the separating region extending along a second direction perpendicular to the first direction and spaced apart along a third direction perpendicular to the first and second directions; a channel structure penetrating the stacked structure along the first direction in the first region; an etch stop structure located on the stacked structure, the etch stop structure extending along the second direction in the first region; a protective layer located on the stacked structure in the second region; a common source conductive layer located on the stacked structure between the etch stop structures in the first region and connected to the channel layer of the channel structure; and a buffer layer located on the common source conductive layer and comprising an insulating material. The upper surface of the common source conductive layer is at the same horizontal height as the upper surface of the etch stop structure. At least one of the etch stop structures includes an end connected to the protective layer and extending from the protective layer along the second direction.

[0008] According to another aspect of an example embodiment, a method of manufacturing a semiconductor device includes: forming a molded structure in a first region and a second region on a substrate by stacking an interlayer insulating layer and a sacrificial insulating layer in a first direction; forming a channel structure in the first region that penetrates the molded structure in the first direction; forming a separation opening in the first region and the second region, the separation opening penetrating the molded structure in the first direction, extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first and second directions; and forming a semiconductor device by replacing the sacrificial insulating layer with a gate electrode via the separation opening and filling the separation opening. The process involves separating regions to form a stacked structure; transferring the stacked structure onto a carrier substrate to remove the substrate exposed on top and forming preliminary insulating layers in the first and second regions; dry etching the preliminary insulating layers to form etch stop structures extending in the second direction and spaced apart from each other in the third direction in the first region; forming a preliminary common source conductive layer in the first region that covers the etch stop structures and is connected to the channel structure; forming a preliminary buffer layer disposed on the preliminary common source conductive layer; and performing etching up to the upper surface of the etch stop structure by planarizing the preliminary buffer layer and the preliminary common source conductive layer.

[0009] In structures where two or more substrate structures are bonded, a protective layer can be formed on an extension region of the stacked structure exposed from the rear surface of the upper substrate structure, and a common source line can be formed in the cell region. In this case, when the common source line and the insulating layer thereon are planarized in the cell region, an etch stop structure can be formed as part of the protective layer as an etch stop layer. The insulating layer formed to be as high as the upper part of the protective layer in the cell region can be etched, thereby enabling device miniaturization. In addition, multiple etch stop structures can be provided in the cell region to prevent surface dishing during the planarization process.

[0010] In addition, by applying H-rich nitrides as a protective layer, hydrogen can be supplied to the channel structure, thereby facilitating the activation of each channel layer.

[0011] The advantages and effects of this disclosure are not limited to the foregoing, and can be more readily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0012] The above and other aspects, features, and advantages will become clearer from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic top view of a semiconductor device according to an example embodiment; Figure 2 This is a partial enlarged view of a semiconductor device according to an example embodiment; Figure 3A and Figure 3B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment; Figure 4A and Figure 4B yes Figure 3B A magnified view of a local area; Figures 5 to 7 This is an enlarged view of the semiconductor device according to an example embodiment; Figure 8 and Figure 9 This is a schematic top view of a semiconductor device according to an example embodiment; Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I , Figure 10J , Figure 10K , Figure 10L and Figure 10M This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment; Figure 11 This is a schematic view illustrating a data storage system including semiconductor devices according to an example embodiment; Figure 12 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment. Detailed Implementation

[0013] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings. In the following description, the terms “above,” “upper,” “upper surface,” “lower,” “lower,” “lower surface,” “side surface,” etc., are understood to be indicated based on the drawings, except that they are indicated by reference numerals and are mentioned separately. The same components are indicated throughout the specification by the same reference numerals, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as “on”, “connected to,” or “bonded to” another element or layer, it can be directly on, connected to, or bonded to the other element or layer, or intermediate elements or layers may be present. In contrast, when an element is referred to as “directly on”, “directly connected to,” or “directly bonded to” another element or layer, no intermediate elements or layers are present. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment similarly provided herein or not provided herein but consistent with this disclosure.

[0014] In the following text, reference will be made to Figures 1 to 4B A semiconductor device according to an example embodiment is described.

[0015] Figure 1 This is a schematic top view of a semiconductor device according to an example embodiment.

[0016] Semiconductor device 10 may include a first semiconductor structure S1 (see Figure 3A and Figure 3B ) and the second semiconductor structure S2 (see Figure 3A and Figure 3B Furthermore, the first semiconductor structure S1 can be stacked relative to the second semiconductor structure S2 in the Z-direction (vertical direction). Specifically, the first semiconductor structure S1 can be disposed below the second semiconductor structure S2 in the Z-direction. The example embodiment is not limited thereto, and the second semiconductor structure S2 can be disposed below the first semiconductor structure S1.

[0017] In an example embodiment, semiconductor device 10 may include a peripheral circuit structure PERI (see [link to example]). Figure 3A and Figure 3B ) and the CELL storage cell structure (see Figure 3A and Figure 3B The peripheral circuit structure PERI is a first semiconductor structure S1 in which a peripheral circuit region is formed on the first substrate 101, and the memory cell structure CELL is a second semiconductor structure S2 including a common source line CSL.

[0018] In the example embodiment, the first semiconductor structure S1 can form a peripheral circuit by forming transistors and metal patterns for wiring the transistors on the first substrate 101. After the peripheral circuit is formed on the first semiconductor structure S1, a second semiconductor structure S2 can be formed, but the example embodiment is not limited thereto.

[0019] The semiconductor device 10 may include a cell region R1 in the X direction and an extension region R2 on at least one side of the cell region R1.

[0020] Cell region R1 is a memory cell region in which memory cells are disposed, and may be a region in which a channel structure CH is disposed. Extension region R2 may correspond to a region for electrically connecting memory cells to peripheral circuit structure PERI, and may be a region in which the gate electrode layer extends to different lengths for this purpose, but the example embodiment is not limited thereto.

[0021] Edge region EA can be disposed on each side of semiconductor device 10. Edge region EA can be disposed outside the extension region R2 and above, side and below the cell region R1, and can be a region including the upper cover layer 290 without a gate electrode. Edge region EA can be defined as a region in which a pad region connected to the outside is disposed, an external contact path 275 connected to the pad region is disposed, or various through paths connected to the first semiconductor structure S1 are disposed. Figure 1 The example shows an edge region EA set on each side to have a frame shape, but the example embodiment is not limited to this.

[0022] The protective layer 251 can be disposed within the extension area R2, and the protective layer 251 can cover the extension area R2 and the edge area EA and can be disposed in a board type.

[0023] Multiple etch stop structures 250 can be disposed within the cell region R1. The etch stop structures 250 can extend in the X direction within the cell region R1 and can be spaced apart from each other in the Y direction. The etch stop structures 250 can be arranged in parallel. The etch stop structures 250 can have the same material and the same height as the protective layer 251, and can be connected to each other at the boundary between the cell region R1 and the extended region R2, and at the boundary between the cell region R1 and the edge region EA.

[0024] Therefore, as Figure 1 and Figure 2 As shown, the etch stop structure 250 may have a comb shape extending from the protective layer 251 toward the cell region R1, but the example embodiment is not limited thereto.

[0025] The unit region R1 can be divided into multiple regions by the protective layer 251 and the etch stop structure 250.

[0026] A common source line (CSL) can be set in each of the multiple regions of cell region R1. The common source line (CSL) can be configured to have a plate shape in each of the multiple regions and can be physically spaced apart from the common source lines (CSL) of multiple adjacent regions.

[0027] Nitride films, specifically silicon nitride films, such as H-rich SiN, which are nitride films containing a large amount of hydrogen, can be applied to the protective layer 251 and the etch stop structure 250. H-rich SiN can be applied as plasma-enhanced SiN (PE-SiN), etc., and is a material layer with significantly low thermal conductivity, high energy absorption, and minimal thermal stress variation. H-rich SiN can be used as a buffer layer. During the melt laser annealing (MLA) process of the semiconductor layer included in the common source line CSL, because selective processing is not possible, energy and heat can be transferred to the extension region R2 and the edge region EA in which a large number of lower interconnects are formed, and therefore, device defects may occur due to accidental metal migration of the copper material forming the lower interconnects. Therefore, a protective layer 251 can be provided on the extension region R2 and the edge region EA to minimize the impact on the underside and protect the lower interconnects while performing crystallization and planarization of the semiconductor layer of the cell region R1 by the melt laser annealing process.

[0028] Each etch stop structure 250 may have a strip or line shape with a predetermined width in the XY plane, and the predetermined width may be 3 to 5 times the width of the upper end of the channel structure CH. For example, the etch stop structure 250 may have a width of 300 nm to 500 nm, preferably 300 nm to 400 nm, but the example embodiment is not limited thereto.

[0029] When the etch stop structure 250 is disposed in the cell region R1 and the common source line CSL and the buffer layer 205 thereon are thickly formed over the entire region and then planarized, the etch stop structure 250 can be used as an etch stop layer, thereby preventing surface dishing of the common source line CSL and the buffer layer 205 disposed over the large region.

[0030] In the following text, reference will be made to Figures 2 to 4B The example implementation is described in more detail.

[0031] Figure 2 This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 3A and Figure 3B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment, and Figure 4A and Figure 4B This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 2 yes Figure 1 A magnified view of part of the "A", and Figure 3A and Figure 3B Showing along Figure 1 The cutting line I-I' and Figure 2 The cross-sectional view of the cutting line II-II'. Figure 4A and Figure 4B They are Figure 3B Enlarged images of parts "B" and parts "C".

[0032] refer to Figures 2 to 4B The semiconductor device 10 may include a first semiconductor structure S1 defined as a peripheral circuit structure PERI and a second semiconductor structure S2 defined as a memory cell structure CELL and located on the first semiconductor structure S1. The first semiconductor structure S1 and the second semiconductor structure S2 may be joined together by bonding structures 180 and 280.

[0033] The first semiconductor structure S1 may include a first substrate 101, circuit elements 120 located on the first substrate 101, a lower interconnect structure 130, a lower bonding structure 180, and a lower cover layer 190.

[0034] The first substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 101 may be provided as a bulk wafer or an epitaxial layer. An active region may be defined in the first substrate 101 by a device isolation layer 110. A source / drain region 105 including impurities may be disposed in a portion of the active region.

[0035] Circuit element 120 may include a transistor. Each circuit element 120 may include a circuit gate dielectric layer 122, a circuit gate electrode 124, a spacer layer 126, and a source / drain region 105. The source / drain regions 105, including impurities, may be disposed on both sides of the circuit gate electrode 124 in the first substrate 101. The spacer layer 126 may be disposed on both sides of the circuit gate electrode 124. The circuit gate dielectric layer 122 may include silicon oxide, silicon nitride, or a high-k material. The circuit gate electrode 124 may include at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), or ruthenium (Ru). For example, the circuit gate electrode 124 may include a doped polysilicon layer. According to an example embodiment, the circuit gate electrode 124 may be formed of two or more layers.

[0036] The lower interconnect structure 130 can be electrically connected to the circuit gate electrode 124 and the source / drain region 105 of the circuit element 120. The lower interconnect structure 130 can include lower contact plugs 135 and lower interconnect lines 137, in which at least one region of the lower interconnect line 137 has a line shape. Some lower contact plugs 135 can be connected to the source / drain region 105, and other lower contact plugs 135 can be connected to the circuit gate electrode 124. The lower contact plugs 135 can electrically connect the lower interconnect lines 137 disposed at different horizontal heights from the upper surface of the first substrate 101 to each other. The lower interconnect structure 130 can include a conductive material, and can include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each component can also include a diffusion barrier comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). According to the example embodiment, the number of layers and arrangement of the lower contact plug 135 and the lower interconnect line 137 included in the lower interconnect structure 130 can be varied.

[0037] The lower bonding structure 180 can be connected to the lower interconnect structure 130. The lower bonding structure 180 may include a lower bonding path 182, a lower bonding pad 184, and a lower bonding insulating layer 186. The lower bonding path 182 can be connected to the lower interconnect structure 130. The lower bonding pad 184 can be connected to the lower bonding path 182. The lower bonding path 182 and the lower bonding pad 184 may include conductive materials, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each component may also include a diffusion barrier. The lower bonding insulating layer 186 may also serve as a diffusion barrier for the lower bonding pad 184, and may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The thickness of the lower bonding insulating layer 186 may be thinner than the thickness of the lower bonding pad 184, but the example implementation is not limited thereto. The lower bonding structure 180 may directly contact and be bonded to or connected to the upper bonding structure 280 by hybrid bonding. For example, the lower bonding pad 184 can contact the upper bonding pad 284 and can be bonded to the upper bonding pad 284 by copper-to-copper bonding, and the lower bonding insulating layer 186 can contact the upper bonding insulating layer 286 and can be bonded to the upper bonding insulating layer 286 by dielectric bonding. The lower bonding structure 180, together with the upper bonding structure 280, can provide an electrical connection path between the first semiconductor structure S1 and the second semiconductor structure S2.

[0038] A lower cover layer 190 may be disposed on the first substrate 101 to cover the circuit element 120 and the lower interconnect structure 130. The lower cover layer 190 may include multiple insulating layers. The lower cover layer 190 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0039] The second semiconductor structure S2, as a memory cell structure, may include within the cell region R1 (i.e., the memory cell region) a first conductive layer 201, a second conductive layer 202 located on the upper surface of the first conductive layer 201, a buffer layer 205 located on the upper surface of the second conductive layer 202, a gate electrode 230 stacked on the lower surface of the first conductive layer 201 and disposed in the cell region R1 and the extension region R2, an interlayer insulating layer 220 alternately stacked with the gate electrode 230, a channel structure CH configured to penetrate the gate electrode 230, a separating region MS extending in one direction through the gate electrode 230, and an insulating region SS penetrating a portion of the gate electrode 230. The second semiconductor structure S2 may surround the cell region R1 and the extension region R2 and may include an edge region EA, and may include an upper capping layer 290 located within the edge region EA. The second semiconductor structure S2 may include a protective layer 251 disposed horizontally on the lowest interlayer insulating layer 222 in the extended region R2 and the edge region EA, and may also include an upper cover layer 290 covering the gate electrode 230, and an upper insulating structure 210 and a passivation layer 215 located on the buffer layer 205 and the protective layer 251.

[0040] The second semiconductor structure S2 may include pillars 272 for electrical connection with the first semiconductor structure S1, an upper interconnect structure 271 located below the stacked structures GS1 and GS2, and an upper bonding structure 280 connected to the upper interconnect structure 271.

[0041] The second semiconductor structure S2 may also include a support structure 265, a contact plug 270 located in the extension region R2, and an external contact passage 275 located in the edge region EA.

[0042] like Figure 3A As shown, cell region R1 may be a region in which gate electrodes 230 are spaced apart and stacked in the vertical direction (e.g., the Z direction) and a channel structure CH is provided therein. Extension region R2 may be disposed on at least one side of cell region R1 in the X direction and may be a region in which contact plugs 270, respectively connected to the gate electrodes 230, are configured to electrically connect the memory cell to the first semiconductor structure S1. Figure 2 and Figure 3A In the example, the gate electrode 230 is shown extending to different lengths to form contact pads for connection between the respective gate electrode 230 and the contact plug 270, but the example embodiment is not limited thereto.

[0043] An edge region EA can be disposed outside the extension region R2 and outside the cell region R1. A pad region 258 for transmitting and receiving signals from the outside can be disposed in the edge region EA. An external contact path 275 for transmitting signals from the outside to the first semiconductor structure S1 can be disposed in the edge region EA. The edge region EA is the region in which the gate electrode 230 does not extend and in which an upper cover layer 290 is disposed, and can be connected to the first semiconductor structure S1 in a state where the external contact path 275 is insulated from the gate electrode 230.

[0044] In the unit region R1, the extension region R2 and the edge region EA, the upper insulating structure 210 can be disposed on the stacked structures GS1 and GS2, and the passivation layer 215 can be disposed on the upper part of the upper insulating structure 210.

[0045] Gate electrodes 230 may be vertically spaced and stacked on the lower surfaces of the first conductive layer 201 and the protective layer 251 to form stacked structures GS1 and GS2 together with the interlayer insulating layer 220. Stacked structures GS1 and GS2 may include multiple vertically stacked structures GS1 and GS2. Figure 3A and Figure 3B The diagram illustrates a lower stacking structure GS1 and an upper stacking structure GS2, but is not limited thereto, and may include 3 to 5 stacking structures GS1 to GSn. However, according to the example embodiment, the stacking structures GS1 to GSn may be formed as a single stacking structure.

[0046] The gate electrode 230 may include at least one lower gate electrode 230L of the gate of a ground select transistor, memory gate electrodes 230M of a plurality of memory cells, and an upper gate electrode 230U of the gate of a string select transistor. Here, the lower gate electrode 230L and the upper gate electrode 230U may be referred to as "lower" and "upper" based on the orientation during the manufacturing process. The number of memory gate electrodes 230M included in the memory cell may be determined according to the capacity of the semiconductor device 10. According to an example embodiment, the number of upper gate electrodes 230U and the number of lower gate electrodes 230L may be one to two or more, and the upper gate electrodes 230U and the lower gate electrodes 230L may have the same or different structures as the memory gate electrodes 230M. In an example embodiment, an erase gate electrode may be further disposed below the upper gate electrode 230U. In addition, some gate electrodes 230 (e.g., memory gate electrodes 230M adjacent to the upper gate electrode 230U or the lower gate electrode 230L) may be dummy gate electrodes, but the example embodiment is not limited thereto.

[0047] The gate electrode 230 can be configured to be separated from each other in the Y direction by partition regions MS that extend continuously within the cell region R1 and the extension region R2. The gate electrode 230 located between a pair of partition regions MS can form a memory block BLK, but the scope of the memory block BLK is not limited thereto. Some gate electrodes 230 (e.g., memory gate electrode 230M) can each form a layer within a memory block BLK.

[0048] Gate electrodes 230 can be perpendicularly spaced and stacked within the cell region R1 and the extension region R2, and can extend from the cell region R1 to the extension region R2 by different lengths. Therefore, the gate electrodes 230 can form a stepped structure in a portion of the extension region R2 (e.g., within the extension region R2). The gate electrodes 230 can also be configured to have a stepped structure in the Y direction. With the stepped structure, the gate electrodes 230 can extend longer than the upper gate electrode 230, and each gate electrode 230 can have an area on its upper surface exposed upwards from the interlayer insulating layer 220 and other gate electrodes 230, and this upper area can be referred to as a pad area. In each gate electrode 230, the pad area can be a region including the end of the gate electrode 230 in the X direction. The pad area can correspond to a region of the uppermost gate electrode 230 in each region of the stacked structures GS1 and GS2 within the extension region R2. The gate electrodes 230 can be connected to contact plugs 270 in the pad areas respectively. The gate electrode 230 can have increased thickness in the pad area.

[0049] The gate electrode 230 may include a metallic material, such as tungsten (W). According to an example embodiment, the gate electrode 230 may include polycrystalline silicon or a metal silicide material. According to an example embodiment, the gate electrode 230 may also include a diffusion barrier 231, and for example, the diffusion barrier 231 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0050] Interlayer insulating layer 220 may be disposed between gate electrodes 230 to form stacked structures GS1 and GS2. Similar to gate electrodes 230, interlayer insulating layer 220 may also be spaced apart from each other in a direction perpendicular to the lower surface of the first conductive layer 201 and the lower surface of the protective layer 251, and may be configured to extend in the X direction. Interlayer insulating layer 220 may comprise an insulating material such as silicon oxide or silicon nitride.

[0051] In the example embodiment, the thickness of the interlayer insulating layer 220 may not be entirely uniform. For example, among the interlayer insulating layers 220, the uppermost interlayer insulating layer 223, the lowermost interlayer insulating layer 222, and the intermediate interlayer insulating layer 225 may have a greater thickness compared to the other interlayer insulating layers 220, but the example embodiment is not limited thereto. The intermediate interlayer insulating layer 225 can be defined as the interlayer insulating layer between the stacked structures GS1 and GS2.

[0052] The separator region MS can be configured to extend through at least a portion of the gate electrode 230 in the X direction. The separator regions MS can be configured to be parallel to each other. The separator region MS can penetrate the entire stack of gate electrodes 230 and can be connected to the lower insulating layer 291. The separator region MS can extend in the X direction in a shape, but can extend intermittently in some regions or can be set only in some regions.

[0053] A separating insulating layer 264 may be disposed in the separating region MS. The separating insulating layer 264 may have a shape in which its width increases toward the first substrate 101 due to a high aspect ratio, but the exemplary embodiment is not limited thereto. The lower end of the separating insulating layer 264 may contact the lower insulating layer 291, and the upper end may be included in a protrusion that protrudes from the upper surfaces of the stacked structures GS1 and GS2, and the protrusion may contact the etch stop structure 250. The first width W1 of the upper end of the separating region MS in the Y direction may be greater than the width of the upper end of each channel structure CH, but the exemplary embodiment is not limited thereto. The separating insulating layer 264 may not extend to the edge region EA and may only be disposed within the cell region R1 and the extension region R2. Figure 2 As shown, the partition region MS can be formed such that its side surface has a flat plane, but the example embodiment is not limited to this.

[0054] The insulating region SS can extend in the X direction between adjacent separating regions MS. The insulating region SS can be disposed within a portion of the extended region R2 and within the cell region R1. The insulating region SS can penetrate the upper gate electrode 230U disposed on the uppermost gate electrode 230. For example... Figure 3B As shown, the insulating region SS can divide the gate electrode 230U in the Y direction. However, in the example embodiment, the number of gate electrodes 130U separated by the insulating region SS can vary.

[0055] The insulating region SS may intersect a portion of the channel structure CH. The insulating region SS may have a predetermined width in the Y direction and may extend to intersect multiple channel structures CH arranged in a zigzag shape in the X direction. Therefore, when multiple channel structures CH are arranged with the same spacing, the insulating region SS may extend to intersect a row of channel structures CH simultaneously. The insulating region SS may be recessed into the upper part of the channel structure CH (e.g., the portion of the channel structure CH facing an upper gate electrode 230U), and thus, a portion of the channel structure CH may be removed. In this case, the insulating region SS may extend from the inner wall of the channel hole towards the channel center axis. c is the length of the recess that is shorter than the radius of the channel structure CH. Therefore, the insulating region SS does not need to cross the central axis of the channel structure CH. c. The trench structure CH can be configured such that at least half of it remains on its upper surface, but the example embodiment is not limited thereto. The insulating region SS recessed therein into the trench structure CH can be an effective trench structure that is actually used as a memory cell, rather than a dummy trench structure. Each insulating region SS can include an upper separating insulating layer 266. The upper separating insulating layer 266 can include an insulating material and can include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0056] The channel structures CH can be arranged in rows and columns on the lower surface of the first conductive layer 201 of the cell region R1 and can be spaced apart from each other. The channel structures CH can be arranged in a Z-shape in one direction in the XY plane. The channel structures CH can penetrate the gate electrode 230 and can extend in a vertical direction perpendicular to the lower surface of the first conductive layer 201 (e.g., in the Z direction), and can have a pillar shape and can have inclined side surfaces, wherein the width of the channel structures CH increases according to the aspect ratio as they approach the first conductive layer 201.

[0057] Each channel structure CH can have a form in which the lower stacked structure GS1 and the upper stacked structure GS2 penetrating the gate electrode 230 are connected to each other, and can have a curved portion due to the width difference or variation of the connection region. For example, the curved portion can be oblique with respect to the X and Y directions.

[0058] As in Figure 4A As shown in the enlarged view, each channel structure CH may include a first portion located within the stacked structures GS1 and GS2 and a second portion protruding from the stacked structures GS1 and GS2.

[0059] The channel layer 240 can be completely disposed within the first and second portions of the channel structure CH, and can be configured to extend to the upper end of the second portion. The channel layer 240 may include a protruding portion 240a disposed within the second portion of the channel structure CH and projecting upwards and exposed from the stacked structures GS1 and GS2, and a non-protruding portion 240b disposed on the first portion of the channel structure CH. The protruding length h1 of the second portion of the channel structure CH (the protruding portion 240a of the channel layer 240) may not be the same for each other, but the example embodiment is not limited thereto. The channel layer 240 may be formed in an annular shape with its side surface surrounding the internal buried insulating layer 247, but according to the example embodiment, it may also have a columnar shape, such as a cylindrical or angular column without the buried insulating layer 247. The protruding portion 240a of the channel layer 240 may be covered by the first conductive layer 201 and may be in direct contact with the first conductive layer 201. The protruding portion 240a may be formed with a gentle slope compared to the non-protruding portion 240b, such that... Figure 4A The ring shape is maintained as shown. The channel layer 240 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type impurities or N-type impurities.

[0060] In the channel structure CH, channel pads 249 may be disposed on the lower part of the channel layer 240. Channel pads 249 may be configured to cover the lower surface of the buried insulating layer 247 and may be electrically connected to the channel layer 240. Channel pads 249 may comprise, for example, doped polysilicon.

[0061] Information storage structure 245 may be disposed between gate electrode 230 and channel layer 240. Information storage structure 245 may include a tunneling layer 241, a charge storage layer 242, and a barrier layer 243 sequentially stacked from channel layer 240. Tunneling layer 241 allows charge to tunnel into charge storage layer 242 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. Charge storage layer 242 may be a charge trapping layer or a floating gate conductive layer. Barrier layer 243 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. According to an example embodiment, at least a portion of information storage structure 245 may form a channel dielectric layer extending horizontally along gate electrode 230.

[0062] The information storage structure 245 can be removed from the top of the stacked structures GS1 and GS2, so that the protruding portion 240a of the channel layer 240 is exposed to the outside in the second part. Therefore, the upper part of the information storage structure 245 can contact the first conductive layer 201, and the side surface of the information storage structure 245 located in the first part can be configured to surround the non-protruding portion 240b of the channel layer 240.

[0063] The channel layer 240, the information storage structure 245, and the buried insulation layer 247 can be connected to each other between the upper channel structure CH2 and the lower channel structure CH1. As described above, a relatively thick intermediate interlayer insulation layer 225 can be provided between the upper channel structure CH2 and the lower channel structure CH1.

[0064] Support structure 265 may be disposed in extension region R2 and may have the same or similar structure as channel structure CH, but may not perform actual function in semiconductor device 10. Support structure 265 may be disposed in rows and columns in extension region R2. Support structure 265 may have a diameter equal to or smaller than the maximum diameter of contact plug 270. The shape, number and / or spacing of support structure 265 may be different. Channel structure CH and support structure 265 may have circular or near-circular shapes, but are not limited thereto, and may have another shape, such as elliptical shape, in some example embodiments. Support structure 265 may provide structural support to prevent deformation such as bending of stacked structures GS1 and GS2.

[0065] Contact plug 270 can be connected to the contact area of ​​gate electrode 230 in the gate pad region of extension region R2. Contact plug 270 can penetrate at least a portion of the upper cover layer 290 and can be connected to each upwardly exposed contact area of ​​gate electrode 230. Contact plug 270 can penetrate gate electrode 230 below the contact area and can be connected to upper interconnect structures 271 and 272. Contact plug 270 can be spaced apart from gate electrode 230 below the contact area by contact insulating layer 260. However, in some example embodiments, contact plug 270 can be configured not to penetrate gate electrode 230, in which case contact plug 270 can be connected to each upwardly exposed contact area of ​​gate electrode 230.

[0066] The contact plug 270 may have a shape corresponding to the channel structure CH or a shape corresponding to the partition region MS. Each contact plug 270 may include an upper region that penetrates one of the stacked structures GS1 and GS2 and a lower region that extends along with the upper region, penetrates the other of the stacked structures GS1 and GS2, and is disposed below the upper region. The lower and upper regions may have sloping side surfaces, wherein their width decreases due to aspect ratio as they approach the protective layer 251 in each of the stacked structures GS1 and GS2, and the lower and upper regions may have a cylindrical shape.

[0067] like Figure 3A As shown, each contact plug 270 may have a horizontally expanding shape in the contact area. The contact plug 270 may include a vertically extending portion 270V extending in the Z direction and a horizontally extending portion 270H extending horizontally from the vertically extending portion 270V and contacting the gate electrode 230. The horizontally extending portion 270H may be disposed along the periphery of the vertically extending portion 270V and may be surrounded by the gate electrode 230 on its entire side surface. The length from the side surface of the vertically extending portion 270V to the end of the horizontally extending portion 270H may be less than the length from the side surface of the vertically extending portion 270V to the outer surface of the contact insulating layer 260. The contact plug 270 may be spaced apart from the gate electrode 230 (i.e., the unconnected gate electrode 230) below the contact area by the contact insulating layer 260.

[0068] The contact plug 270 may include a conductive material and may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example embodiments, the contact plug 270 may include a barrier layer extending along its side and bottom surfaces, or may have an air gap therein.

[0069] The contact insulating layer 260 may be configured to surround the side surface of each contact plug 270 below the contact area. The contact insulating layers 260 may be spaced apart from each other in the Z direction around each contact plug 270. The contact insulating layers 260 may each be disposed at substantially the same horizontal height as the gate electrode 230. The contact insulating layer 260 may comprise an insulating material and may comprise, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0070] In the edge region EA, the external contact path 275 can be connected to the first semiconductor structure S1 via the externally exposed pad region 258 and the upper interconnect structures 271 and 272 of the second semiconductor structure S2. The external contact path 275 can penetrate the upper cover layer 290 and can be connected to the upwardly exposed pad region 258 via the upper pillar 257.

[0071] The external contact passage 275 may have a shape corresponding to the channel structure CH or a shape corresponding to the contact plug 270. Each external contact passage 275 may include a lower region and an upper region extending together with and disposed above the lower region, thereby having a curved portion corresponding to the shape of the lower channel structure CH1 and the upper channel structure CH2 of the channel structure CH. The lower region and the upper region may have inclined side surfaces, wherein their width decreases due to aspect ratio as the lower region and the upper region approach the protective layer 251, and the lower region and the upper region may have a cylindrical shape. The upper width of the external contact passage 275 may be 1.5 to 3 times the upper width of the channel structure CH, but the example embodiment is not limited thereto. The external contact passage 275 may include a conductive material and may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), or alloys thereof.

[0072] At least one etch stop structure 250 may be disposed within the cell region R1. Each of the at least one etch stop structure 250 may include a strip shape or a line shape extending in the X direction.

[0073] Each of at least one etch stop structure 250 may include a lower surface at the same horizontal level as the lower surface of the protective layer 251 and an upper surface at the same horizontal level as the upper surface of the protective layer 251.

[0074] The etch stop structure 250 may include the same material as the protective layer 251 and may be defined as a strip structure that is similarly stacked and deposited over the entire upper portion of the second semiconductor structure S2 and then patterned by an etching process.

[0075] At least one etch stop structure 250 may include two short-side surfaces with short lengths and two long-side surfaces with long lengths between the upper and lower surfaces, and at least one short-side surface may be connected to and integrated with the protective layer 251. All etch stop structures 250 may be connected to the protective layer 251 and may be connected to the protective layer 251 at the boundary between the unit region R1 and the extension region R2 and / or at the boundary between the unit region R1 and the edge region EA.

[0076] Therefore, the protective layer 251 can be defined as an insulating layer disposed on the upper part of the stacked structures GS1 and GS2 or the upper cover layer 290 in the extension region R2 and the edge region EA, and at least one etch stop structure 250 can be defined as an insulating structure disposed on the upper part of the stacked structures GS1 and GS2 in the cell region R1.

[0077] exist Figures 1 to 4B In this embodiment, the etch stop structure 250 can be simultaneously connected to and integrated with the protective layer 251, but the example embodiment is not limited to this.

[0078] The etch stop structures 250 may be spaced apart from each other in the Y direction in the cell region R1 and may extend parallel to each other and may have substantially the same size and shape, but the example embodiment is not limited thereto.

[0079] The etch stop structures 250 may be spaced apart from each other in the Y direction by a first separation distance I1. The first separation distance I1 may be equal to or less than a critical distance, and the critical distance may be the maximum distance at which the buffer layer 205 does not have a depression during the planarization process. The critical distance may be, for example, in the range of 3 μm to 4 μm, but the example embodiment is not limited thereto.

[0080] The etch stop structure 250 may be spaced apart from the channel structure CH. Specifically, at least one etch stop structure 250 may be spaced apart from the nearest channel structure CH by at least a first distance d1 or greater. The first distance d1 may be equal to the channel pitch, which is the center distance between the channel structures CH, but the example embodiment is not limited thereto.

[0081] Each etch stop structure 250 can be spaced apart from the channel structure CH, and can therefore be configured such that at least a portion of it overlaps with the separating region MS. For example... Figures 1 to 4B As shown, each etch stop structure 250 can overlap with the separator region MS within the cell region R1, and can be configured to cover the protruding portion of the upper end of the separator region MS (i.e., the upper surface of the stacked structures GS1 and GS2). Therefore, the separator region MS can be kept within the cell region R1 without being exposed to the outside of the etch stop structure 250.

[0082] Specifically, each etch stop structure 250 can be configured such that its lower surface has a second width W2 in the Y direction, and the second width W2 can be greater than the first width W1 of the separating region MS. For example, the second width W2 can be two to three times the first width W1, and can be 300 nm to 500 nm, preferably 300 nm to 350 nm.

[0083] In this way, an etch stop structure 250 can be set in the unit region R1 corresponding to each partition region MS, and the partition region MS can extend to the extension region R2, but the etch stop structure 250 can be integrated with the protective layer 251 in the extension region R2.

[0084] When the central axis of the first width W1 of the dividing region MS in the Y direction is defined as the first axis At time 0, the central axis of the second width W2 of the etch stop structure 250 on it in the Y direction can be defined as the second axis. 1. Second axis 1 and the first axis 0 can be coaxial, but the example embodiments are not limited to this.

[0085] Second axis 1. The central axis of the nearest channel structure CH The separation distance between c can satisfy the first distance d1.

[0086] When the second part of the channel structure CH protrudes upward from the stacked structures GS1 and GS2 to a first length h1, the protruding part of the separating region MS can protrude to a second length h2, and the second length h2 can be equal to or greater than the first length h1. In this case, the second length h1 can be no greater than 1.5 times the first length h1 and can have a length within a similar range.

[0087] Each etch stop structure 250 may have a third length h3 in the Z direction, and may be substantially the same as the second width W2 in the Y direction. The third length h3 may be greater than the first length h1 of the channel structure CH, and may be greater than the second length h2, which is the length of the protruding portion of the partition region MS. Therefore, the upper surface of the partition region MS disposed inside may be spaced apart from the upper surface of the etch stop structure 250.

[0088] Each etch stop structure 250 can be configured such that the width of its upper surface and the width of its lower surface are substantially the same. Therefore, the side surface of each etch stop structure 250 can be substantially perpendicular to the upper surface of the stacked structures GS1 and GS2.

[0089] The third length h3 of the etch stop structure 250 can be 300 nm to 500 nm, preferably 300 nm to 350 nm, but the example embodiment is not limited thereto.

[0090] In this way, the etch stop structure 250 configured to surround the partition region MS can be disposed within the cell region R1, such that each block BLK can have an isolation shape isolated from the etch stop structure 250 spaced apart from the protective layer 251.

[0091] The first conductive layer 201 and the second conductive layer 202 can be disposed on the stacked structures GS1 and GS2 inside a block isolated from the etch stop structure 250 spaced apart from the protective layer 251.

[0092] A first conductive layer 201 may be disposed in the cell region R1 between the lower surface of the second conductive layer 202 and the stacked structures GS1 and GS2. The first conductive layer 201 may include a semiconductor material. For example, the first conductive layer 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The first conductive layer 201 may serve as the common source line CSL of the semiconductor device 10. The first conductive layer 201 may include a silicon layer, and may include, for example, a silicon layer having an N-type conductivity type. For example, the first conductive layer 201 may be provided as a doped crystalline semiconductor layer or an epitaxial layer, such as a single-crystal silicon layer or a polycrystalline silicon layer. Figure 4A As shown in the enlarged view, the first conductive layer 201 can cover the second part of the channel structure CH and can be in direct contact with the protrusion 240a of the channel layer 240.

[0093] In the first conductive layer 201 disposed in each block, a bottom region completely covering the stacked structures GS1 and GS2 of each block can be provided as a plate layer, and the first conductive layer 201 can be configured such that the upper surface of the bottom region has a flat surface. In each block, the first conductive layer 201 can be configured such that the bottom region has a first thickness t1, and the first thickness t1 can be greater than the first length h1 of the protrusion 240a of the channel layer 240. For example, when the first length h1 of the protrusion 240a of the channel layer 240 is 150nm to 180nm, the first thickness t1 of the first conductive layer 201 can be greater than the length h1 of the protrusion 240a by 200nm to 220nm, and the first conductive layer 201 can remain above the protrusion 240a.

[0094] In each block, the upper surface of the bottom region of the first conductive layer 201 can be set at a horizontal height lower than the upper surface of the etch stop structure 250, and the lower surface of the bottom region of the first conductive layer 201 can be set at a horizontal height equal to or lower than the lower surface of the etch stop structure 250.

[0095] The first conductive layer 201 may have a bottom region and side regions curved from the bottom region. Each side region of the first conductive layer 201 may be formed to contact the side surface of the etch stop structure 250 and the side surface of the protective layer 251, and may be substantially perpendicular to the upper surface of the interlayer insulating layer 222 (i.e., the lower surface of the bottom region of the first conductive layer 201), such as... Figure 4B As shown. The curved side regions of the first conductive layer 201 may have a thickness thinner than the bottom region within each block, but the example embodiment is not limited thereto.

[0096] The second conductive layer 202 may be disposed along the first conductive layer 201. The second conductive layer 202 may have a thickness smaller than that of the first conductive layer 201 and may be a conductive layer in contact with the first conductive layer 201. The second conductive layer 202 may also include a bottom surface filling the interior of each block and side surfaces curved from the bottom surface. Unlike the first conductive layer 201, the bottom surface and side surfaces of the second conductive layer 202 may also have substantially the same thickness, but the example embodiment is not limited thereto.

[0097] The curved structure of the second conductive layer 202 allows for the formation of a recessed portion on the upper surface of the bottom surface of the second conductive layer 202. Specifically, within each block surrounded by the etch stop structure 250 and the protective layer 251, the recessed portion can be formed by the first conductive layer 201, and also by the second conductive layer 202 formed along the recessed portion.

[0098] The second conductive layer 202 may include at least one of a metal semiconductor compound, a metal nitride, and a metal (e.g., tungsten (W), copper (Cu), aluminum (Al)). The second conductive layer 202 may be aligned perpendicularly to the first conductive layer 201. The second conductive layer 202 may have a multilayer structure, but the example embodiments are not limited thereto. For example, the second conductive layer 202 may include a layered structure of an ohmic contact layer, a conductive layer, and a diffusion barrier.

[0099] Within each block, the first conductive layer 201 and the second conductive layer 202 can serve as source layers and together form a source structure. The source structure can serve as the common source line CSL of the semiconductor device 10.

[0100] A buffer layer 205 may be further formed on the second conductive layer 202 within a recessed portion of the second conductive layer 202. When the second conductive layer 202 and the first conductive layer 201 are patterned, the buffer layer 205 can protect the first conductive layer 201 and the second conductive layer 202. The buffer layer 205 can fill the recessed portion of the second conductive layer 202, and its upper surface can be coplanar with the upper surface of the etch stop structure 250 and the upper surface of the protective layer 251, and can be coplanar with the upper end of the side surface of the first conductive layer 201 and the upper end of the side surface of the second conductive layer 202.

[0101] The buffer layer 205, the second conductive layer 202, and the first conductive layer 201 can be stacked sequentially, and their thickness can be reduced by planarization via a chemical mechanical polishing process. Therefore, when viewed in the XY plane, the buffer layer 205, the second conductive layer 202, and the first conductive layer 201 can have a structure in which each block is completely filled by the buffer layer 205, the second conductive layer 202 surrounds the periphery of the buffer layer 205 in a frame shape, and the first conductive layer 201 surrounds the periphery of the second conductive layer 202 in a frame shape.

[0102] In addition, the etch stop structure 250 and the protective layer 251 surround the periphery of the first conductive layer 201.

[0103] The etch stop structure 250 can be used as an etch stop layer in a chemical mechanical polishing process, and planarization can terminate on the upper surface of the etch stop structure 250, such that the upper surface of the etch stop structure 250, the upper end of the buffer layer 205, the upper end of the first conductive layer 201, and the upper end of the second conductive layer 202 can all form coplanar surfaces. The buffer layer 205 may include oxides, and may include, for example, silicon oxide, silicon nitride, etc.

[0104] The upper insulation structure 210 can be configured to cover both the common source line CSL and the protective layer 251.

[0105] The upper insulating structure 210 may include a first insulating layer 211 and a hydrogen supply layer 213. The first insulating layer 211 may cover the buffer layer 205, the etch stop structure 250, and the protective layer 251, and may be formed with a flat upper surface. It may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The hydrogen supply layer 213 may be H-rich SiN and may be formed from a material such as PE-SiN. An annealing process may be performed while the hydrogen supply layer 213 is formed, thus forming a hydrogen path to the channel layer 240. For this purpose, the first insulating layer 211 may include TEOS, and may include an HDP oxide as a second insulating layer in between, but the example embodiment is not limited thereto.

[0106] The second semiconductor structure S2 may also include a source contact path 255 located on the second conductive layer 202 of the common source line in each block and a source interconnect line 256 located on the source contact path 255.

[0107] The source contact path 255 can penetrate the buffer layer 205, so that the source interconnect 256 located on the second conductive layer 202 can be disposed in the first insulating layer 211.

[0108] Additionally, the upper pillar 257 connecting the external contact path 275 and the pad area 258 can be disposed in the edge region EA, and the pad area 258 can be disposed on the first insulating layer 211. The upper pillar 257 can be disposed in a multi-layer structure, and when the upper pillar 257 is disposed in a multi-layer structure, additional interconnect structures can be disposed between them, but the example embodiment is not limited thereto. The first insulating layer 211 and the hydrogen supply layer 213 can be disposed to cover the edge of the pad area 258, and the central region of the pad area 258 can be disposed in a state in which the central region can be exposed to the outside and connected to wiring, etc.

[0109] Passivation layer 215 may be disposed on the upper surface of hydrogen supply layer 213. Passivation layer 215 may serve as a layer protecting semiconductor device 10. In an example embodiment, passivation layer 215 has openings OI in some areas, thereby defining pad areas 258 connected to the outside. Passivation layer 215 may include organic materials, but may alternatively include at least one of silicon oxide or silicon carbide, and may serve as a capping layer.

[0110] Upper interconnect structures 271 and 272 can electrically connect the gate electrode 230 and the channel structure CH to the circuit element 120. Upper interconnect structures 271 and 272 may include pillars 272 connected to the channel structure CH, pillars 272 connected to contact plugs 270, and pillars 272 connected to external contact paths 275. The pillars 272 connected to the channel structure CH can be connected to the channel pads 249 of the channel structure CH. In cell region R1, the pillars 272 connected to the channel structure CH can be electrically connected to the channel layer 240 via the channel pads 249 of the channel structure CH. In extension region R2, the pillars 272 can be connected to the contact plugs 270 connected to the gate electrode 230. Upper interconnect 271 can be connected to the pillars 272. The upper interconnect structures 271 and 272 may include conductive materials, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al). Each component may also include a diffusion barrier comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). According to the example embodiment, the number and arrangement of the pillars 272 and the upper interconnect lines 271 included in the upper interconnect structures 271 and 272 may be varied, and high energy and heat can be blocked by the protective layer 251 disposed on top, so that the diffusion of the metallic material in the upper interconnect structures 271 and 272 does not continue, thereby improving the reliability of the components.

[0111] Upper bonding structure 280 can be connected to upper interconnect structures 271 and 272. For example, post 272 can be electrically connected to upper bonding structure 280. Upper bonding structure 280 may include upper bonding path 282, upper bonding pad 284, and upper bonding insulating layer 286. Upper bonding path 282 can be connected to upper interconnect 271. Upper bonding pad 284 can be connected to upper bonding path 282. Upper bonding path 282 and upper bonding pad 284 may include conductive materials, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each component may also include a diffusion barrier. Upper bonding insulating layer 286 may also serve as a diffusion barrier for upper bonding pad 284, and may include at least one of SiCN, SiO, SiN, SiOC, SiON, or SiOCN. Upper bonding insulating layer 286 may have a thickness thinner than that of upper bonding pad 284, but the example embodiment is not limited thereto.

[0112] In the following text, reference will be made to Figures 5 to 7 Describe an example implementation. Figures 5 to 7 This is an enlarged view of a semiconductor device according to an example embodiment, and is Figure 3B A magnified view of region "C".

[0113] refer to Figure 5 Apart from the shape of the etch stop structure 250 and the shape of the common source line CSL, the semiconductor device 10a and Figure 4B The semiconductor device 10 is the same.

[0114] Specifically, in the semiconductor device 10a, at least one etch stop structure 250 extends in the X direction, and the etch stop structures 250 are spaced apart from each other in the Y direction within the cell region R1.

[0115] Each etch stop structure 250 may include a side surface located between the upper and lower surfaces. The etch stop structure 250 may be configured such that the upper and lower surfaces overlap, and the area of ​​the upper surface may be smaller than the area of ​​the lower surface. For example, the area of ​​the etch stop structure 250 may gradually decrease from the lower surface to the upper surface, and the etch stop structure 250 may have a minimum area on the upper surface. Therefore, when the width of the lower surface in the Y direction has a second width W2, the width of the upper surface may have a third width W3 that is smaller than the second width W2.

[0116] Due to the difference between the second width W2 of the lower surface and the third width W3 of the upper surface, the side surface can have an inclination relative to the lower surface. This inclination of the side surface can have a first angle θ1 relative to the lower surface, and the first angle θ1 can be an acute angle greater than 70 degrees and less than 90 degrees.

[0117] By adjusting the slope of the side surface of the etch stop structure 250 described above, the common source line CSL located within the block BLK surrounded by adjacent etch stop structures 250 and protective layer 251 can be configured such that the side region has a slope relative to the bottom region.

[0118] That is, the side region of the first conductive layer 201 can be configured to be inclined at an angle greater than 90 degrees with the bottom region, and the second conductive layer 202 located on the first conductive layer 201 can also be configured such that its side surface is inclined at an obtuse angle with the bottom surface. Therefore, the recessed portion of the second conductive layer 202 can have a larger area towards its upper end.

[0119] The recessed portion of the second conductive layer 202 can be filled, and the buffer layer 205 can be disposed therein, such that the buffer layer 205 can have a shape in which its area increases toward its upper part.

[0120] In this way, because the side surface of the etch stop structure 250 has an acute angle of inclination, the internal common source line CSL and buffer layer 205 can also be enlarged, so that their area increases towards the top.

[0121] In this case, the etch stop structure 250 can also be configured such that the protruding portion of the partition region MS is buried inside.

[0122] refer to Figure 6 In addition to the shape of the etch stop structure 250, the semiconductor device 10b and Figure 4B The semiconductor device 10 is the same.

[0123] Specifically, in the semiconductor device 10b, at least one etch stop structure 250 extends in the cell region R1 in the X direction, and the etch stop structures 250 are spaced apart from each other in the Y direction.

[0124] The center of the width of the upper surface of the etch stop structure 250 in the Y direction can be defined as the second axis. 1. And the central axis of the channel structure CH closest to the etch stop structure 250 can be defined as the channel axis. c. In this case, each etch stop structure 250 may at least partially overlap with the separating region MS.

[0125] Specifically, in Figure 6 In the semiconductor device 10b, the second axis of the etch stop structure 250 1 can be set as the first axis relative to the center of the width of the dividing region MS in the Y direction. 0 is offset by a second distance d2 in the Y direction.

[0126] In this configuration, at least a portion of the etch stop structure 250 may overlap with the partition region MS and may be configured to cover, for example, at least half of a protruding portion of the partition region MS. Alternatively, the etch stop structure 250 may be configured to cover at least a portion of the upper surface of the partition region MS.

[0127] Even if the partition region MS overlapping with the etch stop structure 250 is not coaxial, the second axis of the etch stop structure 250 1. The channel axis of the closest channel structure CH The separation distance between c can also satisfy the first distance d1. Therefore, the common source line CSL can fully cover and contact the exposed channel layer 240 of the channel structure CH. In addition, even if the etch stop structure 250 is partially offset from the separation region MS, the first separation distance I1 with the adjacent etch stop structure 250 can be formed to satisfy the critical distance or less, thereby maintaining the effect of preventing surface depressions during the planarization process.

[0128] refer to Figure 7 Except for the shape of the protruding portion 240a of each channel structure CH, including the head CH_a, the semiconductor device 10c and Figure 4A The semiconductor device 10 is the same.

[0129] Specifically, the channel structure CH may further include a head CH_a with an enlarged width at one end. The head CH_a of the channel structure CH may have a width W4 larger than the width of the protrusion 240a of the channel layer 240. The head CH_a of the channel structure CH may be formed by a stop for consistently maintaining the depth of the channel hole during the manufacturing process, but the example embodiments are not limited thereto.

[0130] The head CH_a can have different widths in the Z direction, and for example, it can have a width that decreases towards its upper part, but the example embodiment is not limited to this, and the width of the upper part of the head CH_a and the width of the lower part of the head CH_a can be formed to be the same. In this case, the width W4 of the lower part of the largest head CH_a can be formed to be greater than the width of the non-protruding portion 240b of the channel layer 240.

[0131] In this case, the width W4 of the head CH_a can satisfy approximately 1 / 2 to 3 / 5 of the separation distance between the channel structure CH and the adjacent channel structure CH.

[0132] Even if the head CH_a is formed, it can still be used with... Figure 4A The first part of the channel structure CH is formed in the same way as in the example, and the height of the protrusion 240a can be the same as the first length h1, and the head CH_a can be formed to have a length less than the first length h1 of the protrusion 240a. The protrusion 240a of the channel layer 240 can be disposed on the outermost surface of the head CH_a, and its interior can be filled with a buried insulating layer 247, or it can be formed entirely together with the channel layer 240 according to the example embodiment.

[0133] In this way, when the head CH_a is formed on the protrusion 240a, the contact area between the first conductive layer 201 and the channel layer 240 is increased due to the enlarged end, thereby increasing the charge inflow.

[0134] Not only the channel structure CH, but also other vertical structures (such as support structure 265 and contact plug 270) may include a head. The head of contact plug 270 may also be formed by a stop for consistently maintaining the depth of the contact hole during the manufacturing process, but the example embodiment is not limited thereto.

[0135] In the following text, reference will be made to Figure 8 and Figure 9 Describe an example implementation. Figure 8 and Figure 9 This is a top view of a semiconductor device according to an example embodiment.

[0136] refer to Figure 8 In addition to the arrangement of multiple etch stop structures 250, the semiconductor device 10d and Figure 1 The semiconductor device 10 is the same.

[0137] exist Figure 8 In the semiconductor device 10d, the etch stop structure 250 extends in the cell region R1 in the X direction, and the etch stop structures 250 are spaced apart from each other in the Y direction.

[0138] In this case, the etch stop structure 250 can overlap with the separator region MS in the Z direction within the cell region R1.

[0139] In this configuration, the partition region MS may include a first partition region MSa that overlaps with the etch stop structure 250 and a second partition region MSb that does not overlap with the etch stop structure 250. The shape and size of the first partition region MSa and the second partition region MSb may be substantially the same.

[0140] Specifically, the etch stop structure 250 can be configured to cover the upper end and protruding portion of each first partition region MSa. The second width W2 of the etch stop structure 250 in the Y direction can be greater than the first width W1 of each first partition region MSa in the Y direction, and the third length h3 of the etch stop structure 250 in the Z direction can be greater than the second length h2 of the protruding portion of the first partition region MSa exposed to the upper part of the stacked structures GS1 and GS2, so that the first partition region MSa is not exposed to the outside of the etch stop structure 250.

[0141] Because the second separation region MSb does not overlap with the etch stop structure 250, the second separation region MSb can be configured to be in direct contact with the first conductive layer 201 of the common source line CSL within the cell region R1.

[0142] The first dividing region MSa and the second dividing region MSb can be set in alternating rows. Therefore, the etch stop structure 250 covering the second dividing region MSb can have a second dividing distance da intersecting with the two blocks BLK within the cell region R1.

[0143] The second separation distance da can be greater than Figure 1 The first separating distance I1 can be less than the critical distance. Therefore, with Figure 1 A common source line with a larger area can be formed to have a common plate shape on two blocks, but the example embodiment is not limited to this.

[0144] For example, a first dividing region MSa can be set in every Kth dividing region MS, and K can be 2 to 4. That is, within the critical distance range, the common source line CSL can be set physically continuously to include multiple blocks.

[0145] Therefore, at least one second separation region MSb can be disposed at the bottom of a common source line CSL, but the common source line CSL can be formed to have a flat bottom region by forming a sufficiently thick first conductive layer 201 covering the channel structure CH and planarizing it by heat treatment.

[0146] refer to Figure 9 In addition to the arrangement of multiple etch stop structures 250, the semiconductor device 10e and Figure 1 The semiconductor device 10 is the same.

[0147] exist Figure 9 In the semiconductor device 10e, etch stop structures 250 extend in the X direction, and at least some etch stop structures 250 are spaced apart from each other in the Y direction within the cell region R1.

[0148] The etch stop structure 250 can overlap with the separator region MS in the Z direction within the cell region R1.

[0149] On a separated region MS, the etch stop structure 250 may include at least one stop pattern 250I in which its short side surface is exposed.

[0150] The etch stop structure 250 may include a stop pattern 250I, similar to the etch stop structure 250 on the dividing region MS of the first row, and the stop pattern 250I may not be connected to the protective layer 251 of the extension region R2 and may be spaced apart from the protective layer 251 by a first gap Ia at the boundary between the unit region R1 and the extension region R2. The first gap Ia may be less than a critical distance.

[0151] The side surface of the stop pattern 250I can be exposed within the unit region R1 through the first gap Ia between the stop pattern 250I and the protective layer 251.

[0152] The etch stop structure 250 may include a plurality of stop patterns 250I spaced apart from each other, similar to the etch stop structure 250 on the dividing area MS of the second to fourth rows.

[0153] Multiple stop patterns 250I located on a separating region MS can have a separation distance of a second gap Ib, a third gap Ic, and a fourth gap Id, and their short-side surfaces can be spaced apart from each other. In this case, the separation distance of the stop patterns 250I in each row can be different from each other, but can be equal to or less than the critical distance.

[0154] The separation distance between stop patterns 250I on adjacent separation regions MS in the Y direction can be offset so that they do not overlap in the Y direction. In this case, "offset" does not mean that the intermediate values ​​of the separation distances do not match, but rather that the second gap Ib and the third gap Ic do not overlap at all in the Y direction, and the third gap Ic and the fourth gap Id do not overlap at all in the Y direction. In this case, the first gap Ia may also not overlap with the second gap Ib at all in the Y direction. In this way, because the separation distances between each stop pattern 250I do not overlap in the Y direction, surface depressions that may occur between the separation distances can be prevented.

[0155] Figure 9 The semiconductor device 10e can be formed such that at least some etch stop structures 250 located in the cell region R1 have a separation distance along the X direction, and thus, the common source line CSL disposed on each block can be physically connected to each other.

[0156] That is, because the first conductive layer 201 is continuously formed along the separation distance and the second conductive layer 202 and the buffer layer 205 are disposed on the first conductive layer 201, even if the planarization is advanced to the etch stop structure 250, the common source line CSL disposed in each block can have a structure in which the common source line CSL is integrated into a structure that is physically / electrically connected to each other in space along the separation distance.

[0157] Therefore, the common source line CSL of each block can be physically connected in the lower part through the upper interconnect structure 271 and 272, while ensuring structural stability.

[0158] In this case, each etch stop structure 250 may not be set on all separator regions MS, and may only be set on some separator regions MSa, such as in Figure 8 Same as in China.

[0159] Figures 10A to 10M This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Figures 10A to 10M Showing with Figure 3B The corresponding area.

[0160] refer to Figure 10A A first semiconductor structure (S1: PERI) can be formed on the first substrate 101. The first semiconductor structure includes circuit elements 120 forming the peripheral circuit structure PERI, a lower interconnect structure 130, a lower bonding structure 180, and a lower cover layer 190.

[0161] A device isolation layer 110 may be formed in a first substrate 101, and a circuit gate dielectric layer 122 and a circuit gate electrode 124 may be sequentially formed on the first substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 122 may be formed on the first substrate 101, and the circuit gate electrode 124 may be formed on the circuit gate dielectric layer 122. The circuit gate dielectric layer 122 and the circuit gate electrode 124 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 122 may be formed of silicon oxide, and the circuit gate electrode 124 may be formed of at least one of polysilicon or metal silicide layers, but the exemplary embodiments are not limited thereto. A spacer layer 126 may be formed on both sidewalls of the circuit gate dielectric layer 122 and the circuit gate electrode 124, and impurities may be implanted into the active regions on both sides of the circuit gate electrode 124 of the first substrate 101 to form source / drain regions 105.

[0162] In the lower interconnect structure 130, the lower contact plug 135 may be formed by forming a portion of the lower cover layer 190, etching and removing a portion thereof, and then filling the removed portion with a conductive material. The lower interconnect line 137 may be formed, for example, by depositing a conductive material and then patterning the conductive material.

[0163] In the lower bonding structure 180, the lower bonding passage 182 may be formed by forming a portion of the lower cover layer 190, etching and removing a portion thereof, and then filling the removed portion with a conductive material. The lower bonding pad 184 may be formed, for example, by depositing a conductive material and then patterning the conductive material. The lower bonding structure 180 may be formed, for example, by a deposition process or a plating process. The lower bonding insulating layer 186 may be formed by covering a portion of the upper surface and side surface of the lower bonding pad 184 and then performing a planarization process until the upper surface of the lower bonding pad 184 is exposed.

[0164] The lower cover layer 190 can be formed from multiple insulating layers. The lower cover layer 190 can be part of each operation that forms the lower interconnect structure 130 and the lower bonding structure 180. As a result, a first semiconductor structure S1 can be formed as the peripheral circuit structure PERI.

[0165] refer to Figure 10B The manufacturing process for the second semiconductor structure (S2: CELL) can then begin.

[0166] refer to Figure 10B The fabrication process for the second semiconductor structure (S2: CELL) can then begin. On the substrate 300 (SUB), sacrificial insulating layers 218 and interlayer insulating layers 220 can be alternately stacked to form molded structures MS1 and MS2, and sacrificial vertical structures can be formed at the locations where each vertical structure is formed.

[0167] The lower molding structure MS1 can be formed on the substrate 300 at the height set by the lower channel structure CH1.

[0168] The substrate 300 may include semiconductor materials, and may include, for example, group IV semiconductors, group III-V compound semiconductors or group II-VI compound semiconductors.

[0169] The sacrificial insulating layer 218 may be a layer in which at least a portion is replaced by a portion of the gate electrode 230 through a subsequent process. The sacrificial insulating layer 218 may be formed of a different material than the interlayer insulating layer 220. For example, the interlayer insulating layer 220, as well as the uppermost interlayer insulating layer 222, the middle interlayer insulating layer 223, and the lowermost interlayer insulating layer 225, may be made of at least one of silicon oxide or silicon nitride, and the sacrificial insulating layer 218 may be formed of a different material selected from silicon, silicon oxide, silicon carbide, and silicon nitride than the material of the interlayer insulating layer 220. In the example embodiment, the thickness of the interlayer insulating layer 220 may not all be the same. Furthermore, the thickness of the interlayer insulating layer 220 and the thickness of the sacrificial insulating layer 218, as well as the number of films included therein, may be varied from those shown.

[0170] The interlayer insulating layer 220 and the sacrificial insulating layer 218 included in the lower molded structure MS1 are alternately stacked on the substrate 300.

[0171] The gate pad region can be formed by repeatedly performing photolithography and etching processes on the sacrificial insulating layer 218 and the interlayer insulating layer 220. The gate pad region can be formed in the extension region R2 and can be formed to include a region in which the upper sacrificial insulating layer 218 extends shorter than the lower sacrificial insulating layer 218. In the gate pad region, an asymmetrical stepped structure can be formed such that the upper surfaces and upper ends of the plurality of sacrificial insulating layers 218 are exposed upwards. However, in the example embodiment, the specific shape of the gate pad region can be varied. The sacrificial insulating layers 218 can be further formed on the stepped structure of the gate pad region such that the uppermost sacrificial insulating layer 218 in each region has a relatively thick thickness.

[0172] When forming the channel holes for forming the vertical sacrificial layers 216a and 216b, a stop structure can be formed first to consistently maintain the depth of the channel holes recessed into the substrate 300.

[0173] A stop structure can be formed in the location where the channel hole is formed in the substrate 300 using a material that has etch selectivity with respect to anisotropic etching, and the material can be, for example, a metallic material such as tungsten (W). When the channel hole is formed with the stop structure in each channel hole, the channel hole may not be formed below the stop structure due to the stop structure. Then, the stop structure can be removed through the channel hole, and depending on the shape of the stop structure, a structure with... Figure 7 The channel structure CH of the head CH_a is shown.

[0174] Next, an upper cover layer 290 covering the undermolded structure MS1 can be formed, and a first vertical sacrificial layer 216a penetrating the undermolded structure MS1 can be formed.

[0175] The first vertical sacrificial layer 216a can be formed in the cell region R1 at a position corresponding to the lower part of the lower channel structure CH1. The first vertical sacrificial layer 216a can be formed by forming holes to penetrate the lower molded structure MS1, depositing sacrificial layer material in the holes, and performing a planarization process. The holes can include holes corresponding to the channel structure CH, the support structure 265, the contact plug 270, and the external contact passage 275. The vertical sacrificial layer including the first vertical sacrificial layer 216a can include at least one of, for example, TiN or polysilicon.

[0176] Next, the sacrificial insulating layer 218 and the interlayer insulating layer 220 included in the upper molded structure MS2 can be alternately stacked on the lower molded structure MS1 to form a stepped structure. An upper cover layer 290 can be formed on the edge region and the stepped structure, and a second vertical sacrificial layer 216b can be formed.

[0177] Each component of the upper molded structure MS2 can be formed in the same manner as the lower molded structure MS1.

[0178] The second vertical sacrificial layer 216b can be formed to be connected to the first vertical sacrificial layer 216a. The second vertical sacrificial layer 216b can be formed by depositing the same material as the first vertical sacrificial layer 216a (e.g., polysilicon). In addition, the vertical sacrificial layers for the support structure 265, the vertical sacrificial layers for the contact plug 270, and the vertical sacrificial layers for the external contact passage 275 can all be formed by depositing the same material (e.g., polysilicon).

[0179] like Figure 10C As shown, a channel structure CH, which penetrates the sacrificial insulating layer 218 and the interlayer insulating layer 220, can be formed on the substrate 300.

[0180] The channel structure CH can be formed by forming upper vias on vertical sacrificial layers 216a and 216b and then removing the vertical sacrificial layers 216a and 216b to form a via-shaped channel, and filling the vias with multiple layers. The multiple layers may include an information storage structure 245, a channel layer 240, a buried insulating layer 247, and a channel pad 249. The upper via in the channel can be formed by anisotropically etching an upper stacked structure of sacrificial insulating layer 218 and interlayer insulating layer 220 using separate mask layers. The lower via in the channel can be formed by removing the vertical sacrificial layers exposed through the upper via.

[0181] Due to the heights of the molded structures MS1 and MS2, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the substrate 300. The channel structure CH can be formed such that a portion of the substrate 300 is recessed according to the depth of the channel holes.

[0182] The information storage structure 245 can be formed to have a uniform thickness. The information storage structure 245 can be formed wholly or partially in this operation, and a portion extending vertically along the channel structure CH to the substrate 300 can be formed in this operation. The channel layer 240 can be formed on the information storage structure 245 within the channel structure CH. The buried insulating layer 247 can be formed to fill the channel structure CH and can be an insulating material. The channel pads 249 can be formed of a conductive material (e.g., polysilicon). The support structure 265 for the extended region R2 (see...) Figure 2 The support structure 265 can also be formed in a similar manner. Specifically, the support structure 265 can be formed by removing the vertical sacrificial layer to form a support hole and then filling the support hole with a support insulating layer. In this case, the vertical sacrificial layer in the region corresponding to the contact plug 270 can be removed, and a contact insulating layer and a contact sacrificial layer can be formed.

[0183] like Figure 10D As shown, a partition opening OP1 can be formed in the region corresponding to the partition region MS. The partition opening OP1 can be formed as a line that intersects the cell region R1 and the extension region R2 in the X direction and penetrates the molded structures MS1 and MS2 in the Z direction. Each partition opening OP1 can be formed to open a portion of the substrate 300.

[0184] like Figure 10E As shown, wet etching can be performed by separating the opening OP1 to selectively remove the sacrificial insulating layer 218 relative to the interlayer insulating layer 220, thereby forming the gate electrode 230.

[0185] The gate electrode 230 may be formed by depositing a conductive material in a region from which the sacrificial insulating layer 218 has been removed. The conductive material may include a metal, polysilicon, or a metal silicide. In some example embodiments, a portion of the gate dielectric layer may be formed first before the gate electrode 230 is formed.

[0186] After the gate electrode 230 is formed, a gate separation insulating layer 264 can be formed within the separation opening OP1, which is formed to correspond to the separation region MS, and at least one upper gate electrode 230U can be etched to form an insulating region SS. In this case, a contact plug 270 can be formed in the extension region R2.

[0187] refer to Figure 10F It can form an upper interconnection structure 271 and 272 including a post 272 and an upper interconnection line 271, and can form an upper bonding structure 280.

[0188] In unit region R1, post 272 can be formed to connect to channel structure CH. In extension region R2, post 272 can be formed to connect to contact plug 270. Alternatively, post 272 can be formed in extension region R2 to connect to external contact passage 275. Each post 272 can be connected upwards and downwards to upper interconnect 271, and can be connected in multiple layers via individual plugs.

[0189] Next, the upper bonding structure 280 can be formed in a similar manner to forming the lower bonding structure 180. Therefore, a second semiconductor structure S2, serving as a memory cell structure (CELL), can be formed. However, in the manufacturing process of the semiconductor device 10, the second semiconductor structure S2 may also include a substrate 300.

[0190] Referring to 10G, the stacked structures GS1 and GS2 on which the substrate 300 is formed can be transferred to the carrier substrate 310 and can be inverted so that the substrate 300 is exposed upward.

[0191] Specifically, when the stacked structures GS1 and GS2 are inverted so that the upper bonding structure 280 contacts the carrier substrate 310, the channel structure CH, the separator region MS, the contact plug 270, and the external contact passage 275 located below the upwardly exposed substrate 300 can be reversed, increasing their width downwards. Next, the substrate 300 can be removed, and the lowest interlayer insulating layer 222, as well as the lowest ends of the channel structure CH, the separator region MS, and the contact plug 270, can be formed in a protruding state. In this case, a separate layer as an etch-preventing film for the channel structure CH can be omitted between the substrates 300, allowing for significantly faster removal of the substrate 300. Next, a preliminary protective layer 251P can be formed on the uppermost surface of the exposed stacked structures GS1 and GS2. The preliminary protective layer 251P can be formed to cover the entire semiconductor device 10 and has a predetermined thickness, which can be formed to have a third length h3 corresponding to the height of the etch-stop structure 250, and can be 300 nm to 500 nm. The initial protective layer 251P can be completely subjected to plasma CVD by applying PE-SiN to it, and in this case, plasma CVD can be performed in a hydrogen environment, thereby forming a H-rich SiN layer containing a large amount of hydrogen.

[0192] like Figure 10H As shown, the initial protective layer 251P can be patterned to form an opening OP2 that defines each block within the unit region R1.

[0193] The opening OP2 can be formed until the upper surface of the bottommost interlayer insulating layer 222 is exposed, and the opening OP2 can be formed between the linear etch stop structures 250, so that... Figure 2 The etch stop structure 250 remains within the cell region R1. The opening OP2 can be formed by selectively removing the initial protective layer 251P via the mask pattern ML, and can be formed with a sloping side surface such that the upper width of the opening OP2 is greater than its lower width, or it can be formed vertically. The side surface of the etch stop structure 250 can be formed by dry etching without sloping, and when the etch stop structure 250 is placed on the separator region MS, the etch stop structure 250 at the lower part of the mask pattern ML can be etched vertically so as not to recess inward along its side surface, thereby securely supporting the layer structure that will be subsequently stacked.

[0194] Next, as Figure 10IAs shown, the information storage structure 245 on the second portion of the channel structure CH exposed within the opening OP2 can be removed. The information storage structure 245 can be removed by photolithography and etching processes such as wet etching and / or dry etching. As a result, within the opening, the second portion of the channel structure CH protruding onto the stacked structures GS1 and GS2 can be exposed to the channel layer 240, thereby allowing the protrusion 240a to be formed. Therefore, when subsequent processes are performed, the channel layer 240 of the second portion can directly contact the first conductive layer 201. In this case, an etching process for the continuous removal of oxide films, nitride films, and oxide films can be performed, and a portion of the uppermost interlayer insulating layer 222, including oxide, can be etched together, such that the upper surface of the uppermost interlayer insulating layer 222 within the opening OP2 can be lowered to a level lower than the level of the lower surface of the etch stop structure 250 and the lower surface of the protective layer 251, but the example embodiment is not limited to this.

[0195] like Figure 10J As shown, the first conductive layer 201 can be formed to cover the entire semiconductor device 10. The first conductive layer 201 can be formed by depositing a semiconductor layer (specifically, a crystalline silicon layer, such as a polycrystalline silicon layer 201a). In this case, the polycrystalline silicon layer 201a, which is formed entirely on the upper surface of the semiconductor device, can be formed to have an inflection protruding along the channel structure CH within the opening OP2. Therefore, the thickness of the polycrystalline silicon layer 201a above the protective layer 251 and the thickness of the polycrystalline silicon layer 201a within the opening can be different from each other.

[0196] In this case, a Melt Laser Annealing (MLA) process can be performed to activate the polysilicon layer 201a. The MLA process involves diffusing impurities in the polysilicon layer 201a and recrystallizing the crystal through laser annealing, performed using high temperature and high-energy lasers, and simultaneously applied to the entire semiconductor device. During this MLA process, the extended region R2 and edge region EA in which the protective layer 251 is formed prevent energy and heat from being transferred downwards because the protective layer 251 absorbs high energy and heat. Therefore, the copper-containing upper interconnect structures 271 and 272 located below the stacked structures GS1 and GS2 are unaffected, thus preventing defects caused by copper metal diffusion. Through this MLA process, when the polysilicon layer 201a melts and then recrystallizes, the upper surface of the polysilicon layer 201a, which has tortuous sections within the opening, can be flattened to form the first conductive layer 201. Therefore, the upper surface of the first conductive layer 201 within the unit region R1 can be flat, and its thickness can be greater than the thickness of the first conductive layer 201 located on the etch stop structure 250.

[0197] like Figure 10K As shown, a preliminary second conductive layer 202P can be formed on the first conductive layer 201, and a preliminary buffer layer 205P can be formed continuously. Specifically, the preliminary second conductive layer 202P can be formed by continuously depositing an ohmic contact layer, a conductive metal layer, and a diffusion barrier, and the thickness of the conductive metal layer can be formed to have a significantly large value. The preliminary second conductive layer 202P can be completely covered, and the preliminary buffer layer 205P can be formed conformally, and an oxide film (e.g., a silicon oxide film) can be formed as the preliminary buffer layer 205P. The preliminary second conductive layer 202P and the preliminary buffer layer 205P can also be deposited and disposed on the entire semiconductor device 10.

[0198] like Figure 10L As shown, the first conductive layer 201, the second conductive layer 202, and the buffer layer 205 can be disposed within the block of the opening OP2, which serves as the unit region R1, and can be etched so as not to extend into the extension region R2 and the edge region EA. The etching of the first conductive layer 201, the second conductive layer 202, and the buffer layer 205 can be performed by a planarization process (e.g., chemical mechanical polishing (CMP)), and polishing can be performed such that the planarization terminates on the upper surface of the etch stop structure 250 and the protective layer 251, which have the same height.

[0199] In this way, the first conductive layer 201, the second conductive layer 202 and the buffer layer 205 can all be etched by a planarization process, so that the upper surface of the buffer layer 205, the upper end of the first conductive layer 201 and the upper end of the second conductive layer 202 and the upper surface of the etch stop structure 250 form a coplanar surface.

[0200] In addition, by planarization, the etch stop structure 250 can be set at a separation distance equal to or less than the critical distance, thereby preventing surface depression of the buffer layer 205 set above a relatively wide area, thereby improving physical reliability.

[0201] like Figure 10MAs shown, a hydrogen supply layer 213 can be continuously formed on the first insulating layer 211 to form an upper insulating structure 210, and a passivation layer 215 can be formed to complete the upper structure. Specifically, before further forming the hydrogen supply layer 213 on the first insulating layer 211, the first insulating layer 211 and the buffer layer 205 can be opened to form source contact paths 255 in the buffer layer 205, and then source interconnects 256 connected to the source contact paths 255 can be formed within the first insulating layer 211. Multiple source contact paths 255 can be formed within a single semiconductor device to simultaneously transmit a common source voltage to a common source line CSL, and the source interconnects 256 for this purpose can be interconnected with each other. The passivation layer 215 can be formed to cover the common source line CSL. The passivation layer 215 can be planarized by a polishing process such as a grinding process or a chemical mechanical polishing process. A portion of the passivation layer 215 can be removed by a subsequent process to form input / output pad regions 258, but the example embodiment is not limited thereto.

[0202] The first semiconductor structure S1, which serves as the peripheral circuit structure PERI, and the second semiconductor structure S2, which serves as the storage cell structure CELL, can be connected to each other.

[0203] The first semiconductor structure S1 and the second semiconductor structure S2, which are separate from the carrier substrate 310, can be connected by applying pressure to the downward bonding pad 184 and the upper bonding pad 284 to bond them together. The downward bonding insulating layer 186 and the upper bonding insulating layer 286 can be bonded and connected by applying pressure to them. The second semiconductor structure S2 can be bonded to the first semiconductor structure S1 such that the upper bonding pad 284 can face downwards. The first semiconductor structure S1 and the second semiconductor structure S2 can be directly bonded without the intervention of an adhesive such as a separate adhesive layer.

[0204] Figure 11 This is a schematic diagram illustrating a data storage system including semiconductor devices according to an example embodiment.

[0205] refer to Figure 11 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device, including one or more semiconductor devices 1100.

[0206] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, related to a reference. Figures 1 to 9 The NAND flash memory device provided is consistent with the above description. Semiconductor device 1100 may include a first semiconductor structure 1100F and a second semiconductor structure 1100S located on the first semiconductor structure 1100F. According to an example embodiment, the first semiconductor structure 1100F may be disposed close to the second semiconductor structure 1100S. The first semiconductor structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second semiconductor structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR located between the bit line BL and the common source line CSL.

[0207] In the second semiconductor structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to an example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0208] According to the example embodiment, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0209] According to an example embodiment, the lower transistors LT1 and LT2 may include series-connected ground selection transistors LT1 and LT2. The upper transistors UT1 and UT2 may include series-connected string selection transistors UT1 and UT2.

[0210] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0211] In the first semiconductor structure 1100F, decoder circuit 1110 and page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). Decoder circuit 1110 and page buffer 1120 can be controlled by logic circuit 1130. Semiconductor device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output interconnects 1135 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0212] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0213] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0214] Figure 12 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment.

[0215] refer to Figure 12 A data storage system 2000 according to an example embodiment of the present disclosure may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0216] The motherboard 2001 may include a connector 2006 having multiple pins coupled to an external host. The number and arrangement of the multiple pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. According to an example embodiment, the data storage system 2000 may communicate with the external host via any of the following interfaces: Universal Serial Bus (USB), PCI-Express, Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). According to an example embodiment, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied by the external host to the controller 2002 and the semiconductor package 2003.

[0217] The controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the data storage system 2000.

[0218] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can also be used as a cache memory and can provide space for temporary data storage during control operations on the semiconductor package 2003. When DRAM 2004 is included in the data storage system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0219] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0220] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 11 The input / output pads 1101, and may include Figure 3A The pad region 258. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the above-mentioned references. Figures 1 to 9 The semiconductor device described.

[0221] According to an example embodiment, the connection structure 2400 may be a bonding wiring that electrically connects the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wiring and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs), rather than via a bonding wiring connection structure 2400.

[0222] According to an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. According to an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via interconnects formed on the interposer substrate.

[0223] While various aspects of the exemplary embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, said semiconductor device comprising: A first semiconductor structure, the first semiconductor structure including a first substrate, circuit elements located on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure; as well as A second semiconductor structure is located on top of the first semiconductor structure. The second semiconductor structure includes: A stacked structure comprising an interlayer insulating layer and a gate electrode stacked along a first direction, the stacked structure being located in a first region and a second region; An upper interconnect structure is located below the stacked structure; An upper bonding structure, which is connected to the upper interconnect structure and bonded to the lower bonding structure; A trench structure comprising a first portion penetrating the stacked structure along the first direction and a second portion extending upward from the first portion, the trench structure being located within the first region; An etch stop structure is located on the stacked structure within the first region, the etch stop structure extends along a second direction perpendicular to the first direction, and is spaced along a third direction perpendicular to both the first and second directions; A common source conductive layer, wherein the common source conductive layer is located on the stacked structure between the etch stop structures in the first region, and the common source conductive layer is connected to the second portion of the channel structure; and A buffer layer is located on the common source conductive layer.

2. The semiconductor device of claim 1, further comprising a protective layer located on the stacked structure in the second region. in, The protective layer and the etch-stop structure share a common material.

3. The semiconductor device according to claim 2, wherein, The protective layer and the etch-stop structure comprise nitrides.

4. The semiconductor device according to claim 2, wherein, The upper surface of the etching stop structure is at the same horizontal height as the upper surface of the protective layer.

5. The semiconductor device according to claim 2, wherein, At least one of the etch stop structures extends along the second direction in the first region and includes an end connected to the protective layer.

6. The semiconductor device according to claim 2, wherein, The common source conductive layer includes a bottom region located on the stacked structure and a side region that curves from the bottom region along either side surface of the etch stop structure and the side surface of the protective layer. The thickness of the bottom region is greater than the thickness of the side region.

7. The semiconductor device according to claim 6, wherein, The upper surface of the buffer layer and the upper end of the side region of the common source conductive layer form a coplanar surface.

8. The semiconductor device according to claim 1, wherein, The common source conductive layer includes: A first conductive layer, the first conductive layer being in contact with the second portion of the channel structure; and A second conductive layer, which lies above the first conductive layer along the first conductive layer and comprises a material different from the first conductive layer, is further described. The buffer layer is located on the second conductive layer.

9. The semiconductor device according to claim 1, wherein, The upper surface of the buffer layer and the upper surface of the etch stop structure are at the same horizontal height.

10. The semiconductor device according to claim 1, wherein, The etch stop structure is spaced apart by a reference distance or less along the third direction, and The reference distance ranges from 3 μm to 4 μm.

11. The semiconductor device according to claim 10, wherein, The etch stop structure has the same separation distance along the third direction.

12. The semiconductor device according to claim 1, wherein, The etch stop structure includes stop patterns spaced apart along the second direction.

13. The semiconductor device according to claim 1, wherein, The channel structure is one of multiple channel structures. Each of the etch stop structures is spaced apart from the nearest channel structure among the plurality of channel structures by a first distance or a greater distance, and Wherein, the first distance is the channel pitch of the plurality of channel structures.

14. A semiconductor device, the semiconductor device comprising: A stacked structure comprising an interlayer insulating layer and a gate electrode stacked along a first direction, the stacked structure being located in a first region and a second region; A separating region, which penetrates the stacked structure along a first direction within the first region and the second region, extends along a second direction perpendicular to the first direction, and is spaced apart along a third direction perpendicular to both the first and second directions; A channel structure that penetrates the stacked structure along the first direction within the first region; An etch stop structure is located on the stacked structure within the first region, and the etch stop structure extends along the second direction; A common source conductive layer, wherein the common source conductive layer is located on the stacked structure between the etch stop structures in the first region and is connected to the channel layer of the channel structure; as well as A buffer layer, located on the common source conductive layer and comprising an insulating material, The upper surface of the buffer layer and the upper surface of the etch stop structure are at the same horizontal height.

15. The semiconductor device according to claim 14, wherein, In the first region, one of the etch stop structures covers at least a portion of one of the separated regions.

16. The semiconductor device according to claim 15, wherein, The width of the etch stop structure along the third direction is greater than the width of the partition region along the third direction, and Wherein, the length of the etch stop structure along the first direction is greater than the protruding length of the dividing region on the stacked structure along the first direction.

17. The semiconductor device according to claim 15, wherein, The protruding area in the partition region on the stacked structure is completely covered by the etch stop structure in the first region.

18. The semiconductor device according to claim 15, wherein, At least a portion of one of the separated regions is exposed within the first region from the corresponding etch stop structure in the etch stop structure and is in contact with the common source conductive layer.

19. The semiconductor device of claim 14, further comprising a protective layer located in a plate shape on the stacked structure in the second region. in, The protective layer and the etch stop structure comprise a common material, and The upper surface of the protective layer and the upper surface of the etching stop structure form a coplanar surface.

20. A semiconductor device, the semiconductor device comprising: A stacked structure comprising an interlayer insulating layer and a gate electrode stacked along a first direction, the stacked structure being located in a first region and a second region; A separating region, which penetrates the stacked structure along a first direction within the first region and the second region, extends along a second direction perpendicular to the first direction, and is spaced apart along a third direction perpendicular to both the first and second directions; A channel structure that penetrates the stacked structure along the first direction within the first region; An etch stop structure is located on the stacked structure and extends along the second direction within the first region; A protective layer is located on the stacked structure within the second region; A common source conductive layer, wherein the common source conductive layer is located on the stacked structure between the etch stop structures in the first region and is connected to the channel layer of the channel structure; as well as A buffer layer, located on the common source conductive layer and comprising an insulating material, Wherein, the upper surface of the common source conductive layer and the upper surface of the etch stop structure are at the same horizontal height, and Wherein, at least one of the etch stop structures includes an end connected to the protective layer and extends from the protective layer along the second direction.

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