A neuromorphic primitive circuit based on a two-dimensional material ferroelectric floating gate transistor and a preparation method thereof

Abstract

The application belongs to the technical field of neuromorphic computing hardware, and particularly relates to a neuromorphic cell circuit based on a two-dimensional material ferroelectric floating gate transistor and a preparation method thereof. The neuromorphic cell circuit adopts a synapse and neuron nested topological structure, that is, one ferroelectric floating gate transistor is used as an electronic synapse, and a threshold switch memristor and a capacitor are used to cooperatively constitute a biological neuron function module. The application utilizes polarization reversal of a ferroelectric insulating layer and a floating gate mechanism to realize dynamic nonvolatile adjustment of a two-dimensional semiconductor channel conductance; in combination with a volatile threshold switch characteristic of a memristor and a charging and discharging mechanism of a capacitor, the synapse plasticity and action potential leakage integral-discharge behavior of a biological nervous system are perfectly simulated. The application can realize extremely high device consistency and yield; the circuit has sub-nanowatt ultra-low power consumption and high-density integration potential, and provides a device-level solution for the next generation of underlying neuromorphic hardware.

Description

Technical Field

[0001] This invention belongs to the field of neuromorphic computing hardware technology, specifically relating to a neuromorphic primitive circuit based on a two-dimensional material ferroelectric floating gate transistor and its fabrication method. Background Technology

[0002] Neuromorphic computing, as an important direction for breaking through the "memory wall" and "power wall" bottlenecks of the traditional von Neumann computing architecture, is based on directly simulating the spatiotemporal information processing mechanism of biological nervous systems through underlying hardware devices. The basic units of biological nervous systems are mainly composed of synapses (responsible for weighted signal transmission and plastic memory) and neurons (responsible for signal leakage integration and threshold discharge).

[0003] However, current neuromorphic circuits based on traditional CMOS processes face severe energy efficiency bottlenecks and device miniaturization challenges. Most mainstream solutions employ discrete modular designs, physically separating the synaptic array from the peripheral neuron circuitry. This design not only leads to significant interconnect delays and parasitic capacitance dissipation, but also generally results in high system-level static power consumption. Furthermore, traditional silicon-based transistors face severe short-channel effects and leakage current problems at the nanoscale, making it difficult to meet the demands of ultra-low-power edge computing.

[0004] In recent years, atomically thin two-dimensional semiconductor materials have become highly promising next-generation channel materials due to their excellent electrostatic control capabilities and dangling bond-free surface properties. Combining two-dimensional materials with memristors is a hot topic in constructing novel neural circuits. However, achieving high-yield and high-stability heterogeneous integration of "synapses and neurons" in an extremely compact physical space, while simultaneously satisfying extremely low leakage current and highly consistent discharge thresholds, remains a major challenge in the field of microelectronics manufacturing. Summary of the Invention

[0005] The purpose of this invention is to provide a neuromorphic primitive circuit based on two-dimensional material ferroelectric floating gate transistor and its fabrication method that overcomes the shortcomings of existing distributed circuits, such as large area, high power consumption and poor consistency of traditional memristors, and achieves extremely low power consumption and high yield.

[0006] The neuromorphic primitive circuit based on a two-dimensional material ferroelectric floating gate transistor provided by this invention adopts a synapse-neuron nested structure (1F-1M-1C), that is, a ferroelectric floating gate transistor acts as an electronic synapse, which, together with a threshold-switched memristor and a capacitor, constitutes a biological neuron functional module; specifically, it includes: an insulating substrate; a ferroelectric floating gate transistor located on the surface of the insulating substrate, acting as an electronic synapse, the channel layer of the ferroelectric floating gate transistor being composed of a two-dimensional semiconductor material, used to simulate the dynamic update and memory characteristics of biological synaptic conductance; a threshold-switched memristor, connected in series with the ferroelectric floating gate transistor, used to simulate the pulse threshold regulation and dynamic discharge behavior of biological neurons; and a capacitor, connected in parallel with the threshold-switched memristor, used to realize the leakage integral-discharge characteristics of the neuron; wherein, the ferroelectric floating gate transistor, the threshold-switched memristor, and the capacitor are heterogeneously integrated on the same insulating substrate surface through multilayer metal interconnects to form a 1F-1M-1C primitive circuit.

[0007] For the ferroelectric floating gate transistor and threshold-switched memristor, by selecting the polarization reversal of the ferroelectric insulating layer and the floating gate charge storage mechanism, the linear and high-precision dynamic adjustment of the channel conductance of the two-dimensional material can be achieved, which is beneficial to perfectly simulating synaptic weights; and by introducing a barrier layer in the threshold-switched memristor to limit the diffusion of metal ions, the consistency and yield of the device can be significantly improved, thereby perfectly combining the capacitor charging and discharging mechanism to simulate the leakage integral-discharge behavior of biological neurons.

[0008] Preferably, the ferroelectric floating gate transistor has a bottom-gate structure, comprising, from bottom to top:

[0009] Back gate electrode;

[0010] A barrier layer, wherein the barrier layer is made of a ferroelectric material;

[0011] The floating gate layer, located above the barrier layer, is made of a high work function metal and is used for charge trapping and storage.

[0012] The tunneling layer, located above the floating gate layer, is composed of an insulating medium;

[0013] And a two-dimensional semiconductor channel layer located above the tunneling layer and a source electrode and a drain electrode in contact with the channel layer.

[0014] Preferably, the back gate electrode material of the ferroelectric floating gate transistor is a Ti / Pt multilayer metal;

[0015] Preferably, the barrier layer material of the ferroelectric floating gate transistor is HZO with a thickness of 10-20 nanometers;

[0016] Preferably, the floating gate layer material of the ferroelectric floating gate transistor is Pt, with a thickness of 1-5 nanometers;

[0017] Preferably, the tunneling layer material of the ferroelectric floating gate transistor is HfO2, with a thickness of 5-10 nanometers;

[0018] Preferably, the two-dimensional semiconductor channel layer material of the ferroelectric floating gate transistor is selected from monolayer MoS2 with a thickness of 0.5-1.0 nanometers;

[0019] The threshold-switched memristor has a vertical sandwich structure, comprising, from bottom to top: a bottom electrode, a resistive switching layer, an active layer, and a top electrode; wherein:

[0020] The bottom electrode is selected from Ti / Pt multilayer metals;

[0021] A resistive switching layer, located above the bottom electrode, is made of SiO2 and has a thickness of 8-15 nanometers;

[0022] The active layer and top electrode are located on the resistive switching layer and are composed of a TiW alloy layer and an Ag metal layer stacked together. The TiW alloy layer contacts the resistive switching layer to suppress the lateral random diffusion of Ag ions. The thickness of the TiW alloy layer is 0.5-2 nanometers and the thickness of the Ag metal layer is 15-35 nanometers.

[0023] This invention also provides a method for fabricating the neuromorphic primitive circuit based on a two-dimensional material ferroelectric floating gate transistor. Specifically, it reduces system interconnect delay and parasitic power consumption through a nested synapse-neuron hardware structure, thereby promoting high-density integration; it achieves extremely high consistency and extremely high device yield by introducing a TiW alloy barrier layer to suppress the random diffusion of Ag ions; the heterogeneous integration of the primitive circuit is achieved through step-by-step deposition and two-dimensional material-assisted transfer, and each device unit is tightly coupled on the same substrate through multilayer metal interconnects; the specific steps are as follows:

[0024] (1) Back gate electrode and bottom electrode are fabricated on an insulating substrate using photolithography and physical vapor deposition processes to form the back gate electrode of a ferroelectric floating gate transistor and the bottom electrode of a threshold switch memristor and a capacitor.

[0025] (2) A ferroelectric layer is grown on a substrate with patterned back gate electrodes using techniques such as atomic layer deposition as a barrier layer, and then a metal thin film is deposited as a floating gate layer.

[0026] (3) An insulating dielectric is grown above the floating gate layer using atomic layer deposition (ALD) as a tunneling layer; and a dielectric thin film is deposited above the bottom electrode of the memristor using physical vapor deposition (PVD) and other processes as a resistive switching layer.

[0027] (4) In an ultra-high vacuum environment, alloy layers and metal layers are deposited sequentially by electron beam evaporation to form the top active layer and top electrode of the memristor;

[0028] (5) The single-layer two-dimensional semiconductor material grown by chemical vapor deposition is transferred to the surface of the tunneling layer by a transfer method. After annealing, the transistor channel pattern and position are defined by photolithography and etching techniques.

[0029] (6) Fabricate the source, drain and interconnects by photolithography and metal thin film deposition to form the source and drain electrodes of the transistor, the upper electrode of the capacitor, and complete the metal interconnects inside the basic circuit.

[0030] In step (2), the barrier layer is a zirconium-doped hafnium oxide ferroelectric thin film grown at 200℃-300℃ using thermal atomic layer deposition.

[0031] In step (4), the pressure of the ultra-high vacuum environment is approximately 9 × 10⁻⁶. -9 Torr;

[0032] In step (5), after transferring the two-dimensional semiconductor material, it is subjected to thermal annealing at 200°C for 2-4 hours in an N2 atmosphere.

[0033] This invention provides a neuromorphic primitive circuit based on two-dimensional materials by combining the excellent controllability of ferroelectric floating gate transistors and the barrier layer design of memristor active layers. The tight physical coupling between synapses and neurons eliminates cumbersome signal transmission between modules. This circuit features sub-nanowatt ultra-low static power consumption, microsecond-level action potential response delay, extremely high device yield (100%), and switching voltage consistency, which can drive the development of high-density, high-consistency, and ultra-low-power underlying neuromorphic computing hardware technology. Attached Figure Description

[0034] Figure 1 This is a three-dimensional cross-sectional structural diagram of the neuromorphic primitive circuit of the present invention.

[0035] Figure 2 This is a schematic diagram of the topological connection principle of the neuromorphic primitive circuit of the present invention.

[0036] Figure 3 This is a flowchart illustrating the fabrication process of the neuromorphic primitive circuit of the present invention.

[0037] Figure 4 This is a test curve of the synaptic conductance update and neuronal firing characteristics of the present invention.

[0038] Figure 5 This is a schematic diagram illustrating the effect of dynamic parameter adjustment on the neuromorphic primitive circuit of the present invention.

[0039] The numbers in the diagram are as follows: 1 is the resistive switching layer of the memristor, 2 is the bottom electrode and back gate of the memristor, 3 is the blocking layer of the floating gate transistor, 4 is the source and drain electrodes and via filling, 5 is the top electrode of the memristor, 6 is the floating gate layer of the floating gate transistor, 7 is the tunneling layer of the floating gate transistor, 8 is the channel layer, and 9 is the active layer of the memristor. Detailed Implementation

[0040] The present invention will be further described below with reference to the embodiments and accompanying drawings.

[0041] In the following description, the terms "upper," "lower," "vertical," "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation.

[0042] Furthermore, regarding certain details, such as the structure, materials, dimensions, and processing techniques of the device, to enable those skilled in the art to understand, the invention may not be implemented in accordance with these specific details. Unless otherwise specified, the various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functions developed in the future.

[0043] Figure 1 and Figure 2 The topological connection principle of the neuromorphic primitive circuit, the ferroelectric floating gate transistor structure, and the cross-sectional structure of the threshold-switched memristor are illustrated respectively. The method for fabricating the neuromorphic primitive circuit of this invention includes the following steps:

[0044] Step 1: On a Si / SiO2 insulating substrate, a 5 nm / 30 nm Ti / Pt stack is deposited by ultraviolet lithography and electron beam evaporation to form the back gate electrode of the transistor, the memristor and the bottom electrode of the capacitor.

[0045] Step 2: A 16-nanometer-thick zirconium-doped hafnium oxide ferroelectric layer is grown at 250°C using thermal atomic layer deposition as the transistor blocking layer, and a 3-nanometer-thick Pt layer is deposited again as the metal floating gate layer.

[0046] Step 3: Use atomic layer deposition (ALD) to grow an 8-nanometer-thick HfO2 layer as the tunneling layer of the transistor; at the same time, use physical vapor deposition (PVD) to deposit a 10-nanometer-thick SiO2 layer as the resistive switching layer of the memristor.

[0047] Step 4: In an ultra-high vacuum environment, 1 nanometer of TiW alloy and 30 nanometers of Ag are sequentially deposited by electron beam evaporation to form the top active layer and top electrode of the memristor.

[0048] Step 5: Transfer the monolayer MoS2 to the surface of the tunneling layer, remove the auxiliary layer with toluene, anneal at 200°C for 3 hours in an N2 atmosphere, and define the transistor channel by plasma etching.

[0049] Step 6: Photolithography defines and electron beam evaporation deposits 5 nm / 35 nm Cr / Au stacks to form transistor source and drain electrodes and interconnect metal lines.

[0050] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A neuromorphic primitive circuit based on a two-dimensional material ferroelectric floating gate transistor, characterized in that, The synapse-neuron nested structure includes: an insulating substrate; a ferroelectric floating gate transistor located on the surface of the insulating substrate, serving as an electronic synapse, with the channel layer of the ferroelectric floating gate transistor composed of a two-dimensional semiconductor material to simulate the dynamic updating and memory characteristics of biological synaptic conductance; a threshold-switched memristor connected in series with the ferroelectric floating gate transistor to simulate the pulse threshold regulation and dynamic discharge behavior of biological neurons; and a capacitor connected in parallel with the threshold-switched memristor to realize the leakage integral-discharge characteristics of the neuron; wherein the ferroelectric floating gate transistor, the threshold-switched memristor, and the capacitor are heterogeneously integrated on the same insulating substrate surface through multilayer metal interconnects, forming a 1F-1M-1C basic circuit.

2. The neuromorphic primitive circuit according to claim 1, characterized in that, The ferroelectric floating gate transistor has a bottom gate structure, and its gate stack from bottom to top includes: Back gate electrode; A barrier layer, wherein the barrier layer is made of a ferroelectric material; The floating gate layer, located above the barrier layer, is made of a high work function metal and is used for charge trapping and storage. The tunneling layer, located above the floating gate layer, is composed of an insulating medium; And a two-dimensional semiconductor channel layer located above the tunneling layer and a source electrode and a drain electrode in contact with the channel layer.

3. The neuromorphic primitive circuit according to claim 2, characterized in that: The back gate electrode is selected from Ti / Pt multilayer metal; The barrier layer material is zirconium-doped hafnium oxide, with a thickness of 10-20 nanometers; The floating gate layer is made of Pt and has a thickness of 1-5 nanometers. The tunneling layer material is HfO2, and the thickness is 5-10 nanometers. The two-dimensional semiconductor channel material is a single-layer transition metal chalcogenide selected from MoS2, with a thickness of 0.5-1.0 nanometers.

4. The neuromorphic primitive circuit according to claim 1, characterized in that, The threshold switch memristor has a vertical sandwich structure, which includes, from bottom to top: a bottom electrode, a resistive switching layer, an active layer, and a top electrode.

5. The neuromorphic primitive circuit according to claim 4, characterized in that, In the threshold-switched memristor: The bottom electrode is selected from Ti / Pt multilayer metals; The resistive switching layer is made of SiO2 and has a thickness of 8-15 nanometers. The active layer and the top electrode are composed of a TiW alloy layer and an Ag metal layer stacked together. The TiW alloy layer contacts the resistive switching layer to suppress the lateral random diffusion of Ag ions. The thickness of the TiW alloy layer is 0.5-2 nanometers, and the thickness of the Ag metal layer is 15-35 nanometers.

6. The neuromorphic primitive circuit according to claim 1, characterized in that, Its working method is as follows: An input pulse voltage is applied to the back gate electrode of the ferroelectric floating gate transistor. By modulating the polarization state of the ferroelectric layer and the tunneling charge of the floating gate layer, the conductivity of the two-dimensional semiconductor channel is non-volatilely changed to simulate the long-term enhancement and long-term suppression of synaptic weights. The current injected into the channel charges and integrates the parallel capacitor. When the potential difference across the capacitor reaches the turn-on threshold voltage of the threshold switch memristor, the memristor spontaneously turns on to release the charge and generates an action potential pulse. After the discharge ends, the memristor returns to a high-resistance state.

7. A method for fabricating a neuromorphic primitive circuit as described in any one of claims 1-6, characterized in that, The specific steps are as follows: Step 1, Fabrication of back gate electrode and bottom electrode: On an insulating substrate, the back gate electrode of the ferroelectric floating gate transistor and the bottom electrode of the threshold switch memristor and capacitor are deposited and stripped by photolithography and physical vapor deposition. Step 2, Deposit barrier layer and floating gate layer: A ferroelectric layer is grown on the back gate electrode as a barrier layer by atomic layer deposition, and then a metal thin film is deposited as a floating gate layer; Step 3, Deposit tunneling layer and resistive switching layer: An insulating dielectric is grown above the floating gate layer as a tunneling layer using atomic layer deposition; a SiO2 thin film is deposited above the bottom electrode of the memristor as a resistive switching layer using physical vapor deposition. Step 4, Preparation of the top active layer of the memristor: In an ultra-high vacuum environment, a TiW alloy layer and an Ag metal layer are sequentially deposited by electron beam evaporation to form the top electrode of the memristor; Step 5, Transfer of two-dimensional channel material: The monolayer two-dimensional semiconductor material grown by chemical vapor deposition is transferred to the surface of the tunneling layer, and after inert gas annealing, it is patterned to form a transistor channel; Step 6, Fabrication of source and drain electrodes and interconnects: Photolithography and deposition of metal thin films to form the source and drain electrodes of the transistor, the upper electrode of the capacitor, and to complete the metal interconnects inside the basic circuit.

8. The method according to claim 7, characterized in that, In step 2, the barrier layer is a zirconium-doped hafnium oxide ferroelectric thin film grown at 200℃-300℃ using thermal atomic layer deposition.

9. The method according to claim 7, characterized in that, In step 5, after transferring the two-dimensional semiconductor material, a thermal annealing treatment at 200°C is performed in an N2 atmosphere for 2-4 hours to eliminate residual stress and enhance the adhesion between the film and the tunneling layer interface.

Images