Dual-in-line field sequential display circuit, driving method and medium

Abstract

The application relates to a double-row reversed field sequence display circuit, a driving method and a medium, the display circuit comprising a plurality of first pixel units and second pixel units arranged at intervals; wherein the first pixel unit comprises a first pixel circuit and a second pixel circuit sharing a global signal line, the first pixel circuit and the second pixel circuit are mutually Y-mirrored pixel circuits, and the inversion polarities at the same time are the same; the second pixel unit comprises a third pixel circuit and a fourth pixel circuit sharing a global signal line, the third pixel circuit and the fourth pixel circuit are mutually Y-mirrored pixel circuits, and the inversion polarities at the same time are the same; the inversion polarities of the first pixel unit and the second pixel unit at the same time are opposite. Thus, for the two pixel circuits included in any one pixel unit, since the global signal line can be shared to form a mirror in the film layer structure, the line space in the film layer structure can be saved, and the aperture ratio can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of field sequence display technology, specifically to a dual-row inverted field sequence display circuit, driving method, and medium. Background Technology

[0002] Compared to traditional RGB sub-pixel circuits, field-sequence display circuits eliminate color filters, offering unique advantages such as improved luminous efficiency and brightness, reduced power consumption, increased resolution, and expanded color gamut. Traditional field-sequence display driving technology can separate computation and display, improving overall illumination time. Whether it's a 3T3C with reset or a 2T3C without reset, it's more complex than the traditional 1T2C structure, requiring not only more MOSFETs but also more pre-storage capacitors. Therefore, field-sequence circuit design has a relatively low aperture ratio, making it difficult to achieve in high-resolution designs. Summary of the Invention

[0003] The technical problem to be solved by this application is to provide a dual-row inverted field sequence display circuit, driving method and medium, which has the feature of improving the aperture ratio of the field sequence circuit.

[0004] In one aspect, an embodiment provides a dual-column inverted field sequence display circuit, including a plurality of spaced-apart first pixel units and second pixel units; the first pixel unit includes a first pixel circuit and a second pixel circuit sharing a global signal line, the first pixel circuit and the second pixel circuit being Y-mirrored to each other, and having the same inversion polarity at the same time; the second pixel unit includes a third pixel circuit and a fourth pixel circuit sharing a global signal line, the third pixel circuit and the fourth pixel circuit being Y-mirrored to each other, and having the same inversion polarity at the same time; the inversion polarities of the first pixel unit and the second pixel unit are opposite at the same time.

[0005] Secondly, in one embodiment, a driving method for a dual-column inverted field sequence display circuit is provided, based on the dual-column inverted field sequence circuit of the above embodiment. The driving method includes: for any Nth frame, controlling the pixel electrodes of the two pixel circuits included in the first pixel unit to be positive voltages, and controlling the pixel electrodes of the two pixel circuits included in the second pixel unit to be negative voltages; for the (N+1)th frame, controlling the pixel electrodes of the two pixel circuits included in the first pixel unit to be negative voltages, and controlling the pixel electrodes of the two pixel circuits included in the second pixel unit to be positive voltages; the positive voltages and negative voltages are both based on a preset reference voltage.

[0006] Thirdly, in one embodiment, a computer-readable storage medium is provided, the medium storing a program that can be loaded by a processor and executed by the dual-column inverted field sequence display circuit driving method described in the above embodiment.

[0007] The beneficial effects of this invention are:

[0008] Since the first pixel unit includes a first pixel circuit and a second pixel circuit sharing a global signal line, and the first pixel circuit and the second pixel circuit are Y-mirrored pixel circuits that are the same inversion polarity at the same time; the second pixel unit includes a third pixel circuit and a fourth pixel circuit sharing a global signal line, and the third pixel circuit and the fourth pixel circuit are Y-mirrored pixel circuits that are the same inversion polarity at the same time; and the first pixel unit and the second pixel unit have opposite inversion polarities at the same time, for any two pixel circuits included in a pixel unit, since they can share a global signal line to form a mirror image in the film structure, the line space in the film structure can be saved, and the aperture ratio can be effectively improved. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a field sequence display circuit of 3T3C according to one embodiment of this application;

[0010] Figure 2 This is a schematic diagram of the field sequence display circuit of a 2T3C according to one embodiment of this application;

[0011] Figure 3 This is a schematic diagram of dual-row reverse drive polarity;

[0012] Figure 4 This is a schematic diagram of a dual-column inverted field sequence display circuit with a shared reset signal line Reset and control signal line Vref according to one embodiment of this application.

[0013] Figure 5 This is a schematic diagram of the principle of a dual-column inverted field sequence display circuit with a shared coupling signal line (Couple) according to one embodiment of this application;

[0014] Figure 6 This is a schematic diagram of a single-column inverted field sequence display circuit with a reset signal line Reset and a control signal line Vref according to one embodiment of this application;

[0015] Figure 7 This application Figure 6 The pixel circuit layout structure of the display circuit is shown.

[0016] Figure 8 This is a schematic diagram of the 3T3C dual-row inverted field sequence display circuit model architecture according to one embodiment of this application;

[0017] Figure 9 yes Figure 8 The pixel circuit layout structure corresponding to the film layer architecture shown;

[0018] Figure 10 This is a schematic diagram of a single-column inverted field sequence display circuit with a shared coupled signal line (Couple) according to one embodiment of this application.

[0019] Figure 11 This application Figure 10 The pixel circuit layout structure of the display circuit is shown.

[0020] Figure 12 This is a schematic diagram of the dual-row inverted field sequence display circuit model architecture of a 2T3C according to an embodiment of this application;

[0021] Figure 13 yes Figure 12 The pixel circuit layout structure corresponding to the film layer architecture shown;

[0022] Figure 14 This is a schematic diagram of the specific circuit of the 3T3C dual-row inverted field sequence display circuit according to one embodiment of this application;

[0023] Figure 15 This is a driving timing diagram of a 3T3C dual-row inverted field sequence display circuit according to an embodiment of this application;

[0024] Figure 16 This is a schematic diagram of the specific circuit of the dual-row inverted field sequence display circuit of 2T3C according to one embodiment of this application;

[0025] Figure 17 This is a driving timing diagram of a dual-row inverted field sequence display circuit of 2T3C according to an embodiment of this application. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0027] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0028] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0029] To facilitate the explanation of the inventive concept of this application, the field sequence display technology will be briefly described below.

[0030] Please refer to Figure 1 and Figure 2 These are schematic diagrams of the field-sequence display circuits for 3T3C and 2T3C, respectively. The 3T3C field-sequence display circuit includes a write switch TFT T1, a pre-storage capacitor Cs1, a signal transfer switch TFT T2, a holding capacitor Cs2, a pixel capacitor Clc, and a reset switch TFT T3. The data signal voltage line Data provides the data signal voltage to the write switch TFT T1; the scan signal line Scan controls the switching of the write switch TFT T1; the voltage transfer control signal line Tran controls the switching of the signal transfer switch TFT T2; the reset signal line Reset controls the switching of the reset switch TFT T3; Vcom is a common reference signal line with a preset reference potential; and the control signal line Vref provides a reference voltage to the source and drain terminals of the voltage output of the reset switch TFT T3. The node between the write switch TFT T1 and the pre-storage capacitor Cs1 is the pre-charge node, and the node between the signal transfer switch TFT T2 and the pixel capacitor Clc is the pixel node. The difference between the 2T3C field sequence display circuit and the 3T3C field sequence display circuit is that there is no reset switch TFT T3, reset signal line Reset, and control signal line Vref. The other end of the pre-storage capacitor Cs1 is not connected to the reference signal line Vcom, but to the coupling signal line Couple.

[0031] However, the applicant found in their research that both the 3T3C with reset and the 2T3C without reset structure are more complex to design than the traditional 1T2C structure, requiring not only an increase in the number of MOSFETs but also an increase in pre-storage capacitors. Therefore, the aperture ratio is relatively low in the design of field-sequence circuits.

[0032] In view of this, this application provides a dual-row inverted field sequence display circuit, driving method, and medium. The display circuit includes a plurality of spaced-apart first pixel units and second pixel units. Each first pixel unit includes a first pixel circuit and a second pixel circuit sharing a global signal line. The first and second pixel circuits are Y-mirrored pixel circuits and have the same inversion polarity at the same time. Each second pixel unit includes a third pixel circuit and a fourth pixel circuit sharing a global signal line. The third and fourth pixel circuits are Y-mirrored pixel circuits and have the same inversion polarity at the same time. The first and second pixel units have opposite inversion polarities at the same time. Therefore, for any two pixel circuits included in a pixel unit, since they can share a global signal line to form a mirror image in the film structure, the line space in the film structure can be saved, effectively improving the aperture ratio.

[0033] For ease of understanding, the following will first explain the dual-row inverted field sequence display circuit.

[0034] This application provides a dual-column inverted field sequence display circuit, including multiple spaced-apart first pixel units and second pixel units. Please refer to... Figure 3 Two adjacent pixels marked with a "+" sign form a pixel unit, and these two pixels have the same polarity reversal at the same time. Similarly, two pixels marked with a "-" sign form a pixel unit, and these two pixels have the same polarity reversal at the same time. These two pixel units are spaced apart, thus forming multiple spaced first pixel units and second pixel units, with the polarities of the two pixel units being opposite at the same time. Both the first and second pixel units include two pixel circuits sharing a global signal line. For ease of understanding, we will use two adjacent pixels marked with a "+" sign as the first and second pixels, and two pixels marked with a "-" sign as the third and fourth pixels as examples.

[0035] Please refer to Figure 4 and Figure 5 The first pixel circuit A and the second pixel circuit B are pixel circuits that are Y-mirrored to each other, and the third pixel circuit A' and the fourth pixel circuit B' are pixel circuits that are Y-mirrored to each other.

[0036] The following describes in detail the dual-row inverted field sequence display circuit of this application using two specific embodiments.

[0037] Specific Implementation 1:

[0038] Please refer to Figure 4In the dual-column inverted field sequence display circuit of this application, for any pixel circuit, including the 3T3C circuit, the global signal lines include the reset signal line Reset and the control signal lines Vref (OVref, EVref).

[0039] The applicant found in their research that, for current 3T3C circuits, please refer to... Figure 6 This is a single-column inverted field-sequence display circuit. Each pixel circuit is connected to its corresponding reset signal line (Reset) and control signal line (Vref). Adjacent pixels A and B are in odd and even columns, with Vref corresponding to signals OVref and EVref respectively. When the pixels are working, pixels A and B undergo an odd-even polarity flip. The pixel circuit layout corresponding to these two pixel circuits is shown below. Figure 7 As shown, there is a gap between the Vref signal line and the Data signal line of two adjacent pixel circuits (i.e., between the two pixel circuits), which results in a relatively low aperture ratio for the field sequence circuit.

[0040] To improve the aperture ratio, in this specific embodiment, the film layer architecture for any pixel circuit is described in reference to... Figure 8 The structure includes four metal traces: M1, M2, M3, and M4. These metal layers are isolated by insulating layers (in this specific implementation, different insulating layers are used for isolation). Specifically, the scan signal line (Scan) and the voltage transfer control signal line (Tran) use the first metal trace M1; the control signal line (Vref) and the pre-charge electrode (Prechage) of the pre-storage capacitor both use the second metal trace M2; the reference signal line (Vcom) uses the third metal trace M3; and the data signal voltage line (Data) and the reset signal line (Reset) use the fourth metal trace M4. For any pixel unit, in its film structure, the control signal line (Vref) and the reset signal line (Reset) are centrally located and each connects to one of the two pixel circuits it contains. This allows for pixel units that share global signal lines and are Y-mirrored to each other within the film structure. The corresponding layout structure can be found in [reference needed]. Figure 9 This eliminates the gap between the two pixel circuits, increasing the aperture ratio of the field sequence circuit.

[0041] Those skilled in the art will understand that the scope of protection of this application is not limited to dual-row inverted field sequence display circuits that share a common reset signal line Reset and a control signal line Vref, including 3T3C circuits. Within the scope of the inventive concept of this application, dual-row inverted field sequence display circuits that share a common reset signal line Reset and a control signal line Vref are all within the scope of protection of this application.

[0042] Implementation 2:

[0043] Please refer to Figure 5 In the dual-column inverted field sequence display circuit of this application, for any pixel circuit, including the 2T3C circuit, the global signal line includes a coupling signal line Couple, which is coupled to one end of the pre-storage capacitor Cs1.

[0044] The applicant found in their research that, for the current 2T3C circuit, please refer to... Figure 10 This is a single-column inverted field-sequence display circuit. Each pixel circuit is connected to its corresponding coupling signal line (Couple). Adjacent pixels A and B are odd-even columns (Couple), corresponding to signals OCouple and ECouple respectively. When the pixels are working, pixels A and B undergo an odd-even polarity flip. The pixel circuit layout corresponding to these two pixel circuits is shown below. Figure 11 As shown, there is a gap between the Couple and Data signal lines of two adjacent pixel circuits (i.e., between the two pixel circuits), which results in a relatively low aperture ratio for the field sequence circuit.

[0045] To improve the aperture ratio, in this specific embodiment, for any pixel circuit, please refer to... Figure 12 Its film layer architecture includes four metal traces: a first metal trace M1, a second metal trace M2, a third metal trace M3, and a fourth metal trace M4. The metal layers are isolated by insulating layers (in this specific implementation, different insulating layers are used for isolation). The scan signal line Scan and the voltage transfer control signal line Tran use the first metal trace M1, the pre-charge electrode nodes of the pre-storage capacitor all use the second metal trace M2, and the data signal voltage line Data uses the fourth metal trace M4. For any pixel unit, in its film layer architecture, the coupling signal line Couple is centrally located and connects to the two pixel circuits it includes. Thus, pixel units are obtained by sharing global signal lines and being Y-mirrored to each other within the film layer architecture. For the corresponding layout structure, please refer to [reference needed]. Figure 13 This eliminates the gap between the two pixel circuits, increasing the aperture ratio of the field sequence circuit.

[0046] Those skilled in the art will understand that the scope of protection of this application is not limited to dual-row inverted field sequence display circuits that use a common coupled signal line coupler including 2T3C circuits. Within the scope of the inventive concept of this application, dual-row inverted field sequence display circuits using a common coupled signal line coupler are all within the scope of protection of this application.

[0047] The following describes the driving method for the dual-column inverted field sequence display circuit provided in the embodiments of this application.

[0048] This application provides a driving method for a dual-column inverted field-sequence display circuit, implemented based on a dual-column inverted field-sequence circuit. This circuit includes multiple spaced-apart first pixel units and second pixel units. Each first pixel unit includes a first pixel circuit and a second pixel circuit sharing a global signal line. These first and second pixel circuits are Y-mirrored and have the same inversion polarity at any given time. Each second pixel unit includes a third pixel circuit and a fourth pixel circuit sharing a global signal line. These third and fourth pixel circuits are Y-mirrored and have the same inversion polarity at any given time. The inversion polarities of the first and second pixel units are opposite at any given time. The driving method includes: for any Nth frame, controlling the pixel electrodes of the two pixel circuits included in the first pixel unit to have positive voltages and controlling the pixel electrodes of the two pixel circuits included in the second pixel unit to have negative voltages; for the (N+1)th frame, controlling the pixel electrodes of the two pixel circuits included in the first pixel unit to have negative voltages and controlling the pixel electrodes of the two pixel circuits included in the second pixel unit to have positive voltages. Both the positive and negative voltages are based on a preset reference voltage.

[0049] It should be noted that the solution in this application is not limited to whether the Nth frame is an even frame or an odd frame; both are within the scope of protection of this application.

[0050] For ease of understanding, corresponding to the dual-column inverted field sequence display circuit, the driving method of the dual-column inverted field sequence display circuit in this application will also be described in detail with two specific embodiments. Specific Implementation Example 1:

[0052] Corresponding to a specific implementation in a dual-row inverted field-sequence display circuit, for any pixel circuit, including the 3T3C circuit, the global signal lines include a reset signal line Reset and a control signal line Vref. The reset signal line Reset is coupled to the gate of the reset switch TFT T3, and the control signal line Vref is coupled to the source-drain of the voltage output terminal of the reset switch TFT T3. In one specific implementation, the specific circuit structure can be found in [reference needed]. Figure 14 In this embodiment, an N-type TFT is used as an example. A high-level control signal voltage turns the TFT on, and a low-level control signal turns it off. ACs1 and BCs1 are data storage capacitors, used to pre-store the pixel data voltage of the next frame during the backlight illumination time. AClc and BClc are the pixel capacitors and the common electrode capacitances at the liquid crystal terminals. ACs2 and BCs2 are holding capacitors, used to maintain the stability of the pixel electrode voltage within one frame. Please refer to... Figure 15In the timing diagram, Data Charge represents the time it takes for the pre-stored nodes of the next frame to write data signals line by line, and it is also the time when the backlight turns on to emit light in the current frame. Blank time is used by the IC to process data signals and other control signals, as well as to reset the pixel electrodes and share the next frame data signals stored in ACs1 and BCs1 onto the pixel electrodes. The driving methods include:

[0053] For any pixel unit and any Nth frame, during the data writing and display phase (DataCharge & Display phase): the control scan signal line Scan is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; simultaneously, the control signal transfer switch TFT T2 and the reset switch TFT T3 are in the off state. During this phase, the pixel capacitors of pixels A and B are in the holding phase for display. During the pixel voltage transfer and reset phase (Blank & Transfer phase): first, a high and low potential signal is given to the reset signal line Reset to complete one switching of the reset switch TFT T3; then, a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFT T2; then, the polarity potential of the control signal line Vref is switched. The polarity potential can be switched from positive to negative, such as from Vref=Vop to Vref=-Vop, or from negative to positive, such as from Vref=-Vop to Vref=Vop. If the polarity is switched from positive to negative, then when the reset switch TFTT3 completes one switching operation, the A and B pixel electrodes simultaneously reset the Vref=Vop potential.

[0054] For the (N+1)th frame, during the data writing and display phase: the Scan control signal line is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; simultaneously, the control signal transfer switch TFT T2 and the reset switch TFT T3 are in the off state. During this phase, the pixel capacitors of pixels A and B are in the holding phase for Display display, showing the voltage after sharing the voltage of the previous frame's Tran. During the pixel voltage transfer and reset phase: first, a high and low potential signal is given to the Reset signal line to complete one switching of the reset switch TFT T3; then, a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFT T2; then, the control signal line Vref switches the polarity potential. If the polarity changes from positive to negative in the Nth frame, then when the reset switch TFT T3 completes one switching in the N+1th frame, the A and B pixel electrodes simultaneously reset to the Vref=-Vop potential.

[0055] Repeat the above steps to complete the display sequence of the lights on the entire field. Specific Implementation Example 2:

[0057] Corresponding to the second specific implementation of the dual-row inverted field-sequence display circuit, for any pixel circuit, including the 2T3C circuit, the global signal line includes a coupling signal line Couple, which is coupled to one end of the pre-storage capacitor Cs1. In one specific implementation, the specific circuit structure can be found in [reference needed]. Figure 16 In this embodiment, an N-type TFT is used as an example. A high-level control signal voltage turns the TFT on, and a low-level control signal turns it off. ACs1 and BCs1 are data storage capacitors, used to pre-store the pixel data voltage of the next frame during the backlight illumination time. AClc and BClc are the pixel capacitors and the common electrode capacitances at the liquid crystal terminals. ACs2 and BCs2 are holding capacitors, used to maintain the stability of the pixel electrode voltage within one frame. Please refer to... Figure 17 In the timing diagram, Data Charge represents the time it takes for the pre-stored nodes of the next frame to write data signals line by line, and it is also the time when the backlight turns on to emit light in the current frame. Blank time is used by the IC to process data signals and other control signals, as well as to reset the pixel electrodes and share the next frame data signals stored in ACs1 and BCs1 onto the pixel electrodes. The driving methods include:

[0058] For any pixel unit and any Nth frame, during the data writing and display phase (DataCharge & Display phase): the control scan signal line Scan is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; simultaneously, the control signal transfer switch TFT T2 is in the off state. During this phase, the pixel capacitors of pixels A and B are in the holding phase for display. During the pixel voltage transfer and reset phase: a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFT T2, and then the polarity potential of the control coupling signal line Couple is switched. The polarity potential can be switched from positive to negative, such as from Vref=Vop / 2 to Vref=-Vop / 2, or from negative to positive, such as from Vref=-Vop / 2 to Vref=Vop / 2. If it is a switch from positive to negative, when the control signal transfer switch TFT T2 is completed, the A and B pixel electrodes are simultaneously reset to the Vref=Vop / 2 potential.

[0059] For the (N+1)th frame, during the data writing and display phase: the control scan signal line Scan is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; simultaneously, the control signal transfer switch TFT T2 is in the off state. During this phase, the pixel capacitors of pixels A and B are in the holding phase for Display display, showing the voltage after sharing the voltage of the previous frame Tran. During the pixel voltage transfer and reset phase: a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFT T2, and then the polarity potential of the control coupling signal line Couple is switched. If the polarity is switched from positive to negative in the Nth frame, then when the control signal transfer switch TFT T2 is switched once in the N+1th frame, the A and B pixel electrodes are simultaneously reset to the Vref=-Vop / 2 potential.

[0060] Repeat the above steps to complete the display sequence of the lights on the entire field.

[0061] One embodiment of this application provides a computer-readable storage medium storing a program, the stored program including methods that can be loaded by a processor and processed in any of the above embodiments.

[0062] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0063] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A dual-row inverted field sequence display circuit, characterized in that, The system includes multiple spaced-apart first pixel units and second pixel units. Each first pixel unit includes a first pixel circuit and a second pixel circuit sharing a global signal line. These first and second pixel circuits are Y-mirrored pixel circuits and have the same polarity inversion at the same time. Each second pixel unit includes a third pixel circuit and a fourth pixel circuit sharing a global signal line. These third and fourth pixel circuits are Y-mirrored pixel circuits and have the same polarity inversion at the same time. The first and second pixel units have opposite polarities inversion at the same time.

2. The dual-row inverted field sequence display circuit as described in claim 1, characterized in that, For any pixel circuit, including the 3T3C circuit, the global signal lines include a reset signal line Reset and a control signal line Vref.

3. The dual-row inverted field sequence display circuit as described in claim 2, characterized in that, For any pixel circuit, its film layer architecture includes four metal traces: a first metal trace M1, a second metal trace M2, a third metal trace M3, and a fourth metal trace M4. The metal layers are isolated by an insulating layer. The scan signal line Scan and the voltage transfer control signal line Tran use the first metal trace M1, the control signal line Vref and the pre-charge electrode of the pre-storage capacitor both use the second metal trace M2, the reference signal line Vcom uses the third metal trace M3, and the data signal voltage line Data and the reset signal line Reset use the fourth metal trace M4. In the film layer architecture of any pixel unit, the control signal line Vref and the reset signal line Reset are centrally located and are respectively connected to the two pixel circuits included therein.

4. The dual-row inverted field sequence display circuit as described in claim 1, characterized in that, For any pixel circuit, including the 2T3C circuit, the global signal line includes a coupling signal line Couple, which is coupled to one end of the pre-storage capacitor Cs1.

5. The dual-row inverted field sequence display circuit as described in claim 4, characterized in that, For any pixel unit, its film structure includes four metal traces: a first metal trace M1, a second metal trace M2, a third metal trace M3, and a fourth metal trace M4. The metal layers are isolated by an insulating layer. The scan signal line Scan and the voltage transfer control signal line Tran use the first metal trace M1, the pre-charge electrode of the pre-storage capacitor uses the second metal trace M2, and the data signal voltage line Data uses the fourth metal trace M4. In the film structure of any pixel unit, the coupling signal line Couple is centrally located and connects to the two pixel circuits it includes.

6. A driving method for a dual-row inverted field sequence display circuit, characterized in that, Based on the dual-column inverted field sequence circuit as described in claim 1, the driving method includes: for any Nth frame, controlling the pixel electrodes of the two pixel circuits included in the first pixel unit to be positive voltages, and controlling the pixel electrodes of the two pixel circuits included in the second pixel unit to be negative voltages; for the (N+1)th frame, controlling the pixel electrodes of the two pixel circuits included in the first pixel unit to be negative voltages, and controlling the pixel electrodes of the two pixel circuits included in the second pixel unit to be positive voltages; the positive voltages and negative voltages are both based on a preset reference voltage.

7. The driving method for a dual-row inverted field sequence display circuit as described in claim 6, characterized in that, For any pixel circuit, including a 3T3C circuit, the global signal lines include a reset signal line Reset and a control signal line Vref. The reset signal line Reset is coupled to the gate of the reset switch TFT T3, and the control signal line Vref is coupled to the source-drain terminals of the voltage output of the reset switch TFT T3. The driving method includes: For any pixel unit and any Nth frame, during the data writing and display phase: the control scan signal line Scan is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; at the same time, the control signal transfer switch TFT T2 and the reset switch TFT T3 are in the off state; during the pixel voltage transfer and reset phase: first, a high and low potential signal is given to the reset signal line Reset to complete one switching of the reset switch TFT T3, then a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFT T2, and then the polarity potential of the control signal line Vref is switched; For the N+1th frame, during the data writing and display phase: the Scan control signal line is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; at the same time, the control signal transfer switch TFTT2 and the reset switch TFTT3 are in the off state; during the pixel voltage transfer and reset phase: first, a high and low potential signal is given to the Reset reset signal line to complete one switching of the reset switch TFTT3, then a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFTT2, and then the polarity potential of the control signal line Vref is switched.

8. The driving method for a dual-row inverted field sequence display circuit as described in claim 6, characterized in that, For any pixel circuit, including a 2T3C circuit, the global signal line includes a coupling signal line Couple, which is coupled to one end of a pre-storage capacitor Cs1; the driving method includes: For any pixel unit and any Nth frame, during the data writing and display phase: the control scan signal line Scan is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; at the same time, the control signal transfer switch TFT T2 is in the off state; during the pixel voltage transfer and reset phase: a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFT T2, and then the polarity potential of the control coupling signal line Couple is switched. For the N+1th frame, during the data writing and display phase: the control scan signal line Scan is turned on line by line to write pre-stored data to the pre-stored capacitors of the two pixel circuits contained in the pixel unit; at the same time, the control signal transfer switch TFTT2 is in the off state; during the pixel voltage transfer and reset phase: a high and low potential signal is given to the voltage transfer control signal line Tran to complete one switching of the control signal transfer switch TFTT2, and then the polarity potential of the control coupling signal line Couple is switched.

9. A computer-readable storage medium, characterized in that, The medium stores a program that can be loaded by a processor and executed as described in any one of claims 6 to 8 for driving a dual-column inverted field sequence display circuit.

Images