MOSFET device-based strong electromagnetic pulse suppressor and method of manufacture

Abstract

This invention discloses a strong electromagnetic pulse suppressor based on a MOSFET device and its fabrication method, relating to the field of filter technology. The strong electromagnetic pulse suppressor includes a filter circuit and a protection circuit comprising an NMOS device, a first resistor, a second resistor, and a varistor. A first terminal of the first resistor is connected to a first conductive line, and a second terminal of the first resistor is connected to the gate of the NMOS device. A first terminal of the second resistor is connected to the gate of the NMOS device, and a second terminal of the second resistor is connected to a second conductive line. The drain of the NMOS device is connected to the first conductive line. The source of the NMOS device is connected to the first terminal of the varistor, and the second terminal of the varistor is connected to the second conductive line. The filter circuit is connected between the first and second conductive lines. The protection circuit receives input signals through the first and second conductive lines. This invention improves the protection capability against strong electromagnetic pulses while ensuring the integrity of normal signals.

Description

Technical Field

[0001] This invention relates to the field of filter technology, and in particular to a strong electromagnetic pulse suppressor based on MOSFET devices and its fabrication method. Background Technology

[0002] With the development of electronic technology, the damage caused by strong electromagnetic pulses (TEPs) in complex electromagnetic environments to electronic components of equipment is receiving increasing attention. A complex electromagnetic environment typically refers to an environment in which various natural and man-made electromagnetic activities are intertwined, densely overlapping, and have uneven power distributions within a specific spatial, temporal, and frequency domain, significantly impacting beneficial electromagnetic activities. The main factors constituting a complex electromagnetic environment include electronic countermeasures between adversaries and friendly forces, high-density, high-intensity, multi-spectral electromagnetic waves released by various weapons and equipment, radiation from civilian electromagnetic equipment, and electromagnetic waves generated by nature. In complex electromagnetic environments, strong electromagnetic pulse (TEP) interference sources pose the greatest threat and have the strongest destructive power to air defense and anti-missile weapon systems. TEPs have rapid rise times, reaching the nanosecond level, and peak pulse intensity can reach up to 50 kV / m. To improve system reliability, effective suppression of TEP interference is necessary.

[0003] Currently, common protection methods against such strong electromagnetic pulses involve connecting voltage-limiting devices such as varistors and transient voltage suppressor diodes in parallel between the signal line and ground. These devices utilize their nonlinear characteristics to clamp the pulse voltage to a safe level. Alternatively, inductors and capacitors can be connected in series along the signal path to form a filter circuit, attenuating the high-frequency pulse energy. Some protection schemes also combine these devices to simultaneously achieve pulse discharge and interference filtering.

[0004] However, traditional protection devices face a trade-off between response time and distributed capacitance when applied to protect against strong electromagnetic pulses with nanosecond-level rise times. Specifically, devices such as varistors and transient voltage suppressor diodes have relatively large junction capacitances, typically ranging from tens to hundreds of picofarads. Directly connecting them in parallel between the signal line and ground significantly increases the distributed capacitance of the line, causing attenuation, distortion, or reflection of normally transmitted high-frequency signals, thus affecting system performance. If fast-switching devices with smaller junction capacitances are selected, their current-carrying capacity and energy tolerance are often insufficient to withstand the high-energy impact of strong electromagnetic pulses. Therefore, traditional protection circuits struggle to achieve a balance between ensuring normal signal integrity and effectively suppressing nanosecond-level strong electromagnetic pulses.

[0005] To address this issue, the present invention provides a strong electromagnetic pulse suppressor based on MOSFET devices. By connecting an NMOS device in series with a varistor and combining it with a resistive coupling circuit, the distributed capacitance of the suppressor is effectively reduced while achieving a nanosecond-level fast response, thus solving the technical problem in the prior art where response time and distributed capacitance are difficult to balance. Summary of the Invention

[0006] This invention aims to address the shortcomings of existing technologies by providing a strong electromagnetic pulse suppressor based on MOSFET devices, as detailed below: 1) In a first aspect, the present invention provides a strong electromagnetic pulse suppressor based on a MOSFET device, the specific technical solution of which is as follows: It includes a filter circuit, as well as a protection circuit containing an NMOS device, a first resistor, a second resistor, and a varistor; The first end of the first resistor is connected to the first wire, and the second end of the first resistor is connected to the gate of the NMOS device. The first end of the second resistor is connected to the gate of the NMOS device, and the second end of the second resistor is connected to the second wire. The drain of the NMOS device is connected to the first conductor; The source of the NMOS device is connected to the first end of the varistor, and the second end of the varistor is connected to the second wire. The filter circuit is connected between the first wire and the second wire; The protection circuit is used to receive input signals through the first wire and the second wire.

[0007] The beneficial effects of the strong electromagnetic pulse suppressor based on MOSFET devices provided by this invention are as follows: By connecting an NMOS device in series with a varistor and forming a coupling circuit with a first resistor and a second resistor, the problem of balancing response time and distributed capacitance in traditional protection devices is solved. When the input signal is a strong electromagnetic pulse, the input voltage increases, and the gate-source voltage of the NMOS device rises rapidly through the coupling of the first and second resistors. The NMOS device quickly turns on, guiding the energy of the strong electromagnetic pulse to the varistor for discharge. Since the switching time of the NMOS device is much shorter than the nanosecond-level rise time of the strong electromagnetic pulse, a nanosecond-level fast response is achieved. When the input signal is a normal transmission signal, the gate-source voltage of the NMOS device is lower than the threshold voltage, and the NMOS device is in the off state, effectively isolating the varistor from the signal path. This significantly reduces the distributed capacitance of the suppressor and ensures low-loss transmission of normal signals. At the same time, the filtering circuit further suppresses out-of-band interference in the residual pulse, ensuring the integrity of normal signals while improving the protection capability against strong electromagnetic pulses.

[0008] Based on the above scheme, the strong electromagnetic pulse suppressor based on MOSFET devices of the present invention can be further improved as follows.

[0009] Furthermore, the filter circuit includes a first capacitor, with a first end connected to a first wire and a second end connected to a second wire.

[0010] The beneficial effects of adopting the above-mentioned further scheme are as follows: By setting a first capacitor in the filter circuit, and connecting the first end of the first capacitor to the first wire and the second end of the first capacitor to the second wire, the first capacitor forms a high-frequency, low-impedance path bridging the first and second wires. After the strong electromagnetic pulse is discharged by the protection circuit, its residual waveform still contains high-frequency interference components. The first capacitor utilizes the characteristic that the capacitive reactance decreases with increasing frequency to provide a low-impedance bypass path for these high-frequency interference components, allowing them to be directly shunted from the first wire to the second wire, thereby reducing the high-frequency interference energy entering the subsequent circuit. At the same time, for normal signals within the operating frequency band, the first capacitor presents a high impedance and will not significantly affect the transmission of normal signals. Through the above method, the first capacitor achieves primary filtering of the residual high-frequency components of the strong electromagnetic pulse, further improving the electromagnetic pulse suppression effect of the suppressor.

[0011] Furthermore, the filter circuit also includes a first inductor, a second capacitor, a third capacitor, a first end of the first inductor connected to a first wire, a second end of the first inductor connected to a first end of the second capacitor, a second end of the second capacitor connected to a second wire, a first end of the second inductor connected to a second end of the first inductor, a second end of the second inductor connected to a first end of the third capacitor, and a second end of the third capacitor connected to a second wire.

[0012] The beneficial effects of adopting the above-mentioned further scheme are as follows: The combination of the low-frequency pass-through and high-frequency blockage characteristics of an inductor and the high-frequency pass-through and low-frequency blockage characteristics of a capacitor effectively attenuates the high-frequency components in the residual pulse. The first end of the second inductor is connected to the second end of the first inductor, the second end of the second inductor is connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the second wire, forming a second-stage low-pass filter unit together with the first inductor and the second capacitor, further attenuating the high-frequency interference components. Through the cascading of the two-stage filter structure, the attenuation degree of interference outside the operating frequency band is significantly increased, and the frequency selectivity is improved. This ensures low-loss transmission of normal signals within the operating frequency band while more effectively suppressing broadband interference components in the residual waveform of strong electromagnetic pulses.

[0013] Furthermore, the filter circuit also includes a third inductor, a fourth inductor, and a fifth inductor. The first end of the third inductor is connected to the second end of the second inductor, and the second end of the third inductor is connected to the second wire. The first end of the fourth inductor is connected to the first wire, and the second end of the fourth inductor is connected to the second wire. The first end of the fifth inductor is connected to the first wire, and the second end of the fifth inductor is connected to the second wire.

[0014] The beneficial effects of adopting the above-mentioned further scheme are as follows: By further adding a third, fourth, and fifth inductor to the filter circuit, and connecting the first end of the third inductor to the second end of the second inductor, and the second end of the third inductor to the second conductor, the third inductor forms an inductive bypass branch connected in parallel between the first and second conductors, providing a low-impedance discharge path for interference signals in a specific frequency band. The first end of the fourth inductor is connected to the first conductor, and the second end of the fourth inductor is connected to the second conductor; the first end of the fifth inductor is connected to the first conductor, and the second end of the fifth inductor is connected to the second conductor. These two parallel branches, together with the aforementioned filter network, constitute a multi-stage filter structure, further expanding the operating frequency coverage of the filter circuit and enhancing the suppression depth of out-of-band interference. With the addition of the above three inductors, the filter circuit's attenuation capability for broadband interference in the residual waveform of strong electromagnetic pulses is improved, while making the frequency response of the filter circuit smoother and reducing insertion loss fluctuations in the passband. Thus, while ensuring the normal signal transmission quality, the suppression effect of the suppressor on strong electromagnetic pulses is further improved.

[0015] Furthermore, the filtering circuit and the protection circuit are integrated on the same printed circuit board, which has a ground plane, and the second conductor is connected to the ground plane.

[0016] The advantages of adopting the above-mentioned further solution are as follows: Integrating the filter circuit and the protection circuit on the same printed circuit board shortens the interconnection path between components, reduces parasitic inductance and resistance, and makes the transmission of strong electromagnetic pulse energy between the protection circuit and the filter circuit more direct and rapid. The ground plane on the printed circuit board provides a complete and continuous zero-potential reference plane for the entire suppressor. The second conductor is directly connected to the ground plane, minimizing the impedance of the discharge path and ensuring that strong electromagnetic pulse energy can be quickly and uniformly diffused through the ground plane and conducted into the casing or system ground, avoiding voltage bounce caused by excessively long grounding paths or excessively high impedance. Simultaneously, the presence of the ground plane also provides low-impedance grounding connection points for the capacitors in the filter circuit, improving the high-frequency filtering effect and ensuring the electromagnetic compatibility performance and pulse suppression performance of the suppressor in a compact structure.

[0017] 2) In a second aspect, the present invention also provides a method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device, the specific technical solution of which is as follows: Based on the frequency range and power level of the input signal, calculate the specifications of the suitable NMOS device, first resistor, second resistor, varistor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor, and select the corresponding components. Design a protection circuit based on the selected NMOS device, first resistor, second resistor, and varistor; Design a filter circuit based on the selected first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor; Based on the size requirements and production quantity of the strong electromagnetic pulse suppressor, a printed circuit board is designed and fabricated. A grounding layer is set on the printed circuit board, and the second conductor is electrically connected to the grounding layer. The selected NMOS device, first resistor, second resistor, varistor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor are soldered onto the printed circuit board according to the designed positions to obtain a strong electromagnetic pulse suppressor.

[0018] The beneficial effects of the method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device according to the present invention are as follows: The specifications of each component are precisely calculated and selected based on the frequency range and power level of the input signal, ensuring the compatibility of the NMOS device, first resistor, second resistor, varistor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor, thus providing a design basis for the suppressor's performance indicators. By designing protection and filtering circuits based on the selected components, the functional modules are clearly defined and work collaboratively. Printed circuit boards are designed and fabricated according to size requirements and production quantities. A ground plane is set on the printed circuit board, and a second conductor is electrically connected to the ground plane, ensuring the suppressor's compact structure and reliable grounding. The selected components are soldered onto the printed circuit board according to the designed positions, realizing a complete manufacturing process from component selection to finished circuit, ensuring the consistency and repeatability of the suppressor's performance.

[0019] Based on the above scheme, the method for preparing a strong electromagnetic pulse suppressor based on MOSFET devices according to the present invention can be further improved as follows.

[0020] Furthermore, a protection circuit is designed based on the selected NMOS device, the first resistor, the second resistor, and the varistor, including: Connect the first end of the first resistor to the first wire, connect the second end of the first resistor to the gate of the NMOS device, connect the first end of the second resistor to the gate of the NMOS device, connect the second end of the second resistor to the second wire, connect the drain of the NMOS device to the first wire, connect the source of the NMOS device to the first end of the varistor, and connect the second end of the varistor to the second wire.

[0021] The beneficial effects of adopting the above-mentioned further scheme are as follows: By connecting the first end of the first resistor to the first wire, the second end of the first resistor to the gate of the NMOS device, the first end of the second resistor to the gate of the NMOS device, and the second end of the second resistor to the second wire, a voltage divider coupling circuit is formed, enabling the voltage change of the input signal to be rapidly transmitted to the gate of the NMOS device, thus achieving rapid detection of strong electromagnetic pulses. Connecting the drain of the NMOS device to the first wire, the source of the NMOS device to the first end of the varistor, and the second end of the varistor to the second wire forms a series discharge path. When the input signal is a strong electromagnetic pulse, the NMOS device quickly turns on, guiding the pulse energy to the varistor for discharge; when the input signal is a normal transmission signal, the NMOS device remains off, isolating the varistor from the first wire, reducing the distributed capacitance of the entire suppressor, while retaining the advantages of the varistor's large current carrying capacity and fast response.

[0022] Furthermore, a filter circuit is designed based on the selected first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor, including: Connect the first terminal of the first capacitor to the first wire, connect the second terminal of the first capacitor to the second wire, connect the first terminal of the first inductor to the first wire, connect the second terminal of the first inductor to the first terminal of the second capacitor, connect the second terminal of the second capacitor to the second wire, connect the first terminal of the second inductor to the second terminal of the first inductor, connect the second terminal of the second inductor to the first terminal of the third capacitor, connect the second terminal of the third capacitor to the second wire, connect the first terminal of the third inductor to the second terminal of the second inductor, connect the second terminal of the third inductor to the second wire, connect the first terminal of the fourth inductor to the first wire, connect the second terminal of the fourth inductor to the second wire, connect the first terminal of the fifth inductor to the first wire, and connect the second terminal of the fifth inductor to the second wire.

[0023] The beneficial effects of adopting the above-mentioned further scheme are as follows: By connecting the first capacitor across the first and second wires, a first-stage high-frequency bypass is formed; by connecting the first inductor in series with the first wire and then the second capacitor, with the other end of the second capacitor connected to the second wire, a first-stage L-shaped filter unit is formed; by connecting the second inductor in series with the first inductor and then the third capacitor, with the other end of the third capacitor connected to the second wire, a second-stage L-shaped filter unit is formed; by connecting the third inductor in parallel between the output terminal of the second inductor and the second wire, and by connecting the fourth and fifth inductors in parallel between the first and second wires respectively, a multi-order low-pass filter network is formed. The above connection method enables the filter circuit to have a higher order and a steeper frequency attenuation characteristic, which can deeply suppress wide-band interference components in the residual waveform of strong electromagnetic pulses, while maintaining low-loss signal transmission within the operating frequency band, thus improving the overall filtering performance of the suppressor.

[0024] Furthermore, it also includes: assembling the soldered printed circuit board into a housing to obtain a strong electromagnetic pulse suppressor with a housing.

[0025] The beneficial effects of adopting the above-mentioned further solution are as follows: By assembling the soldered printed circuit board into the housing, a strong electromagnetic pulse suppressor with a housing is obtained, providing mechanical support and physical protection for the printed circuit board, preventing damage to components due to external impact or vibration. The housing, as a metal shield, isolates the internal circuitry from the complex external electromagnetic environment, reducing the impact of external electromagnetic interference on the suppressor's internal circuitry, while also effectively shielding the electromagnetic radiation generated by the suppressor itself. The housing and the grounding layer on the printed circuit board are electrically connected through assembly, forming a complete low-impedance discharge path, allowing the strong electromagnetic pulse energy to be quickly conducted to the system ground through the housing, further improving the suppressor's pulse discharge efficiency. The housing's encapsulation structure also provides the suppressor with moisture-proof, dust-proof, and heat dissipation capabilities, enhancing the suppressor's environmental adaptability and long-term operational reliability.

[0026] Furthermore, it also includes: performance verification of a high electromagnetic pulse suppressor with a housing.

[0027] The beneficial effects of adopting the above-mentioned further solution are as follows: By performing performance verification on a housing-equipped high electromagnetic pulse (ESP) suppressor, the performance indicators of the suppressor under actual operating conditions can be comprehensively verified to ensure that they meet the design requirements. The performance verification process includes insertion loss measurement, normal signal transmission testing, ESP suppression capability testing, and stability testing under multiple pulse impacts. These test results objectively reflect the signal transmission quality of the suppressor within its operating frequency band and its protection effect against ESP. Verification allows for the timely identification of defects in component selection, circuit design, or assembly processes, providing a basis for design improvements. For mass-produced suppressors, performance verification also serves as a quality sampling inspection, ensuring the performance consistency of each batch of products and guaranteeing the reliable application of the suppressor in actual systems. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below: Figure 1 This is one of the structural schematic diagrams of a strong electromagnetic pulse suppressor based on a MOSFET device according to an embodiment of the present invention; Figure 2 This is a second schematic diagram of a high electromagnetic pulse suppressor based on a MOSFET device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the equivalent circuit of the parasitic capacitance of a MOSFET device. Figure 4This is a schematic diagram of the switching characteristics of the MOSFET device of the present invention; Figure 5 This is a schematic diagram of the insertion loss of a high electromagnetic pulse suppressor based on a MOSFET device according to the present invention; Figure 6 The time-domain waveform of a nuclear electromagnetic pulse with a rise time of 5 ns and a half-wave width of 20 ns; Figure 7 for Figure 6 The diagram shows the time-domain waveform of a strong electromagnetic pulse after passing through a suppressor circuit. Figure 8 This is a schematic flowchart of a method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device. Detailed Implementation

[0029] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0030] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0031] like Figure 1 As shown in the figure, an embodiment of the present invention provides a strong electromagnetic pulse suppressor based on a MOSFET device, including a filter circuit and a protection circuit containing an NMOS device Q, a first resistor R1, a second resistor R2, and a varistor MOV. The first end of the first resistor R1 is connected to a first wire, and the second end of the first resistor R1 is connected to the gate of the NMOS device Q. The first end of the second resistor R2 is connected to the gate of the NMOS device Q, and the second end of the second resistor R2 is connected to a second wire. The drain of the NMOS device Q is connected to the first wire. The source of the NMOS device Q is connected to the first end of the varistor MOV, and the second end of the varistor MOV is connected to the second wire. The filter circuit is connected between the first wire and the second wire. The protection circuit is used to receive input signals through the first wire and the second wire.

[0032] Optionally, in the above technical solutions, such as Figure 2 As shown, the filter circuit includes a first capacitor C1, with the first end of the first capacitor C1 connected to a first wire and the second end of the first capacitor C1 connected to a second wire.

[0033] Optionally, in the above technical solutions, such as Figure 2As shown, the filter circuit also includes a first inductor L1, a second capacitor C2, a second inductor L2, and a third capacitor C3. The first end of the first inductor L1 is connected to the first wire, the second end of the first inductor L1 is connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is connected to the second wire, the first end of the second inductor L2 is connected to the second end of the first inductor L1, the second end of the second inductor L2 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is connected to the second wire.

[0034] Optionally, in the above technical solutions, such as Figure 2 As shown, the filter circuit also includes a third inductor L3, a fourth inductor L4, and a fifth inductor L5. The first end of the third inductor L3 is connected to the second end of the second inductor L2, and the second end of the third inductor L3 is connected to the second wire. The first end of the fourth inductor L4 is connected to the first wire, and the second end of the fourth inductor L4 is connected to the second wire. The first end of the fifth inductor L5 is connected to the first wire, and the second end of the fifth inductor L5 is connected to the second wire.

[0035] Optionally, in the above technical solution, the filtering circuit and the protection circuit are integrated on the same printed circuit board, the printed circuit board is provided with a ground layer, and the second wire is connected to the ground layer.

[0036] Figure 3 This paper presents the equivalent circuit of the parasitic capacitance of the NMOS device Q, the core switching element constituting a strong electromagnetic pulse (ESP) suppressor. This equivalent circuit describes the inherent capacitive characteristics of the NMOS device Q in its physical structure. These parasitic capacitances directly affect the suppressor's response to normal transmitted signals and strong EMPs. Specifically, the parasitic capacitance of the NMOS device Q includes the parasitic capacitance between the gate and source. Parasitic capacitance between gate and drain and the parasitic capacitance between the drain and source. .in, This represents the equivalent capacitance formed between the gate and source terminals of the NMOS device Q due to the insulating layer and electrode structure. This represents the equivalent capacitance formed between the gate and drain terminals of the NMOS device Q. This capacitance affects the switching speed during device switching due to the Miller effect. This represents the equivalent capacitance formed between the drain and source terminals of the NMOS device Q, primarily manifested as the depletion layer capacitance of the PN junction. Based on these three basic parasitic capacitances, three comprehensive parameters can be defined to describe the capacitive characteristics of the NMOS device Q under different port conditions. Input capacitance Defined as the equivalent capacitance seen from the gate and source terminals when the drain and source of an NMOS device Q are AC short-circuited, its calculation formula is: This parameter reflects the total capacitive load required for the Q-gate drive circuit of the NMOS device, directly determining the time constant of the gate drive loop composed of the first resistor R1 and the second resistor R2. Reverse transfer capacitance. Defined as the equivalent capacitance seen from the gate and drain terminals when the source of an NMOS device Q is grounded, its calculation formula is: This parameter determines the feedback strength between the gate and drain, affecting the dynamic characteristics of the NMOS device Q during turn-on and turn-off. Output capacitance. Defined as the equivalent capacitance seen from the drain and source terminals when the gate and source of an NMOS device Q are AC short-circuited, its calculation formula is: This parameter directly determines the total equivalent capacitance between the drain and source terminals to ground when the NMOS device Q is in the off state, thus affecting the insertion loss of the suppressor for normal transmission signals. In the suppressor of this invention, when the input signal is a normal transmission signal, the NMOS device Q is in the off state, and the impedance between its drain and source is high. At this time, the output capacitance... This becomes a major factor limiting high-frequency signal transmission. This is due to the output capacitance of the NMOS device's Q. The value is typically in the picofarad range and much smaller than the parasitic capacitance of the varistor MOV. When the NMOS device Q is connected in series with the varistor MOV, the NMOS device Q in the off state has a very small output capacitance. The large parasitic capacitance of the varistor MOV is isolated from the first conductor, thereby significantly reducing the additional capacitance of the entire protection circuit to the signal line and ensuring low-loss transmission of normal signals within the operating frequency band.

[0037] Based on the parasitic capacitance equivalent circuit of the NMOS device Q, the working principle of a strong electromagnetic pulse suppressor based on a MOSFET device according to the present invention is described as follows: When the input signal is a normal transmission signal, its voltage amplitude is low and cannot establish a gate-source voltage VGS sufficient to turn on the NMOS device Q on the voltage divider coupling circuit composed of the first resistor R1 and the second resistor R2. Therefore, the drain and source of the NMOS device Q are in the off state. At this time, since the NMOS device Q is in a high-impedance state, the branch connected in series with the varistor MOV presents a high impedance and has almost no shunt effect to ground. The input signal is mainly transmitted to the next stage circuit through the filter circuit of the subsequent stage along the first wire. This design effectively reduces the overall ground distributed capacitance of the suppressor. Because the traditional varistor MOV itself has a large parasitic capacitance, if it is directly connected between the signal line and ground, it will seriously affect the transmission of high-frequency signals, causing signal distortion or attenuation. This invention, by connecting the NMOS device Q in series with the varistor MOV, utilizes the extremely small drain-source capacitance of the NMOS device Q in the off state to greatly reduce the influence of the large capacitance of the varistor MOV on the signal line, thereby ensuring low insertion loss transmission of normal signals, such as Figure 5 As shown, the insertion loss is less than 0.6dB within the operating frequency band.

[0038] The situation is completely different when the input signal is a strong electromagnetic pulse. A strong electromagnetic pulse has an extremely high voltage amplitude and an extremely fast rise time, reaching the nanosecond level. This high-voltage pulse, through the first wire and the coupling effect of the first resistor R1 and the second resistor R2, rapidly establishes a voltage VGS between the gate and source of the NMOS device Q. Because MOSFET devices have... Figure 4 The switching characteristics shown exhibit extremely short switching times, typically ranging from 50 to 200 picoseconds. When VGS rises above the threshold voltage VTH of the NMOS device Q, the NMOS device Q responds immediately, its drain and source rapidly conducting, presenting a low-impedance state. At this time, the main path of the strong electromagnetic pulse becomes: from the first conductor, through the conducting NMOS device Q, then through the varistor MOV, and finally to the second conductor, i.e., the ground plane, for discharge. The varistor MOV has the characteristics of fast response time (nanosecond level) and large current carrying capacity. It can absorb and discharge the huge pulse energy as heat to ground at the instant the NMOS device Q turns on, thereby effectively clamping the pulse voltage at a low level and protecting the downstream sensitive circuit connected to the output. When the strong electromagnetic pulse passes, the input voltage returns to normal, and the gate-source voltage VGS of the NMOS device Q drops below the threshold voltage VTH. The NMOS device Q quickly turns off, and the suppressor automatically returns to a high-impedance state for normal signals, waiting for the next protection.

[0039] Even after initial discharge and peak clipping by the protection circuit, the signal may still contain some residual high-frequency interference components. At this point, the signal enters the filtering circuit for further purification. The filtering circuit of this invention is a multi-stage bandpass filter network. Specifically, the connection is as follows: the first terminal of the first capacitor C1 is connected to the first wire, and the second terminal of the first capacitor C1 is connected to the second wire, forming the first stage of high-frequency filtering to ground. The first terminal of the first inductor L1 is connected to the first wire, the second terminal of the first inductor L1 is connected to the first terminal of the second capacitor C2, the second terminal of the second capacitor C2 is connected to the second wire, the first terminal of the second inductor L2 is connected to the second terminal of the first inductor L1, the second terminal of the second inductor L2 is connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is connected to the second wire. These components constitute a π-type or T-type filter structure of series inductors and parallel capacitors, used to smooth the pulse leading edge and filter out high-frequency noise. Furthermore, the first end of the third inductor L3 is connected to the second end of the second inductor L2, and the second end of the third inductor L3 is connected to the second wire; the first end of the fourth inductor L4 is connected to the first wire, and the second end of the fourth inductor L4 is connected to the second wire; the first end of the fifth inductor L5 is connected to the first wire, and the second end of the fifth inductor L5 is connected to the second wire. The third inductor L3, the fourth inductor L4, and the fifth inductor L5 also serve as filtering elements, providing a low-impedance path to ground for interference at specific frequencies, or forming a resonant circuit with capacitors to further enhance the suppression capability against interference outside the operating frequency band. Through the complex filtering network composed of inductors L1 to L5 and capacitors C1, C2, and C3, the residual energy of strong electromagnetic pulse signals is further reduced, and their waveform becomes smoother, such as... Figure 6 and Figure 7 As shown in the comparison, a strong electromagnetic pulse with a rising edge of 5 nanoseconds and a half-wave width of 20 nanoseconds is greatly reduced in amplitude after passing through the suppressor, thus achieving effective protection for the subsequent circuits.

[0040] In implementation, the filtering circuit and the protection circuit are integrated on the same printed circuit board, which is specifically designed with a ground plane. The second conductor must be reliably connected to this ground plane. This design is crucial, ensuring that when the protection circuit activates, the large transient current flows into the system ground through the shortest and most direct path, avoiding high reverse voltage caused by excessive parasitic inductance in the grounding path, thus guaranteeing the protection effect and safety of the suppressor. Through the coordinated operation of all the above components, this invention achieves rapid response and effective suppression of strong electromagnetic pulses with nanosecond-level rising edges, while ensuring the passage of normal signals, significantly improving the electromagnetic protection performance of the entire system.

[0041] The input signal refers to the electrical signal externally connected between the first and second conductors. This signal includes both the signal within the useful operating frequency band that the equipment needs to transmit during normal operation (i.e., the normal transmission signal) and strong electromagnetic pulse interference signals that need to be suppressed, such as lightning pulses, nuclear electromagnetic pulses, or high-power microwaves. The function of the suppressor is to distinguish and process these two different types of input signals. The normal transmission signal and the strong electromagnetic pulse are explained as follows: 1) Normal transmission signals refer to the electrical signals used by electronic devices in their intended operating environment to perform functions such as communication, control, or data processing. These signals typically have low voltage amplitudes, and their frequency range depends on the specific application. Taking a typical industrial control bus RS-422 or RS-485 interface as an example, its differential voltage signal amplitude during normal operation... Typically, the voltage range is between 200 millivolts and 5 volts, and the data transmission rate can vary from several kilohertz to tens of megahertz. For radio frequency communication equipment, the normal transmission signal is likely a continuous wave signal with a center frequency of 70 MHz and a power level of 0 dBm, approximately 1 milliwatt. In this invention, the suppressor is designed to operate without affecting these normal signals. Figure 5 The insertion loss curve shown illustrates the insertion loss of the suppressor for normal signals within the operating frequency band, for example, from DC to 80 MHz. Less than 0.6 dB. The definition of insertion loss is: ,in, This indicates the voltage amplitude of the input signal. This represents the voltage amplitude of the output signal after passing through the suppressor. From this, the relationship between the output voltage and the input voltage can be derived: .

[0042] For an amplitude A normal transmission signal of volts, through insertion loss After the decibel suppressor, its output voltage is: Volts, voltage attenuation for: The attenuation is less than 0.335 volts, ensuring signal integrity. Normally transmitted signals have continuous, regular waveforms that conform to specific encoding rules, such as sine waves or square waves. Their energy is concentrated within a specified operating frequency band and will not trigger the NMOS device Q in the suppressor to conduct.

[0043] 2) A strong electromagnetic pulse (ESP) is a transient, high-energy electromagnetic phenomenon characterized by a rapid increase in electric field intensity, reaching its peak within a very short time, followed by decay. The spectral range of these pulses is extremely wide, extending from several kilohertz to several hundred megahertz or even higher. (See the accompanying drawings of this invention.) Figure 6The nuclear electromagnetic pulse shown is an example; this is a typical waveform that has been quantized. Its rise time... Defined as the time required for the pulse to rise from 10% to 90% of its peak value, the rise time of this pulse is only... Nanosecond, that is: The pulse width of a high-power electromagnetic pulse (HMP) is typically referred to as its half-width at half-maximum (HWHM), which is the time it takes for the pulse to rise to half its peak value and then fall back to half its peak value. The HWHM of this pulse is 20 nanoseconds. Its electric field strength can reach a peak value of up to 50 kilovolts per meter, which, when applied to cables or circuits, can couple together to generate voltage spikes of thousands or even tens of thousands of volts and current surges of hundreds to thousands of amperes. For example, according to the surge immunity test waveform defined by the International Electrotechnical Commission (IEC) standard IEC 61000-4-5, the open-circuit voltage waveform of a combined wave signal generator is a 1.2 / 50 microsecond waveform with a rise time of 1.2 microseconds and a pulse width of 50 microseconds, while the short-circuit current waveform is an 8 / 20 microsecond waveform with a rise time of 8 microseconds and a pulse width of 20 microseconds. These all fall under the category of high-power electromagnetic pulses. Unlike normal transmission signals, high-power electromagnetic pulses have the following quantitative characteristics: extremely high voltage amplitude... Extremely high voltage means extremely fast energy injection rate; huge current peak; and wide spectrum coverage. These characteristics make it difficult for traditional protection devices to simultaneously achieve fast response and low junction capacitance. The NMOS device Q of this invention has a switching time... and Within the range of 50 picoseconds to 200 picoseconds, that is: This time is much faster than the rise time of a strong electromagnetic pulse, that is, it satisfies... The specific numerical relationships are as follows: ,and Therefore, the NMOS device Q can quickly turn on through the coupling of resistors R1 and R2 before the pulse energy causes damage, guiding the pulse energy to the varistor MOV for discharge, such as... Figure 7 As shown, the amplitude of the strong electromagnetic pulse is effectively suppressed, thus protecting the subsequent circuitry.

[0044] The ground plane is a conductive layer on a printed circuit board specifically used to connect to the system reference ground. In the suppressor, the second conductor is ultimately connected to this ground plane. The ground plane provides a low-impedance discharge path for strong electromagnetic pulse energy, ensuring that the pulse energy released by the varistor MOV can be quickly and safely conducted to ground, avoiding secondary interference or damage to subsequent circuits or the entire system. At the same time, the ground plane also provides a stable reference potential for the DC bias in the circuit.

[0045] like Figure 8 As shown, an embodiment of the present invention provides a method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device, comprising: S1. Based on the frequency range and power level of the input signal, calculate the specifications of the suitable NMOS device Q, first resistor R1, second resistor R2, varistor MOV, first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, first capacitor C1, second capacitor C2, and third capacitor C3, and select the corresponding components. The specific implementation process is as follows: S10. Based on the form and power level of the input signal, select appropriate protection and filtering devices to protect against strong electromagnetic pulse signals. The form of the input signal includes the signal type (e.g., continuous wave or pulse signal), waveform characteristics (e.g., rise time, pulse width), and frequency range (e.g., lower limit of the operating frequency band). and upper limit frequency The power level includes the average power of a normal signal. and peak power of strong electromagnetic pulse By comprehensively considering these factors, the specifications of each component are determined. Based on the application scenario of the suppressor, the lower limit frequency of the input signal's operating bandwidth is determined. and upper limit frequency For example, for radio frequency communication equipment, the operating frequency band may be 30 MHz to 80 MHz; for industrial control buses, the operating frequency band may be DC to 10 MHz. Simultaneously, the peak voltage of the normal signal needs to be determined. and average power And the peak voltage of the expected strong electromagnetic pulse. Peak current Ascent time Pulse width And waveform characteristics. These parameters can be obtained through system design specifications, electromagnetic compatibility standards such as IEC61000-4-5, or actual measurements.

[0046] S11. Calculate the specifications of each inductor and capacitor in the filter circuit based on the frequency range. The filter circuit consists of inductors L1, L2, L3, L4, L5, and capacitors C1, C2, and C3. Its function is to allow normal signals within the operating frequency band to pass through with low loss while suppressing out-of-band interference. A low-pass filter structure is typically used in the design, with a cutoff frequency of... Slightly above the upper limit frequency For example, take To ensure passband flatness. Based on the system characteristic impedance. For example, for 50 ohms, select a filter type such as Butterworth response, and obtain the normalized low-pass prototype element value by looking up a table. .for Figure 2In the circuit topology shown, the first inductor L1, the second inductor L2, and the third inductor L3 are inductors connected in series on the main path, and their actual inductance values ​​are... Calculated by the following formula: The fourth inductor L4 and the fifth inductor L5 are inductors connected in parallel between the first and second conductors. Their inductance values ​​are also subject to the above formula, but it should be noted that their positions in the network correspond to the parallel inductors in the normalized prototype. The first capacitor C1, the second capacitor C2, and the third capacitor C3 are all parallel capacitors, and their actual capacitance values ​​are... Calculated by the following formula: If the input signal has a defined lower frequency limit Furthermore, since low-frequency interference needs to be suppressed, a bandpass filter must be designed. This can be achieved through low-pass to bandpass frequency conversion, transforming the low-pass prototype into a bandpass network. Each inductor or capacitor will then be converted into an LC parallel or series resonant circuit. However, the circuit structure of this invention is pre-defined; therefore, in actual design, component values ​​can be adjusted according to bandpass specifications, for example, by optimizing the specific values ​​of each component using simulation software. The calculated theoretical values ​​need to be rounded according to standard series such as E12 and E24, selecting the closest standard inductor and capacitor values.

[0047] S12. Calculate the specifications of each component in the protection circuit based on the power rating. The protection circuit consists of an NMOS device Q, a first resistor R1, a second resistor R2, and a varistor MOV, specifically: First, select the NMOS device Q. Its drain-source breakdown voltage must be considered. It should be greater than the maximum peak voltage that the input signal may produce, including the peak voltage of the normal signal. and peak value of strong electromagnetic pulse , usually take Its pulsed drain current It needs to be greater than the peak current of a strong electromagnetic pulse. Continuous drain current Average power requirements must be met. Simultaneously, the switching time of the NMOS must be... and It should be much smaller than the rise time of a strong electromagnetic pulse. That is, satisfy For example, for Nanosecond pulses should be selected Picosecond devices. Additionally, on-resistance. The impedance of the discharge path should be minimized to reduce its overall impedance. When selecting an NMOS device Q, its characteristics of high current carrying capacity, short switching time, and high breakdown voltage must be fully considered. High current carrying capacity is reflected in the device's pulsed drain current. It needs to be greater than the peak current of a strong electromagnetic pulse. Short switching time is reflected in the device's on-time. and shutdown time Both must be much shorter than the rise time of a strong electromagnetic pulse. , usually requires Picosecond and Picoseconds; the breakdown voltage is largely reflected in the drain-source breakdown voltage of the device. Must meet By selecting the appropriate circuitry, the response time of the protection circuit can be ensured to be less than the rise time of a strong electromagnetic pulse, thus meeting the protection requirements.

[0048] Secondly, select a varistor (MOV). Its varistor voltage... It should be slightly higher than the peak voltage of the normal signal to avoid malfunction under normal signal conditions. Generally, it should be taken as... Maximum peak current It needs to be greater than the peak current of a strong electromagnetic pulse. Energy tolerance Requires greater than pulse energy The pulse energy can be estimated using an approximate formula: ,in, This is a waveform coefficient, which can be taken as 0.5 to 0.8 for exponentially decaying pulses, depending on the waveform shape. The parasitic capacitance of the varistor. It should be as small as possible, but since the NMOS device Q is connected in series, the effect of this capacitor on the signal has been weakened, so the requirement can be relaxed appropriately.

[0049] Next, select the first resistor R1 and the second resistor R2. These two resistors form a voltage divider coupling circuit, used to detect the input signal voltage and drive the gate of the NMOS. Their resistance values ​​need to be determined based on the gate input capacitance of the NMOS. The desired response time is determined. Let the gate equivalent resistance be... and Parallel values: Then the gate drive time constant To enable NMOS to turn on quickly, the following conditions must be met. Therefore, the solution can be found The range. For example, if nanosecond Pifa requires Ohms. At the same time, the resistor's rated power must take into account power consumption under normal signal conditions and the gate voltage during normal operation. Typically low power consumption, 1 / 8 watt or 1 / 4 watt surface-mount resistors can be selected. Furthermore, the values ​​of the first resistor R1 and the second resistor R2 must ensure that the gate voltage is below the NMOS threshold voltage under normal signal conditions. Under a strong electromagnetic pulse, it can rise rapidly to The above. The specific resistance ratio can be determined through the voltage divider relationship. For example, let the input voltage be... Then the gate voltage is: Normal signal Strong electromagnetic pulse Adjustments can be made accordingly. and The ratio of .

[0050] S13. Based on the above calculations, select component models that meet the specifications from the market. Since the actual component parameters are standard series, the theoretical calculation values ​​need to be adjusted to the closest standard values, and the circuit performance needs to be recalculated. For example, standard series inductors such as 2.2 nanohenries and 4.7 nanohenries can be selected, and capacitor values ​​such as 1 picofarad and 10 picofarad can be selected. When selecting specific models, engineering factors such as package type, operating temperature range, and reliability also need to be considered. Afterwards, the protection circuit and filter circuit can be jointly simulated using circuit simulation software such as SPICE to verify whether the insertion loss, response time, pulse suppression effect, and other indicators meet the design requirements. If the simulation results are not ideal, the component values ​​need to be fine-tuned or the components need to be reselected until all performance indicators are met.

[0051] By following the four steps above, the specifications of the appropriate NMOS device Q, first resistor R1, second resistor R2, varistor MOV, first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, first capacitor C1, second capacitor C2, and third capacitor C3 can be accurately calculated based on the frequency range and power level of the input signal. This allows for the selection of the corresponding components and provides a reliable foundation for subsequent circuit design and fabrication.

[0052] In this context, power rating refers to the power level of the input signal under normal operating conditions and the potential impact of strong electromagnetic pulses, including average power and peak power. Average power determines the rated power selection of resistive devices and some semiconductor devices in the circuit, usually measured in watts. Peak power determines the withstand voltage, current carrying capacity, and energy absorption capacity of semiconductor devices such as NMOS devices (Q) and varistors (MOV), usually measured in watts or kilowatts. For strong electromagnetic pulses, the power rating also needs to be comprehensively evaluated in conjunction with factors such as pulse width, rise time, and duty cycle to ensure that the selected components can operate reliably without damage under transient high-energy impacts.

[0053] S2. Design a protection circuit based on the selected NMOS device Q, the first resistor R1, the second resistor R2, and the varistor MOV; S3. Design a filter circuit based on the selected first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, first capacitor C1, second capacitor C2 and third capacitor C3. S4. Based on the size requirements and production quantity of the strong electromagnetic pulse suppressor, design and fabricate a printed circuit board. Set a ground plane on the printed circuit board and electrically connect the second conductor to the ground plane. The specific implementation process is as follows: S40. Based on the size requirements of the strong electromagnetic pulse suppressor, determine the external dimensions, thickness, and mounting hole positions of the printed circuit board (PCB). Size requirements typically stem from the structural space constraints of the overall system, such as a rectangular shape with length, width, and height of a few millimeters. The internal space of the housing and the positional compatibility of the input and output interfaces must also be considered. Determine the PCB manufacturing process based on the production quantity. For small batches (less than one hundred pieces), select standard FR-4 substrate and conventional processes, using panelization to reduce per-board costs. For large batches (more than one thousand pieces), consider compatibility with automated production lines, selecting high-precision drilling and solder mask processes, and designing process edges and positioning holes to accommodate the automated placement requirements of pick-and-place machines.

[0054] S41. Determine the number of layers on the printed circuit board (PCB) based on the circuit complexity and electromagnetic compatibility requirements of the strong electromagnetic pulse suppressor. Since the protection and filtering circuits contain multiple inductors, capacitors, and NMOS devices (Q), and low-impedance grounding is required, a four-layer structure is typically used. The first layer is the top layer, used to place all components and the traces for the first and second conductors; the second layer is the ground layer, set as a complete, continuous copper foil plane to provide a low-impedance reference ground; the third layer is the power layer or auxiliary routing layer, arranged according to actual needs; the fourth layer is the bottom layer, used for auxiliary routing or as an additional ground layer. The spacing between the ground layer and the top layer is controlled within the range of 0.2 mm to 0.3 mm to form a microstrip line structure and control the characteristic impedance of the signal lines. By setting the ground layer as a complete plane, the electromagnetic field is ensured to be confined between the signal layer and the ground layer, reducing electromagnetic radiation and external interference coupling.

[0055] S42. A ground plane is provided on the second layer of the printed circuit board. The ground plane is covered with copper foil, with a thickness of 1 ounce or 2 ounces, to provide sufficient current carrying capacity. Electrical connection between the ground plane and the top layer is achieved through an array of vias. For the second conductor, its trace on the top layer is directly connected to the ground plane through multiple vias, the number of which is determined based on the peak current of the strong electromagnetic pulse. For example, if the peak current of the strong electromagnetic pulse... For a current carrying capacity of 100 amps, and with a single via having a current carrying capacity of approximately 1 amp, at least 100 vias need to be evenly distributed along the trace path of the second conductor to form a low-impedance discharge path. The via diameter is typically 0.3 mm, and the copper plating thickness on the via wall is 25 micrometers. The ground plane also corresponds to the mounting studs of the housing, and exposed copper foil pads are provided in the area where the printed circuit board contacts the housing for low-impedance electrical connection with the housing during subsequent assembly.

[0056] S43. The first and second conductors serve as the main paths for the input and output signals, respectively. Their characteristic impedances must be strictly controlled to match the system's characteristic impedance. Typically, it is 50 ohms. According to the microstrip line characteristic impedance calculation formula: ,in, Characteristic impedance, The relative permittivity of the printed circuit board substrate. The dielectric thickness between the top layer and the ground layer. The width of the conductor. The thickness is the copper foil thickness. Based on the target impedance. Ohm, the wire width can be calculated by reverse calculation. When routing the first and second conductors, avoid sharp bends and use 45-degree angles or rounded traces to reduce signal reflection. The second conductor is connected to the ground plane through vias at multiple locations to ensure that the impedance between the second conductor and the ground plane is as low as possible at any point.

[0057] S44. According to the circuit schematic, arrange the NMOS device Q, first resistor R1, second resistor R2, varistor MOV, first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, first capacitor C1, second capacitor C2, and third capacitor C3 according to the signal flow direction. The NMOS device Q and varistor MOV form a protection circuit, which needs to be placed near the first conductor entrance to ensure that the energy of strong electromagnetic pulses is quickly discharged before entering the subsequent circuit. The inductors L1 to L5 and capacitors C1 to C3 in the filter circuit are arranged in the order of signal flow to form a multi-stage filter structure. The pad size of all components is designed according to the package type. For surface mount components, the pad width and length are determined according to the component size. For example, for resistors and capacitors in a 0402 package, the pad size is 0.5 mm by 0.5 mm. For the NMOS device Q, the corresponding pad shape and size are designed according to its package type, such as SOT-23 or DPAK.

[0058] S45. Exposed copper foil areas, called ground pads, are designed at the four corners of the printed circuit board or at locations corresponding to the mounting studs of the housing. These ground pads are directly connected to the ground plane through multiple vias, forming a low-impedance grounding path. No solder mask is placed around the ground pads to ensure direct electrical contact with the mounting studs or bosses of the housing during subsequent assembly. The ground pads are typically circular with a diameter of 3 mm to 5 mm, with a 2.5 mm diameter through-hole in the center for screw mounting. The number of ground pads is determined by the size of the suppressor, ensuring multiple parallel discharge paths between the ground plane and the housing.

[0059] S46. After completing the layout and routing, use electronic design automation (EDA) software to export the photoplot files required for processing, including the top copper foil layer, ground copper foil layer, bottom copper foil layer, top solder mask layer, bottom solder mask layer, top silkscreen layer, bottom silkscreen layer, and drilling files. Verify that the layer stack-up order, via dimensions, pad dimensions, and conductor widths in all files conform to the design rules. Send the processing files to the PCB manufacturer and select the appropriate processing technology based on the production quantity. For small-batch production, select standard processes such as chemical copper plating, outer layer pattern plating, hot air leveling, or organic solder mask surface treatment; for large-batch production, select more automated processes such as vertical continuous plating, automated optical inspection, and flying probe testing or fixture testing.

[0060] S47. Upon receiving the printed circuit board, first inspect its appearance to ensure there are no scratches, bubbles, or peeling solder mask. Use a multimeter to measure the DC resistance between the second conductor and the ground plane to verify the reliability of the via connection; theoretically, the resistance should be less than 0.1 ohms. Use an impedance meter to measure the characteristic impedance of the first and second conductors to verify that they meet the design requirement of 50 ohms, with an allowable error range of ±10%. Use a flying probe tester or a custom fixture to perform electrical continuity testing on the printed circuit board to confirm that there are no short circuits or open circuits between all component pads. For mass-produced printed circuit boards, take samples for temperature cycling and solderability testing to ensure the reliability of the printed circuit board in subsequent soldering processes.

[0061] When designing printed circuit boards (PCBs), special attention must be paid to the grounding design to ensure that the strong electromagnetic pulse suppressor can effectively dissipate the energy of the strong electromagnetic pulse. Specific measures include setting a complete ground plane on the PCB, connecting the second conductor to the ground plane with low impedance through multiple vias, and reserving sufficient pads or mounting holes at the contact point between the ground plane and the casing to form a low-impedance discharge path.

[0062] S5. The selected NMOS device Q, first resistor R1, second resistor R2, varistor MOV, first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, first capacitor C1, second capacitor C2 and third capacitor C3 are soldered onto the printed circuit board according to the designed positions to obtain a strong electromagnetic pulse suppressor.

[0063] For surface mount components, a program is created using a pick-and-place machine to automate the placement of these components. When creating the program, the pick-and-place machine's pick-up position, placement sequence, and placement pressure must be set according to the bill of materials and placement coordinate file to ensure that all surface mount components are accurately placed onto their corresponding pads on the printed circuit board. Reflow soldering is then used to complete the soldering process.

[0064] Optionally, in S2, a protection circuit is designed based on the selected NMOS device Q, the first resistor R1, the second resistor R2, and the varistor MOV, including: S20. Connect the first end of the first resistor R1 to the first wire, connect the second end of the first resistor R1 to the gate of the NMOS device Q, connect the first end of the second resistor R2 to the gate of the NMOS device Q, connect the second end of the second resistor R2 to the second wire, connect the drain of the NMOS device Q to the first wire, connect the source of the NMOS device Q to the first end of the varistor MOV, and connect the second end of the varistor MOV to the second wire.

[0065] The NMOS device Q exhibits switching characteristics, specifically: when the voltage between the gate and source of the NMOS device Q changes... Rise to the threshold voltage of the NMOS device Q When the source and drain of the NMOS device Q are connected, the device is in a state of conduction; when... Reduce to When the NMOS device Q is in a certain state, the source and drain are disconnected. Based on this characteristic, a protection circuit is designed. The first resistor R1 and the second resistor R2 form a coupling circuit. When a strong electromagnetic pulse appears in the input signal, the input voltage increases. The voltage is then reduced by the voltage divider effect of the first resistor R1 and the second resistor R2. Rising rapidly to In this configuration, the source and drain of the NMOS device Q are connected, allowing a strong electromagnetic pulse signal to be discharged across the varistor MOV, thus protecting the downstream circuitry. After the strong electromagnetic pulse signal is discharged, the input voltage returns to normal. Reduce to In this case, the source and drain of the NMOS device Q are disconnected, and the normal transmission signal is transmitted to the next stage circuit. This resistive coupling method can detect single-pulse signals and achieves a fast response.

[0066] Optionally, in S3, a filter circuit is designed based on the selected first inductor L1, second inductor L2, third inductor L3, fourth inductor L4, fifth inductor L5, first capacitor C1, second capacitor C2, and third capacitor C3, including: S30. Connect the first terminal of the first capacitor C1 to the first wire, connect the second terminal of the first capacitor C1 to the second wire, connect the first terminal of the first inductor L1 to the first wire, connect the second terminal of the first inductor L1 to the first terminal of the second capacitor C2, connect the second terminal of the second capacitor C2 to the second wire, connect the first terminal of the second inductor L2 to the second terminal of the first inductor L1, connect the second terminal of the second inductor L2 to the first terminal of the third capacitor C3, connect the second terminal of the third capacitor C3 to the second wire, connect the first terminal of the third inductor L3 to the second terminal of the second inductor L2, connect the second terminal of the third inductor L3 to the second wire, connect the first terminal of the fourth inductor L4 to the first wire, connect the second terminal of the fourth inductor L4 to the second wire, connect the first terminal of the fifth inductor L5 to the first wire, and connect the second terminal of the fifth inductor L5 to the second wire.

[0067] In designing the filter circuit, a bandpass filter is used to ensure normal signal transmission within the operating frequency band. The bandpass filter circuit consists of a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, and a first capacitor C1, a second capacitor C2, and a third capacitor C3 connected as described above. Its passband range is set according to the frequency range of the input signal, allowing normal signals within the operating frequency band to pass through with low loss, while effectively suppressing residual interference from strong electromagnetic pulses outside the operating frequency band.

[0068] Optionally, the above technical solution also includes: S6. Assemble the soldered printed circuit board into the housing to obtain a strong electromagnetic pulse suppressor with a housing.

[0069] The outer casing can be designed as a rectangular metal box, made of aluminum alloy or galvanized steel sheet to provide good electromagnetic shielding performance and mechanical strength. The inside of the box has a cavity for accommodating the printed circuit board, and mounting studs or soldering bosses are reserved at the position corresponding to the ground layer of the printed circuit board to realize the electrical connection of the printed circuit board to the ground. Input and output interfaces, such as RF coaxial connectors or terminals, are respectively provided at both ends of the box for connecting the first and second wires. Grounding studs may be designed on the side wall or bottom of the box for connecting the outer casing to the system ground. The process of assembling the soldered printed circuit board (PCB) into the housing is as follows: First, the ground layer of the PCB with all soldered components is tightly fitted to the mounting studs or bosses inside the housing using conductive pads or direct contact, and then secured with screws to ensure that the second conductor achieves a low-impedance electrical connection with the housing through the PCB ground layer. Next, the inner conductors of the input and output interfaces are soldered or crimped to the first and second conductors on the PCB, respectively, and the interface flanges are fixed to the housing end face with screws. Finally, the housing cover is closed and secured with screws, completing the mechanical assembly and electrical encapsulation of the entire suppressor. This allows the housing to not only provide physical protection but also serve as an electromagnetic shield and part of the grounding reference plane, contributing to the suppressor's operation.

[0070] During assembly, care must be taken to avoid introducing additional electromagnetic compatibility issues. Specific measures include ensuring good conductive contact between the cover plate and the housing, which can be achieved by using conductive gaskets or conductive strips to enhance shielding continuity; maintaining low impedance laps between the flanges of input and output interfaces and the housing; avoiding routing internal cables parallel to sensitive signal paths; and checking the torque values ​​of all fastening screws after assembly to ensure assembly reliability.

[0071] After the outer casing is assembled, the high electromagnetic pulse suppressor is finally manufactured through processes such as welding, assembly, and potting. The potting process uses thermally conductive epoxy resin potting compound to completely encapsulate the printed circuit board within the cavity of the outer casing. After the potting compound cures, it forms a protective layer, enhancing the suppressor's resistance to vibration and impact, as well as its environmental adaptability.

[0072] Optionally, the above technical solution also includes: S7. The performance of the high electromagnetic pulse suppressor with a shell is verified. The specific implementation process is as follows: S70. Prepare a vector network analyzer, a pulse generator, an oscilloscope, a signal source, a spectrum analyzer, and the corresponding test cables and adapters. The vector network analyzer is used to measure the insertion loss. The pulse generator is used to simulate the waveform of a strong electromagnetic pulse. The oscilloscope is used to observe the time-domain waveforms before and after the pulse passes through the suppressor. Connect the strong electromagnetic pulse suppressor with a housing to be tested to the signal output terminal of the test equipment through the input interface, and connect it to the signal input terminal or load terminal of the test equipment through the output interface. The grounding stud of the suppressor housing is connected to the system reference ground through a low-impedance ground wire to ensure reliable grounding of the test circuit.

[0073] S71. After calibrating the vector network analyzer, set the frequency sweep range from DC to 1.5 times the upper limit frequency, for example, sweep from 100 kHz to 120 MHz, and set the intermediate frequency bandwidth to 10 kHz to obtain sufficient dynamic range. Connect the suppressor to be tested between port 1 and port 2 of the vector network analyzer, and measure the transmission coefficient in its scattering parameters. Record the insertion loss values within the entire operating frequency band and verify whether they meet the design specifications. Insertion loss is calculated by the formula: , where represents the voltage transmission coefficient from port 1 to port 2, which is a complex number, and its modulus reflects the amplitude ratio of the output voltage to the input voltage. If the measured insertion loss is less than 0.6 dB within the operating frequency band, it is determined that this indicator is qualified.

[0074] S72. Set the signal source to a certain frequency within the operating frequency band, for example, 70 MHz, and set the output power to the level corresponding to the normal signal power level, for example, 0 dBm corresponds to 1 mW. Connect the suppressor to be tested between the signal source and the spectrum analyzer, measure the power level of the output signal, and calculate the power attenuation after the signal passes through the suppressor. At the same time, set the signal source to output a modulated signal, such as an amplitude-modulated signal or a frequency-modulated signal, and observe the waveform distortion of the output signal through the oscilloscope to verify whether the influence of the suppressor on the normal signal waveform is within an acceptable range.

[0075] S73. Set the pulse generator to output a strong electromagnetic pulse waveform that meets the design requirements, for example, a nuclear electromagnetic pulse simulation waveform with a rise time of 5 ns, a full width at half maximum of 20 ns, and a peak voltage of 1 kV. Connect the suppressor to be tested between the pulse generator and the oscilloscope. The oscilloscope monitors the voltage waveforms at the input and output terminals of the suppressor through a high-voltage probe respectively. The waveform observed at the input terminal should be consistent with the waveform set by the pulse generator, and record the peak voltage of the input pulse. Observe the waveform after passing through the suppressor at the output terminal and record the peak voltage Calculate the pulse attenuation factor of the suppressor: and protection efficiency: Verify that the residual voltage at the output terminal is lower than the safe operating voltage threshold of the subsequent circuit. For example, suppressing a 1 kV input pulse to below 50 V will achieve a protection efficiency of over 95%. Simultaneously, use an oscilloscope to observe the action time of the protection circuit to verify whether the NMOS device Q turns on rapidly during the pulse rising edge. Its response time should match the design value, i.e., within the range of 50 picoseconds to 200 picoseconds.

[0076] After a strong electromagnetic pulse signal passes through the protection circuit, its energy is reduced. The subsequent filtering circuit further suppresses interference outside the operating frequency band in the residual waveform, protecting the subsequent circuitry. During verification, the residual waveform at the suppressor output was observed using an oscilloscope, confirming that the signal components within the operating frequency band were preserved, while high-frequency interference components outside the operating frequency band were effectively attenuated. This verifies that the bandpass filtering effect of the filtering circuit meets the design requirements.

[0077] S74. Set a pulse generator to continuously output strong electromagnetic pulses with the same parameters at a repetition frequency, such as once per minute, to subject the suppressor under test to multiple impacts, for example, 100 consecutive impacts. After each impact, observe the insertion loss and protection efficiency of the suppressor to verify whether its performance has degraded. Simultaneously, use a thermal imager to monitor the temperature change of the suppressor casing to verify whether the temperature rise of the varistor MOV and NMOS device Q after absorbing pulse energy is within the rated operating temperature range of the components.

[0078] S75. Place the suppressor in an electromagnetic compatibility test environment and apply a radio frequency radiation field within its operating frequency band to verify whether the suppressor will malfunction or experience performance degradation due to radiated interference within its own operating frequency band. Simultaneously test the shielding effectiveness of the suppressor housing. By placing the suppressor housing between the antenna transmitter and receiver, measure the difference in received power with and without the housing to verify whether the shielding capability of the metal housing against electromagnetic interference meets the design requirements.

[0079] S76. Compile all test data into a verification report, including insertion loss curve, normal signal transmission waveform, strong electromagnetic pulse input / output waveform, pulse attenuation calculation results, protection efficiency calculation results, performance change data after multiple impacts, and electromagnetic compatibility test data. Compare each data point with the design specifications one by one. If all specifications meet the requirements, the performance verification of the enclosed strong electromagnetic pulse suppressor is deemed qualified and it can be put into practical application. If any specification fails to meet the requirements, it is necessary to return to the previous steps to troubleshoot the problem, adjust the component selection or assembly process, and then re-verify.

[0080] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0081] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A strong electromagnetic pulse suppressor based on MOSFET devices, characterized in that, It includes a filter circuit, as well as a protection circuit containing an NMOS device, a first resistor, a second resistor, and a varistor; The first end of the first resistor is connected to the first wire, and the second end of the first resistor is connected to the gate of the NMOS device; The first end of the second resistor is connected to the gate of the NMOS device, and the second end of the second resistor is connected to the second wire; The drain of the NMOS device is connected to the first wire; The source of the NMOS device is connected to the first end of the varistor, and the second end of the varistor is connected to the second wire; The filter circuit is connected between the first wire and the second wire; The protection circuit is used to receive input signals through the first wire and the second wire.

2. The strong electromagnetic pulse suppressor based on a MOSFET device according to claim 1, characterized in that, The filtering circuit includes a first capacitor, a first end of which is connected to the first wire, and a second end of which is connected to the second wire.

3. A strong electromagnetic pulse suppressor based on a MOSFET device according to claim 2, characterized in that, The filter circuit further includes a first inductor, a second capacitor, a third capacitor, a first end of the first inductor connected to the first wire, a second end of the first inductor connected to the first end of the second capacitor, a second end of the second capacitor connected to the second wire, a first end of the second inductor connected to the second end of the first inductor, a second end of the second inductor connected to the first end of the third capacitor, and a second end of the third capacitor connected to the second wire.

4. A strong electromagnetic pulse suppressor based on a MOSFET device according to claim 3, characterized in that, The filter circuit further includes a third inductor, a fourth inductor, and a fifth inductor. The first end of the third inductor is connected to the second end of the second inductor, and the second end of the third inductor is connected to the second wire. The first end of the fourth inductor is connected to the first wire, and the second end of the fourth inductor is connected to the second wire. The first end of the fifth inductor is connected to the first wire, and the second end of the fifth inductor is connected to the second wire.

5. A strong electromagnetic pulse suppressor based on a MOSFET device according to any one of claims 1 to 4, characterized in that, The filtering circuit and the protection circuit are integrated on the same printed circuit board, which has a grounding layer, and the second conductor is connected to the grounding layer.

6. A method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device, characterized in that, include: Based on the frequency range and power level of the input signal, calculate the specifications of the suitable NMOS device, first resistor, second resistor, varistor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor, and select the corresponding components. Design a protection circuit based on the selected NMOS device, first resistor, second resistor, and varistor; Design a filter circuit based on the selected first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor; Based on the size requirements and production quantity of the strong electromagnetic pulse suppressor, a printed circuit board is designed and manufactured. A grounding layer is set on the printed circuit board, and the second conductor is electrically connected to the grounding layer. The selected NMOS device, first resistor, second resistor, varistor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor are soldered onto the printed circuit board at the designed positions to obtain a strong electromagnetic pulse suppressor.

7. The method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device according to claim 6, characterized in that, Design a protection circuit based on the selected NMOS device, first resistor, second resistor, and varistor, including: Connect the first end of the first resistor to the first wire, connect the second end of the first resistor to the gate of the NMOS device, connect the first end of the second resistor to the gate of the NMOS device, connect the second end of the second resistor to the second wire, connect the drain of the NMOS device to the first wire, connect the source of the NMOS device to the first end of the varistor, and connect the second end of the varistor to the second wire.

8. The method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device according to claim 7, characterized in that, Design a filter circuit based on the selected first inductor, second inductor, third inductor, fourth inductor, fifth inductor, first capacitor, second capacitor, and third capacitor, including: Connect the first terminal of the first capacitor to the first wire, connect the second terminal of the first capacitor to the second wire, connect the first terminal of the first inductor to the first wire, connect the second terminal of the first inductor to the first terminal of the second capacitor, connect the second terminal of the second capacitor to the second wire, connect the first terminal of the second inductor to the second terminal of the first inductor, connect the second terminal of the second inductor to the first terminal of the third capacitor, connect the second terminal of the third capacitor to the second wire, connect the first terminal of the third inductor to the second terminal of the second inductor, connect the second terminal of the third inductor to the second wire, connect the first terminal of the fourth inductor to the first wire, connect the second terminal of the fourth inductor to the second wire, connect the first terminal of the fifth inductor to the first wire, and connect the second terminal of the fifth inductor to the second wire.

9. A method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device according to any one of claims 6 to 8, characterized in that, Also includes: The soldered printed circuit board is assembled into a housing to obtain a strong electromagnetic pulse suppressor with a housing.

10. The method for fabricating a strong electromagnetic pulse suppressor based on a MOSFET device according to claim 9, characterized in that, Also includes: Performance verification was performed on a high electromagnetic pulse suppressor with a housing.

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