High drive IO power glitch handling circuit

Abstract

The application discloses a kind of high drive IO power supply burr processing circuits, by setting multiple IO modules and ESD protection modules on chip base guide, IO module includes first delay drive circuit and second delay drive circuit, level conversion unit receives the digital square wave signal input by digital signal input end, respectively obtains DRP signal and DRN signal by DRP signal processing unit and DRN signal processing unit processing, DRP signal and DRN signal drive multiple MOS in each group of effective delay circuit in turn and obtain square wave signal, digital signal output unit is processed to the square wave signal of surge protection unit and is output to first delay drive circuit, utilize the gate-source capacitance of drive pipe and resistance and form multiple groups of effective delay circuit, ensure that effective delay is formed between each group of effective delay circuit, solve the influence of through current to power supply from IO module inside, solve IO to power supply in combination with chip layout processing, enhance power anti-interference performance.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a high-drive IO power supply glitch processing circuit. Background Technology

[0002] I / O (Input / Output) is the interface between the chip's internal components and the external environment. With increasing customer demands, beyond simple ESD protection, greater drive capability is required to meet user needs. Therefore, improving I / O drive capability is essential. Traditional high-drive I / O systems exhibit significant sink and source currents during high-speed switching, pulling the I / O power ground high or low. If the I / O power supply shares a power line with the internal chip, the impact of the I / O on the power supply can range from poor performance to serious chip malfunctions—a major drawback of traditional chip I / O design. Technological advancements have led to separating I / O traces from internal chip module traces, significantly reducing I / O interference. However, when I / O with high drive capability is operating, the through-current can affect power supply stability, leading to abnormal operation or poor performance of internal chip modules. Therefore, a high-drive I / O power supply glitches processing circuit is urgently needed to address these technical problems. Summary of the Invention

[0003] In view of this, the present invention provides a high-drive IO power supply glitch processing circuit, which can effectively solve the problem of through current affecting the power supply and reduce power supply interference. Specifically, the following technical solution is adopted to achieve this.

[0004] This invention provides a high-drive IO power supply glitch processing circuit, including a chip base conductor, a plurality of IO modules disposed on the chip base conductor, and an ESD protection module located between two of the IO modules; The IO module includes a first delay driving circuit and a second delay driving circuit. The first delay driving circuit includes a digital signal input terminal, a level conversion unit, a DRP signal processing unit, and a DRN signal processing unit. The digital signal input terminal, the DRP signal processing unit, and the DRN signal processing unit are all connected to the level conversion unit. The second delay drive circuit includes a rectifier unit, an effective delay unit, a surge protection unit, and a digital signal output unit. The effective delay unit and the surge protection unit are both connected to the rectifier unit. The effective delay unit and the digital signal output unit are both connected to the surge protection unit. The effective delay unit includes multiple sets of effective delay circuits connected to the DRP signal processing unit and the DRN signal processing unit. The level conversion unit receives the digital square wave signal input from the digital signal input terminal, and processes it through the DRP signal processing unit and the DRN signal processing unit to obtain the DRP signal and the DRN signal, respectively. The DRP signal and the DRN signal sequentially drive multiple MOS transistors in each group of effective delay circuits to turn on and off to obtain the square wave signal. The digital signal output unit outputs the square wave signal processed by the surge protection unit to the first delay drive circuit.

[0005] As a preferred embodiment of the above technical solution, the DRP signal processing unit includes a NAND gate ANAND1, a first delay unit and an inverter INV7, and the DRN signal processing unit includes an inverter INV4, a NAND gate ANAND2, a second delay unit, an inverter INV5 and an inverter INV6. The first input of NAND gate ANAND1 is connected to the level conversion unit, the second input of NAND gate ANAND1 is connected to the output of the second delay unit, the output of NAND gate ANAND1 is connected to the input of inverter INV7 and the first delay unit, the input of inverter INV4 is connected to the level conversion unit, the output of inverter INV4 is connected to the second input of NAND gate ANAND2, the first input of NAND gate ANAND2 is connected to the output of the first delay unit, the output of NAND gate ANAND2 is connected to the input of the second delay unit and the input of inverter INV5, and the output of inverter INV5 is connected to the input of inverter INV6. The output of inverter INV7 is used to output a DRP signal to the second delay drive circuit, and the output of inverter INV6 is used to output a DRN signal to the second delay drive circuit.

[0006] As a preferred embodiment of the above technical solution, the level conversion unit is used to convert digital voltage into analog voltage, and both the first delay unit and the second delay unit include a plurality of inverters.

[0007] As a preferred embodiment of the above technical solution, the first input terminal of the NAND gate ANAND1 receives the digital square wave signal and outputs a first output signal after passing through the first delay unit. The inverter INV4 receives the digital square wave signal and outputs a second output signal to the second input terminal of the NAND gate ANAND2. The first output signal and the second output signal are ANDed to obtain a third output signal. The third output signal is sequentially passed through inverters INV5 and INV6 to obtain the DRN signal. The third output signal is output to the second output terminal of the NAND gate ANAND1 through the second delay unit and ANDed with the digital square wave signal to obtain the fourth output signal. The fourth output signal is then passed through the inverter IVV7 to obtain the DRP signal.

[0008] As a preferred embodiment of the above technical solution, the rectifier unit includes diode D3 and diode D4. The cathode of diode D4 is connected to the power input terminal, the anode of diode D4 and the cathode of diode D3 are connected to the surge protection unit, and the anode of diode D3 is connected to the ground terminal.

[0009] As a preferred embodiment of the above technical solution, the second delay driving circuit further includes a PAD unit. The effective delay unit includes a first effective delay circuit, a second effective delay circuit, and a third effective delay circuit. Diodes D3 and D4, the first effective delay circuit, the second effective delay circuit, the third effective delay circuit, and the surge protection unit are all connected to the PAD unit. The first effective delay circuit includes MOSFETs P1 and P2. The second effective delay circuit includes resistors R1, P2, R2, and N2. The third effective delay circuit includes resistors R3, P3, R4, and N3. The cathode of diode D4 is connected to the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3. The anode of diode D4 is connected to the PAD unit, the drain of MOSFET P1, the drain of MOSFET N1, the drain of MOSFET P2, the drain of MOSFET N2, the drain of MOSFET P3, and the drain of MOSFET P3. The gate of MOSFET P1 is connected to one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is connected to the gate of MOSFET P2. The other end of resistor R3 is connected to the gate of MOSFET P3. The gate of MOSFET N1 is connected to one end of resistor R2 and one end of resistor R4. The other end of resistor R2 is connected to the gate of MOSFET N2. The other end of resistor R4 is connected to the gate of MOSFET N3. The anode of diode D3 is connected to the source of MOSFET N1, the source of MOSFET N2, and the source of MOSFET N3 and then connected to the ground terminal.

[0010] As a preferred embodiment of the above technical solution, the resistance value of resistor R3 is twice the resistance value of resistor R1, and the resistance value of resistor R4 is twice the resistance value of resistor R2.

[0011] As a preferred embodiment of the above technical solution, the surge protection unit includes a resistor SR1, the DRP signal and the DRN signal drive the MOSFET and MOSFET P1 respectively, the DRN signal passes through resistors R2 and R4 to obtain the DRN1 signal and the DRN2 signal, and the DRN1 signal and the DRN2 signal drive the MOSFET N2 and the MOSFET N3 respectively. The DRP signal passes through resistors R1 and R3 to obtain DRP1 and DRP2 signals. The DRP1 and DRP2 signals drive MOSFETs P2 and P3 respectively, and the resulting square wave signals are transmitted to the PAD unit and then fed back to the digital signal output unit through resistor SR1.

[0012] As a preferred embodiment of the above technical solution, the DRN signal and DRP signal in each group of effective delay circuits are staggered, MOS transistors P1, P2 and P3 are all PMOS transistors, and MOS transistors N1, N2 and N3 are all NMOS transistors. The bit width range of MOSFETs P1, P2 and P3 is 15~40um, and the bit width range of MOSFETs N1, N2 and N3 is 20~40um.

[0013] As a preferred embodiment of the above technical solution, the ESD protection module includes a resistor R, a capacitor C, an inverter INV, and an NMOS transistor. The other end of the resistor R is connected to the first input terminal of the inverter INV and one end of the capacitor C. The other end of the resistor R is connected to the second input terminal of the inverter INV and the drain of the NMOS transistor, which is connected to the power input terminal. The other end of the capacitor C is connected to the third input terminal of the inverter INV and the source of the NMOS transistor, which is connected to the ground terminal. The output terminal of the inverter INV is connected to the gate of the NMOS transistor.

[0014] This invention provides a high-drive I / O power supply glitch handling circuit. Multiple I / O modules and an ESD protection module are arranged on the chip substrate. Each I / O module includes a first delay drive circuit and a second delay drive circuit. A level conversion unit receives a digital square wave signal input from the digital signal input terminal, and processes it through a DRP signal processing unit and a DRN signal processing unit to obtain DRP and DRN signals respectively. The DRP and DRN signals sequentially drive multiple MOS transistors in each effective delay circuit to turn on and off, resulting in a square wave signal. A digital signal output unit outputs the square wave signal processed by the surge protection unit to the first delay drive circuit. Multiple effective delay circuits formed by the gate-source capacitance and resistance of the drive transistors ensure an effective delay between each group of effective delay circuits. This addresses the impact of through-current on the power supply from within the I / O module and combines chip layout processing to mitigate the influence of I / O on the power supply, reducing I / O power supply glitches and enhancing the power supply's anti-interference performance. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 Circuit diagrams designed for traditional I / O; Figure 2 Timing waveform diagram for traditional I / O design; Figure 3 The structural block diagram of the high-drive IO power supply glitch processing circuit provided by the present invention; Figure 4 A circuit diagram of the high-drive IO power supply glitch processing circuit provided by the present invention; Figure 5 The IO timing waveform diagram provided for the IO design of this invention; Figure 6 This is a schematic diagram of the IO layout provided by the present invention; Figure 7 A circuit diagram of the ESD protection module provided by this invention; Figure 8 Simulation renderings of a traditional I / O design; Figure 9 Simulation results of the IO design provided for this invention.

[0017] The symbols for the main components are explained below: 100 - Chip baseboard; 110 - IO module; 120 - ESD protection module; 130 - First delay drive circuit; 140 - Second delay drive circuit; 150 - Digital signal input terminal; 160 - Level conversion unit; 170 - DRP signal processing unit; 180 - DRN signal processing unit; 190 - Rectification unit; 200 - Effective delay unit; 210 - Surge protection unit; 220 - Digital signal output unit. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] See Figure 1 and Figure 2A traditional I / O module includes a digital signal input terminal DOUT0, a level shifting unit LS0, inverters INV1, INV2, and INV3, a PAD0 unit, diodes D1 and D2, MOSFETs P0 and N0, a resistor SR, and a digital signal output unit Dig0. The digital signal input terminal is connected to one end of the level shifting unit LS0, and the other end of the level shifting unit is connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is connected to the input terminal of inverter INV3. Inverters INV1 and INV3... The NV2 circuit is used to generate the DRP0 signal, and the output of the inverter INV3 is used to generate the DRN0 signal. The PAD0 unit is connected to the anode of diode D1, the cathode of diode D2, the drain of MOSFET P0, the drain of MOSFET N0, and one end of resistor SR. The cathode of diode D1 is connected to the power input terminal (VCC) and the source of MOSFET P0. The anode of diode D2 is connected to the source of MOSFET N0 and ground. The gate of MOSFET P0 is used to receive the DRP0 signal, and the gate of MOSFET N0 is used to receive the DRN0 signal. The other end of resistor SR is connected to the digital signal output unit Dig0. To achieve high output drive capability, traditional I / O requires adding NMOS and PMOS driver transistors. Ideally, the DRP signal should be turned off before the DRN signal is turned on. However, in reality, the DRN (NMOS driver signal) is already on at the same time as the DRP (PMOS driver signal) is turned off (e.g., ...). Figure 2 (at time t1 in the context). Similarly, the case where DRP is open also exists (e.g., ... Figure 2 (at time t2 in the diagram). This will directly connect the power supply and ground in a very short time, resulting in a large current, which will affect the fluctuations in the I / O power supply and ground. These fluctuations will affect the internal modules of the chip.

[0020] In response to this, the following analysis is made regarding the causes of power supply jitter: The root cause of power supply jitter is through current, which is formed by the simultaneous conduction of the PMOS and NMOS driving transistors. To solve the power supply glitches problem, the through current problem must be addressed.

[0021] To address the problem of through current, see [reference needed]. Figure 3 , Figure 4 and Figure 6 The present invention provides a high-drive IO power supply glitch processing circuit, including a chip base 100, a plurality of IO modules 110 disposed on the chip base 100, and an ESD protection module 120 located between two of the IO modules 110; The IO module 110 includes a first delay driving circuit 130 and a second delay driving circuit 140. The first delay driving circuit 130 includes a digital signal input terminal 150, a level conversion unit 160, a DRP signal processing unit 170, and a DRN signal processing unit 180. The digital signal input terminal 150, the DRP signal processing unit 170, and the DRN signal processing unit 180 are all connected to the level conversion unit 160. The second delay driving circuit 140 includes a rectifier unit 190, an effective delay unit 200, a surge protection unit 210, and a digital signal output unit 220. The effective delay unit 200 and the surge protection unit 210 are both connected to the rectifier unit 190, and the effective delay unit 200 and the digital signal output unit 220 are both connected to the surge protection unit 210. The effective delay unit 200 includes multiple sets of effective delay circuits connected to the DRP signal processing unit 170 and the DRN signal processing unit 180. The level conversion unit 160 receives the digital square wave signal input from the digital signal input terminal 150, and processes it through the DRP signal processing unit 170 and the DRN signal processing unit 180 to obtain the DRP signal and the DRN signal, respectively. The DRP signal and the DRN signal sequentially drive multiple MOS transistors in each group of effective delay circuits to turn on and off to obtain the square wave signal. The digital signal output unit 220 outputs the square wave signal processed by the surge protection unit 210 to the first delay drive circuit 130.

[0022] In this embodiment, the DRP signal processing unit 170 includes a NAND gate ANAND1, a first delay unit, and an inverter INV7; the DRN signal processing unit 180 includes an inverter INV4, a NAND gate ANAND2, a second delay unit, an inverter INV5, and an inverter INV6. The first input terminal of the NAND gate ANAND1 is connected to the level conversion unit 160; the second input terminal of the NAND gate ANAND1 is connected to the output terminal of the second delay unit; the output terminal of the NAND gate ANAND1 is connected to the input terminals of the inverter INV7 and the first delay unit; and the output terminal of the inverter INV4 is connected to the input terminals of the inverter INV7 and the first delay unit. The input terminal is connected to the level conversion unit 160. The output terminal of inverter INV4 is connected to the second input terminal of NAND gate ANAND2. The first input terminal of NAND gate ANAND2 is connected to the output terminal of the first delay unit. The output terminal of NAND gate ANAND2 is connected to the input terminal of the second delay unit and the input terminal of inverter INV5. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6. The output terminal of inverter INV7 is used to output a DRP signal to the second delay drive circuit, and the output terminal of inverter INV6 is used to output a DRN signal to the second delay drive circuit 140. The level conversion unit 160 is used to convert digital voltage into analog voltage. Both the first delay unit and the second delay unit include several inverters.

[0023] It should be noted that the first input terminal of the NAND gate ANAND1 receives the digital square wave signal and outputs a first output signal after passing through the first delay unit. The inverter INV4 receives the digital square wave signal and outputs a second output signal to the second input terminal of the NAND gate ANAND2. The first output signal and the second output signal are ANDed to obtain a third output signal. The third output signal is sequentially passed through inverters INV5 and INV6 to obtain a DRN signal. The third output signal is output to the second output terminal of the NAND gate ANAND1 after passing through the second delay unit and ANDed with the digital square wave signal to obtain a fourth output signal. The fourth output signal is passed through inverter IVV7 to obtain a DRP signal. The rectifier unit 190 includes diodes D3 and D4. The cathode of diode D4 is connected to the power input terminal (VCC), the anode of diode D4 and the cathode of diode D3 are connected to the surge protection unit 210, and the anode of diode D3 is connected to the ground terminal (VSS).

[0024] The above describes the workflow of the high-drive IO power supply glitch processing circuit provided by this invention: A digital square wave signal is transmitted from Dout, undergoes LS level conversion (digital voltage converted to analog voltage), then passes through the upper NAND gate ANAND1 and the lower inverter INV4, and then through the NAND gate ANAND2. Simultaneously, the output signals of these two NAND gates pass through a delay unit (which can be composed of several inverters INV4), then through delay units (first delay unit delay1, second delay unit delay2), and are ANDed with the input signals of the NAND gates. The outputs then pass through inverters INV5, INV6, and INV7 respectively, yielding the DRN signal and DRP signal (e.g., ...). Figure 4 As shown); the DRN signal and DRP signal drive MOS transistors N1 and P1 respectively; the DRN signal then passes through resistors R2 (resistance value R) and R4 (resistance value 2R) to obtain the DRN1 signal and DRN2 signal; the DRN1 signal and DRN2 signal drive NMOS transistors N2 and N3 respectively. Similarly, the DRP signal passes through resistors R1 (resistance value R) and R3 (resistance value 2R) to obtain the DRP1 signal and DRP2 signal, which drive PMOS transistors P2 and P3 respectively. The resulting square wave (signal) is transmitted to the PAD (cell), and can then be transmitted back to the digital signal output unit (Dig) through the PAD cell and resistor SR1.

[0025] Specifically, the second delay drive circuit 140 further includes a PAD unit. The effective delay unit includes a first effective delay circuit, a second effective delay circuit, and a third effective delay circuit. Diode D3, diode D4, the first effective delay circuit, the second effective delay circuit, the third effective delay circuit, and the surge protection unit 210 are all connected to the PAD unit. The first effective delay circuit includes MOSFET P1 and MOSFET P2. The second effective delay circuit includes resistor R1, MOSFET P2, resistor R2, and MOSFET N2. The third effective delay circuit includes resistor R3, MOSFET P3, resistor R4, and MOSFET N3. The cathode of diode D4 is connected to the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3. The anode of diode D4 is connected to the PAD unit, the drain of MOSFET P1, the drain of MOSFET N1, the drain of MOSFET P2, the drain of MOSFET N2, the drain of MOSFET P3, and the drain of MOSFET P3. The gate of MOSFET P1 is connected to one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is connected to the gate of MOSFET P2. The other end of resistor R3 is connected to the gate of MOSFET P3. The gate of MOSFET N1 is connected to one end of resistor R2 and one end of resistor R4. The other end of resistor R2 is connected to the gate of MOSFET N2. The other end of resistor R4 is connected to the gate of MOSFET N3. The anode of diode D3 is connected to the source of MOSFET N1, the source of MOSFET N2, and the source of MOSFET N3 and then connected to the ground terminal. The resistance of resistor R3 is twice the resistance of resistor R1, and the resistance of resistor R4 is twice the resistance of resistor R2.

[0026] It should be understood that by setting multiple IO modules 110 and ESD protection modules 120 on the chip substrate, the IO module 110 includes a first delay drive circuit 130 and a second delay drive circuit 140. The level conversion unit 160 receives the digital square wave signal input from the digital signal input terminal 150, and processes it through the DRP signal processing unit 170 and the DRN signal processing unit 180 to obtain the DRP signal and the DRN signal, respectively. The DRP signal and the DRN signal sequentially drive multiple MOS transistors in each group of effective delay circuits to turn on and off to obtain the square wave signal. The digital signal output unit 220 outputs the square wave signal processed by the surge protection unit 210 to the first delay drive circuit 130. The multiple groups of effective delay circuits formed by the gate-source capacitance and resistance of the drive transistors ensure that there is an effective delay between each group of effective delay circuits. By grouping and driving the IO drive transistors in a time-division manner, the through current can be ensured to be small enough. VSS is interspersed next to the IO in the chip layout. The clamp promptly discharges large currents, ensuring a clean internal power supply. The impact of through current on the power supply is addressed from within the IO module 110, and the influence of IO on the power supply is mitigated through chip layout processing, thereby enhancing the power supply's anti-interference performance.

[0027] Optionally, the surge protection unit 210 includes a resistor SR1, the DRP signal and the DRN signal drive MOSFET P1 and MOSFET P1 respectively, the DRN signal passes through resistors R2 and R4 to obtain DRN1 signal and DRN2 signal, and the DRN1 signal and DRN2 signal drive MOSFET N2 and MOSFET N3 respectively; The DRP signal passes through resistors R1 and R3 to obtain DRP1 and DRP2 signals. The DRP1 and DRP2 signals drive MOSFETs P2 and P3 respectively, and the resulting square wave signals are transmitted to the PAD unit and then transmitted back to the digital signal output unit 220 through resistor SR1.

[0028] In this embodiment, the rising edges of the DRN and DRP signals in each group of effective delay circuits are staggered. MOSFETs P1, P2, and P3 are all PMOS transistors, while MOSFETs N1, N2, and N3 are all NMOS transistors. The bit width range of MOSFETs P1, P2, and P3 is 15~40µm, and the bit width range of MOSFETs N1, N2, and N3 is 20~40µm. The staggered rising edges of the DRN and DRP signals mean that the rising edges of DRP1 and DRP2 are not driven at the same time. The falling edges can be understood similarly, to ensure that DRP1 and DRP2 are not turned on or off simultaneously, creating a scenario where the transistors turn off sequentially.

[0029] Specifically, in the second delay drive circuit 140, DRN and DRP form the first group, DRP1 and DRN1 form the second group, and DRP2 and DRN2 form the third group. The circuits containing the first, second, and third groups correspond to the first effective delay circuit, the second effective delay circuit, and the third effective delay circuit, respectively. DRN and DRP within the first group can be connected via an RS flip-flop and some delay units (such as...). Figure 4 As shown, the edges of DRN (signal) and DRP (signal) are staggered to ensure that DRP is turned off before DRN is turned on, and vice versa. This significantly reduces through current, thereby reducing power supply jitter. Simultaneously, resistor ranges of 0R, 1R, and 2R are inserted between groups, effectively utilizing the Cgs capacitor (gate-source capacitor) of the driving transistor and the resistors to form an effective delay circuit, thus ensuring effective delay between groups. The corresponding timing effect is shown in the figure. Figure 5 As shown. The values ​​of the RS delay unit and resistors can be adjusted to ensure that the NMOS transistor is turned on only after the last PMOS transistor is completely turned off (e.g., ...). Figure 5 (as shown in t3); after ensuring the NMOS transistor is completely turned off, the PMOS transistor is then turned on again (as shown in t3). Figure 5 (as shown in t4). Wherein, Figure 4 In the diagram, INV1~INV7 are all inverters of the same type (such as standard cells), ANAND1 and ANAND2 are ordinary standard cells, D1~D4 are also ordinary diodes of the same type, P1~P3 are required to have a width range of 15~40um, and N1~N3 are required to have a width range of 20~40um.

[0030] Optionally, such as Figure 7 As shown, the ESD protection module 120 includes a resistor R, a capacitor C, an inverter INV, and an NMOS transistor. The other end of resistor R is connected to the first input terminal of inverter INV and one end of capacitor C. The other end of resistor R is connected to the second input terminal of inverter INV and the drain of the NMOS transistor, which is then connected to the power input terminal. The other end of capacitor C is connected to the third input terminal of inverter INV and the source of the NMOS transistor, which is then connected to ground. The output terminal of inverter INV is connected to the gate of the NMOS transistor. For example, in high-precision ADCs and important power supply modules within a chip, the improved I / O design described above can significantly reduce I / O interference to the power supply, thereby achieving good power supply performance for both the internal power supply and the internal ADC. In this embodiment, see again Figure 6 In semiconductor packaging technology, the chip baseband 100 is a key component. The leadframe is a crucial component in semiconductor packaging, forming an electrical circuit by using bonding materials (such as gold, aluminum, or copper wires) to connect the internal circuit leads and leads. It acts as a bridge connecting to external wires. The ground clamp acts as a voltage clamp. To further address power supply interference and ensure a good power environment for the internal modules, the I / O layout was improved and optimized. A ground clamp (VSS pad) is interspersed next to the I / O module 110. The ground clamp is wired to the chip baseband, allowing strong driving interference from the I / O to be directly discharged to the baseband through the adjacent clamp and then to the outside of the chip. The ESD protection module 120 includes multiple ground clamps; see reference for details. Figure 6 and Figure 7 .

[0031] Specifically, the RC clamp can serve as an isolation mechanism, acting as a discharge path. When the input of the inverter INV is high (equal to VCC), the gate of the ESD NMOS transistor after passing through the inverter INV is low (VSS), so the ESD NMOS transistor remains off. When a spike voltage (instantaneous high voltage) appears in VCC, because the capacitor cannot change abruptly, the input of the inverter INV remains high (the original VCC voltage). However, the current VCC is much higher than the original VCC, so the output of the inverter INV is high, driving the ESD NMOS transistor to turn on. The ESD NMOS transistor pulls the spike voltage on VCC down, back to the original VCC. Once the capacitor C reacts, the ESD NMOS transistor turns off.

[0032] It should be noted that with traditional I / O designs, the power supply VCC fluctuation at I / O output is around 220mV, and the ground VSS fluctuation is also around 220mV, resulting in a relative voltage difference on the order of 440mV. Such power supply jitter can severely impact the performance of internal components (such as high-precision DACs). The through-current is on the order of 9.5mA. The improved I / O module of this invention significantly reduces the through-current of the I / O, while also significantly reducing power supply fluctuations, thus providing a stable voltage source for the internal chip.

[0033] like Figure 8 As shown, Figure 8 This is a simulation result using a traditional I / O design; it shows a one-cycle waveform of the I / O switching. Figure 7 There are four waveforms in total: VCC (x-axis represents time, y-axis represents voltage), VSS (x-axis represents time, y-axis represents voltage), IO flip (x-axis represents time, y-axis represents voltage), and through current (x-axis represents time, y-axis represents current). When the IO flip rotates upward at 6µs, the voltage on VCC drops from 5V to 4.76V, VSS rises from 0V to 0.223V, and the through current rises from 0mA to the 19.7mA level. The voltage difference between VCC and VSS decreases by a total of 0.473V. Similarly, when the IO flip rotates downward at 7µs, the voltage on VCC drops from 5V to 4.85V, VSS rises from 0V to 0.147V, and the through current rises from 0mA to the 6.2mA level. The voltage difference between VCC and VSS decreases by a total of 0.297V.

[0034] In addition, such as Figure 9 As shown, Figure 9 This is a periodic waveform of the improved IO designer IO toggle in this invention. Figure 9 There are four waveforms in total: VCC (X-axis represents time, Y-axis represents voltage), VSS (X-axis represents time, Y-axis represents voltage), IO flip (X-axis represents time, Y-axis represents voltage), and through current (X-axis represents time, Y-axis represents current). When the IO flip flips upward at 6µs, the voltage on VCC drops from 5V to 4.86V, VSS rises from 0V to 0.143V, and the through current rises from 0mA to the 7mA level. The voltage difference between VCC and VSS decreases by a total of 0.283V. Similarly, when the IO flip flips downward at 7µs, the voltage on VCC drops from 5V to 4.92V, VSS rises from 0V to 0.076V, and the through current rises from 0mA to the 4.5mA level. The voltage difference between VCC and VSS decreases by a total of 0.156V.

[0035] It should be understood that the improved I / O design of this invention is optimized compared to the traditional I / O design in the following aspects: The voltage difference between VCC and VSS is optimized at the rising edge of the flip, and the corresponding expression is: [(0.473-0.283) / 0.473]*100%=40.2%; The optimized expression for overshoot current is: [(19.7-7) / 19.7]*100%=64.4%; The expression for falling edge optimization is: [(0.297-0.156) / 0.297]*100%=47.7%; The optimized expression for overshoot current is: [(6.2-4.5) / 6.2]*100%=27.5%.

[0036] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0037] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0038] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A high-drive I / O power supply glitch processing circuit, characterized in that, It includes a chip base conductor, multiple IO modules disposed on the chip base conductor, and an ESD protection module located between two of the IO modules; The IO module includes a first delay driving circuit and a second delay driving circuit. The first delay driving circuit includes a digital signal input terminal, a level conversion unit, a DRP signal processing unit, and a DRN signal processing unit. The digital signal input terminal, the DRP signal processing unit, and the DRN signal processing unit are all connected to the level conversion unit. The second delay drive circuit includes a rectifier unit, an effective delay unit, a surge protection unit, and a digital signal output unit. The effective delay unit and the surge protection unit are both connected to the rectifier unit. The effective delay unit and the digital signal output unit are both connected to the surge protection unit. The effective delay unit includes multiple sets of effective delay circuits connected to the DRP signal processing unit and the DRN signal processing unit. The level conversion unit receives the digital square wave signal input from the digital signal input terminal, and processes it through the DRP signal processing unit and the DRN signal processing unit to obtain the DRP signal and the DRN signal, respectively. The DRP signal and the DRN signal sequentially drive multiple MOS transistors in each group of effective delay circuits to turn on and off to obtain the square wave signal. The digital signal output unit outputs the square wave signal processed by the surge protection unit to the first delay drive circuit.

2. The high-drive IO power supply glitch processing circuit according to claim 1, characterized in that, The DRP signal processing unit includes a NAND gate ANAND1, a first delay unit, and an inverter INV7; the DRN signal processing unit includes an inverter INV4, a NAND gate ANAND2, a second delay unit, an inverter INV5, and an inverter INV6. The first input of NAND gate ANAND1 is connected to the level conversion unit, the second input of NAND gate ANAND1 is connected to the output of the second delay unit, the output of NAND gate ANAND1 is connected to the input of inverter INV7 and the first delay unit, the input of inverter INV4 is connected to the level conversion unit, the output of inverter INV4 is connected to the second input of NAND gate ANAND2, the first input of NAND gate ANAND2 is connected to the output of the first delay unit, the output of NAND gate ANAND2 is connected to the input of the second delay unit and the input of inverter INV5, and the output of inverter INV5 is connected to the input of inverter INV6. The output of inverter INV7 is used to output a DRP signal to the second delay drive circuit, and the output of inverter INV6 is used to output a DRN signal to the second delay drive circuit.

3. The high-drive IO power supply glitch processing circuit according to claim 2, characterized in that, The level conversion unit is used to convert digital voltage into analog voltage, and both the first delay unit and the second delay unit include several inverters.

4. The high-drive IO power supply glitch processing circuit according to claim 3, characterized in that, The first input terminal of the NAND gate ANAND1 receives the digital square wave signal and outputs a first output signal after passing through the first delay unit. The inverter INV4 receives the digital square wave signal and outputs a second output signal to the second input terminal of the NAND gate ANAND2. The first output signal and the second output signal are ANDed to obtain a third output signal. The third output signal is sequentially passed through inverters INV5 and INV6 to obtain the DRN signal. The third output signal is output to the second output terminal of the NAND gate ANAND1 through the second delay unit and ANDed with the digital square wave signal to obtain the fourth output signal. The fourth output signal is then passed through the inverter IVV7 to obtain the DRP signal.

5. The high-drive IO power supply glitch processing circuit according to claim 1, characterized in that, The rectifier unit includes diode D3 and diode D4. The cathode of diode D4 is connected to the power input terminal, the anode of diode D4 and the cathode of diode D3 are connected to the surge protection unit, and the anode of diode D3 is connected to the ground terminal.

6. The high-drive IO power supply glitch processing circuit according to claim 5, characterized in that, The second delay drive circuit also includes a PAD unit. The effective delay unit includes a first effective delay circuit, a second effective delay circuit, and a third effective delay circuit. Diodes D3 and D4, the first effective delay circuit, the second effective delay circuit, the third effective delay circuit, and the surge protection unit are all connected to the PAD unit. The first effective delay circuit includes MOSFETs P1 and P2. The second effective delay circuit includes resistors R1, P2, R2, and N2. The third effective delay circuit includes resistors R3, P3, R4, and N3. The cathode of diode D4 is connected to the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3. The anode of diode D4 is connected to the PAD unit, the drain of MOSFET P1, the drain of MOSFET N1, the drain of MOSFET P2, the drain of MOSFET N2, the drain of MOSFET P3, and the drain of MOSFET P3. The gate of MOSFET P1 is connected to one end of resistor R1 and one end of resistor R3. The other end of resistor R1 is connected to the gate of MOSFET P2. The other end of resistor R3 is connected to the gate of MOSFET P3. The gate of MOSFET N1 is connected to one end of resistor R2 and one end of resistor R4. The other end of resistor R2 is connected to the gate of MOSFET N2. The other end of resistor R4 is connected to the gate of MOSFET N3. The anode of diode D3 is connected to the source of MOSFET N1, the source of MOSFET N2, and the source of MOSFET N3 and then connected to the ground terminal.

7. The high-drive IO power supply glitch processing circuit according to claim 6, characterized in that, The resistance of resistor R3 is twice the resistance of resistor R1, and the resistance of resistor R4 is twice the resistance of resistor R2.

8. The high-drive IO power supply glitch processing circuit according to claim 6, characterized in that, The surge protection unit includes a resistor SR1. The DRP signal and the DRN signal drive MOSFET P1 and MOSFET P1 respectively. The DRN signal passes through resistors R2 and R4 to obtain DRN1 signal and DRN2 signal. The DRN1 signal and DRN2 signal drive MOSFET N2 and MOSFET N3 respectively. The DRP signal passes through resistors R1 and R3 to obtain DRP1 and DRP2 signals. The DRP1 and DRP2 signals drive MOSFETs P2 and P3 respectively, and the resulting square wave signals are transmitted to the PAD unit and then fed back to the digital signal output unit through resistor SR1.

9. The high-drive IO power supply glitch processing circuit according to claim 8, characterized in that, In each group of effective delay circuits, the DRN signal and DRP signal are staggered. MOS transistors P1, P2, and P3 are all PMOS transistors, and MOS transistors N1, N2, and N3 are all NMOS transistors. The bit width range of MOSFETs P1, P2 and P3 is 15~40um, and the bit width range of MOSFETs N1, N2 and N3 is 20~40um.

10. The high-drive IO power supply glitch processing circuit according to claim 1, characterized in that, The ESD protection module includes a resistor R, a capacitor C, an inverter INV, and an NMOS transistor. The other end of the resistor R is connected to the first input terminal of the inverter INV and one end of the capacitor C. The other end of the resistor R is connected to the second input terminal of the inverter INV and the drain of the NMOS transistor, which is connected to the power input terminal. The other end of the capacitor C is connected to the third input terminal of the inverter INV and the source of the NMOS transistor, which is connected to the ground terminal. The output terminal of the inverter INV is connected to the gate of the NMOS transistor.

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