A method, device and medium for suppressing electromagnetic interference at a source end of an inverter

Abstract

This application discloses a method, device, and medium for suppressing electromagnetic interference (EMI) at the source end of an inverter. The method includes: constructing a three-phase inverter topology with each phase arm consisting of N series-connected insulated-gate bipolar transistors (IGBTs), and connecting an RCD buffer circuit in parallel to each IGBT; generating a main pulse width modulation (PWM) signal through sinusoidal pulse width modulation; delaying the PWM signal using a shift register chain composed of cascaded D flip-flops in the CPLD control module to generate N gate drive signals with sequentially increasing preset delays; sequentially driving the IGBTs on the same bridge arm to turn on and off using the N drive signals, shaping the output voltage pulse edges into a stepped waveform with N voltage steps to periodically suppress high-frequency EMI; and feeding energy back to the DC bus through a flyback converter recovery buffer circuit. This invention has a simple structure and low cost, reducing total switching losses while suppressing source-end EMI.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a method, device and medium for suppressing electromagnetic interference at the source end of an inverter. Background Technology

[0002] Medium- and high-voltage three-phase inverters are core components of industrial transmission equipment such as explosion-proof motors in mines, large fans, water pumps, and compressors. Insulated-gate bipolar transistors (IGBTs), with their fast switching speed, high power density, and excellent withstand voltage, have become the mainstream power switching devices in medium- and high-voltage inverters. However, the rapid switching of IGBTs generates steep voltage pulses, and the extremely high dv / dt, coupled through circuit and device parasitic parameters, creates strong conducted and radiated electromagnetic interference. This can easily lead to faults such as electrical erosion of motor bearings, overvoltage damage to power devices, distortion of analog sensor signals, and malfunctions in control systems, seriously threatening equipment operation safety and system stability.

[0003] Current electromagnetic interference suppression technologies are mainly divided into two categories: path suppression and source suppression. Traditional passive / active filters can attenuate interference, but they significantly increase system size, weight, and hardware costs, resulting in poor adaptability and cost-effectiveness.

[0004] Source-side solutions such as variable frequency PWM and active gate drive have drawbacks such as complex control logic, difficulty in controlling current ripple and switching losses, and cumbersome circuit implementation. Multi-level and device series topologies are mostly aimed at increasing voltage levels and are not optimized for electromagnetic interference sources, resulting in high overall complexity and cost.

[0005] In other words, existing technologies struggle to achieve a balance between low complexity, low cost, low loss, and efficient electromagnetic interference suppression, thus failing to meet the engineering application requirements of medium- and high-voltage industrial inverter systems. Summary of the Invention

[0006] To address the technical problems existing in the background art, embodiments of this application provide a method, device, and medium for suppressing electromagnetic interference at the source end of an inverter. The method includes: constructing a three-phase series-connected insulated-gate bipolar transistor (IGBT) inverter topology; each phase's upper and lower bridge arm switching branch of the three-phase series-connected IGBT inverter is composed of N IGBTs connected in series, and an RCD buffer circuit is connected in parallel to each IGBT; N is an integer greater than or equal to 2; the RCD buffer circuit consists of a voltage-equalizing resistor, a buffer capacitor, and a decoupling diode; based on the frequency and amplitude of the target output voltage of the three-phase series-connected IGBT inverter, a main pulse width modulation signal for controlling the switching state of each phase bridge arm is generated using a sinusoidal pulse width modulation strategy; and the main pulse width modulation signal is received by a CPLD control module. The signal, according to the shift register chain composed of cascaded D flip-flops, performs timing delay processing on the main pulse width modulation signal to generate N gate drive signals; the N gate drive signals respectively control N series insulated gate bipolar transistors on the same bridge arm, and the x-th drive signal has a preset time delay relative to the (x-1)-th drive signal; where x is an integer from 2 to N; through the N gate drive signals, the N series insulated gate bipolar transistors on the same bridge arm are sequentially driven to turn on or off, so as to shape the rising edge and / or falling edge of the output voltage pulse of the same bridge arm into a stepped waveform composed of N voltage steps; during the sequential switching process of the insulated gate bipolar transistors, the energy stored in the RCD buffer circuit is recovered and fed back to the DC bus through the flyback converter associated with each bridge arm.

[0007] In one example, the preset time delay is greater than the time required for the insulated gate bipolar transistor to complete the collector-emitter voltage transition during the turn-off process, and the total delay time of all series-connected insulated gate bipolar transistors does not exceed 3% of the pulse width modulation carrier period.

[0008] In one example, the sequential turn-on or turn-off steps of an insulated-gate bipolar transistor are as follows: Depending on the direction of the load current, when the load current is greater than zero, the upper bridge arm insulated gate bipolar transistors are controlled to turn on or off sequentially; when the load current is less than zero, the lower bridge arm insulated gate bipolar transistors are controlled to turn on or off sequentially.

[0009] In one example, the N gate drive signals sequentially drive the N series-connected insulated-gate bipolar transistors (IGBTs) on the same bridge arm to turn on or off, shaping the rising and / or falling edges of the output voltage pulses of the same bridge arm into a stepped waveform composed of N voltage steps. Specifically, during the turn-off process, turn-off drive signals are applied sequentially to the N series-connected IGBTs on the same bridge arm, from the furthest point from the phase output terminal to the closest point. Each time an IGBT is turned off, the load current is transferred to the corresponding buffer capacitor of the IGBT for charging, causing the phase voltage to drop by one step. The step amplitude is equal to the DC bus voltage. During the conduction process, conduction drive signals are sequentially applied to N series-connected insulated-gate bipolar transistors (IGBTs) on the same bridge arm, from the furthest point from the phase output terminal to the closest point. Each time an IGBT is turned on, the corresponding buffer capacitor is bypassed by a decoupling diode, causing the phase voltage to rise by a step; the step amplitude is equal to the DC bus voltage. .

[0010] In one example, the CPLD control module receives the main pulse width modulation signal and performs timing delay processing on the main pulse width modulation signal according to the shift register chain composed of cascaded D flip-flops to generate N gate drive signals. Specifically, this includes: using the main pulse width modulation signal as the first gate drive signal and directly outputting it to the first insulated-gate bipolar transistor on the same bridge arm; simultaneously inputting the main pulse width modulation signal to the input of the shift register chain composed of cascaded D flip-flops; at the arrival of each clock cycle, each stage of the shift register chain passes the currently stored state of the main pulse width modulation signal to the next stage of the D flip-flop; extracting the signal after a preset delay from the output of the first stage of the shift register chain and outputting it as the second gate drive signal to the second insulated-gate bipolar transistor on the same bridge arm; and so on, starting from the... The output of the stage D flip-flop extracts the delayed signal and outputs it as the xth drive signal to the xth insulated gate bipolar transistor on the same bridge arm, until all N gate drive signals with sequentially increasing delays are generated.

[0011] In one example, during the sequential turn-on or turn-off of the insulated gate bipolar transistor (IGBT), the energy stored in the RCD snubber circuit is recovered and fed back to the DC bus via a flyback converter associated with each bridge arm. Specifically, during the sequential turn-on of the bridge arms, the charge stored in each snubber capacitor in the RCD snubber circuit is guided to the energy storage capacitor on the primary side of the flyback converter through diodes connected to each snubber capacitor. When the voltage across the energy storage capacitor reaches a preset clamping voltage value, the switch on the primary side of the flyback converter is triggered to turn on. The energy stored in the energy storage capacitor is injected into the primary winding of the flyback transformer in the form of current. During the sequential turn-off of the bridge arms, the switching transistors on the primary side are turned off to cut off the primary winding current, causing the voltage polarity of each winding of the flyback transformer to reverse, and the corresponding terminal of the secondary winding changes from low potential to high potential. Through the reversal of the voltage polarity of the secondary winding, the diodes in the secondary circuit are forward biased and turned on, converting the magnetic field energy stored in the flyback transformer into electrical energy, which is then delivered to the output filter capacitor connected to the DC bus to complete the energy feedback.

[0012] In one example, based on the frequency and amplitude of the target output voltage of a three-phase series insulated-gate bipolar transistor inverter, a sinusoidal pulse width modulation (PWM) strategy is used to generate a main PWM signal for controlling the switching state of each phase arm. Specifically, this includes: receiving a command signal from the controller; the command signal includes amplitude and frequency information of the fundamental voltage expected to be output by the inverter; generating a sinusoidal modulated wave signal of the corresponding frequency based on the frequency information, and determining the amplitude of the sinusoidal modulated wave signal based on the amplitude information; generating a triangular carrier signal with a frequency higher than the sinusoidal modulated wave signal; the frequency of the triangular carrier signal is a preset carrier frequency; comparing the instantaneous value of the sinusoidal modulated wave signal with the instantaneous value of the triangular carrier signal in real time; outputting a high-level pulse when the instantaneous value of the sinusoidal modulated wave is greater than the instantaneous value of the triangular carrier signal; outputting a low-level pulse when the instantaneous value of the sinusoidal modulated wave is less than or equal to the instantaneous value of the triangular carrier signal; and outputting the comparison result as the main PWM signal to the CPLD control module of each corresponding arm.

[0013] In one example, the method further includes reducing the voltage and high-frequency harmonic amplitude according to the stepped waveform to achieve periodic suppression of electromagnetic interference at the inverter source end, while reducing total switching losses.

[0014] On the other hand, embodiments of this application provide an inverter source-side electromagnetic interference suppression device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the above-mentioned inverter source-side electromagnetic interference suppression methods.

[0015] On the other hand, embodiments of this application provide a non-volatile computer storage medium for suppressing electromagnetic interference at the source end of an inverter, which stores computer-executable instructions that can execute any of the above-mentioned methods for suppressing electromagnetic interference at the source end of an inverter.

[0016] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: By shaping the rising and / or falling edges of the output voltage pulse of the same bridge arm into a stepped waveform consisting of N voltage steps, the spectral distribution characteristics of the output voltage are altered. This causes the high-frequency harmonic energy to exhibit a periodic peak-and-trough distribution, suppressing harmonic components to near zero at the trough frequencies, thus achieving effective suppression of electromagnetic interference at its source. Experimental results show that effective harmonic attenuation can be achieved within a 0 to 2 MHz spectral bandwidth, reducing the root mean square value of the near-field radiated noise period by more than 50%. Furthermore, by adjusting the number N of series-connected insulated-gate bipolar transistors and the preset time delay, the duration of each voltage step in the stepped waveform can be flexibly controlled, thereby specifically suppressing harmonic components within a specific frequency band to the trough frequency. This achieves customized suppression of electromagnetic interference in different frequency bands, improving the adaptability and designability of the solution.

[0017] Furthermore, due to the stepped voltage change, the current spikes of the series-connected insulated-gate bipolar transistors on the same bridge arm are significantly reduced during sequential conduction, resulting in a lower total switching loss for the bridge arm compared to traditional synchronous switching methods. Finally, timing delay processing only requires cascaded D flip-flops in the CPLD control module, without complex modifications to the existing gate drive circuit or the adoption of specific pulse width modulation strategies. The structure is simple, low-cost, and highly compatible, and can be used in conjunction with other electromagnetic interference suppression technologies, making it suitable for motor drive systems of different power levels. Attached Figure Description

[0018] To more clearly illustrate the technical solution of this application, some embodiments of this application will be described in detail below with reference to the accompanying drawings, in which: Figure 1 A flowchart illustrating an inverter source-side electromagnetic interference suppression method provided in this application embodiment; Figure 2 The bridge arm conduction and turn-off diagram for a method to suppress electromagnetic interference at the source end of an inverter provided in this application embodiment when the load current changes; Figure 3 A flyback converter structure diagram of an inverter source-side electromagnetic interference suppression method provided in this application embodiment; Figure 4 This is a schematic diagram of the structure of an inverter source-side electromagnetic interference suppression device provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Some embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a flowchart illustrating an inverter source-side electromagnetic interference suppression method provided in this application embodiment. This method can be applied to various business areas. Certain input parameters or intermediate results in this process can be manually adjusted to help improve accuracy.

[0022] The analysis method involved in the embodiments of this application can be implemented by a terminal device or a server, and this application does not impose any special restrictions on it.

[0023] Before introducing the implementation scheme, it should be noted that the core principle of this application lies in reshaping the originally steep trapezoidal edges of the inverter output voltage pulse into a stepped waveform composed of multiple voltage steps, thereby fundamentally changing the spectral distribution characteristics of the output voltage. Traditional inverter output voltage pulses have extremely high voltage change rates, which couple into strong displacement currents on parasitic capacitances, a major source of conducted and radiated electromagnetic interference. This application utilizes the flexibility of the series IGBT topology by introducing sequentially increasing preset time delays to the gate drive signals of each IGBT on the same bridge arm, enabling each IGBT to turn on or off sequentially. Each action of a single IGBT causes only 1 / N of the phase voltage to change the DC bus voltage, thus decomposing a single high-amplitude, high-voltage-change-rate voltage jump into N low-amplitude, low-voltage-change-rate stepped jumps.

[0024] This stepped voltage waveform exhibits a periodic oscillating envelope in the frequency domain, with each suppression cycle containing N-1 peaks and N-1 troughs. At the trough frequencies, harmonic components are suppressed to near zero, achieving periodic and controllable effective suppression of electromagnetic interference sources. Simultaneously, due to the stepped voltage changes, current spikes are significantly reduced, resulting in a substantial decrease in the total switching loss of the bridge arms compared to synchronous switching methods. This, in turn, improves system efficiency while suppressing electromagnetic interference.

[0025] Based on this Figure 1 The process may include the following steps: S101: Construct a three-phase series insulated-gate bipolar transistor inverter topology; each phase of the three-phase series insulated-gate bipolar transistor inverter consists of N insulated-gate bipolar transistors connected in series, and each insulated-gate bipolar transistor is connected in parallel with an RCD buffer circuit; N is an integer greater than or equal to 2; the RCD buffer circuit consists of an equalizing resistor, a buffer capacitor and a decoupling diode.

[0026] In some embodiments of this application, a hardware foundation for implementing stepped voltage shaping and electromagnetic interference suppression is constructed. Taking a 1140V explosion-proof induction motor drive platform as an example, the number N of IGBTs connected in series in the upper and lower bridge arm switching branches of each phase is first determined, for example, N is taken as 3 or 4. Taking N=4 as an example, IGBT devices of model IKW40T120 are selected, and each upper bridge arm of the phase consists of 4 IGBTs (e.g., to The upper arm is composed of four IGBTs connected in series, with subscripts 1 to 4 indicating the position of the IGBTs relative to the phase output terminals. The device is closest to the phase output terminal. The device furthest from the phase output terminal, DC bus voltage Set to 1900V.

[0027] To achieve static and dynamic voltage equalization of series-connected IGBTs, each IGBT is connected in parallel with a set of voltage equalization resistors ( to ), buffer capacitor ( to ) and decoupling diodes ( to The circuit consists of an RCD buffer circuit. The resistance of the voltage equalization resistor is usually selected from tens to hundreds of kiloohms, which is much lower than the leakage resistance of the IGBT in the off state. Therefore, in the off state, the current flowing through the voltage equalization resistor is significantly greater than the leakage current of the IGBT. The voltage across each IGBT is determined by the ratio of the resistance of the voltage equalization resistor, and is not affected by the difference in leakage resistance of the individual IGBTs, thus achieving reliable static voltage equalization.

[0028] During IGBT turn-off, excess energy generated by transient voltage imbalances due to differences in the dynamic parameters of various devices will be introduced into the buffer capacitor through the decoupling diode. The buffer capacitor will absorb and suppress overvoltage spikes, thereby achieving dynamic voltage equalization and device protection.

[0029] In addition, each phase arm is equipped with a flyback converter interface that connects to the energy recovery step described later, as well as a CPLD control module (e.g., EPM240T100C5N) for generating multiple timing delay drive signals. This completes the construction of a hardware platform with stepped voltage shaping capabilities.

[0030] S102: Based on the frequency and amplitude of the target output voltage of the three-phase series insulated gate bipolar transistor inverter, a main pulse width modulation signal is generated to control the switching state of each phase bridge arm through a sinusoidal pulse width modulation strategy.

[0031] In some embodiments of this application, core control signals that drive the entire inverter are generated based on the constructed hardware topology.

[0032] First, it receives a command signal from the upper-level controller (e.g., a microprocessor). This command signal contains the amplitude and frequency information of the fundamental voltage that the inverter expects to output. For example, for a mining explosion-proof three-phase asynchronous motor with a rated voltage of 1140V and a rated speed of 1430r / min, its target output is a sinusoidal fundamental voltage with a frequency of 50Hz and a corresponding amplitude.

[0033] Based on the frequency information, a sinusoidal modulated wave signal with a corresponding frequency is generated, and the modulation depth of the sinusoidal modulated wave signal is determined based on the amplitude information. Simultaneously, a triangular carrier signal with a frequency much higher than the modulated wave frequency is generated; its frequency is the preset carrier frequency.

[0034] Subsequently, the instantaneous value of the sinusoidal modulated wave signal is compared with the instantaneous value of the triangular carrier signal in real time: when the instantaneous value of the sinusoidal modulated wave is greater than the instantaneous value of the triangular carrier signal, a high-level pulse is output; when the instantaneous value of the sinusoidal modulated wave is less than or equal to the instantaneous value of the triangular carrier signal, a low-level pulse is output. The resulting series of pulse sequences with widths varying sinusoidally constitutes the main pulse width modulation signal.

[0035] These main pulse width modulation (PWM) signals correspond to each arm of the three-phase bridge and are output to the input terminal of the CPLD control module of each corresponding arm for timing delay processing in subsequent steps. Without delay, these main PWM signals are equivalent to the drive signals of a traditional two-level inverter. If they directly drive the synchronous switches of each IGBT, they will generate trapezoidal output voltage pulses with steep edges and extremely high voltage change rates, which are the main source of electromagnetic interference in the system.

[0036] S103: Receive the main pulse width modulation signal through the CPLD control module, perform timing delay processing on the main pulse width modulation signal according to the shift register chain composed of cascaded D flip-flops, and generate N gate drive signals; the N gate drive signals respectively control N series insulated gate bipolar transistors on the same bridge arm, and the x-th gate drive signal has a preset time delay relative to the (x-1)-th gate drive signal; where x is an integer from 2 to N.

[0037] In some embodiments of this application, the digital logic resources inside the CPLD control module are used to convert the generated single main pulse width modulation signal into a multi-channel drive signal with precise timing relationship.

[0038] Specifically, after receiving the main pulse width modulation signal, the CPLD control module first uses the main pulse width modulation signal as the first gate drive signal. It outputs directly without delay and is used to control the first IGBT on the same bridge arm that is furthest from the output terminal of the phase.

[0039] Simultaneously, the main pulse width modulation signal is also fed into the input of a shift register chain composed of multiple cascaded D flip-flops. The clock inputs of all D flip-flops are connected to a unified clock signal, the period of which is denoted as . The clock frequency can be configured according to the required time resolution; for example, when a 0.5μs step delay is required, it can be selected. It is 0.5 μs or one integer fraction thereof.

[0040] At the effective edge of each clock cycle, each D flip-flop in the shift register chain passes the currently stored logic signal state to the next D flip-flop. The output of the first-stage D flip-flop extracts the signal after a preset delay time Δt from the main pulse width modulation signal; this signal serves as the second gate drive signal. The output is connected to the second IGBT on the same bridge arm that is furthest from the phase output terminal, where , where n is the number of clock cycles corresponding to this stage.

[0041] Similarly, extract the output of the (x-1)th stage D flip-flop after... The delayed signal is used as the x-th gate drive signal. The signal is output to the x-th IGBT furthest from the phase output terminal on the same bridge arm. This process continues until all N gate drive signals with sequentially increasing delays Δt are generated.

[0042] The preset time delay Δt must meet strict constraints: its lower limit must be greater than the time required for the IGBT to complete the voltage transition from collector to emitter during the turn-off process. For the IKW40T120 device, its turn-off delay time is about 480ns, the fall time is about 70ns, and the total voltage transition time is about 0.5μs. If Δt is less than this value, the switching process of the series IGBTs will overlap in the active region, resulting in severe dynamic voltage imbalance and drive signal crosstalk. This may cause individual IGBTs to withstand voltages far exceeding their rated withstand voltage, posing a high risk of overvoltage breakdown.

[0043] Its upper limit is limited by the minimum pulse width under SPWM control, and according to engineering practice, the total delay time of all IGBT devices is also limited. It should not exceed 3% of the carrier cycle to avoid increasing switching losses and affecting system efficiency due to excessively long overall switching process.

[0044] Under the premise of satisfying the above constraints, by precisely setting the Δt value, the duration τ of each voltage step in the stepped waveform can be flexibly adjusted, thereby controlling the periodic bandwidth and peak / trough frequency position of subsequent electromagnetic interference suppression.

[0045] S104: The N gate drive signals sequentially drive the N series insulated gate bipolar transistors on the same bridge arm to turn on or off, so as to shape the rising edge and / or falling edge of the output voltage pulse of the same bridge arm into a stepped waveform composed of N voltage steps.

[0046] In some embodiments of this application, N gate drive signals with sequentially increasing time delays are used to control the sequential operation of series-connected IGBTs to achieve stepped shaping of the output voltage waveform.

[0047] For a three-phase inverter using SPWM control, the motor load has mechanical inertia and inductive characteristics. During the brief switching transition of the series IGBT, the load current... It can be basically considered to remain constant. The following explanation takes the U-phase upper arm as an example, which consists of 4 IGBTs connected in series.

[0048] Define the switching state as State1, where the upper bridge arm is on and the lower bridge arm is off, and State0, conversely, State0. Under ideal voltage equalization conditions, the steady-state voltage across each buffer capacitor is... When the load current I_L is greater than zero (current flows from the inverter to the motor), and the upper bridge arm performs a sequential turn-off process from State1 to State0, a low-level gate drive signal is generated. The time is sequentially delayed by Δt to reach the gate of each IGBT.

[0049] first Turn-off, load current Forced from The channel is transferred to its parallel RCD snubber circuit, and the snubber capacitor begins to... As the battery charges, the potential of node U decreases. That is, the phase voltage drops by an amplitude of The voltage change is shared by the lower bridge arm, which is in the off state, and all devices experience a decrease. .

[0050] After Δt, Turn-off, load current Continue to As the battery charges, the phase voltage drops by another step; this process continues until... When turned off, the total phase voltage drops. When the upper bridge arm is completely turned off, the load current switches to the freewheeling diodes of each IGBT in the lower bridge arm, and phase U enters State 0.

[0051] Conversely, when the upper bridge arm performs the sequential conduction process from State0 to State1, a high-level gate drive signal... Arriving sequentially with a delay of Δt. First When it is turned on, its corresponding decoupling diode buffer capacitor Bypass decoupling, node U potential rises The phase voltage rises by an amplitude of The steps; then As the circuits are turned on sequentially, the phase voltage increases step by step until it reaches State 1.

[0052] When the load current When the current is less than zero (current flows from the motor to the inverter), the stepped waveform shaping is achieved by the sequential operation of the lower bridge arm IGBT.

[0053] Therefore, regardless of the current direction, the rising and falling edges of the output voltage pulse of the same bridge arm are shaped into a stepped waveform consisting of N voltage steps, each step having an amplitude of [missing value]. This stepped waveform transforms the output voltage's spectral envelope from a smooth type to an oscillating and decaying type, forming a periodic peak and trough distribution on the spectrum, with each suppression bandwidth being [missing information]. Hz (where τ is the step duration, i.e., Δt=τ+b, b is the IGBT voltage switching time), each suppression cycle contains N-1 peaks and N-1 troughs. At the trough frequency, the harmonic components are suppressed to near zero, thus achieving periodic suppression of electromagnetic interference at the source.

[0054] S105: During the sequential turn-on or turn-off process of the insulated gate bipolar transistor, the energy stored in the RCD buffer circuit is recovered and fed back to the DC bus through the flyback converter associated with each bridge arm.

[0055] In some embodiments of this application, the energy absorbed by the buffer capacitor during the sequential switching process is recovered to avoid additional energy loss due to the introduction of step shaping.

[0056] During the sequential turn-on or turn-off process of the IGBT, the load current charges the snubber capacitors in each RCD snubber circuit, temporarily storing some energy in these capacitors. Taking the upper arm of phase U as an example, when it is in the on state, When the circuit is turned on, each buffer capacitor is connected to a shared energy storage capacitor through its corresponding decoupling diode. A pathway is formed, and excess charge stored in the buffer capacitor is transferred to... middle.

[0057] The primary circuit of the flyback converter includes a Zener diode. and resistance The clamping branch is formed, and a primary-side switch is used to drive it. The driver integrated circuit. When the energy storage capacitor (Upper bridge arm) or The voltage across the lower bridge arm gradually increases with charge accumulation, reaching the level of a Zener diode. With resistance When the preset clamping voltage value is set, the resistor The voltage generated will trigger the driver integrated circuit to work, causing the primary-side switching transistor to switch. Conduction.

[0058] At this time, the energy stored in the energy storage capacitor is injected into the primary winding of the flyback transformer T in the form of current. Since the polarities of the primary and secondary windings of the transformer are opposite, the rectifier diodes on the secondary side are reverse biased and cut off, and the energy is temporarily stored in the transformer core in the form of a magnetic field.

[0059] Subsequently, when the bridge arm enters the sequential turn-off state, the primary-side switch transistor... When the circuit is switched off, the current flowing through the primary winding is abruptly cut off. To maintain magnetic flux continuity, the voltage polarity of all windings in the transformer is reversed: the negative primary winding terminal becomes positive, while the negative secondary winding terminal becomes negative. This reversal causes the rectifier diodes in the secondary circuit to become forward-biased and conduct, converting the magnetic field energy stored in the transformer into electrical energy, which is then delivered as current to the output filter capacitor connected to the DC bus. The entire flyback converter structure is as follows: Figure 3 As shown.

[0060] Through this complete energy recovery process, the energy absorbed by the buffer circuit during the step switch transient is effectively fed back to the DC bus, reducing energy dissipation as heat.

[0061] It should be noted that, to verify the suppression effect of the proposed scheme, experimental verification was conducted on a 1140V / 3kW explosion-proof motor drive platform. The experiment used four series-connected IGBTs per phase, with Δt set to 0.5μs. Measurement results show that, compared with traditional synchronous switching, this method achieves effective phase voltage harmonic attenuation within a 2MHz spectral bandwidth. The measured spectrum exhibits clear periodic peak-and-trough characteristics, consistent with theoretical predictions. Radiated noise captured in the near-field of the motor drive system by a calibrated antenna shows that the root mean square value of the period decreased from 1.04V to 375mV, achieving a reduction of over 50%. Regarding switching losses, the total equivalent switching loss of the bridge arm in sequential switching mode is only 1.192mJ, significantly lower than that in synchronous switching mode. Power measurements show that the active power increase accounts for approximately 1.64% of the rated power, demonstrating good engineering acceptability. All experimental data fully verify the significant effect of this application in suppressing electromagnetic interference at the source and reducing switching losses.

[0062] It should be noted that, although the embodiments in this application are based on... Figure 1 Steps S101 to S105 will be described sequentially, but this does not mean that steps S101 and S105 must be performed in a strict order. The reason this embodiment follows this order is... Figure 1 The order in which steps S101 to S105 are described is provided to facilitate understanding of the technical solutions of the embodiments of this application by those skilled in the art. In other words, in the embodiments of this application, the order of steps S101 to S105 can be appropriately adjusted according to actual needs.

[0063] pass Figure 1 This method shapes the rising and / or falling edges of the output voltage pulse of the same bridge arm into a stepped waveform composed of N voltage steps, thereby altering the spectral distribution characteristics of the output voltage. This causes high-frequency harmonic energy to exhibit a periodic peak-and-trough distribution, suppressing harmonic components to near zero at the trough frequencies, thus achieving effective suppression of electromagnetic interference at its source. Experimental results show that effective harmonic attenuation can be achieved within a 0 to 2 MHz spectral bandwidth, reducing the root mean square value of the near-field radiated noise period by more than 50%. Furthermore, by adjusting the number N of series-connected insulated-gate bipolar transistors and the preset time delay, the duration of each voltage step in the stepped waveform can be flexibly controlled, thereby specifically suppressing harmonic components within a specific frequency band to the trough frequency. This achieves customized suppression of electromagnetic interference in different frequency bands, improving the adaptability and designability of the solution.

[0064] Furthermore, due to the stepped voltage change, the current spikes of the series-connected insulated-gate bipolar transistors on the same bridge arm are significantly reduced when they are sequentially turned on. This lowers the total switching loss of the bridge arm compared to traditional synchronous switching methods, thus suppressing electromagnetic interference. Finally, timing delay processing can be achieved simply by using cascaded D flip-flops in the CPLD control module. No complex modifications to the existing gate drive circuit are required, nor is a specific pulse width modulation strategy necessary. The structure is simple, low-cost, and highly compatible, allowing for use in conjunction with other electromagnetic interference suppression technologies. It is suitable for motor drive systems of different power levels.

[0065] Figure 2 The diagram shows the on / off state of the bridge arm when the load current changes, according to an embodiment of this application for an inverter source-side electromagnetic interference suppression method.

[0066] exist Figure 2 The diagram shows a detailed timing diagram of the sequential turn-on and turn-off process of the series-connected insulated-gate bipolar transistors (IGBTs) in the upper bridge arm under different load current directions. When the load current is greater than zero, the upper bridge arm performs a sequential turn-off process from fully on to fully off. The control signal is applied sequentially from the phase output terminal furthest from the phase output terminal to the phase output terminal closest to the phase output terminal. Each time an IGBT is turned off, the load current is transferred to the corresponding buffer capacitor for charging, causing the phase voltage to drop by an amplitude equal to the DC bus voltage. The steps are formed, and the series insulated gate bipolar transistors corresponding to the lower bridge arm perform a sequential conduction process; when the load current is less than zero, the sequential action is to turn off the lower bridge arm and turn on the upper bridge arm, which also forms a stepped waveform.

[0067] The figure clearly shows the delay time Δt of the gate drive signal of each insulated gate bipolar transistor, the charging and discharging path of the buffer capacitor, the bypassing effect of the decoupling diode, and the step-like rising and falling edges of the phase voltage as the switching action changes. It intuitively presents the complete mechanism of shaping the traditional steep voltage pulse into a multi-stage stepped waveform through sequential switching.

[0068] Figure 3 This is a structural diagram of a flyback converter for an inverter source-side electromagnetic interference suppression method provided in an embodiment of this application.

[0069] exist Figure 3 The diagram illustrates a flyback converter structure used to recover energy temporarily stored in the RCD snubber circuit during the sequential switching of the insulated-gate bipolar transistors (IGBTs) and feed it back to the DC bus. The left side of the diagram shows multiple RCD snubber circuits connected in parallel for each phase arm of the bridge, with each snubber capacitor connected to a shared energy storage capacitor (i.e., the one shown in the diagram) via a decoupling diode. or The primary side of the flyback converter includes a clamping voltage detection branch consisting of a Zener diode and a resistor, a primary-side switching transistor and its driver integrated circuit. When the voltage across the energy storage capacitor reaches a preset clamping value, the primary-side switching transistor is triggered to conduct, allowing the energy stored in the energy storage capacitor to be injected into the primary winding of the flyback transformer in the form of current. The secondary side includes a rectifier diode and an output filter capacitor, which is directly connected in parallel to the DC bus. The two stages of energy feedback are clearly marked by arrows in the figure: during the conduction stage, the primary current path and the magnetic field energy storage are established; during the turn-off stage, the polarity of the secondary winding voltage is reversed, the rectifier diode is forward biased and conducts, and the magnetic field energy is converted into electrical energy and delivered to the output filter capacitor and fed back to the DC bus.

[0070] Figure 4 A schematic diagram of an inverter source-side electromagnetic interference suppression device provided in this application embodiment includes: At least one processor; and, A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, which, when executed by at least one processor, enable the at least one processor to perform any of the above-mentioned methods for suppressing electromagnetic interference at the source end of an inverter.

[0071] Some embodiments of this application provide a non-volatile computer storage medium for suppressing electromagnetic interference at the source end of an inverter, which stores computer-executable instructions capable of executing any of the above-mentioned methods for suppressing electromagnetic interference at the source end of an inverter.

[0072] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device and medium embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the description of the method embodiments.

[0073] The devices and media provided in this application are one-to-one with the methods. Therefore, the devices and media also have similar beneficial technical effects as their corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0074] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0077] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0078] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0079] Memory may include non-persistent storage in computer-readable media, random access memory (RAM), and non-volatile memory such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0080] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0081] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0082] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the technical principles of this application should fall within the protection scope of this application.

Claims

1. A method for suppressing electromagnetic interference at the source end of an inverter, characterized in that, The method includes: A three-phase series insulated-gate bipolar transistor inverter topology is constructed; each phase of the three-phase series insulated-gate bipolar transistor inverter consists of N insulated-gate bipolar transistors connected in series in the upper and lower bridge arm switching branches, and an RCD buffer circuit is connected in parallel to each insulated-gate bipolar transistor; N is an integer greater than or equal to 2; the RCD buffer circuit consists of a voltage equalizing resistor, a buffer capacitor, and a decoupling diode; Based on the frequency and amplitude of the target output voltage of the three-phase series insulated gate bipolar transistor inverter, a main pulse width modulation signal for controlling the switching state of each phase bridge arm is generated through a sinusoidal pulse width modulation strategy. The CPLD control module receives the main pulse width modulation signal and performs timing delay processing on the main pulse width modulation signal according to the shift register chain composed of cascaded D flip-flops to generate N gate drive signals. The N gate drive signals respectively control N series insulated gate bipolar transistors on the same bridge arm, and the x-th gate drive signal has a preset time delay relative to the (x-1)-th gate drive signal. x is an integer from 2 to N. The N gate drive signals sequentially drive the N series insulated gate bipolar transistors on the same bridge arm to turn on or off, so as to shape the rising edge and / or falling edge of the output voltage pulse of the same bridge arm into a stepped waveform composed of N voltage steps. During the sequential turn-on or turn-off of the insulated gate bipolar transistor, the energy stored in the RCD buffer circuit is recovered and fed back to the DC bus through the flyback converter associated with each bridge arm.

2. The method according to claim 1, characterized in that, The preset time delay is greater than the time required for the collector-emitter voltage of the insulated gate bipolar transistor to complete the transition during the turn-off process, and the total delay time of all series-connected insulated gate bipolar transistors does not exceed 3% of the pulse width modulation carrier period.

3. The method according to claim 1, characterized in that, The execution steps for sequentially turning on or off the insulated gate bipolar transistor are as follows: Depending on the direction of the load current, when the load current is greater than zero, the upper bridge arm insulated gate bipolar transistors are controlled to turn on or off sequentially; when the load current is less than zero, the lower bridge arm insulated gate bipolar transistors are controlled to turn on or off sequentially.

4. The method according to claim 1, characterized in that, The step of sequentially driving the N series-connected insulated-gate bipolar transistors on the same bridge arm to turn on or off via the N gate drive signals, so as to shape the rising and / or falling edges of the output voltage pulse of the same bridge arm into a stepped waveform composed of N voltage steps, specifically includes: During the turn-off process, turn-off drive signals are sequentially applied to N series-connected insulated-gate bipolar transistors (IGBTs) on the same bridge arm, from the phase output terminal furthest from the output terminal to the phase output terminal closest to the output terminal. Each time an IGBT is turned off, the load current is transferred to the corresponding buffer capacitor of that IGBT for charging, causing the phase voltage to drop by one step; the step amplitude is equal to the DC bus voltage. ; During the conduction process, conduction drive signals are sequentially applied to N series-connected insulated-gate bipolar transistors (IGBTs) on the same bridge arm, from the furthest point from the phase output terminal to the closest point. Each time an IGBT is turned on, the corresponding buffer capacitor is bypassed by a decoupling diode, causing the phase voltage to rise by a step; the step amplitude is equal to the DC bus voltage. .

5. The method according to claim 1, characterized in that, The process of receiving the main pulse width modulation signal through the CPLD control module, performing timing delay processing on the main pulse width modulation signal according to the shift register chain composed of cascaded D flip-flops, and generating N gate drive signals specifically includes: The main pulse width modulation signal is used as the first gate drive signal and directly output to the first insulated gate bipolar transistor on the same bridge arm. The main pulse width modulation signal is simultaneously input to the input terminal of a shift register chain composed of cascaded D flip-flops; At the arrival of each clock cycle, each stage of the shift register chain of D flip-flops passes the currently stored state of the main pulse width modulation signal to the next stage of D flip-flops; The signal after a preset delay time is extracted from the output of the first-stage D flip-flop in the shift register chain and output as the second gate drive signal to the second insulated gate bipolar transistor on the same bridge arm; And so on, starting from the first The output of the stage D flip-flop extracts the delayed signal and outputs it as the xth drive signal to the xth insulated gate bipolar transistor on the same bridge arm, until all N gate drive signals with sequentially increasing delays are generated.

6. The method according to claim 1, characterized in that, During the sequential turn-on or turn-off process of the insulated gate bipolar transistor, the energy stored in the RCD buffer circuit is recovered and fed back to the DC bus through the flyback converter associated with each bridge arm, specifically including: During the sequential conduction of the bridge arm, the charge stored in each buffer capacitor in the RCD buffer circuit is guided to the energy storage capacitor on the primary side of the flyback converter through the diodes connected to each buffer capacitor. When the voltage across the energy storage capacitor reaches the preset clamping voltage value, the switch on the primary side of the flyback converter is triggered to turn on, so that the energy stored in the energy storage capacitor is injected into the primary winding of the flyback transformer in the form of current. During the sequential turn-off of the bridge arm, the primary side switch is turned off to cut off the primary winding current, causing the voltage polarity of each winding of the flyback transformer to reverse, and the corresponding terminal of the secondary winding changes from low potential to high potential. By reversing the polarity of the secondary winding voltage, the diode in the secondary circuit is forward biased and turned on, converting the magnetic field energy stored in the flyback transformer into electrical energy, which is then delivered to the output filter capacitor connected to the DC bus to complete the energy feedback.

7. The method according to claim 1, characterized in that, The process of generating a main pulse width modulation signal for controlling the switching state of each phase bridge arm based on the frequency and amplitude of the target output voltage of the three-phase series insulated-gate bipolar transistor inverter using a sinusoidal pulse width modulation strategy specifically includes: Receives command signals from the controller; the command signals include amplitude and frequency information of the fundamental voltage that the inverter is expected to output; A sinusoidal modulated wave signal of the corresponding frequency is generated based on the frequency information, and the amplitude of the sinusoidal modulated wave signal is determined based on the amplitude information. A triangular carrier signal with a frequency higher than that of the sinusoidal modulated wave signal is generated; the frequency of the triangular carrier signal is a preset carrier frequency. The instantaneous value of the sinusoidal modulated wave signal is compared with the instantaneous value of the triangular carrier signal in real time. When the instantaneous value of the sinusoidal modulated wave is greater than the instantaneous value of the triangular carrier signal, a high-level pulse is output. When the instantaneous value of the sinusoidal modulation wave is less than or equal to the instantaneous value of the triangular carrier wave, a low-level pulse is output. The comparison results are used as the main pulse width modulation signal and output to the CPLD control module of each corresponding bridge arm.

8. The method according to claim 1, characterized in that, The method further includes: Based on the stepped waveform, the voltage and high-frequency harmonic amplitude are reduced to achieve periodic suppression of electromagnetic interference at the inverter source end, while reducing total switching losses.

9. An inverter source-side electromagnetic interference suppression device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform an inverter source-side electromagnetic interference suppression method according to any one of claims 1-8.

10. An inverter source-side electromagnetic interference suppression storage medium, storing computer-executable instructions, characterized in that, The computer-executable instructions are capable of executing the inverter source-side electromagnetic interference suppression method according to any one of claims 1-8.

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