Power-down reset circuit and electronic device

Abstract

This application discloses a power-down reset circuit and electronic device. The power-down reset circuit includes a voltage detection circuit and a PDR threshold setting circuit. The voltage detection circuit acquires the power supply voltage and generates a voltage detection signal characterizing the power supply voltage. The PDR threshold setting circuit responds to the voltage detection signal and outputs a corresponding reset signal. This application can output a reset signal corresponding to the voltage detection signal, so that the reset signal is adapted to the power supply voltage, thereby enabling the power-down reset circuit to match the requirements of corresponding application scenarios.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a power-down reset circuit and electronic device. Background Technology

[0002] In recent years, with the miniaturization and multifunctionality of electronic devices, the semiconductor integrated circuits used in them have become increasingly complex. To ensure the stable and reliable operation of the system, power supply voltage detection circuits are usually incorporated into these semiconductor integrated circuits. For example, the well-known power-down reset (PDR) circuit is used to monitor whether the power supply voltage is stable.

[0003] Traditional PDR circuits typically have a preset threshold voltage (also known as the PDR threshold) to determine whether the power supply voltage has dropped to a level that could cause circuit logic corruption or data loss. When the power supply voltage is detected to be below the PDR threshold, the PDR circuit outputs a reset signal, forcing the system to return to its initial state to prevent malfunctions.

[0004] In the integrated circuit design and manufacturing stage, some solutions fix the PDR threshold to an unchangeable value through process options or fuse blowing. While simple, this approach lacks flexibility. Because the normal operating voltage, tolerance to power supply noise, and logic levels of other interface circuits may vary across different application scenarios, a fixed PDR threshold often cannot be optimal in all applications. This can lead to frequent false resets due to an excessively high threshold, or ineffective data protection due to an excessively low threshold. Therefore, providing a power-down reset circuit that can automatically determine the corresponding threshold based on the actual application environment has become a pressing problem for those skilled in the art. Summary of the Invention

[0005] In view of this, this application provides a power-down reset circuit and an electronic device, so that the power-down reset circuit can automatically determine the corresponding threshold.

[0006] This application provides a power-down reset circuit, which includes a voltage detection circuit and a PDR threshold setting circuit; The voltage detection circuit is used to acquire the power supply voltage and generate a voltage detection signal characterizing the power supply voltage. The PDR threshold setting circuit is used to respond to the voltage detection signal and output a corresponding reset signal.

[0007] Optionally, the voltage detection circuit includes multiple pull-up units, a selection unit, a MOSFET, a buffer unit, and a pull-down unit corresponding to each pull-up unit; the first terminal of each pull-up unit is used to connect to the power supply voltage, and the second terminal is connected to the first terminal of the corresponding selection unit and the gate of the corresponding MOSFET; the second terminal of each selection unit is grounded; the first terminal of each MOSFET is used to connect to the power supply voltage, and the second terminal is connected to the first terminal of the corresponding buffer unit and the first terminal of the corresponding pull-down unit; the second terminal of each pull-down unit is grounded; the second terminal of each buffer unit is used to output the voltage detection signal.

[0008] Optionally, the number of pull-up units is N; the i-th gating unit corresponding to the i-th pull-up unit includes i transistors connected in series; 1≤i≤N.

[0009] Optionally, the i-th gating unit includes i diodes connected in series.

[0010] Optionally, the i-th pull-up unit corresponds to the i-th gating unit, which includes i MOS transistors connected in series.

[0011] Optionally, the i-th pull-up unit corresponds to the i-th gating unit, which includes i transistors connected in series.

[0012] Optionally, the buffer unit includes a Schmitt trigger buffer.

[0013] Optionally, the pull-up unit includes a first resistor; the pull-down unit includes a second resistor.

[0014] Optionally, the PDR threshold setting circuit includes a latch circuit, a decoding circuit, and a multiplexer; the latch circuit includes N-1 input terminals, the i-th input terminal is connected to the output terminal of the (i+1)-th buffer unit and the (i+1)-th input terminal of the multiplexer, the i-th output terminal is connected to the i-th input terminal of the decoding circuit, and the setting terminal is used to receive a setting signal; the i-th output terminal of the decoding circuit is connected to the i-th setting terminal of the multiplexer; the first input terminal of the multiplexer is connected to the output terminal of the first buffer unit, the N-th setting terminal is used to receive the setting signal, and the output terminal is used to output the reset signal; the latch circuit is used to respond to the setting signal SET when the power supply voltage VDD is applied, sample and latch the voltage detection signal, and output the latched value; the decoding circuit is used to perform logical decoding on the latched value, converting the latched value into a corresponding threshold selection signal; the multiplexer is used to respond to the setting signal and the threshold selection signal, select one of the multiple voltage detection signals as the final reset signal output.

[0015] This application also provides an electronic device, which includes any of the above-described power-off reset circuits.

[0016] In the power-down reset circuit and electronic device described above in this application, the voltage detection circuit can acquire the power supply voltage and generate a voltage detection signal characterizing the power supply voltage. The PDR threshold setting circuit can perform corresponding calculations on the voltage detection signal and output a reset signal corresponding to the voltage detection signal so that the reset signal is adapted to the power supply voltage, thereby enabling the power-down reset circuit to match the corresponding application scenario requirements. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a power-down reset circuit according to an embodiment of this application; Figure 2 This is a schematic diagram of a voltage detection circuit structure according to an embodiment of this application; Figure 3 This is a schematic diagram of a voltage detection circuit structure according to another embodiment of this application; Figure 4 This is a schematic diagram of a voltage detection circuit structure according to another embodiment of this application; Figure 5 This is a schematic diagram of a voltage detection circuit structure according to another embodiment of this application; Figure 6 This is a schematic diagram of the PDR threshold setting circuit structure according to an embodiment of this application; Figure 7 This is a schematic representation of the truth values ​​of relevant signals according to an embodiment of this application; Figure 8 This is a schematic representation of the truth value of a related signal according to another embodiment of this application; Figure 9 This is a schematic representation of the truth value of a related signal according to another embodiment of this application; Figure 10 This is a schematic diagram of the relevant signal waveforms according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0020] The first aspect of this application provides a power-down reset circuit, as referenced... Figure 1 As shown, the power-down reset circuit includes a voltage detection circuit 100 and a PDR threshold setting circuit 200. The voltage detection circuit 100 is used to acquire the power supply voltage VDD and generate a voltage detection signal characterizing the power supply voltage VDD. The PDR threshold setting circuit 200 is used to respond to the voltage detection signal and output a corresponding reset signal, so that the reset signal is determined according to the voltage detection signal, that is, according to the power supply voltage VDD, and is adapted to the power supply voltage VDD.

[0021] Optionally, the voltage detection signal is used to characterize the magnitude of the power supply voltage VDD. For example, the voltage detection signal includes a 5-bit binary number, where 00001 can indicate that the power supply voltage VDD is within a certain range, 00011 can indicate that the power supply voltage VDD is within another range, and so on. Optionally, the PDR threshold setting circuit 200 can be implemented in a multi-level configuration to perform relevant calculations on the voltage detection signal and output a reset signal corresponding to the voltage detection signal.

[0022] In the aforementioned power-down reset circuit, the voltage detection circuit 100 can acquire the power supply voltage VDD and generate a voltage detection signal characterizing the power supply voltage VDD. The PDR threshold setting circuit 200 can perform corresponding calculations on the voltage detection signal and output a reset signal corresponding to the voltage detection signal, so that the reset signal is adapted to the power supply voltage VDD, thereby enabling the power-down reset circuit to match the corresponding application scenario requirements.

[0023] In some embodiments, reference Figure 2 As shown, the voltage detection circuit 100 includes multiple pull-up units 110, a selection unit 120 corresponding to each pull-up unit, a MOSFET 130, a buffer unit 140, and a pull-down unit 150. The MOSFET 130 may include a PMOS transistor. Specifically, as shown... Figure 2As shown, the pull-up unit 110 may include five pull-up units, from the first pull-up unit 111 to the fifth pull-up unit 115; the gating unit 120 may include five gating units, from the first gating unit 121 to the fifth gating unit 125; the MOSFET 130 may include five MOSFETs, from MOSFET M1 to MOSFET M5; the buffer unit 140 may include five buffer units, from the first buffer unit Q1 to the fifth buffer unit Q5; and the pull-down unit 150 may include five pull-down units, from the first pull-down unit 151 to the fifth pull-down unit 155. The first pull-up unit 111 corresponds to the first gating unit 121, the MOSFET M1, the first buffer unit Q1, and the first pull-down unit 151; the second pull-up unit 112 corresponds to the second gating unit 122, the MOSFET M2, the second buffer unit Q2, and the third pull-down unit 152, and so on, so that each pull-up unit has a corresponding gating unit 120, MOSFET 130, buffer unit 140, and pull-down unit 150.

[0024] Each pull-up unit 110 has its first terminal connected to the power supply voltage VDD, and its second terminal connected to the first terminal of the corresponding gating unit 120 and the gate of the corresponding MOSFET 130. The second terminal of each gating unit 120 is grounded. Each MOSFET 130 has its first terminal connected to the power supply voltage VDD, and its second terminal connected to the first terminal of the corresponding buffer unit 140 and the first terminal of the corresponding pull-down unit 150. The second terminal of each pull-down unit 150 is grounded. The second terminal of each buffer unit 140 is used to output a voltage detection signal. In each MOSFET 130, the first terminal is one of its source and drain, and the second terminal is the other of its source and drain. The pull-up units 110 and 150 can be implemented using impedance elements; for example, the i-th pull-up unit 110 may include i series-connected impedance devices, the i-th pull-down unit 150 may include i series-connected impedance devices, and so on.

[0025] Specifically, the number of pull-up units 110 is N; the i-th gating unit corresponding to the i-th pull-up unit includes i transistors connected in series, and each transistor can be turned on when the voltage value at one end reaches the corresponding voltage threshold, so as to connect the first end of the corresponding pull-up unit 110 and the second end of the gating unit 120 to which it belongs; 1≤i≤N.

[0026] The i-th gating unit comprises i transistors connected in series. Optionally, the transistors can be implemented using diodes, each diode having a forward voltage of VF, wherein the forward voltage of the diode includes the voltage drop across the diode when current flows from the anode (+) to the cathode (-) (i.e., forward). The i-th pull-down unit 150 is turned on when VDD≥VF×i. At this time, the i-th pull-up unit 110 limits the current input to the i-th gating unit. The voltage at the first terminal of the i-th gating unit is Vthi=VF×i, which makes the gate-source voltage of the MOS transistor corresponding to the i-th diode Vgsi>VDD-(Vthi+Vdsat), where Vgsi represents the gate-source voltage of the MOS transistor corresponding to the i-th diode, Vthi represents the threshold voltage corresponding to the i-th gating unit, and Vdsat represents the saturated drain-source voltage of the MOS transistor corresponding to the i-th diode. The saturated drain-source voltage refers to the critical point of the drain-source voltage (Vds) when the transistor switches from the "linear region" to the "saturated region (the region where the current becomes constant)". When the i-th transistor is turned on, the i-th pull-down unit 150 limits the current at the second terminal of the i-th transistor. The i-th buffer unit 140 converts the signal input at its first terminal into a high level or a low voltage, so that each buffer unit 140 cooperates with each other to output the corresponding voltage detection signal PDR_VTH.<N-1:0> Voltage detection signal PDR_VTH<N-1:0> Includes N binary numbers, for example Figure 2 As shown, N=5, PDR_VTH<N-1:0> Including the binary number PDR_VTH output by the first buffer unit Q1 <0> The binary number PDR_VTH output by the second buffer unit Q2 <1> The binary number PDR_VTH output by the third buffer unit Q3 <2> The binary number PDR_VTH output by the fourth buffer unit Q4 <3> And the binary number PDR_VTH output by the fifth buffer unit Q5 <4> etc.

[0027] Optionally, the buffer unit 140 is implemented using a Schmitt trigger buffer, with the input of the Schmitt trigger buffer being the first end of the buffer unit 140 and the output of the Schmitt trigger buffer being the second end of the buffer unit 140.

[0028] In some examples, such as Figure 3 As shown, the i-th pull-up unit 110 corresponds to the i-th gating unit 120, which includes i diodes connected in series.

[0029] In some examples, such as Figure 4As shown, the i-th pull-up unit 110 corresponds to the i-th gating unit 120, which includes i MOSFETs connected in series. The gate of each MOSFET is connected to its first terminal, and its second terminal is connected to the first terminal and gate of the next MOSFET. The first terminal of the first MOSFET serves as the first terminal of the corresponding gating unit 120, and the second terminal of the last MOSFET serves as the second terminal of the corresponding gating unit 120. For each MOSFET, its first terminal is one of its source and drain, and its second terminal is the other of its source and drain.

[0030] In some examples, such as Figure 5 As shown, the i-th pull-up unit 110 corresponds to the i-th gating unit 120, which includes i transistors connected in series. The base of each transistor is connected to the collector of the transistor, and the emitter is connected to the collector and base of the next transistor, respectively. The collector of the first transistor serves as the first terminal of the corresponding gating unit 120, and the emitter of the last transistor serves as the second terminal of the corresponding gating unit 120.

[0031] In some examples, such as Figure 3 As shown, each pull-up unit 110 is implemented using a current mirror circuit with a transistor. Correspondingly, each pull-down unit 150 can also be implemented using a current mirror circuit with a transistor.

[0032] In some examples, such as Figure 4 and Figure 5 As shown, each pull-up unit 110 is implemented using a first resistor, the first end of the first resistor is the first end of the corresponding pull-up unit 110, and the second end of the first resistor is the second end of the corresponding pull-up unit 110.

[0033] In some examples, such as Figure 4 and Figure 5 As shown, each pull-down unit 150 is implemented using a second resistor. The first end of the second resistor is the first end of the corresponding pull-down unit 150, and the second end of the second resistor is the second end of the corresponding pull-down unit 150.

[0034] In some embodiments, reference Figure 6 As shown, the PDR threshold setting circuit 200 includes a latch circuit 210, a decoding circuit 220, and a multiplexer 230.

[0035] The latch circuit 210 includes N-1 input terminals. The i-th input terminal is connected to the output terminal of the (i+1)-th buffer unit 140 and the (i+1)-th input terminal of the multiplexer 230. The i-th output terminal is connected to the i-th input terminal of the decoding circuit 220. The setting terminal is used to receive the setting signal SET. The i-th output terminal of the decoding circuit 220 is connected to the i-th setting terminal of the multiplexer 230. The first input terminal of the multiplexer 230 is connected to the output terminal of the first buffer unit. The N-th setting terminal of the multiplexer 230 is used to receive the setting signal SET. The output terminal of the multiplexer 230 is used to output the reset signal REST.

[0036] Taking N=5 as an example, the PDR threshold setting circuit 200 is described below. The first input terminal of the latch circuit 210 is connected to the output terminal of the second buffer unit Q2 and the second input terminal of the multiplexer 230. The second input terminal is connected to the output terminal of the third buffer unit Q3 and the third input terminal of the multiplexer 230. The third input terminal is connected to the output terminal of the fourth buffer unit Q4 and the fourth input terminal of the multiplexer 230. The fourth input terminal is connected to the output terminal of the fifth buffer unit Q5 and the fifth input terminal of the multiplexer 230. The first output terminal of the latch circuit 210 is connected to the first input terminal of the decoding circuit 220, and the second output terminal is connected to the... The second input terminal and the third output terminal of the code circuit 220 are connected to the third input terminal of the decoding circuit 220, and the fourth output terminal is connected to the fourth input terminal of the decoding circuit 220; the first output terminal of the decoding circuit 220 is connected to the first setting terminal of the multiplexer 230, the second output terminal is connected to the second setting terminal of the multiplexer 230, the third output terminal is connected to the third setting terminal of the multiplexer 230, and the fourth output terminal is connected to the fourth setting terminal of the multiplexer 230; the first input terminal of the multiplexer 230 is connected to the output terminal of the first buffer unit Q1; the fifth setting terminal of the multiplexer 230 is used to receive the setting signal SET.

[0037] The latch circuit 210 is used to respond to the setting signal SET and the voltage detection signal PDR_VTH output by the voltage detection circuit 100 when the power supply voltage VDD is applied (power-on complete and entering a stable operating state).<N-1:0> Sample and latch the data, and output a stable latch value LAT_VTH. <n-1:1>If N=5, the latch value is LAT_VTH. <n-1:1>Including the LAT_VTH output from its first output terminal <1> The second output terminal outputs LAT_VTH <2> The third output terminal outputs LAT_VTH <3> The LAT_VTH output from the fourth output terminal <4> During this process, the latch circuit 210 records the power supply voltage VDD level of the system containing the power-down reset circuit at the moment of normal operation, providing a reference for subsequent threshold selection. Since the latch circuit 210 maintains its output unchanged after the set signal SET is valid, even if the power supply voltage VDD continues to rise or fluctuates, the latched voltage information will not change, thus ensuring that the setting basis of the subsequent output reset signal REST is stable and repeatable. Optionally, the set signal SET can be generated by controlling a combination of input interface signals of the IC on which the power-down reset circuit is installed.

[0038] Decoding circuit 220 is used to latch the value LAT_VTH output by latching circuit 210. <n-1:1>Perform logical decoding to latch the value LAT_VTH. <n-1:1>Converted to the corresponding threshold selection signal SEL_VTH <n-1:1>If N=5, the threshold selection signal SEL_VTH <n-1:1>Including the SEL_VTH output from the first output terminal of the decoding circuit 220 <1> The second output terminal outputs SEL_VTH <2> The third output terminal outputs SEL_VTH <3> The fourth output terminal outputs SEL_VTH <4> The decoding process of the decoding circuit 220 is essentially a logical mapping of the "normal operating voltage level of the system," converting the voltage range information recorded by the latch circuit 210 into a specific control code that indicates which voltage detection point the multiplexer should select. Optionally, the decoding circuit 220 can use a simplified method of extracting the high-level bits, that is, extracting the position of the high-level bit from the latched value and using it as the basis for subsequent selection.

[0039] Multiplexer 230 is used in response to the setting signal SET and the threshold selection signal SEL_VTH output by the decoding circuit 220. <n-1:1>The multi-channel voltage detection signal PDR_VTH output from the voltage detection circuit 100<N-1:0> Choose one path as the final reset signal REST output. During the system power-up phase (when the SET signal is low), the multiplexer 230 can select the lowest voltage detection point (PDR_VTH). <0> This ensures that the reset signal is immediately released when the power supply voltage VDD just reaches the basic operating conditions; after the system enters normal operating state (when the set signal SET is high), the multiplexer 230 selects the threshold selection signal SEL_VTH output by the decoding circuit 220. <n-1:1>The corresponding voltage detection point is selected, thereby enabling the reset signal REST to be active when the power supply voltage VDD drops to the preset optimal threshold.

[0040] In some examples, taking N=5 and the i-th gating unit including i diodes connected in series as an example, the operation of the above power-down reset circuit is explained in detail. When VDD=0V, each gating unit 120 is not turned on, so the voltage at the first terminal of each gating unit 120 is pulled up by the pull-up unit 110 and becomes VDD. When the voltage at the first terminal of each gating unit 120 is VDD, each MOSFET 130 is not turned on, so the voltage at the second terminal of each MOSFET 130 is pulled down by the corresponding pull-down unit 150 and becomes 0V. At this time, the voltage detection signal PDR_VTH<N-1:0> All are low level. (Reference) Figure 7 As shown, Figure 7 In this context, vth_P represents the turn-on voltage of each MOSFET in MOSFET 130, and VF represents the forward voltage of the diode in the selection unit. When VDD < VF × 1 + vth_P, D0 of configuration 10, which connects 1 to n diodes in series, is turned on, and Vvth_P is turned on. <0> It becomes VF, but Mp0 is not conducting, so it is pulled down by resistor 13, PDR_VTH <0> Output low level.

[0041] When VDD is higher than VF+vth_P, the i-th gating unit is turned on, and the voltage at the first terminal of the i-th gating unit changes from Vth1 to VF+vth_P. M1 is turned on, therefore PDR_VTH <0> It is at a high level. The relationship between the change of VDD and the high / low of PDR_VTH<4:0> can be found in [reference]. Figure 7 As shown. The output of the voltage detection circuit 100 is a voltage detection signal PDR_VTH<4:0> that changes with the increase of VDD.

[0042] The PDR_VTH<4:1> output from the voltage detection circuit is latched by the latch circuit 210 using the SET signal, and the latched value LAT_VTH<4:1> is output. LAT_VTH<4:1> is decoded by the decoding circuit 220, and a threshold selection signal SEL_VTH<4:1> is output. This threshold selection signal SEL_VTH<4:1> can be referenced. Figure 8 The truth table is shown. In some examples, the high-order bits of LAT_VTH<4:1> can be output as SEL_VTH<4:1>. Based on the SEL_VTH<4:1> of the output signal of the decoding circuit 220 and the set signal SET, the multiplexer 230 selects it as the output PDR_VTH<4:0> of the voltage detection circuit 100, as shown. Figure 9 As shown. The threshold for the system to transition from a low level to a high level when power is lost is... Figure 9 The voltage in the PDR threshold column. In some examples, the PDR threshold is the detected voltage when the set signal SET goes high.

[0043] The curves corresponding to each signal can be referenced. Figure 10 As shown, Figure 10 In the graph, the horizontal axis represents time and the vertical axis represents voltage. V0 represents VF×1+vth_P, V1 represents VF×2+vth_P, V2 represents VF×3+vth_P, V3 represents VF×4+vth_P, and V4 represents VF×5+vth_P. Figure 10 Characterized by the fact that when the system is powered on, the power supply voltage VDD rises linearly and can reach a certain value. During the rise of VDD, the voltage detection circuit 100 generates a voltage detection signal PDR_VTH<4:0>. When the set signal SET is low, the multiplexer 230 selects PDR_VTH. <0> And when VDD = VF × 1 + vth_P, the reset signal goes low. PDR_VTH<4:1> detected before the supply voltage rises from V0 or higher to a certain constant value is latched high by the set signal SET. When the set signal SET goes high, the power-down reset circuit is in normal operation. LAT_VTH<4:1> based on the VDD voltage at that point in time is used as the setting signal for the PDR threshold. PDR_VTH<4:0> selected by the combination of SEL_VTH<4:1> obtained by decoding LAT_VTH<4:1> and the set signal SET is used as the reset signal RESET. In some examples, LAT_VTH<4:1> = 7 is latched, with only the high-order bits decoded to a high level, SEL_VTH<4:1> = 4. During power-down, the supply voltage VDD decreases linearly to 0V. When the set PDR threshold is reached, the reset signal outputs a high level. In the example, PDR_VTH... <2> The RE setting signal SET is selected by the setting signal SET and SEL_VTH<4:1>, so when the voltage VF x3 + Vth_P is or lower, the RE setting signal SET outputs a high level. The inventors verified that when the above-mentioned power-down reset circuit is powered on, the reset signal is inactive within the range of power supply voltages that the internal circuit can operate on, and when the power is off, the reset signal needs to be activated by detecting the shutdown of the power supply voltage. It can be seen that the output of the reset signal RESET meets the necessary conditions. In addition, the above-mentioned power-down reset circuit has the function of selecting the PDR threshold according to the VDD voltage under normal operating conditions and activating the reset signal when the power is off. This power-down reset circuit does not require a fixed threshold, nor does it require the installation of memory and setting the threshold by registers, nor does it require setting the threshold by terminals. Instead, it operates as a power-down reset circuit and can automatically set an appropriate threshold according to the applied power supply voltage VDD.

[0044] In the above power-down reset circuit, the voltage detection circuit 100 can acquire the power supply voltage VDD and generate a voltage detection signal characterizing the power supply voltage VDD. The PDR threshold setting circuit 200 can perform corresponding calculations on the voltage detection signal and output a reset signal corresponding to the voltage detection signal so that the reset signal is adapted to the power supply voltage VDD, thereby enabling the power-down reset circuit to match the corresponding application scenario requirements.

[0045] This application also provides an electronic device, which includes the power-down reset circuit described in any of the above embodiments.

[0046] The above electronic devices include the power-down reset circuit described in any of the above embodiments, and have all the beneficial effects of the power-down reset circuit described in any of the above embodiments, which will not be repeated here.

[0047] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0048] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0049] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. In addition, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise expressly and specifically defined.

[0050] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A power-down reset circuit, characterized in that, The power-down reset circuit includes a voltage detection circuit and a PDR threshold setting circuit. The voltage detection circuit is used to acquire the power supply voltage and generate a voltage detection signal characterizing the power supply voltage. The PDR threshold setting circuit is used to respond to the voltage detection signal and output a corresponding reset signal.

2. The power-down reset circuit according to claim 1, characterized in that, The voltage detection circuit includes multiple pull-up units, a selection unit, a MOSFET, a buffer unit, and a pull-down unit corresponding to each pull-up unit; The first terminal of each pull-up unit is used to connect to the power supply voltage, and the second terminal is connected to the first terminal of the corresponding gating unit and the gate of the corresponding MOS transistor respectively; the second terminal of each gating unit is grounded; the first terminal of each MOS transistor is used to connect to the power supply voltage, and the second terminal is connected to the first terminal of the corresponding buffer unit and the first terminal of the corresponding pull-down unit respectively; the second terminal of each pull-down unit is grounded; the second terminal of each buffer unit is used to output the voltage detection signal.

3. The power-down reset circuit according to claim 2, characterized in that, The number of pull-up units is N; the i-th gating unit corresponding to the i-th pull-up unit includes i transistors connected in series; 1≤i≤N.

4. The power-down reset circuit according to claim 3, characterized in that, The i-th gating unit consists of i diodes connected in series.

5. The power-down reset circuit according to claim 3, characterized in that, The i-th pull-up unit corresponds to the i-th gating unit, which includes i MOS transistors connected in series.

6. The power-down reset circuit according to claim 3, characterized in that, The i-th pull-up unit corresponds to the i-th gating unit, which consists of i transistors connected in series.

7. The power-down reset circuit according to claim 2, characterized in that, The buffer unit includes a Schmitt trigger buffer.

8. The power-down reset circuit according to claim 2, characterized in that, The pull-up unit includes a first resistor; the pull-down unit includes a second resistor.

9. The power-down reset circuit according to claim 3, characterized in that, The PDR threshold setting circuit includes a latch circuit, a decoding circuit, and a multiplexer. The latch circuit includes N-1 input terminals. The i-th input terminal is connected to the output terminal of the (i+1)-th buffer unit and the (i+1)-th input terminal of the multiplexer. The i-th output terminal is connected to the i-th input terminal of the decoding circuit. The setting terminal is used to receive a setting signal. The i-th output terminal of the decoding circuit is connected to the i-th setting terminal of the multiplexer. The first input terminal of the multiplexer is connected to the output terminal of the first buffer unit. The N-th setting terminal is used to receive the setting signal, and the output terminal is used to output the reset signal. The latching circuit is used to sample and latch the voltage detection signal in response to the setting signal SET when the power supply voltage VDD is applied, and output the latched value. The decoding circuit is used to perform logical decoding on the latched value and convert the latched value into a corresponding threshold selection signal; The multiplexer is used to select one of the multiple voltage detection signals as the final reset signal output in response to the setting signal and the threshold selection signal.

10. An electronic device, characterized in that, The electronic device includes the power-down reset circuit according to any one of claims 1 to 9.

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