A method and device for accurately alleviating host congestion based on DPU

Abstract

The application discloses a kind of based on DPU's host congestion accurate mitigation method and device, the method includes: host monitoring agent is constructed in host side, is generated host congestion signal by reading the hardware counter of PCIe interface and memory subsystem pressure, and is passed to data processor DPU by shared memory channel;DPU processing engine receives host congestion signal, and the load factor of DPU local queue is combined to calculate hybrid congestion index;DPU classifies flow, and directly forwards through fast forwarding path to time delay sensitive stream, and through dynamic queue management to non time delay sensitive stream;Based on hybrid congestion index, DPU executes probabilistic packet loss policy to in-bound traffic sent to host, and executes explicit congestion notification marking strategy to out-bound traffic sent to network.The application utilizes the advantage of DPU, realizes the fast perception and differentiation control to host congestion, reduces packet loss under high load scenario and improves tail delay.

Description

Technical Field

[0001] This invention relates to the fields of computer network communication and high-performance computing technology, specifically to the field of congestion mitigation technology, and particularly to a method and apparatus for precise host congestion mitigation based on a DPU (Data Processing Unit). Background Technology

[0002] With the rapid development of cutting-edge technologies such as cloud computing, big data analytics, and large-scale artificial intelligence training, the demand for network bandwidth and computing power in data center applications has increased dramatically. To meet these demands, modern data center servers are typically equipped with high-performance network interface cards (NICs) that use Direct Memory Access (DMA) technology to transfer received data packets to host memory at high speed. However, in high-throughput scenarios, the NIC's DMA operations compete with the host central processing unit (CPU) for limited memory bandwidth and bus resources.

[0003] This resource contention leads to "host congestion." When the memory subsystem or PCIe bus is overloaded, data packets cannot be written to memory in a timely manner, thus accumulating in the network card buffer and ultimately causing severe packet loss and increased long-tail latency. This host-side congestion problem has become one of the key bottlenecks restricting the overall performance of data centers.

[0004] In existing technologies, congestion control methods based on the host kernel are typically used to mitigate this problem. For example, congestion signals are collected in the operating system kernel, and once congestion is detected, all Transmission Control Protocol (TCP) senders are notified to reduce their transmission rate, or hardware bandwidth allocation tools are used to limit bandwidth usage for non-network traffic.

[0005] However, the aforementioned existing technologies have significant limitations in practical applications. First, existing control strategies are often coarse-grained. Once congestion is detected, they typically apply indiscriminate rate limiting to all TCP flows, ignoring the fact that some traffic does not cause congestion. This can significantly reduce the overall throughput of the system network. Second, existing methods lack differentiated processing for traffic types, failing to distinguish between latency-sensitive flows and ordinary bandwidth flows. This results in critical services with extremely high latency requirements suffering unnecessary delays during congestion, failing to meet quality of service requirements. Third, limited by the size of the network card buffer, overflowing packets are often indiscriminately dropped, further exacerbating the performance degradation of critical services. Finally, relying on the host CPU for congestion monitoring and scheduling introduces additional computational overhead and processing jitter. Under high load scenarios, the host CPU itself may become a bottleneck, making it difficult to guarantee the timeliness and stability of congestion response.

[0006] Therefore, how to reduce the burden on the host CPU, achieve accurate perception of host congestion, and provide differentiated and precise mitigation strategies for different types of traffic are technical problems that urgently need to be solved in the field of data center network technology. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of existing technologies by providing a method and apparatus for precise host congestion mitigation based on DPU.

[0008] The objective of this invention is achieved through the following technical solution: A first aspect of this invention provides a precise host congestion mitigation method based on a Data Processor (DPU). The application environment includes a host and a Data Processor (DPU) connected to it via a PCIe interface. The method includes the following steps: (1) Acquisition and quantification of host-side congestion signals based on host monitoring agent: Run host monitoring agent on host side, read hardware counter indicators representing the pressure of PCIe interface and memory subsystem, calculate instantaneous direct memory access pressure value, and map pressure value into discrete congestion level signal; (2) Synchronization of congestion information between the host and the data processor based on the shared memory mechanism: The host monitoring agent writes the generated congestion level signal into the storage area shared by the host and the data processor so that the data processor can obtain the latest host congestion signal; (3) Fast forwarding of latency-sensitive flows based on flow classification mechanism: The data processor parses the data packet metadata at the entry point and identifies the data flow type. For non-latency-sensitive flows, forwarding is performed through steps (4)-(5); for latency-sensitive flows, forwarding is performed directly to the outgoing port through the fast forwarding path. (4) Calculate the hybrid congestion index based on the hybrid weighting mechanism: The data processor processing engine combines the host congestion signal obtained from the shared storage area with the load factor of the packet processing queue maintained locally by the data processor to calculate the hybrid congestion index that reflects the overall system pressure. (5) Congestion mitigation and recovery based on differentiated strategies: The data processor performs differentiated operations on data flows of different directions according to the mixed congestion index: if it is inbound traffic to the host, a probabilistic packet loss strategy is executed; if it is outbound traffic to the network, an explicit congestion notification marking strategy is executed.

[0009] Furthermore, the acquisition and quantization of the host-side congestion signal specifically includes: The host monitoring agent reads the performance counters of the host integrated I / O controller, which characterize the PCIe interface and memory subsystem pressure, to obtain the number of PCIe read transactions completed per unit time. It calculates the instantaneous direct memory access pressure value based on the rate of change of the number of read completed transactions and compares it with a preset pressure threshold range to quantize and map it to a predefined set of discrete congestion states, generating discrete congestion level signals.

[0010] Furthermore, it also includes: the host monitoring agent continuously and cyclically executes the local backpressure protection mechanism. The host monitoring agent estimates the effective memory bandwidth resources currently allocated to network traffic in real time, and triggers a local flow control mechanism when the effective memory bandwidth resources are lower than the preset bandwidth guarantee threshold: limiting the memory access rate of non-network-intensive applications on the host or adjusting their scheduling priority, so as to reserve PCIe bus and memory bandwidth resources for network traffic.

[0011] Furthermore, the stream classification mechanism specifically includes: When a data processor receives a data packet, it matches the metadata information of the parsed data packet with the static whitelist configuration or the host application registration information. If the match is successful, it is determined to be a latency-sensitive flow; if the match fails, it is determined to be a non-latency-sensitive flow.

[0012] Furthermore, the data processor processing engine maintains a main queue and an auxiliary overflow bucket for at least one processing core; when a data packet arrives and the main queue is full, the data packet is redirected to the auxiliary overflow bucket to absorb burst traffic; the load factor of the main queue is monitored in real time, and only when the load factor is lower than the injection threshold is the injection process executed to reinsert the data packet in the auxiliary overflow bucket into the main queue.

[0013] Furthermore, the calculation of the hybrid congestion index based on the hybrid weighting mechanism specifically includes: The data processor first periodically calculates the load factor of the queue of at least one local processing core and updates the short-term local congestion assessment value using an exponentially weighted moving average algorithm. Then, it obtains the host congestion signal from the shared storage area, performs smoothing processing, and updates the long-term host congestion assessment value. Finally, it performs a weighted sum of the short-term local congestion assessment value and the long-term host congestion assessment value according to a preset weight factor to obtain the hybrid congestion index.

[0014] Furthermore, the congestion mitigation and recovery based on differentiated strategies specifically includes: For inbound traffic, a minimum congestion threshold and a maximum congestion threshold are set. When the mixed congestion index is between the two, random packet loss is performed according to a linearly increasing packet loss probability function. When the mixed congestion index exceeds the maximum congestion threshold, all non-latency-sensitive data packets are dropped. When the mixed congestion index is below the minimum congestion threshold, no packet loss is performed. For outbound traffic, a marking probability is calculated. The marking probability is proportional to the packet loss probability. When the marking probability is hit and the data packet supports displaying congestion notification, a congestion bit is marked in the network layer header of the data packet to notify the sender to reduce the sending rate without dropping the data packet.

[0015] A second aspect of the present invention provides an apparatus for implementing the above-described DPU-based precise host congestion mitigation method, comprising: The host and its data processor (DPU) connected via a PCIe interface; The host is equipped with a host monitoring agent, which reads hardware counter indicators representing the pressure of the PCIe interface and memory subsystem, calculates the instantaneous direct memory access pressure value and maps it into a discrete congestion level signal, and writes the congestion level signal into the storage area shared by the host and the data processor. The data processor includes a parsing and classification module, a congestion calculation module, a queue management module, and a policy execution module. The parsing and classification module is used to parse data packet metadata and identify data flow types, and directly forward latency-sensitive flows through a fast forwarding path. The congestion calculation module is used to obtain host congestion signals from the shared storage area and calculate a hybrid congestion index by combining the load factor of the data packet processing queue maintained locally by the data processor. The queue management module is used to maintain the main queue and auxiliary overflow bucket for the processing core and provide local queue load information. The policy execution module is used to execute a probabilistic packet loss policy on inbound traffic destined for the host and an explicit congestion notification marking policy on outbound traffic destined for the network, based on the hybrid congestion index.

[0016] A third aspect of the present invention provides an electronic device, comprising: The host device includes a first processor and a first memory; The data processor (DPU) is connected to the host device via a PCIe interface and includes a second processor, a second memory, and a network interface. The first memory and the second memory store one or more programs. When one or more programs are executed by the first processor and the second processor, the above-described DPU-based host congestion mitigation method is implemented.

[0017] A fourth aspect of the present invention provides a computer-readable storage medium having a program stored thereon, which, when executed by a corresponding processor, is used to implement the above-described DPU-based host congestion precision mitigation method.

[0018] Compared with the prior art, the beneficial effects of the present invention are: (1) By offloading the main part of the congestion control logic to the DPU and using the DPU as an independent control node, the present invention effectively avoids the interference of the host CPU load on the congestion control algorithm, realizes the decoupling of the control plane and the data plane, and significantly reduces the overhead of the host CPU.

[0019] (2) By implementing a flow classification and fast forwarding mechanism on the DPU side, this invention ensures that latency-sensitive flows can be transmitted preferentially through the fast forwarding path in congestion scenarios, which helps to reduce the long-tail latency problem of critical service flows during congestion.

[0020] (3) The present invention constructs a hybrid congestion index that combines the long-term memory pressure signal on the host side and the short-term queue load signal on the DPU side. This multi-dimensional perception mechanism can not only respond quickly to micro-burst traffic, but also accurately reflect system-level bottlenecks, thus improving the timeliness and robustness of congestion detection.

[0021] (4) The present invention designs probabilistic packet loss and ECN marking strategies for inbound and outbound traffic respectively. While protecting the host memory subsystem from overload, it can send an effective speed reduction signal to the network side, realizing end-to-end congestion collaborative governance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the system architecture of a DPU-based host congestion precision mitigation method provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating a host-side monitoring method according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the DPU-side congestion control logic provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms “a,” “the,” and “the” used in this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0025] It should be understood that although the terms first, second, third, etc., may be used in this invention to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of this invention, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0026] The present invention will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0027] Existing data center host congestion control methods typically rely on the host kernel to collect and respond to congestion signals. This approach not only has coarse-grained control, making it difficult to differentiate between different types of traffic, but also significantly increases the computational burden on the host CPU under high-load scenarios, leading to delayed congestion response. Furthermore, existing technologies often employ a single packet loss or labeling strategy, making it difficult to simultaneously protect the host memory subsystem and effectively control the source transmission rate. Therefore, to address these issues, this invention provides a DPU-based method and apparatus for precise host congestion mitigation. Utilizing the DPU as an independent on-chip system, and combining host-side hardware telemetry signals with DPU-side queue status, it achieves precise perception and differentiated mitigation of host congestion.

[0028] Example 1: A DPU-based method for precise host congestion mitigation like Figure 1 and Figure 4 As shown, the application environment of the DPU-based host congestion mitigation method of the present invention includes a host and a data processor (DPU) connected to it via a PCIe interface (high-speed interconnect bus), and the congestion information on the host side is synchronized to the DPU side through a shared memory channel, which is a heterogeneous computing architecture.

[0029] The host includes an application layer, a host monitoring module (also known as a host monitoring agent (HMA)), a first memory, a first processor, and a first internal bus. The host monitoring module contains a congestion acquisition unit and a congestion quantization unit, which are responsible for acquiring congestion signals from the underlying hardware and calculating the congestion level.

[0030] The data processor, as a standalone system-on-a-chip, includes a second processor, a second memory, a network interface (for connecting to an external network), and a second internal bus. Logically, the DPU runs the parsing and classification module, the queue management module, the congestion calculation module, and the policy execution module.

[0031] In terms of control flow, the host monitoring module directly transmits the host-side pressure signal to the DPU-side congestion calculation module via a shared memory channel. Optionally, the data processor can use a polling method to read the congestion level in the shared memory to reduce the processing overhead caused by interrupt triggering and reduce synchronization latency.

[0032] Based on the above architecture, this DPU-based precise host congestion mitigation method specifically includes the following steps: (1) Acquisition and quantification of host-side congestion signals based on host monitoring agent: Run host monitoring agent on host side, read hardware counter indicators representing the pressure of PCIe interface and memory subsystem, calculate the pressure value of instantaneous direct memory access (DMA), and map the pressure value into discrete congestion level signals.

[0033] Furthermore, the acquisition and quantization of host-side congestion signals specifically includes: the host monitoring agent reading the performance counters of the host integrated I / O controller (IIO) that characterize the PCIe interface and memory subsystem pressure to obtain the number of PCIe read completed transactions per unit time; calculating the instantaneous direct memory access pressure value based on the rate of change of the number of read completed transactions, and comparing it with a preset pressure threshold range to quantize and map it to a predefined discrete congestion state set to generate discrete congestion level signals.

[0034] (2) Synchronization of congestion information between the host and DPU based on shared memory mechanism: The host monitoring agent writes the generated congestion level signal into the storage area shared by the host and DPU so that the DPU can obtain the latest host congestion signal.

[0035] (3) Fast forwarding of latency-sensitive flows based on flow classification mechanism: The DPU parses the data packet metadata at the ingress point and identifies the data flow type. For non-latency-sensitive flows, they are forwarded through subsequent steps (4)-(5); for latency-sensitive flows, they are forwarded directly to the egress port through the fast forwarding path. The ingress and egress ports are both network ports on the DPU.

[0036] (4) Calculate the hybrid congestion index based on the hybrid weighting mechanism: The DPU processing engine combines the host congestion signal obtained from the shared storage area with the load factor of the packet processing queue maintained locally by the DPU to calculate the hybrid congestion index that reflects the overall system pressure.

[0037] Furthermore, the hybrid congestion index is calculated based on a hybrid weighting mechanism, specifically including: the DPU first periodically calculates the load factor of the queue of at least one local processing core, and updates the short-term local congestion assessment value through the Exponential Weighted Moving Average (EWMA) algorithm; then it obtains the host congestion signal from the shared storage area, performs smoothing processing, and updates the long-term host congestion assessment value; finally, according to the preset weighting factor, the short-term local congestion assessment value and the long-term host congestion assessment value are weighted and summed to obtain a unified hybrid congestion index.

[0038] (5) Congestion mitigation and recovery based on differentiated strategies: The DPU performs differentiated operations on data flows of different directions based on the mixed congestion index: if it is inbound traffic to the host, a probabilistic packet loss strategy is executed; if it is outbound traffic to the network, an explicit congestion notification (ECN) marking strategy is executed.

[0039] Example 2: Host-side monitoring method like Figure 2 As shown, the host monitoring module (i.e., the host monitoring agent) performs a cyclic monitoring process on the host side, and its specific implementation process includes steps S201-S205.

[0040] S201, Read the performance counters of the host integrated I / O controller (IIO).

[0041] The host monitoring agent continuously reads the underlying hardware performance counters that characterize the PCIe interface and memory subsystem pressure. Specifically, it reads IIO-related performance counters, such as the Read Outstanding Completion Count (ROCC) counter, to characterize the pressure status related to PCIe read transactions.

[0042] S202. Calculate the instantaneous DMA pressure value and map it to a congestion level signal.

[0043] Calculate the instantaneous direct memory access pressure value based on the rate of change of the number of completed transactions. The calculation formula is as follows:

[0044] In the formula, Indicates the timestamp The performance counter value at that time, Indicates the timestamp The performance counter value at that time, Indicates the timestamp The performance counter value at that time, This indicates the frequency of the non-core interconnect clock.

[0045] Subsequently, the calculated continuous pressure value The signal is compared with a preset pressure threshold range, quantized and mapped to a predefined set of discrete congestion states, and a discrete congestion level signal is generated. The discrete congestion state set includes at least the following states: Idle, Warning, Hot, and Critical.

[0046] An example mapping relationship is as follows: When When, it is mapped to IDLE; when When, it is mapped to WARN; when When, it is mapped to HOT; when When, it is mapped to CRITICAL. Where, , , The preset pressure threshold parameter can be configured by those skilled in the art based on the actual hardware performance.

[0047] S203. Encapsulate the congestion level signal into a descriptor and write it to the storage area shared by the host and DPU.

[0048] Congestion level signal It is encapsulated as a descriptor and written directly to the shared storage area between the host and the DPU. It can be written through the shared memory channel, enabling the DPU to obtain the updated host congestion signal.

[0049] In some embodiments, the shared storage area may be a shared memory ring buffer.

[0050] In some embodiments, the DPU periodically reads host congestion signals in the shared memory region using a polling method. In other embodiments, event notification or interrupt triggering methods can also be used to read host congestion signals in the shared memory region. This avoids additional interrupt overhead to the host CPU, achieves low-latency synchronization of congestion information, reduces processing overhead caused by interrupt triggering, and lowers synchronization latency.

[0051] S204-S205, Execute the local back pressure protection mechanism.

[0052] The host monitoring agent estimates the effective memory bandwidth resources currently allocated to network traffic in real time and determines whether it is below the preset bandwidth guarantee threshold. If the effective memory bandwidth resources currently allocated to network traffic are below the preset bandwidth guarantee threshold, it indicates that the host memory bandwidth is severely insufficient, triggering the local flow control mechanism: limiting the memory access rate of non-network-intensive applications (i.e., non-critical services) on the host or adjusting their scheduling priority, thereby reserving PCIe bus and memory bandwidth resources for critical network services and achieving local backpressure protection. Critical network services refer to service flows that need to participate in external network communication through the network card and DMA; non-critical services involve large amounts of data transfer between the host CPU and memory, consuming memory bus bandwidth, but do not require background computing tasks or background network traffic through the network card.

[0053] Example 3: DPU-side congestion control logic like Figure 3 As shown, the DPU executes congestion control logic. The DPU processing engine receives data and performs congestion management. Its logic includes fast path diversion, hybrid congestion index calculation and differentiated strategy execution. Its specific implementation process includes steps S301-S309.

[0054] S301, Receive data packets and parse metadata.

[0055] After data packets from the external network enter the DPU, the parsing and classification module first extracts metadata such as header features of the data packets, including five-tuple information such as source IP address, destination IP address, source port, destination port, and protocol type.

[0056] S302. Classify and judge the received data stream, specifically based on the stream classification mechanism to determine whether it is a latency-sensitive stream.

[0057] When the DPU receives data packets, it matches the parsed metadata information of the data packets according to the static whitelist configuration or host application registration information. If a match is successful, the packet is determined to be a latency-sensitive flow, and step S303 is executed, forwarding it directly to the outgoing port via a fast forwarding path. If a match fails, the packet is determined to be a non-latency-sensitive flow, and steps S304-S309 are executed, distributing it to the software processing queue to participate in congestion control logic. The static whitelist can pre-configure traffic for specific protocols (such as DNS, ICMP) or specific ports as latency-sensitive flows; the host application registration information allows the application layer to dynamically register its traffic characteristics with the DPU.

[0058] S303, forwarded directly via the fast forwarding path.

[0059] If a flow is identified as latency-sensitive (such as heartbeat packets, control signals, or other critical flows), it bypasses the regular software queue and is delivered to the output port or host memory via a fast forwarding path (i.e., bypass forwarding). This effectively reduces queuing latency and the risk of packet loss, increasing the probability of prioritizing critical traffic. The fast forwarding path can be a hardware-based fast path and can optionally bypass the regular software processing queue.

[0060] S304, Store in the main queue or auxiliary overflow bucket.

[0061] For non-latency-sensitive flows, the data packets are sent to the queue management module for buffering and queuing. The packets are then written to the main queue or auxiliary overflow bucket maintained by the queue management module for buffering. The DPU processing engine maintains at least one main queue and auxiliary overflow bucket for each processing core. Therefore, in this embodiment, the DPU maintains a main queue for each processing core. and auxiliary overflow bucket When packets corresponding to a sudden surge of traffic arrive and the main queue is full, the packets are redirected to an auxiliary overflow bucket to absorb the surge. The load factor of the main queue is monitored in real time, and the injection process is only executed when the load factor is below the injection threshold, in which case the packets in the auxiliary overflow bucket are reinjected into the main queue. This mechanism can effectively absorb instantaneous surges in traffic and reduce packet loss.

[0062] S305. Combine local load and host congestion signals to calculate the mixed congestion index.

[0063] The congestion calculation module combines the short-term local queue pressure of the DPU (i.e., the load factor of the packet processing queue maintained locally by the DPU) and the long-term host pressure signal (i.e., the host congestion signal obtained from the shared storage area) to calculate a unified hybrid congestion index L. The specific calculation process is as follows: ① Calculate the short-time local congestion assessment value : First, periodically calculate the load factor of the local queue of the i-th processing core. :

[0064] In the formula, This represents the main queue corresponding to the i-th processing core. The number of data packets currently in the queue. This represents the main queue corresponding to the i-th processing core. Maximum capacity.

[0065] Then, the short-term local congestion assessment value is updated using an exponentially weighted moving average algorithm. :

[0066]

[0067] In the formula, This represents the current short-term local congestion assessment value of the i-th processing core. This represents the short-term local congestion assessment value of the i-th processing core in the previous (historical) period, which is a smoothing factor, and N is the total number of processing cores in the DPU.

[0068] ② Calculate the long-term host congestion assessment value : The DPU reads host congestion signals from the shared storage area, performs smoothing processing, and updates long-term host congestion assessment values. :

[0069] In the formula, This represents the cumulative long-term host congestion assessment value from the previous (historical) period. This is the host congestion signal (i.e., the host congestion level). This is a smoothing factor.

[0070] ③ Calculate the mixed congestion index L: Using preset weighting factors Short-term local congestion assessment value and long-term host congestion assessment value Weighted summation yields a unified mixed congestion index L:

[0071] In the formula, This reflects the sensitivity to local queue pressure.

[0072] S306. Determine the direction of the data flow.

[0073] Determine whether the currently queued data packets are inbound traffic destined for the host or outbound traffic from the host to an external network.

[0074] S307. For inbound traffic, probabilistic packet loss is performed based on the hybrid congestion index L.

[0075] For inbound traffic destined for the host, to prevent the host's memory subsystem from overloading, a probabilistic packet loss strategy based on the hybrid congestion index L is implemented, which can effectively reduce the risk of host memory subsystem overload. A minimum congestion threshold is set. and maximum congestion threshold Calculate the packet loss probability based on the following piecewise linear function. Perform random packet loss:

[0076] In the formula, The maximum packet loss probability is defined as follows: When the mixed congestion index L is between the two values, random packet loss is performed according to a linearly increasing packet loss probability function; when the mixed congestion index L exceeds the maximum congestion threshold... When the congestion index L is below the minimum congestion threshold, all non-delay-sensitive data packets are discarded with probability 1 to achieve rapid cessation of congestion. At that time, packet loss will not be handled.

[0077] S308. For outbound traffic, the ECN marking strategy is implemented based on the hybrid congestion index L.

[0078] If the traffic is outbound from the host to an external network, packet loss is not performed; instead, the marking probability is calculated. Marking probability With packet loss probability It is directly proportional, as shown in the following formula:

[0079] In the formula, It is an adjustable parameter with a value between [0,1], used to control the proportion of early, non-destructive congestion signals transmitted to the sender.

[0080] When the probability of hitting the mark (i.e. the marking condition is met) and the data packet supports ECN, the policy execution module performs marking in the ECN field of the data packet network layer header, marks the congestion bit, and feeds back the congestion signal to the network peer to trigger the peer's congestion control mechanism (such as reducing the TCP congestion window) to reduce the sending rate and achieve end-to-end congestion relief.

[0081] S309, Forward the remaining data packets normally.

[0082] The packets that are not dropped are processed by the policy enforcement module and then forwarded.

[0083] Example 4: DPU-based host congestion precision mitigation device like Figure 1 As shown, the device includes a host and a data processor (DPU) connected to it via a PCIe interface.

[0084] The host is equipped with a host monitoring agent, which reads hardware counter indicators representing the pressure of the PCIe interface and memory subsystem, calculates the instantaneous direct memory access pressure value and maps it into a discrete congestion level signal, and writes the congestion level signal into the storage area shared by the host and DPU.

[0085] The DPU comprises a parsing and classification module, a congestion calculation module, a queue management module, and a policy enforcement module. The parsing and classification module parses packet metadata and identifies data flow types, forwarding latency-sensitive flows directly via fast forwarding paths. The congestion calculation module obtains host congestion signals from the shared storage area and, combined with the load factor of the packet processing queues maintained locally by the DPU, calculates a mixed congestion index. The queue management module maintains the main queue and auxiliary overflow buckets for the processing core, providing local queue load information. The policy enforcement module, based on the mixed congestion index, executes probabilistic packet loss policies on inbound traffic destined for hosts and ECN marking policies on outbound traffic destined for the network.

[0086] Figure 1 In the diagram, solid lines represent data flow, and dashed lines represent control flow. The congestion level signal generated by the host monitoring module (i.e., the host monitoring agent) is transmitted to the congestion calculation module via the shared memory channel; the queue management module provides local queue load information; and the congestion calculation module outputs the hybrid congestion index L and issues control decisions to the policy execution module.

[0087] For inbound traffic, the parsing and classification module identifies the data packets: latency-sensitive traffic can bypass the queue management module via a fast forwarding path and be directly forwarded to the host side by the policy execution module; non-latency-sensitive traffic enters the queue management module buffer and is then processed and forwarded by the policy execution module according to the policy.

[0088] Example 5: Electronic Devices and Storage Media Based on the above method, embodiments of the present invention also provide an electronic device, such as... Figure 4 As shown, the electronic device includes a host device and a data processor (DPU). The host device includes a first processor and a first memory; the DPU is connected to the host device via a PCIe interface, and the DPU includes a second processor, a second memory, and a network interface. The first and second memories store one or more computer programs, which, when executed by the first and / or second processors, implement the DPU-based precise host congestion mitigation method described in the foregoing embodiments.

[0089] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a non-volatile computer-readable storage medium.

[0090] Furthermore, embodiments of the present invention also provide a computer-readable storage medium storing a program thereon. When executed by a corresponding processor, this program implements the DPU-based precise host congestion mitigation method described in the above embodiments. The computer-readable storage medium can be an internal storage unit of any data processing device as described in any of the foregoing embodiments, such as a hard disk or memory.

[0091] The computer-readable storage medium can also be any device with data processing capabilities, such as a plug-in hard drive, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units of any device with data processing capabilities and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the device with data processing capabilities, and can also be used to temporarily store data that has been output or will be output.

[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A host congestion precision mitigation method based on DPU, characterized in that, The application environment includes a host and a data processor (DPU) connected to it via a PCIe interface, and the method includes the following steps: (1) Acquisition and quantification of host-side congestion signals based on host monitoring agent: Run host monitoring agent on host side, read hardware counter indicators representing the pressure of PCIe interface and memory subsystem, calculate instantaneous direct memory access pressure value, and map pressure value into discrete congestion level signal; (2) Synchronization of congestion information between the host and the data processor based on the shared memory mechanism: The host monitoring agent writes the generated congestion level signal into the storage area shared by the host and the data processor so that the data processor can obtain the latest host congestion signal; (3) Fast forwarding of latency-sensitive flows based on flow classification mechanism: The data processor parses the data packet metadata at the entry point and identifies the data flow type. For non-latency-sensitive flows, forwarding is performed through steps (4)-(5); for latency-sensitive flows, forwarding is performed directly to the outgoing port through the fast forwarding path. (4) Calculate the hybrid congestion index based on the hybrid weighting mechanism: The data processor processing engine combines the host congestion signal obtained from the shared storage area with the load factor of the packet processing queue maintained locally by the data processor to calculate the hybrid congestion index that reflects the overall system pressure. The calculation of the hybrid congestion index based on the hybrid weighting mechanism specifically includes: The data processor first periodically calculates the load factor of the queue of at least one local processing core, and updates the short-term local congestion assessment value using an exponentially weighted moving average algorithm; then it obtains the host congestion signal from the shared storage area, performs smoothing processing, and updates the long-term host congestion assessment value; finally, it performs a weighted sum of the short-term local congestion assessment value and the long-term host congestion assessment value according to the preset weight factor to obtain the hybrid congestion index. (5) Congestion mitigation and recovery based on differentiated strategies: The data processor performs differentiated operations on data flows of different directions according to the mixed congestion index: if it is inbound traffic to the host, a probabilistic packet loss strategy is executed; if it is outbound traffic to the network, an explicit congestion notification marking strategy is executed. The congestion mitigation and recovery based on differentiated strategies specifically includes: For inbound traffic, a minimum congestion threshold and a maximum congestion threshold are set. When the mixed congestion index is between the two, random packet loss is performed according to a linearly increasing packet loss probability function. When the mixed congestion index exceeds the maximum congestion threshold, all non-latency-sensitive data packets are dropped. When the mixed congestion index is below the minimum congestion threshold, no packet loss is performed. For outbound traffic, a marking probability is calculated. The marking probability is proportional to the packet loss probability. When the marking probability is hit and the data packet supports displaying congestion notification, a congestion bit is marked in the network layer header of the data packet to notify the sender to reduce the sending rate without dropping the data packet.

2. The DPU-based host congestion mitigation method according to claim 1, characterized in that, The acquisition and quantization of the host-side congestion signal specifically includes: The host monitoring agent reads the performance counters of the host integrated I / O controller, which characterize the PCIe interface and memory subsystem pressure, to obtain the number of PCIe read transactions completed per unit time. It calculates the instantaneous direct memory access pressure value based on the rate of change of the number of read completed transactions and compares it with a preset pressure threshold range to quantize and map it to a predefined set of discrete congestion states, generating discrete congestion level signals.

3. The DPU-based host congestion precise mitigation method according to claim 1, characterized in that, Also includes: The host monitoring agent continuously executes the local backpressure protection mechanism in a loop: The host monitoring agent estimates the effective memory bandwidth resources currently allocated to network traffic in real time, and triggers a local flow control mechanism when the effective memory bandwidth resources are lower than the preset bandwidth guarantee threshold: limiting the memory access rate of non-network-intensive applications on the host or adjusting their scheduling priority, so as to reserve PCIe bus and memory bandwidth resources for network traffic.

4. The DPU-based host congestion mitigation method according to claim 1, characterized in that, The stream classification mechanism specifically includes: When a data processor receives a data packet, it matches the metadata information of the parsed data packet with the static whitelist configuration or the host application registration information. If the match is successful, it is determined to be a latency-sensitive flow; if the match fails, it is determined to be a non-latency-sensitive flow.

5. The DPU-based host congestion mitigation method according to claim 1, characterized in that, The data processor processing engine consists of at least one processing core that maintains a main queue and an auxiliary overflow bucket. When a data packet arrives and the main queue is full, the data packet is redirected to the auxiliary overflow bucket to absorb the burst traffic; the load factor of the main queue is monitored in real time, and the re-injection process is performed only when the load factor is lower than the re-injection threshold to reinsert the data packets in the auxiliary overflow bucket back into the main queue.

6. An apparatus for implementing the DPU-based host congestion precision mitigation method according to any one of claims 1-5, characterized in that, include: The host and its data processor (DPU) connected via a PCIe interface; The host is equipped with a host monitoring agent, which reads hardware counter indicators representing the pressure of the PCIe interface and memory subsystem, calculates the instantaneous direct memory access pressure value and maps it into a discrete congestion level signal, and writes the congestion level signal into the storage area shared by the host and the data processor. The data processor includes a parsing and classification module, a congestion calculation module, a queue management module, and a policy execution module. The parsing and classification module is used to parse data packet metadata and identify data flow types, and directly forward latency-sensitive flows through a fast forwarding path. The congestion calculation module is used to obtain host congestion signals from the shared storage area and, in conjunction with the load factor of the data packet processing queue maintained locally by the data processor, calculate a mixed congestion index. The queue management module is used to maintain the main queue and auxiliary overflow bucket for the processing core and provide local queue load information. The policy execution module is used to execute a probabilistic packet loss policy on inbound traffic destined for the host and an explicit congestion notification marking policy on outbound traffic destined for the network, based on the hybrid congestion index.

7. An electronic device, characterized in that, include: The host device includes a first processor and a first memory; The data processor (DPU) is connected to the host device via a PCIe interface and includes a second processor, a second memory, and a network interface. The first memory and the second memory store one or more programs, which, when executed by the first processor and the second processor, implement the DPU-based host congestion precision mitigation method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, It stores a program that, when executed by the corresponding processor, is used to implement the DPU-based host congestion precision mitigation method as described in any one of claims 1-5.

Images