Method of manufacturing a semiconductor memory device

Abstract

A method of manufacturing a semiconductor memory device includes: providing a substrate, wherein a plurality of active regions are defined by a device isolation film; forming word line trenches across the plurality of active regions and the device isolation film; forming a lower word line layer that fills a lower portion of the word line trenches; forming an upper word line layer that fills a portion of the word line trenches; performing an etching process that has high etch selectivity on the lower word line layer relative to the upper word line layer; and forming a buried insulating film that covers the lower word line layer and the upper word line layer and fills the word line trenches.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0004220, filed on January 10, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a method of manufacturing a semiconductor memory device, and more specifically, to a method of manufacturing a semiconductor memory device comprising multiple word lines. Background Technology

[0003] With the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. Correspondingly, the semiconductor memory devices used in these devices require high integration, thus compressing the design rules for their components. Consequently, defects in the manufacturing process of semiconductor memory devices are increasing, making it difficult to ensure their operational reliability. Summary of the Invention

[0004] One or more embodiments provide a method for manufacturing a semiconductor memory device with high integration and operational reliability.

[0005] According to one aspect of the embodiments, a method of manufacturing a semiconductor memory device includes: providing a substrate, wherein a plurality of active regions are defined by a device isolation film; forming a word line trench that spans the plurality of active regions and the device isolation film and extends along a first horizontal direction; forming a first preliminary conductive layer that fills at least a portion of the word line trench; performing a first etching process to remove an upper portion of the first preliminary conductive layer and form a lower word line layer that fills a lower portion of the word line trench; forming a second preliminary conductive layer that covers the lower word line layer and fills the word line trench; performing a second etching process to remove an upper portion of the second preliminary conductive layer and form an upper word line layer that fills a portion of the word line trench; performing a third etching process that has high etch selectivity for the lower word line layer relative to the upper word line layer; and forming a buried insulating film that covers the lower word line layer and the upper word line layer and fills the word line trench.

[0006] According to another aspect of the embodiments, a method of manufacturing a semiconductor memory device includes: providing a substrate, wherein a plurality of active regions are defined by a device isolation film; forming a plurality of word line trenches that extend parallel to each other along a first horizontal direction across the plurality of active regions and the device isolation film; forming a first preliminary conductive layer that fills at least a portion of each of the plurality of word line trenches; performing a first etching process to remove an upper portion of the first preliminary conductive layer and form a plurality of lower word line layers that fill the lower portions of the plurality of word line trenches, wherein the first etching process is an anisotropic etching process; forming a second preliminary conductive layer that covers the plurality of lower word line layers and fills the plurality of word line trenches; performing a second etching process to remove an upper portion of the second preliminary conductive layer and form a plurality of upper word line layers that fill portions of the plurality of word line trenches, wherein the second etching process is an anisotropic etching process; performing a third etching process that is an isotropic etching process and has high etch selectivity for the plurality of lower word line layers relative to the plurality of upper word line layers; and forming a plurality of buried insulating films that cover the plurality of lower word line layers and the plurality of upper word line layers and fill the plurality of word line trenches.

[0007] According to another aspect of the embodiments, a method of manufacturing a semiconductor memory device includes: providing a substrate, wherein a plurality of active regions are defined by a device isolation film; forming a plurality of word line trenches that extend parallel to each other across the plurality of active regions and the device isolation film in a first horizontal direction; forming a first preliminary conductive layer that fills at least a portion of each of the plurality of word line trenches; performing a first etching process to remove an upper portion of the first preliminary conductive layer and form a plurality of lower word line layers that fill the lower portions of the plurality of word line trenches, wherein the first etching process is an anisotropic etching process, and wherein at least one of the plurality of lower word line layers includes defects that protrude upwards more than other portions of the plurality of lower word line layers; forming a second preliminary conductive layer that covers the plurality of lower word line layers and fills the plurality of word line trenches; performing a second etching process to remove an upper portion of the second preliminary conductive layer and form a plurality of upper word line layers that fill portions of the plurality of word line trenches, wherein the second etching process is an anisotropic etching process, wherein the plurality of A defect in at least one of the lower word line layers protrudes upward beyond the top surface of a plurality of upper word line layers, wherein the plurality of lower word line layers and the plurality of upper word line layers constitute a plurality of word lines; a third etching process is performed, the third etching process being an isotropic etching process and having high etching selectivity for the plurality of lower word line layers relative to the plurality of upper word line layers, to form electrode recesses by removing at least a portion of the defect in the at least one of the plurality of lower word line layers; a plurality of buried insulating films are formed covering the plurality of lower word line layers and the plurality of upper word line layers and filling the plurality of word line trenches and electrode recesses; a plurality of bit lines extending along a second horizontal direction perpendicular to a first horizontal direction are formed on the plurality of word lines, and a plurality of direct contact conductive patterns connecting the plurality of bit lines to a plurality of active regions are formed; a plurality of buried contacts are formed filling the lower portion of the space between the plurality of bit lines and connecting to the plurality of active regions; a plurality of bonding pads are formed connecting to the plurality of buried contacts; and a plurality of capacitor structures are formed connecting to the plurality of bonding pads.

[0008] According to another aspect of the embodiments, a semiconductor memory device includes: a substrate, wherein a plurality of active regions are defined by a device isolation film; a word line trench, which spans the plurality of active regions and the device isolation film and extends along a first horizontal direction; word lines, which fill the lower portion of the word line trench and include a lower word line layer and an upper word line layer on the lower word line layer; a buried insulating film, which covers the word lines and fills the word line trench; and bit lines, which extend along the word lines in a second horizontal direction orthogonal to the first horizontal direction, wherein the word lines include electrode recesses, wherein the upper word line layer is divided into two portions by the electrode recesses to be spaced apart from each other in the first horizontal direction.

[0009] The buried insulating film may include an extended insulating portion that fills the electrode recess. The extended insulating portion may contact the lower letter line layer.

[0010] The lower word line layer may include a material containing metal atoms, and the upper word line layer may include a semiconductor material.

[0011] The word line may also include a conductive filler layer that fills the electrode recesses. The conductive filler layer may include a semiconductor material.

[0012] The lower letter line layer may include a protrusion that protrudes further toward the electrode recess than the rest of the lower letter line layer.

[0013] The electrode groove may include a first electrode groove and a second electrode groove, wherein the protrusion includes a first protrusion protruding toward the first electrode groove and a second protrusion protruding toward the second electrode groove, wherein the horizontal width of the uppermost end of the first electrode groove is greater than the horizontal width of the uppermost end of the second electrode groove, and the protrusion height of the second protrusion is lower than the protrusion height of the first protrusion.

[0014] The lower letter line layer may include a recessed portion having a recessed top surface at a portion corresponding to the electrode groove.

[0015] The buried insulating film can fill the electrode grooves and recesses. Attached Figure Description

[0016] The above and other aspects will become clearer from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 It is a block diagram used to describe a semiconductor memory device according to an embodiment;

[0018] Figure 2 It is a schematic plan view for describing the main components of a semiconductor memory device according to an embodiment;

[0019] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C and Figure 15D This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to an embodiment;

[0020] Figure 16A , Figure 16B , Figure 16C and Figure 16D It is a cross-sectional view used to describe a semiconductor memory device according to an embodiment;

[0021] Figure 17A , Figure 17B and Figure 17C This is a partially enlarged view of a semiconductor memory device according to an embodiment;

[0022] Figure 18A , Figure 18B , Figure 18C and Figure 18D This is a partially enlarged view of a semiconductor memory device according to an embodiment;

[0023] Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 21C and Figure 21D This is a cross-sectional view used to describe a method of manufacturing a semiconductor memory device according to an embodiment;

[0024] Figure 22A , Figure 22B , Figure 22C and Figure 22DThis shows a cross-sectional view of a semiconductor memory device according to an embodiment;

[0025] Figure 23A , Figure 23B and Figure 23C This is a partially enlarged view showing a semiconductor memory device according to an embodiment; and

[0026] Figure 24A , Figure 24B , Figure 24C and Figure 24D This is a partially enlarged view of a semiconductor memory device according to an embodiment. Detailed Implementation

[0027] In the following description, exemplary embodiments are illustrated with reference to the accompanying drawings. Throughout this specification, similar components are indicated by similar reference numerals, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, directly connected to, or coupled to that other element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers present. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with this disclosure.

[0028] Figure 1 This is a block diagram used to describe a semiconductor memory device according to an embodiment.

[0029] Reference Figure 1 The semiconductor memory device 1 may include a cell region CLR in which memory cells are disposed, and a main peripheral region PRR surrounding the cell region CLR.

[0030] According to an embodiment, the sub-peripheral region (SPR) of a separate cell block (SCB) may be included in a cell region (CLR). Multiple memory cells may be disposed within a cell block (SCB). As used herein, the term "cell block (SCB)" refers to a region where memory cells are arranged regularly at uniform intervals, and a cell block (SCB) may be referred to as a sub-cell block.

[0031] Logic units for inputting / outputting electrical signals to / from memory cells can be disposed in a main peripheral region (PRR) and a sub-peripheral region (SPR). In some embodiments, the main peripheral region (PRR) can be referred to as a peripheral circuit region, and the sub-peripheral region (SPR) can be referred to as a core circuit region. A peripheral region (PR) can include the main peripheral region (PRR) and the sub-peripheral region (SPR). That is, a peripheral region (PR) can be a core and peripheral circuit region that includes both a peripheral circuit region and a core circuit region. In some embodiments, at least a portion of the sub-peripheral region (SPR) can be used solely as space to separate cell blocks (SCBs) from each other.

[0032] Figure 2 It is a schematic plan view for describing the main components of a semiconductor memory device according to an embodiment.

[0033] Reference Figure 2 The semiconductor memory device 1 includes a memory cell region CR. The semiconductor memory device 1 may include multiple active regions ACT disposed within the memory cell region CR. The memory cell region CR may be provided with... Figure 1 The diagram shows a cell block SCB of multiple memory cells. Multiple active regions ACT disposed in the memory cell region CR may have a major axis along a diagonal direction relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction). In some embodiments, the multiple active regions ACT may be arranged in a column along the diagonal direction relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction), and may also be arranged in a column along the second horizontal direction (Y direction).

[0034] Multiple word lines (WL) can extend parallel to each other along a first horizontal direction (X direction) across multiple active regions (ACT) in the memory cell region (CR). In some embodiments, a pair of word lines (WL) can extend parallel to each other along the first horizontal direction (X direction) on an active region (ACT). Multiple bit lines (BL) can extend parallel to each other along the multiple word lines (WL) along a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). In some embodiments, a single bit line (BL) can extend along the second horizontal direction (Y direction) on an active region (ACT). The multiple bit lines (BL) can be connected to the multiple active regions (ACT) via multiple direct contacts (DC). The multiple direct contacts (DC) can be located at the intersections between the multiple bit lines (BL) and the multiple active regions (ACT).

[0035] In some embodiments, multiple buried contacts BC may be formed between two adjacent bit lines BL. In some embodiments, the multiple buried contacts BC may be arranged in a line along a first horizontal direction (X direction) and a second horizontal direction (Y direction). In some embodiments, a pair of buried contacts BC may be connected to an active region ACT. For example, a buried contact BC may be connected to each of the two ends of an active region ACT.

[0036] Multiple bonding pads LP can be formed on multiple buried contacts BC. The multiple bonding pads LP may at least partially overlap with the multiple buried contacts BC. In some embodiments, the multiple bonding pads LP may extend above one of two adjacent bit lines BL.

[0037] Multiple memory nodes (SNs) can be formed on multiple bonding pads (LPs). Multiple memory nodes (SNs) can be formed above multiple bit lines (BLs). Multiple memory nodes (SNs) can each be the lower electrode of multiple capacitors. The memory nodes (SNs) can be connected to the active region (ACT) via bonding pads (LPs) and buried contacts (BCs).

[0038] Figures 3A to 3D , Figures 4A to 4D , Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D , Figures 8A to 8D , Figures 9A to 9D , Figures 10A to 10D , Figures 11A to 11D , Figures 12A to 12D , Figures 13A to 13D , Figures 14A to 14D and Figures 15A to 15D This is a cross-sectional view used to describe a method for manufacturing a semiconductor device according to an embodiment. Figures 16A to 16D This is a cross-sectional view used to describe a semiconductor memory device according to an embodiment. Specifically, Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A It is along Figure 2 A cross-sectional view taken from line A-A'. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B, Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B It is along Figure 2 A cross-sectional view taken from line B-B'. Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C and Figure 16C It is along Figure 2 The cross-sectional view taken by line C-C', and Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D and Figure 16D It is along Figure 2 The cross-sectional view taken by line D-D'.

[0039] Reference Figures 3A to 3D Device isolation trenches 116T can be formed in the substrate 110, and a device isolation film 116 filling the device isolation trenches 116T can be formed. In the memory cell region CR, multiple active regions 118 can be defined in the substrate 110 by the device isolation trenches 116T and the device isolation film 116.

[0040] Substrate 110 may include, for example, silicon (Si), crystalline Si, polycrystalline Si, or amorphous Si. In some embodiments, substrate 110 may include a semiconductor element such as germanium (Ge), or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, substrate 110 may have a silicon-on-insulator (SOI) structure. For example, substrate 110 may include a buried oxide layer (BOX). Substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures. Device isolation film 116 may be formed of a material including at least one of silicon oxide, silicon nitride, and silicon oxynitride. Device isolation film 116 may have a single-layer structure including one insulating film, a double-layer structure including two insulating films, or a multilayer structure including at least three insulating films. For example, device isolation film 116 may have a double-layer structure including an oxide film and a nitride film, or a multilayer structure. However, the configuration of device isolation film 116 is not limited thereto.

[0041] Active zone 118 can be like Figure 2 Like the active region ACT in the diagram, it has a minor axis and a major axis in the plan view, and can have a relatively long island shape extending along the direction of the major axis. Multiple active regions 118 can be arranged in columns along diagonal directions relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction), and can also be arranged in columns along the second horizontal direction (Y direction).

[0042] Reference Figures 4A to 4D A plurality of word line trenches 120T are formed in the substrate 110 by removing a portion of the active region 118 and a portion of the device isolation film 116. The plurality of word line trenches 120T may extend parallel to each other in a first horizontal direction (X direction), and each word line trench 120T may have a linear shape spanning the active region 118 and be arranged at substantially equal intervals along a second horizontal direction (Y direction). In some embodiments, a stepped portion may be formed on the bottom surface of each of the plurality of word line trenches 120T.

[0043] Next, a dielectric material layer 122P is formed covering the inner surfaces of the plurality of word line trenches 120T. The dielectric material layer 122P may be conformally formed on the surfaces of the substrate 110 exposed to the bottom and side surfaces of the plurality of word line trenches 120T. The dielectric material layer 122P may be formed of at least one material selected from silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and high-k dielectric materials with a dielectric constant higher than that of silicon oxide. For example, the dielectric material layer 122P may have a dielectric constant of about 10 to 25. For example, high-k dielectric materials can be formed from at least one material selected from the following: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxysilane (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0044] Reference Figures 5A to 5D A first preliminary conductive layer 120aP is formed to fill at least a portion of each of the plurality of word line trenches 120T. The first preliminary conductive layer 120aP can be formed using a deposition process such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD). The first preliminary conductive layer 120aP may include a material containing metal atoms. For example, the first preliminary conductive layer 120aP may be formed of a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the first preliminary conductive layer 120aP may be formed of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, Mo, or a combination thereof.

[0045] The first preliminary conductive layer 120aP may include defects PT. Defects PT may be formed due to particles or abnormal growth occurring during the process of forming the first preliminary conductive layer 120aP. Defects PT may protrude upwards more in the vertical direction (Z-direction) than other portions of the first preliminary conductive layer 120aP. Although in Figures 5B to 5DIn this embodiment, the top surface of the first preliminary conductive layer 120aP, excluding the defect PT, is at the same vertical height as the top surface of the substrate 110. However, this is merely an example, and the embodiments are not limited thereto. In some embodiments, the first preliminary conductive layer 120aP may cover the top surface of the substrate 110. For example, the top surface of the first preliminary conductive layer 120aP, excluding the defect PT, may be at a higher vertical height than the top surface of the substrate 110.

[0046] Reference Figures 5A to 5D and Figures 6A to 6D The upper portion of the first preliminary conductive layer 120aP is removed to form a plurality of lower word line layers 120a filling the lower portion of the plurality of word line trenches 120T. The plurality of lower word line layers 120a can be formed by performing an anisotropic dry etching process to remove the upper portion of the first preliminary conductive layer 120aP. This process has high etching selectivity for the first preliminary conductive layer 120aP relative to the substrate 110. The anisotropic dry etching process for removing the upper portion of the first preliminary conductive layer 120aP to form the plurality of lower word line layers 120a can be referred to as a first etching process, a first dry etching process, a first anisotropic etching process, or a first anisotropic dry etching process.

[0047] At least some of the plurality of lower word line layers 120a may include a defect PTa. The defect PTa may be formed during a process of removing the upper portion of the first preliminary conductive layer 120aP when a defect PT included in the first preliminary conductive layer 120aP is transferred. The defect PTa may protrude more upward in the vertical direction (Z direction) than other portions of the lower word line layer 120a. Each of the plurality of lower word line layers 120a may be formed of a material containing metal atoms. For example, each of the plurality of lower word line layers 120a may be formed of a metal, a conductive metal nitride, or a combination thereof. In some embodiments, each of the plurality of lower word line layers 120a may be formed of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof.

[0048] Reference Figures 7A to 7DA second preliminary conductive layer 120bP is formed, covering multiple lower word line layers 120a and filling multiple word line trenches 120T. The second preliminary conductive layer 120bP can be formed using a deposition process such as CVD, PECVD, or ALD. The second preliminary conductive layer 120bP may include a semiconductor material. For example, the second preliminary conductive layer 120bP may be formed from doped polysilicon. The second preliminary conductive layer 120bP may cover defects PTa included in the multiple lower word line layers 120a. In some embodiments, the second preliminary conductive layer 120bP may fill all word line trenches in the multiple word line trenches 120T and may cover the top surface of the substrate 110. The second preliminary conductive layer 120bP may have a flat upper surface. Along the vertical direction (Z direction), the second preliminary conductive layer 120bP may be thinner at the portion overlapping with the defects PTa.

[0049] Reference Figures 7A to 7D and Figures 8A to 8D The upper portion of the second preliminary conductive layer 120bP is removed to form multiple upper word line layers 120b on multiple lower word line layers 120a, and portions of the multiple word line trenches 120T are filled. The multiple lower word line layers 120a and multiple upper word line layers 120b can constitute multiple word lines 120. The multiple word lines 120 can constitute... Figure 2Multiple word lines 120 are present. For example, each of the multiple word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. The multiple word lines 120, each having a stacked structure including a lower word line layer 120a and an upper word line layer 120b, may extend parallel to each other along a first horizontal direction (X direction). The multiple word lines 120 may extend parallel to each other along the first horizontal direction (X direction), and each word line may have a line shape that crosses the source region 118 and is configured to have substantially equal spacing along a second horizontal direction (Y direction). The top surface of each word line 120 may be at a lower height than the top surface of the substrate 110. The bottom surface of the multiple word lines 120 may have an uneven shape and may form saddle-fin transistors (FinFETs) in the multiple active regions 118. Multiple upper word line layers 120b can be formed by removing the upper portion of the second preliminary conductive layer 120bP through an anisotropic dry etching process. Each upper word line layer 120b may include a semiconductor material. For example, each upper word line layer 120b may be formed of doped polysilicon. The multiple upper word line layers 120b can be formed by removing the upper portion of the second preliminary conductive layer 120bP through an anisotropic dry etching process that has high etch selectivity for the second preliminary conductive layer 120bP relative to the lower word line layer 120a. The anisotropic dry etching process for removing the upper portion of the second preliminary conductive layer 120bP to form the multiple upper word line layers 120b may be referred to as a second etching process, a second dry etching process, a second anisotropic etching process, or a second anisotropic dry etching process.

[0050] Source and drain regions can be formed in the plurality of active regions 118 by implanting impurity ions into portions of the active regions 118 on both sides of the plurality of word lines 120. In some embodiments, impurity ions can be implanted into portions of the active regions before the plurality of word lines 120 are formed. In some embodiments, impurity ions can be implanted into portions of the active regions after the plurality of word lines 120 are formed.

[0051] In the process of forming multiple upper word line layers 120b, the defect PTa included in the multiple lower word line layers 120a may not need to be removed. For example, the defect PTa may include the same material as the multiple lower word line layers 120a. Because the anisotropic dry etching process has high etching selectivity for the second preliminary conductive layer 120bP relative to the lower word line layers 120a, the defect PTa may not be removed by the anisotropic dry etching process. Therefore, in the process of removing the upper part of the second preliminary conductive layer 120bP to form multiple upper word line layers 120b, the defect PTa included in the multiple lower word line layers 120a may be exposed. For example, the defect PTa may protrude more upward in the vertical direction (Z direction) than the top surface of the multiple upper word line layers 120b. Some of the upper word line layers 120b may be separated by the defect PTa while extending along the first horizontal direction (X direction). For example, some of the multiple upper word line layers 120b may be split into two parts by a defect PTa, thus being spaced apart from each other in the first horizontal direction (X direction).

[0052] In some embodiments, during the process of forming multiple word lines 120, a portion of the dielectric material layer 122P may be removed to form multiple gate dielectric films 122. The multiple gate dielectric films 122 may be disposed between the multiple word lines 120 and the substrate 110. In some embodiments, during each of the processes of forming multiple lower word line layers 120a and forming multiple upper word line layers 120b, a portion of the dielectric material layer 122P may be removed to form multiple gate dielectric films 122. The multiple gate dielectric films 122 may conformally cover at least a portion of the surfaces of the substrate 110 located on the bottom and side surfaces of the multiple word line trenches 120T. In some embodiments, the uppermost ends of the multiple gate dielectric films 122 may be at the same vertical height as the top surfaces of the multiple upper word line layers 120b, but the embodiments are not limited thereto. For example, the uppermost ends of the multiple gate dielectric films 122 may be at a vertical height higher than the top surfaces of the multiple upper word line layers 120b. Each of the plurality of gate dielectric films 122 may be formed of at least one selected from silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k dielectric material with a dielectric constant higher than that of silicon oxide. For example, each of the plurality of gate dielectric films 122 may have a dielectric constant of about 10 to 25. For example, high-k dielectric materials can be formed from at least one material selected from the following: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxysilane (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0053] Reference Figures 8A to 8D and Figures 9A to 9DAt least a portion of the defective PTA included in the plurality of lower word line layers 120a is removed. The defective PTA included in the plurality of lower word line layers 120a can be removed by performing an isotropic wet etching process. For example, the defective PTA included in the plurality of lower word line layers 120a can be removed by performing a wet etching process using an etchant including sulfuric acid. At least a portion of the defective PTA included in the plurality of lower word line layers 120a can be removed by performing an isotropic etching process that has high etching selectivity for the lower word line layers 120a relative to the upper word line layer 120b. The isotropic wet etching process for removing at least a portion of the defective PTA included in the plurality of lower word line layers 120a can be referred to as a third etching process, a wet etching process, or an isotropic etching process.

[0054] At least some of the word lines 120 may include electrode recesses 120RS, which are spaces in which at least a portion of the defect PTa included in the plurality of lower word line layers 120a has been removed. The electrode recesses 120RS may be referred to as defect removal spaces. In some embodiments, a portion of the defect PTa included in the plurality of lower word line layers 120 may not be removed but retained as a protruding PTR. For example, at least some of the lower word line layers 120a may include a protruding PTR. The protruding PTR may protrude more toward the electrode recesses 120RS in the vertical direction (Z direction) than other portions of the lower word line layers 120a.

[0055] Some of the multiple top word line layers 120b can be separated by electrode recesses 120RS while extending along a first horizontal direction (X direction). For example, some of the multiple top word line layers 120b can be divided into two parts by electrode recesses 120RS, thereby being spaced apart from each other in the first horizontal direction (X direction). For example, along the first horizontal direction (X direction), a protrusion PTR can overlap with the multiple top word line layers 120b.

[0056] Reference Figures 10A to 10D A plurality of buried insulating films 124 are formed, covering multiple word lines 120 and filling multiple word line trenches 120T. The plurality of buried insulating films 124 may extend parallel to each other along a first horizontal direction (X direction) on the multiple word lines 120. A plurality of gate dielectric films 122, multiple word lines 120, and a plurality of buried insulating films 124 may fill all word line trenches 120T. The buried insulating films 124 may be formed of at least one material selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0057] In some embodiments, the upper portion of the device isolation film 116 may be removed during the process of forming a plurality of gate dielectric films 122, a plurality of word lines 120, and a plurality of buried insulating films 124. The top surface of the substrate 110, the top surface of the device isolation film 116, and the top surfaces of the plurality of buried insulating films 124 may be at substantially the same vertical height to form a coplanar structure.

[0058] At least some of the buried insulating films 124 may include extended insulating portions 124F that fill electrode recesses 120RS included in at least some of the word lines 120 and extend into the word lines 120. The extended insulating portions 124F may contact the lower word line layer 120a. Along the vertical direction (Z direction), the buried insulating films 124 may be thicker at portions overlapping with protruding PTRs. In some embodiments, the extended insulating portions 124F may contact the protruding PTRs included in the lower word line layer 120a. Some of the upper word line layers 120b may extend along a first horizontal direction (X direction) and may be spaced apart from each other, with the extended insulating portions 124F located therebetween. For example, some of the upper word line layers 120b may be divided into two parts by the extended insulating portions 124F and may be spaced apart from each other in the first horizontal direction (X direction).

[0059] Reference Figures 11A to 11D An insulating structure 113 is formed, comprising a covering device isolation film 116, multiple active regions 118, and multiple buried insulating films 124. For example, the insulating structure 113 may be formed from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal-based dielectric film, or a combination thereof. In some embodiments, the insulating structure 113 may be formed by stacking multiple insulating films, including a first insulating film pattern 112 and a second insulating film pattern 114. In some embodiments, the first insulating film pattern 112 may be formed from a silicon oxide film, and the second insulating film pattern 114 may be formed from a silicon oxynitride film. In some embodiments, the first insulating film pattern 112 may be formed from a non-metallic dielectric film, and the second insulating film pattern 114 may be formed from a metallic dielectric film.

[0060] Next, after forming a conductive semiconductor layer 132P on the insulating structure 113, a direct contact hole 134H is formed through the conductive semiconductor layer 132P and the insulating structure 113 to expose the source region in the active region 118, and a direct contact conductive layer 134P is formed to fill the direct contact hole 134H. In some embodiments, the direct contact hole 134H may extend to the active region 118, i.e., the source region. The conductive semiconductor layer 132P may be formed of, for example, doped polysilicon. In some embodiments, the conductive semiconductor layer 132P and the direct contact conductive layer 134P may be formed of the same type of material. For example, the direct contact conductive layer 134P may be formed of doped polysilicon. In some embodiments, the conductive semiconductor layer 132P and the direct contact conductive layer 134P may be formed of different types of materials. For example, the direct contact conductive layer 134P may be formed of an epitaxial silicon layer, a metal, or a metal compound as a conductive material. In some embodiments, the direct contact conductive layer 134P may be formed of a metal (such as Ti or W) or a conductive material (which is a compound comprising a metal such as Ti or W and a nonmetal such as Si, C, B or N). For example, the direct contact conductive layer 134P may be formed of TiN, WC or WSi.

[0061] when Figure 8B and Figure 8D When the defective PTa remains and is not removed, at least some of the direct contact conductive layers 134P may come into contact with the defective PTa, and therefore, a short circuit may occur whereby the multiple direct contact conductive layers 134P are electrically connected to the multiple word lines 120. However, since the extended insulating portion 124F fills the electrode recess 120RS where the defective PTa has been removed, the multiple direct contact conductive layers 134P and the multiple word lines 120 may not come into contact with each other, but may be spaced apart from each other.

[0062] Reference Figures 11A to 11D and Figures 12A to 12D A metal-based conductive layer and an insulating capping layer are sequentially formed, covering a conductive semiconductor layer 132P and a direct contact conductive layer 134P, and used to form a bit line structure 140. In some embodiments, the metal-based conductive layer may have a stacked structure including a first metal-based conductive layer and a second metal-based conductive layer. By etching the first metal-based conductive layer, the second metal-based conductive layer, and the insulating capping layer, a plurality of bit lines 147 and a plurality of insulating capping lines 148 covering the plurality of bit lines 147 are formed, each bit line having a stacked structure including a linear first metal-based conductive pattern 145 and a second metal-based conductive pattern 146.

[0063] In some embodiments, the first metal-based conductive pattern 145 may be formed of titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based conductive pattern 146 may be formed of tungsten (W) or tungsten and tungsten silicide (WSix). In some embodiments, the first metal-based conductive pattern 145 may serve as a diffusion barrier layer. In some embodiments, multiple insulating capping lines 148 may be formed of a silicon nitride film.

[0064] A bit line 147 and an insulating capping line 148 covering the bit line 147 can constitute a bit line structure 140. Multiple bit line structures 140, each including a bit line 147 and an insulating capping line 148 covering the bit line 147, can extend parallel to each other along a second horizontal direction (Y direction) parallel to the main surface of the substrate 110. Multiple bit lines 147 can constitute... Figure 2 Multiple bit lines BL in the structure. In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132, which is part of a conductive semiconductor layer 132P disposed between the insulating structure 113 and the first metal base conductive pattern 145.

[0065] In the etching process used to form multiple bit lines 147, a plurality of conductive semiconductor patterns 132 and a plurality of direct contact conductive patterns 134 can be formed by simultaneously removing a portion of the conductive semiconductor layer 132P and a portion of the direct contact conductive layer 134P (which does not overlap with the bit lines 147 in the vertical direction) using the etching process. In this case, the insulating structure 113 can be used as an etching stop film in the etching process for forming multiple bit lines 147, multiple conductive semiconductor patterns 132, and multiple direct contact conductive patterns 134. The multiple direct contact conductive patterns 134 can constitute Figure 2 Multiple direct contact portions DC are present in the circuit. Multiple bit lines 147 can be electrically connected to multiple active regions 118 via multiple direct contact conductive patterns 134. The conductive semiconductor pattern 132 can be formed, for example, by doped polysilicon. The direct contact conductive pattern 134 can be formed by doped polysilicon, metal, or a metal compound as a conductive material. For example, the direct contact conductive pattern 134 can be formed by a metal (such as Ti or W) or a conductive material (which is a compound comprising metals such as Ti or W and nonmetals such as Si, C, B, or N). In some embodiments, the direct contact conductive pattern 134 can be formed by TiN, WC, or WSi.

[0066] when Figure 8B and Figure 8DWhen the defective PTa remains and is not removed, at least some of the direct contact conductive patterns 134 may come into contact with the defective PTa, and therefore, a short circuit may occur whereby the direct contact conductive patterns 134 are electrically connected to the multiple word lines 120. However, since the extended insulating portion 124F fills the electrode recess 120RS where the defective PTa has been removed, the direct contact conductive patterns 134 and the multiple word lines 120 can be spaced apart from each other and not come into contact with each other.

[0067] The insulating spacer structure 150 may cover two sidewalls of each of the plurality of bit line structures 140. Each insulating spacer structure of the plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may be formed of a material with a dielectric constant lower than that of the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may be formed of a nitride film, and the second insulating spacer 154 may be formed of an oxide film. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may be formed of a nitride film, and the second insulating spacer 154 may be formed of a material having etch selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when each of the first insulating spacer 152 and the third insulating spacer 156 is formed of a nitride film, the second insulating spacer 154 may be formed of an oxide film, but may be removed in a subsequent process to form an air spacer.

[0068] Multiple buried contact holes 170H can be formed between multiple bit lines 147. The internal space of each buried contact hole 170H can be defined by an active region 118 and an insulating spacer structure 150, which covers the sidewall of each of two adjacent bit lines 147 between the two adjacent bit lines 147.

[0069] Multiple buried contact holes 170H can be formed by using multiple insulating capping lines 148 and insulating spacer structures 150 covering the two sidewalls of each bit line structure in the multiple bit line structures 140 as an etching mask to remove portions of the active region 118 and the insulating structure 113. In some embodiments, the multiple buried contact holes 170H can be formed by first performing an anisotropic etching process to remove a portion of the active region 118 and the insulating structure 113 using multiple insulating capping lines 148 and insulating spacer structures 150 covering the two sidewalls of each bit line structure in the multiple bit line structures 140 as an etching mask, and then performing an isotropic etching process to further remove another portion of the active region 118 to expand the space defined by the active region 118.

[0070] Reference Figures 13A to 13D Multiple buried contacts 170 and multiple insulating barriers 180 are formed in the space between multiple insulating spacer structures 150 covering two sidewalls of multiple bit line structures 140. The multiple buried contacts 170 and multiple insulating barriers 180 can be alternately arranged between a pair of insulating spacer structures 150 facing each other, i.e., along a second horizontal direction (Y direction), within the multiple insulating spacer structures 150 covering two sidewalls of multiple bit line structures 140. For example, the multiple buried contacts 170 can be formed of polysilicon. For example, the multiple insulating barriers 180 can be formed of a nitride film.

[0071] In some embodiments, a plurality of buried contacts 170 may be arranged in a line along a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plurality of buried contacts 170 may extend from the active region 118 along a vertical direction (Z direction) perpendicular to the substrate 110. The plurality of buried contacts 170 may constitute Figure 2 Multiple buried contact points BC.

[0072] Multiple buried contacts 170 can be disposed in a space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 covering the two sidewalls of multiple bit line structures 140. The multiple buried contacts 170 can fill the lower part of the space between the multiple insulating spacer structures 150 covering the two sidewalls of the multiple bit line structures 140.

[0073] The height of the top surface of the multiple buried contact portions 170 may be lower than the height of the top surface of each of the multiple insulating cover lines 148. The top surface of each of the multiple insulating fences 180 and the top surface of each of the multiple insulating cover lines 148 may be at the same height in the vertical direction (Z direction).

[0074] Multiple insulating spacer structures 150 and multiple insulating barriers 180 may define multiple bonding pad holes 190H. Multiple buried contacts 170 may be exposed on the bottom surface of the multiple bonding pad holes 190H.

[0075] In the process of forming multiple buried contacts 170 and / or multiple insulating fences 180, the upper part of the insulating spacer structure 150 and the insulating cover line 148 included in the bit line structure 140 can be removed, and thus the height of the top surface of the bit line structure 140 can be reduced.

[0076] Reference Figures 14A to 14D A bonding pad material layer is formed that fills multiple bonding pad holes 190H and covers multiple bit line structures 140. In some embodiments, the bonding pad material layer may be formed of a conductive barrier film and a conductive pad material layer on the conductive barrier film. For example, the conductive barrier film may be formed of a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier film may have a stacked structure including Ti / TiN. In some embodiments, the conductive pad material layer may include tungsten (W).

[0077] In some embodiments, a metal silicide film may be formed on the plurality of buried contacts 170 before forming the bonding pad material layer. The metal silicide film may be disposed between the plurality of buried contacts 170 and the bonding pad material layer. The metal silicide film may be made of cobalt silicide (CoSi). x Nickel silicide (NiSi) x ) or manganese silicide (MnSi) x (This can be formed, but is not limited to)

[0078] Next, a portion of the bonding pad material layer is removed, and a plurality of bonding pads 190 are formed. The plurality of bonding pads 190 at least fill a portion of a plurality of bonding pad holes 190H, extend onto a plurality of bit line structures 140, and are divided into a plurality of portions by groove portions 190R.

[0079] Multiple bonding pads 190 may be spaced apart from each other, with recesses 190R located therebetween. Multiple bonding pads 190 may be disposed on multiple buried contacts 170 and may extend onto multiple bit line structures 140. In some embodiments, multiple bonding pads 190 may extend onto multiple bit lines 147. Multiple bonding pads 190 may be disposed on multiple buried contacts 170, and corresponding buried contacts 170 and bonding pads 190 may be electrically connected to each other. Corresponding buried contacts 170 and bonding pads 190 may be collectively referred to as contact plugs. Multiple bonding pads 190 may be connected to an active region 118 through multiple buried contacts 170. Multiple bonding pads 190 may constitute... Figure 2 Multiple bonding pads LP in the middle.

[0080] The buried contact 170 may be disposed between two adjacent bit line structures 140, and one of the plurality of bonding pads 190 may extend from between two adjacent bit line structures 140 onto one bit line structure 140, with the buried contact 170 located between the two bit line structures 140.

[0081] Reference Figures 15A to 15D A filling insulating layer 195 can be formed to fill the recessed portion 190R. In some embodiments, the filling insulating layer 195 may have a stacked structure including an oxide film and a nitride film. Although in Figure 15A and Figure 15C The top surface of the insulating layer 195 is at the same height as the top surface of the bonding pad 190, but the embodiment is not limited to this.

[0082] Reference Figures 16A to 16D An etch stop layer 206 is formed, covering multiple bonding pads 190 and a filling insulating layer 195. For example, the etch stop layer 206 may include SiN, SiBN, SiCN, SiC, SiON, SiCO, SiCON, SiBC, SiBON, SiBCO, SiBCN, or SiBCON. Multiple lower electrodes 210, a capacitor dielectric layer 220, and an upper electrode 230 are sequentially formed, extending upward in the vertical direction (Z direction) through the etch stop layer 206 to contact the multiple bonding pads 190, and multiple capacitor structures 200 formed by the multiple lower electrodes 210, capacitor dielectric layers 220, and upper electrodes 230 are formed to form a semiconductor memory device 1.

[0083] For example, after forming a molding layer on the etch stop layer 206 and then forming a plurality of molded vias through the molding layer and exposing the etch stop layer 206 on the bottom surface, at least a portion of each of the plurality of bonding pads 190 can be exposed by removing a portion of the etch stop layer 206 exposed on the bottom surface of the plurality of molded vias. Next, after forming a plurality of lower electrodes 210 filling the plurality of molded vias, the molding layer can be removed. The plurality of lower electrodes 210 can constitute... Figure 2Multiple storage nodes SN are present. Multiple lower electrodes 210 can be electrically connected to multiple bonding pads 190, respectively. Each of the multiple lower electrodes 210 can be columnar, its interior filled to have a circular horizontal cross-section, but embodiments are not limited thereto. In some embodiments, each of the multiple lower electrodes 210 can be a cylinder with a closed bottom. In some embodiments, the multiple lower electrodes 210 can be arranged in a honeycomb pattern in a zigzag manner along a first horizontal direction (X direction) or a second horizontal direction (Y direction). In some embodiments, the multiple lower electrodes 210 can be arranged in a matrix along each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). For example, the multiple lower electrodes 210 can be formed of silicon doped with impurities, a metal (such as tungsten or copper), or a conductive metal compound (such as titanium nitride). In some embodiments, the multiple lower electrodes 210 can include titanium nitride. In some embodiments, at least one support pattern can also be formed in contact with the sidewalls of the multiple lower electrodes 210. For example, multiple support patterns can also be formed in contact with the sidewalls of the multiple lower electrodes 210 and located at different vertical heights.

[0084] The capacitor dielectric layer 220 can be formed to conformally cover the surfaces of the plurality of lower electrodes 210. The upper electrode 230 can be formed to cover the plurality of lower electrodes 210, and the capacitor dielectric layer 220 is located between the upper electrode and the lower electrodes.

[0085] For example, the capacitor dielectric layer 220 can have approximately 40 To approximately 70 The thickness can cover the surface of multiple lower electrodes 210. The capacitor dielectric layer 220 can be formed of, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT ((Pb,Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0086] The upper electrode 230 may be formed of, for example, semiconductor materials (such as doped polycrystalline silicon or doped polycrystalline silicon germanium (SiGe)), metal-based materials (such as W, Ru, Pt, Ir, V, Mo, Ta, Nb, In, TiN, VN, MoN, TaN, NbN, InN, RuO, PtO, IrO, TiO, VO, MoO, TaO, NbO, InO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, or La(Sr,Co)O), or combinations thereof. In some embodiments, the upper electrode 230 may include a metal material (such as W or Ru). In some embodiments, the upper electrode 230 may have a stacked structure comprising semiconductor materials and metal-based materials. For example, the upper electrode 230 may have a stacked structure comprising at least two layers, the at least two layers comprising a metal-based material and a semiconductor material covering the metal-based material, or it may have a stacked structure comprising at least three layers, the at least three layers comprising a semiconductor material, a metal-based material covering the semiconductor material, and a semiconductor material covering the metal-based material.

[0087] Semiconductor memory device 1 includes: a substrate 110 including a plurality of active regions 118; a plurality of gate dielectric films 122; a plurality of word lines 120; and a plurality of buried insulating films 124 sequentially formed in the substrate 110 within a plurality of word line trenches 120T spanning the plurality of active regions 118; an insulating structure 113 covering a device isolation film 116, the plurality of active regions 118, and the plurality of buried insulating films 124; a plurality of bit line structures 140 on the insulating structure 113; a plurality of insulating spacer structures 150 covering two sidewalls of the plurality of bit line structures 140; and a plurality of buried contacts 170. The lower portion of the space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 is filled and connected to multiple active regions 118; multiple bonding pads 190 fill the upper portion of the space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 and extend to the upper portion of the bit line structure 140; an etch stop layer 206 is disposed on the multiple bonding pads 190; and multiple capacitor structures 200 include multiple lower electrodes 210, capacitor dielectric layers 220 and upper electrodes 230 passing through the etch stop layer 206 and connected to the multiple bonding pads 190.

[0088] Figures 17A to 17C This is a partially enlarged view showing a semiconductor memory device according to an embodiment. Specifically, Figures 17A to 17C Each showed Figure 16B An enlarged cross-sectional view of part EX1.

[0089] Reference Figures 16A to 16D and Figure 17AEach of the plurality of word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may have electrode recesses 120RS. At least some of the upper word line layers 120b may be divided into two parts by the electrode recesses 120RS and may be spaced apart from each other in a first horizontal direction (X direction). A plurality of buried insulating films 124 may be located on the plurality of word lines 120 and may cover the plurality of word lines 120. At least some of the lower word line layers 120a may include protrusions PTR at portions corresponding to the electrode recesses 120RS. The protrusions PTR may protrude more toward the electrode recesses 120RS in the vertical direction (Z direction) than other portions of the lower word line layers 120a.

[0090] At least some of the buried insulating films 124 may include extended insulating portions 124F that fill electrode recesses 120RS included in at least some of the word lines 120 and extend into the word lines 120. The extended insulating portions 124F may contact the lower word line layer 120a. In some embodiments, the extended insulating portions 124F may contact protrusions PTR included in the lower word line layer 120a. Some of the upper word line layers 120b may extend along a first horizontal direction (X direction) and may be spaced apart from each other, with the extended insulating portions 124F located therebetween. For example, some of the upper word line layers 120b may be divided into two parts by the extended insulating portions 124F and may be spaced apart in the first horizontal direction (X direction). Because the extended insulating portions 124F fill the electrode recesses 120RS, the plurality of directly contacting conductive patterns 134 and at least some of the word lines 120 may be spaced apart from each other without contacting each other. At the portion corresponding to the protruding PTR, a plurality of insulating films 124 may extend between the protruding PTR and a plurality of upper letter line layers 120b along a first horizontal direction (X direction).

[0091] Accordingly, even if Figures 5A to 5D The formation of defect PT shown can also prevent short circuits in the semiconductor memory device 1 and the method of manufacturing semiconductor memory device 1 according to the embodiment, which are electrically connected to each other by multiple direct contact conductive patterns 134 and multiple word lines 120. Accordingly, the method of manufacturing semiconductor memory device 1 according to the embodiment can form semiconductor memory device 1 with high integration and operational reliability.

[0092] Reference Figures 16A to 16D and Figure 17BEach of the multiple word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may include electrode recesses 120RS. At least some of the upper word line layers 120b may be divided into two parts by the electrode recesses 120RS and may be spaced apart from each other in a first horizontal direction (X direction). A plurality of buried insulating films 124 may be located on the multiple word lines 120 and may cover the multiple word lines 120. The top surface of the portion of the lower word line layer 120a corresponding to the electrode recesses 120RS may be at substantially the same vertical height as the top surfaces of the other portions of the lower word line layer 120a. That is, the top surfaces of the multiple lower word line layers 120a may be at substantially the same vertical height. For example, in reference Figures 8A to 8D and Figures 9A to 9D In the process described for removing defective PTA included in multiple lower word line layers 120, a portion of the defective PTA may not remain.

[0093] At least some of the buried insulating films 124 may include extended insulating portions 124F that fill electrode recesses 120RS included in at least some of the word lines 120 and extend into the word lines 120. The extended insulating portions 124F may contact the top surface of the lower word line layer 120a. Some of the upper word line layers 120b may extend along a first horizontal direction (X direction) and may be spaced apart from each other, with the extended insulating portions 124F located therebetween. For example, some of the upper word line layers 120b may be divided into two parts by the extended insulating portions 124F and may be spaced apart from each other in the first horizontal direction (X direction). Because the extended insulating portions 124F fill the electrode recesses 120RS, at least some of the direct contact conductive patterns 134 may be spaced apart from each other without contacting the word lines 120.

[0094] Reference Figures 16A to 16D and Figure 17CEach of the plurality of word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may include electrode recesses 120RS. At least some of the upper word line layers 120b may be divided into two parts by the electrode recesses 120RS and may be spaced apart from each other in a first horizontal direction (X direction). A plurality of buried insulating films 124 may be located on the plurality of word lines 120 and may cover the plurality of word lines 120. At least some of the lower word line layers 120a may include recesses PTRS at portions corresponding to the electrode recesses 120RS. The recesses PTRS may be referred to as lower electrode recesses. The lower word line layer 120a may have a top surface that is recessed towards the interior of the lower word line layer 120a more than the top surface of other portions of the lower word line layer 120a. For example, in reference Figures 8A to 8D and Figures 9A to 9D In the process described for removing defective PTa included in multiple lower word line layers 120a, the defective PTa and the portion of the lower word line layer 120a other than the defective PTa can be removed simultaneously to form a recessed portion PTRS.

[0095] At least some of the buried insulating films 124 may include extended insulating portions 124F that fill electrode recesses 120RS included in at least some of the word lines 120 and extend into the word lines 120. The extended insulating portions 124F may contact the lower word line layer 120a. The extended insulating portions 124F may fill recesses PTRS included in the lower word line layer 120a. Some of the upper word line layers 120b may extend along a first horizontal direction (X direction) and may be spaced apart from each other, with the extended insulating portions 124F located therebetween. For example, some of the upper word line layers 120b may be divided into two parts by the extended insulating portions 124F and may be spaced apart from each other in the first horizontal direction (X direction). Because the extended insulating portions 124F fill the electrode recesses 120RS, the plurality of directly contacting conductive patterns 134 and at least some of the word lines 120 may be spaced apart from each other without contacting each other. At the portion corresponding to the recessed PTRS, a plurality of insulating films 124 may extend between a plurality of lower letter line layers 120a along the first horizontal direction (X direction).

[0096] Figures 18A to 18D This is a partially enlarged view showing a semiconductor memory device according to an embodiment. Specifically, Figure 18A Parts EX1a and EX1b are related to Figure 16B The other parts corresponding to EX1 in the text, Figure 18B Parts EX1c and EX1d are related to Figure 16B The other parts corresponding to EX1 in the text, Figure 18CThe parts EX1e and EX1f are related to Figure 16B The other parts corresponding to EX1 in the text, and Figure 18D The parts of EX1g and EX1h are related to Figure 16B The other parts corresponding to EX1 in the text.

[0097] Reference Figures 16A to 16D and Figure 18A Each of the plurality of word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may include a first electrode recess 120RSa, and at least some of the word lines 120 may include a second electrode recess 120RSb. In a first horizontal direction (X direction), a first horizontal width W1a (the horizontal width at the uppermost end of the first electrode recess 120RSa) may be greater than a second horizontal width W2a (the horizontal width at the uppermost end of the second electrode recess 120RSb). At least some of the lower word line layers 120a may include a first protrusion PTRa at a portion corresponding to the first electrode recess 120RSa, and at least some of the lower word line layers 120a may include a second protrusion PTRb at a portion corresponding to the second electrode recess 120RSb. A first protrusion PTRa may protrude a first height LV1 in the vertical direction (Z direction) beyond the rest of the lower word line layer 120a toward the first electrode recess 120RSa. A second protrusion PTRb may protrude a second height LV2 in the vertical direction (Z direction) beyond the rest of the lower word line layer 120a toward the second electrode recess 120RSb, below the first height LV1. At least some of the plurality of buried insulating films 124 may include a first extended insulating portion 124Fa, which fills the first electrode recess 120RSa included in at least some of the word lines 120 and extends into the word line 120. The first extended insulating portion 124Fa may contact the first protrusion PTRa. At least some of the plurality of buried insulating films 124 may include a second extended insulating portion 124Fb, which fills the second electrode recess 120RSb included in at least some of the word lines 120 and extends into the word line 120. The second extended insulating portion 124Fb can contact the second protrusion PTRb. At the same vertical height, the horizontal widths of the first electrode groove 120RSa and the first extended insulating portion 124Fa in the first horizontal direction (X direction) can be greater than the horizontal widths of the second electrode groove 120RSb and the second extended insulating portion 124Fb, respectively.

[0098] For example, when Figures 5A to 5DWhen the defect PT shown is relatively large, for example, when the height of the defect PT is relatively high, a first electrode groove 120RSa, a first protrusion PTra, and a first extended insulating portion 124Fa can be formed; while when Figures 5A to 5D When the defect PT is relatively small, for example, when the height of the defect PT is relatively low, a second electrode groove 120RSb, a second protrusion PTRb, and a second extended insulating portion 124Fb can be formed.

[0099] Reference Figures 16A to 16D and Figure 18B Each of the plurality of word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may include a first electrode recess 120RSc, and at least some of the word lines 120 may include a second electrode recess 120RSd. In a first horizontal direction (X direction), a first horizontal width W1b (the horizontal width at the uppermost end of the first electrode recess 120RSc) may be greater than a second horizontal width W2b (the horizontal width at the uppermost end of the second electrode recess 120RSd). At least some of the lower word line layers 120a may include a protrusion PTR at the portion corresponding to the first electrode recess 120RSc, and at least some of the lower word line layers 120a may be formed such that the top surface of the portion corresponding to the second electrode recess 120RSd is at substantially the same vertical height as the top surfaces of the other portions of the lower word line layer 120a.

[0100] At least some of the buried insulating films 124 may include a first extended insulating portion 124Fc that fills and extends into the first electrode recess 120RSc included in at least some of the word lines 120. The first extended insulating portion 124Fc may contact the protrusion PTR. At least some of the buried insulating films 124 may include a second extended insulating portion 124Fd that fills and extends into the second electrode recess 120RSd included in at least some of the word lines 120. The second extended insulating portion 124Fd may contact the top surface of the lower word line layer 120a. At the same vertical height, the horizontal widths of the first electrode recess 120RSc and the first extended insulating portion 124Fc in the first horizontal direction (X direction) may be greater than the horizontal widths of the second electrode recess 120RSd and the second extended insulating portion 124Fd, respectively.

[0101] For example, when Figures 5A to 5DWhen the defect PT shown is relatively large, for example, when the height of the defect PT is relatively high, a first electrode groove 120RSc, a protrusion PTR, and a first extended insulating portion 124Fc can be formed; while when Figures 5A to 5D When the defect PT shown is relatively small, for example, when the height of the defect PT is relatively low, a second electrode groove 120RSd and a second extended insulating portion 124Fd can be formed.

[0102] Reference Figures 16A to 16D and Figure 18C Each of the plurality of word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may include a first electrode recess 120RSe, and at least some of the word lines 120 may include a second electrode recess 120RSf. In a first horizontal direction (X direction), a first horizontal width W1c (the horizontal width at the uppermost end of the first electrode recess 120RSe) may be greater than a second horizontal width W2c (the horizontal width at the uppermost end of the second electrode recess 120RSf). At least some of the lower word line layers 120a may include a protrusion PTR at a portion corresponding to the first electrode recess 120RSe, and at least some of the lower word line layers 120a may include a recess PTRS at a portion corresponding to the second electrode recess 120RSf. At least some of the buried insulating films 124 may include a first extended insulating portion 124Fe that fills and extends into a first electrode recess 120RSe included in at least some of the word lines 120. The first extended insulating portion 124Fe may contact a protrusion PTR. At least some of the buried insulating films 124 may include a second extended insulating portion 124Ff that fills and extends into a second electrode recess 120RSf included in at least some of the word lines 120. The second extended insulating portion 124Ff may fill a recess PTRS. At the same vertical height, the horizontal widths of the first electrode recess 120RSe and the first extended insulating portion 124Fe may be greater than the horizontal widths of the second electrode recess 120RSf and the second extended insulating portion 124Ff, respectively.

[0103] For example, when Figures 5A to 5D When the defect PT shown is relatively large, for example, when the height of the defect PT is relatively high, a first electrode groove 120RSe, a protrusion PTR, and a first extended insulating portion 124Fe can be formed; while when Figures 5A to 5D When the defects shown are relatively small, for example, when the height of the defect PT is relatively low, a second electrode groove 120RSf, a recessed portion PTRS, and a second extended insulating portion 124Ff can be formed.

[0104] Reference Figures 16A to 16D and Figure 18D Each of the plurality of word lines 120 may have a stacked structure including a lower word line layer 120a and an upper word line layer 120b. At least some of the word lines 120 may include a first electrode recess 120RSg, and at least some of the word lines 120 may include a second electrode recess 120RSh. In a first horizontal direction (X direction), a first horizontal width W1d (the horizontal width of the uppermost end of the first electrode recess 120RSg) may be greater than a second horizontal width W2d (the horizontal width of the uppermost end of the second electrode recess 120RSh). At least some of the lower word line layers 120a may be formed such that the top surface of the portion corresponding to the first electrode recess 120RSg is at substantially the same vertical height as the top surfaces of other portions of the lower word line layer 120a, and at least some of the lower word line layers 120 may include a recess PTRS at the portion corresponding to the second electrode recess 120RSh. At least some of the buried insulating films 124 may include a first extended insulating portion 124Fg that fills a first electrode recess 120RSg included in at least some of the word lines 120 and extends into the word line 120. The first extended insulating portion 124Fg may contact the top surface of the lower word line layer 120a. At least some of the buried insulating films 124 may include a second extended insulating portion 124Fh that fills a second electrode recess 120RSh included in at least some of the word lines 120 and extends into the word line 120. The second extended insulating portion 124Fh may fill a recess PTRS. In a first horizontal direction (X direction), the horizontal widths of the first electrode recess 120RSg and the first extended insulating portion 124Fg may be greater than the horizontal widths of the second electrode recess 120RSh and the second extended insulating portion 124Fh, respectively.

[0105] For example, when Figures 5A to 5D When the defect PT shown is relatively large, for example, when the height of the defect PT is relatively high, a first electrode groove 120RSg and a first extended insulating portion 124Fg can be formed; while when Figures 5A to 5D When the defect PT is relatively small, for example, when the height of the defect PT is relatively low, a second electrode groove 120RSh, a recessed portion PTRS, and a second extended insulating portion 124Fh can be formed.

[0106] Figures 19A to 19D , Figures 20A to 20D and Figures 21A to 21D This is a cross-sectional view used to describe a method of manufacturing a semiconductor memory device according to an embodiment. Figures 22A to 22DThis is a cross-sectional view of a semiconductor memory device according to an embodiment. Specifically, Figure 19A , Figure 20A and Figure 21A It is along Figure 2 A cross-sectional view taken from line A-A' in the diagram. Figure 19B , Figure 20B and Figure 21B It is along Figure 2 A cross-sectional view taken from line B-B' in the diagram. Figure 19C , Figure 20C and Figure 21C It is along Figure 2 The cross-sectional view taken by line C-C' in the diagram, and Figure 19D , Figure 20D and Figure 21D It is along Figure 2 The cross-sectional views taken by line D-D' in the diagram are in Figures 9A to 9D The following is a cross-sectional view used to describe the method of manufacturing semiconductor memory devices.

[0107] Reference Figures 19A to 19D A third preliminary conductive layer 120cP is formed, covering multiple lower word line layers 120a and multiple upper word line layers 120b and filling multiple word line trenches 120T. The third preliminary conductive layer 120cP may include a semiconductor material. In some embodiments, the third preliminary conductive layer 120cP may include the same material as the multiple upper word line layers 120b. For example, the third preliminary conductive layer 120cP may be formed of doped polysilicon. The third preliminary conductive layer 120cP may include extended conductive portions 120cF filling the electrode trenches 120RS.

[0108] Reference Figures 19A to 19D and Figures 20A to 20D By removing the upper part of the third preliminary conductive layer 120cP, a filling conductive layer 120c is formed to fill the electrode groove 120RS. Multiple lower word line layers 120a, multiple upper word line layers 120b, and the filling conductive layer 120c can constitute multiple word lines 120R. Multiple word lines 120R can constitute... Figure 2 The multiple letter lines WL in the text.

[0109] Reference Figures 21A to 21D Multiple buried insulating films 124 are formed to cover multiple word lines 120R and fill multiple word line trenches 120T. Multiple gate dielectric films 122, multiple word lines 120R, and multiple buried insulating films 124 can fill all word line trenches in the multiple word line trenches 120T. Multiple buried insulating films 124 can cover multiple upper word line layers 120b. At least some of the buried insulating films 124 can contact the filled conductive layer 120c.

[0110] Reference Figures 22A to 22D Through the Figures 21A to 21DThe final structure shown is executed as a reference. Figures 11A to 11D , Figures 12D to 12D , Figures 13A to 13D , Figures 14A to 14D , Figures 15A to 15D and Figures 16A to 16D The manufacturing method described above forms a semiconductor memory device 2. The semiconductor memory device 2 includes: a substrate 110 including a plurality of active regions 118; a plurality of gate dielectric films 122; a plurality of word lines 120R; and a plurality of buried insulating films 124 sequentially formed in the substrate 110 within a plurality of word line trenches 120T spanning the plurality of active regions 118; an insulating structure 113 covering a device isolation film 116, the plurality of active regions 118, and the plurality of buried insulating films 124; a plurality of bit line structures 140 on the insulating structure 113; a plurality of insulating spacer structures 150 covering two sidewalls of the plurality of bit line structures 140; and a plurality of buried contacts 170. The lower portion of the space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 is filled and connected to multiple active regions 118; multiple bonding pads 190 fill the upper portion of the space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 and extend to the upper portion of the bit line structure 140; an etch stop layer 206 is disposed on the multiple bonding pads 190; and multiple capacitor structures 200 include multiple lower electrodes 210, capacitor dielectric layers 220 and upper electrodes 230 passing through the etch stop layer 206 and connected to the multiple bonding pads 190.

[0111] Figures 23A to 23C This is a partially enlarged view showing a semiconductor memory device according to an embodiment. Specifically, Figures 23A to 23C It shows Figure 21B A magnified cross-sectional view of part EX2.

[0112] Reference Figures 22A to 22D and Figure 23AThe multiple word lines 120R may include multiple lower word line layers 120a, multiple upper word line layers 120b, and a conductive filler layer 120c. At least some of the word lines 120R may include electrode recesses 120RS. The conductive filler layer 120c may fill the electrode recesses 120RS. At least some of the upper word line layers 120b may be divided into two parts by the electrode recesses 120RS and may be spaced apart from each other in a first horizontal direction (X direction). Multiple buried insulating films 124 may be located on the multiple word lines 120R and may cover the multiple word lines 120R. At least some of the lower word line layers 120a may include protrusions PTR at portions corresponding to the electrode recesses 120RS. The protrusions PTR may protrude further toward the electrode recesses 120RS in the vertical direction (Z direction) than other portions of the lower word line layers 120a. The conductive filler layer 120c may contact the upper word line layer 120b and the lower word line layer 120a. In some embodiments, the conductive filler layer 120c may contact the protrusion PTR included in the lower word line layer 120a. Some of the upper word line layers 120b may extend in a first horizontal direction (X direction) and may be spaced apart from each other, with the conductive filler layer 120c located between them. For example, some of the upper word line layers 120b may be divided into two parts by the conductive filler layer 120c and may be spaced apart from each other in the first horizontal direction (X direction).

[0113] Accordingly, in the semiconductor memory device 2 and the method for manufacturing the semiconductor memory device 2 according to the embodiments, even if... Figures 5A to 5D The defect PT shown is formed because the multiple word lines 120R include a filled conductive layer 120c that fills the electrode recesses 120RS. Therefore, the electrical characteristics of the multiple word lines 120R may not deteriorate, and short circuits can be prevented where the multiple direct contact conductive patterns 134 are electrically connected to each other with the multiple word lines 120R. Accordingly, the method for manufacturing the semiconductor memory device 2 according to the embodiment can form a semiconductor memory device 2 with high integration and operational reliability.

[0114] Reference Figures 22A to 22D and Figure 23BThe multiple word lines 120R may include multiple lower word line layers 120a, multiple upper word line layers 120b, and a conductive filler layer 120c. At least some of the word lines 120R may include electrode recesses 120RS. The conductive filler layer 120c may fill the electrode recesses 120RS. At least some of the upper word line layers 120b may be divided into two parts by the electrode recesses 120RS and may be spaced apart from each other in a first horizontal direction (X direction). Multiple buried insulating films 124 may be located on the multiple word lines 120R and may cover the multiple word lines 120R. The top surface of the portion of the lower word line layer 120a corresponding to the electrode recesses 120RS may be at substantially the same vertical height as the top surfaces of other portions of the lower word line layer 120a. That is, the top surfaces of the multiple lower word line layers 120 may be at substantially the same vertical height. For example, in reference Figures 8A to 8D and Figures 9A to 9D In the process described for removing defective PTA included in multiple lower word line layers 120a, a portion of the defective PTA may not remain.

[0115] Multiple buried insulating films 124 may be located on and cover multiple word lines 120R. A conductive filler layer 120c may contact the upper word line layer 120b and the lower word line layer 120a. In some embodiments, the conductive filler layer 120c may contact the top surface of the lower word line layer 120a. Some of the upper word line layers 120b may extend along a first horizontal direction (X direction) and may be spaced apart from each other, with the conductive filler layer 120c located between them. For example, some of the upper word line layers 120b may be divided into two parts by the conductive filler layer 120c and may be spaced apart from each other in the first horizontal direction (X direction).

[0116] Reference Figures 22A to 22D and Figure 23C The multiple word lines 120R may include multiple lower word line layers 120a, multiple upper word line layers 120b, and a filling conductive layer 120c. At least some of the word lines 120R may include electrode recesses 120RS. The filling conductive layer 120c may fill the electrode recesses 120RS. At least some of the upper word line layers 120b may be divided into two parts by the electrode recesses 120RS and may be spaced apart from each other in a first horizontal direction (X direction). Multiple buried insulating films 124 may be located on the multiple word lines 120 and may cover the multiple word lines 120. At least some of the lower word line layers 120a may include recesses PTRS. The lower word line layer 120a may have a top surface that is recessed towards the interior of the lower word line layer 120a more than the top surface of other portions of the lower word line layer 120a. For example, in reference Figures 8A to 8D and Figures 9A to 9DIn the process described for removing defective PTa included in multiple lower word line layers 120a, the defective PTa and the portion of the lower word line layer 120a other than the defective PTa can be removed simultaneously to form a recessed portion PTRS.

[0117] The conductive filler layer 120c can contact the upper word line layer 120b and the lower word line layer 120a. In some embodiments, the conductive filler layer 120c can fill the recessed portion PTRS included in the lower word line layer 120a. Some of the upper word line layers 120b can extend along a first horizontal direction (X direction) and can be spaced apart from each other, with the conductive filler layer 120c located between them. For example, some of the upper word line layers 120b can be divided into two parts by the conductive filler layer 120c and can be spaced apart from each other in the first horizontal direction (X direction).

[0118] Figures 24A to 24D This is a partially enlarged view showing a semiconductor memory device according to an embodiment. Specifically, Figure 24A Parts EX2a and EX2b are related to Figure 21B The other parts corresponding to EX2 in the text, Figure 24B The parts EX2c and EX2d are related to Figure 21B The other parts corresponding to EX2 in the text, Figure 24C The parts EX2e and EX2f in the text are related to Figure 21B The other parts corresponding to EX2 in the text, and Figure 24D The parts of EX2g and EX2h are related to Figure 21B The other parts corresponding to EX2 in the text.

[0119] Reference Figures 22A to 22D and Figure 24AThe plurality of word lines 120R may include a plurality of lower word line layers 120a, a plurality of upper word line layers 120b, and a conductive filler layer 120c. At least some of the word lines 120R may include a first electrode recess 120RSa, and at least some of the word lines 120R may include a second electrode recess 120RSb. The conductive filler layer 120c may fill each of the first electrode recess 120RSa and the second electrode recess 120RSb. In a first horizontal direction (X direction), a first horizontal width W1a (the horizontal width at the uppermost end of the first electrode recess 120RSa) may be greater than a second horizontal width W2a (the horizontal width at the uppermost end of the second electrode recess 120RSb). At least some of the lower word line layers 120a may include a first protrusion PTRb at a portion corresponding to the first electrode recess 120RSa, and at least some of the lower word line layers 120a may include a second protrusion PTRb at a portion corresponding to the second electrode recess 120RSb. The first protrusion PTR1 may protrude a first height LV1 in the vertical direction (Z direction) beyond the rest of the lower word line layer 120a toward the first electrode recess 120RSa. The second protrusion PTRb may protrude a second height LV2 in the vertical direction (Z direction) beyond the rest of the lower word line layer 120a toward the second electrode recess 120RSb, below the first height LV1. The conductive filling layer 120c may contact each of the first protrusion PTR1 and the second protrusion PTRb. At the same vertical height, the horizontal width of the first electrode recess 120RSa and the conductive filling layer 120c filling the first electrode recess 120RSa may be greater than the horizontal width of the conductive filling layer 120c filling the second electrode recess 120RSb, respectively. The conductive filling layer 120c filling the first electrode recess 120RSa may be referred to as the first conductive filling layer, and the conductive filling layer 120c filling the second electrode recess 120RSb may be referred to as the second conductive filling layer.

[0120] Reference Figures 22A to 22D and Figure 24BThe multiple word lines 120R may include multiple lower word line layers 120a, multiple upper word line layers 120b, and a conductive filler layer 120c. At least some of the word lines 120R may include a first electrode recess 120RSc, and at least some of the word lines 120R may include a second electrode recess 120RSd. The conductive filler layer 120c may fill each of the first electrode recess 120RSc and the second electrode recess 120RSd. In the first horizontal direction (X direction), the first horizontal width W1b (the horizontal width of the uppermost end of the first electrode recess 120RSc) may be greater than the second horizontal width W2b (the horizontal width of the uppermost end of the second electrode recess 120RSd). At least some of the plurality of lower word line layers 120a may include a protruding PTR at a portion corresponding to the first electrode recess 120RSc, and at least some of the plurality of lower word line layers 120a may be formed such that the top surface of the portion corresponding to the second electrode recess 120RSd is at substantially the same vertical height as the top surface of the other portions of the lower word line layer 120a. A filling conductive layer 120c filling the first electrode recess 120RSc may contact the protruding PTR. A filling conductive layer 120c filling the second electrode recess 120RSd may contact the top surface of the lower word line layer 120a. At the same vertical height, the horizontal width of the first electrode recess 120RSc and the filling conductive layer 120c filling the first electrode recess 120RSc in the first horizontal direction (X direction) may be greater than the horizontal width of the second electrode recess 120RSd and the filling conductive layer 120c filling the second electrode recess 120RSd, respectively. The conductive filling layer 120c that fills the first electrode groove 120RSc can be referred to as the first conductive filling layer, and the conductive filling layer 120c that fills the second electrode groove 120RSd can be referred to as the second conductive filling layer.

[0121] Reference Figures 22A to 22D and Figure 24CThe plurality of word lines 120R may include a plurality of lower word line layers 120a, a plurality of upper word line layers 120b, and a conductive filler layer 120c. At least some of the word lines 120R may include a first electrode recess 120RSe, and at least some of the word lines 120R may include a second electrode recess 120RSf. The conductive filler layer 120c may fill each of the first electrode recess 120RSe and the second electrode recess 120RSf. In a first horizontal direction (X direction), a first horizontal width W1c (the horizontal width at the uppermost end of the first electrode recess 120RSe) may be greater than a second horizontal width W2c (the horizontal width at the uppermost end of the second electrode recess 120RSf). At least some of the lower word line layers 120a may include a protrusion PTR at a portion corresponding to the first electrode recess 120RSe, and at least some of the lower word line layers 120a may include a recess PTRS at a portion corresponding to the second electrode recess 120RSf. The conductive filling layer 120c filling the first electrode groove 120RSe can contact the protrusion PTR, and the conductive filling layer 120c filling the second electrode groove 120RSf can fill the recessed portion PTRS. At the same vertical height, in the first horizontal direction (X direction), the horizontal width of the first electrode groove 120RSe and the conductive filling layer 120c filling the first electrode groove 120RSe can be greater than the horizontal width of the second electrode groove 120RSf and the conductive filling layer 120c filling the second electrode groove 120RSf, respectively. The conductive filling layer 120c filling the first electrode groove 120RSe can be referred to as the first conductive filling layer, and the conductive filling layer 120c filling the second electrode groove 120RSf can be referred to as the second conductive filling layer.

[0122] Reference Figures 22A to 22D and Figure 24DThe multiple word lines 120R may include multiple lower word line layers 120a, multiple upper word line layers 120b, and a conductive filler layer 120c. At least some of the word lines 120R may include a first electrode recess 120RSg, and at least some of the word lines 120R may include a second electrode recess 120RSh. The conductive filler layer 120c may fill each of the first electrode recess 120RSg and the second electrode recess 120RSh. In the first horizontal direction (X direction), the first horizontal width W1d (the horizontal width of the uppermost end of the first electrode recess 120RSg) may be greater than the second horizontal width W2d (the horizontal width of the uppermost end of the second electrode recess 120RSh). At least some of the plurality of lower digit line layers 120a can be formed such that the top surface of the portion corresponding to the first electrode recess 120RSg is at substantially the same vertical height as the top surface of the other portions of the lower digit line layer 120a, and at least some of the plurality of lower digit line layers 120a can include a recess PTRS at the portion corresponding to the second electrode recess 120RSh. The filling conductive layer 120c filling the first electrode recess 120RSg can contact the top surface of the lower digit line layer 120a, and the filling conductive layer 120c filling the second electrode recess 120RSh can fill the recess PTRS. At the same vertical height, the horizontal width of the first electrode recess 120RSg and the filling conductive layer 120c filling the first electrode recess 120RSg in the first horizontal direction (X direction) can be greater than the horizontal width of the second electrode recess 120RSh and the filling conductive layer 120c filling the second electrode recess 120RSh, respectively. The conductive filling layer 120c that fills the first electrode groove 120RSg can be referred to as the first conductive filling layer, and the conductive filling layer 120c that fills the second electrode groove 120RSh can be referred to as the second conductive filling layer.

[0123] Although various aspects of the embodiments have been specifically shown and described above, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising: A substrate is provided in which a plurality of active regions are defined by a device isolation film; A word line trench is formed that spans the plurality of active regions and the device isolation film and extends along a first horizontal direction; A first preliminary conductive layer is formed to fill at least a portion of the word line trench; Perform a first etching process to remove the upper part of the first preliminary conductive layer and form a lower word line layer that fills the lower part of the word line trench; A second preliminary conductive layer is formed to cover the lower word line layer and fill the word line trench; A second etching process is performed to remove the upper portion of the second preliminary conductive layer and form an upper word line layer that fills a portion of the word line trench; Perform a third etching process that has high etching selectivity for the lower word line layer relative to the upper word line layer; as well as A buried insulating film is formed that covers the lower word line layer and the upper word line layer and fills the word line groove.

2. The method according to claim 1, wherein, Each of the first and second etching processes is an anisotropic dry etching process, and The third etching process is an isotropic wet etching process.

3. The method according to claim 1, wherein, The first preliminary conductive layer comprises a material containing metal atoms, and The second preliminary conductive layer comprises a semiconductor material.

4. The method according to claim 1, wherein, The lower letter line layer includes defects that protrude upwards more than other parts of the lower letter line layer, and The formation of the upper word line layer includes: removing the upper part of the second preliminary conductive layer, so that the defect in the lower word line layer protrudes upward beyond the top surface of the upper word line layer.

5. The method according to claim 4, wherein, Performing the third etching process includes removing at least a portion of the defects in the lower word line layer to form an electrode recess, the electrode recess being a space in which at least a portion of the defects in the lower word line layer has been removed.

6. The method according to claim 5, wherein, Forming the buried insulating film includes: forming the buried insulating film such that the buried insulating film includes an extended insulating portion that fills the electrode groove.

7. The method according to claim 6, wherein, The extended insulation portion contacts the lower letter line layer.

8. The method according to claim 5, further comprising: Before forming the buried insulating film, a filling conductive layer is formed to fill the electrode groove.

9. The method according to claim 5, wherein, After the third etching process is performed, the lower word line layer includes protrusions that protrude more toward the electrode recess than the rest of the lower word line layer.

10. The method according to claim 5, wherein, After the third etching process is performed, the lower letter line layer includes a recessed portion having a recessed top surface at a portion corresponding to the electrode groove.

11. A method for manufacturing a semiconductor memory device, the method comprising: A substrate is provided in which a plurality of active regions are defined by a device isolation film; Multiple word line trenches are formed, spanning the plurality of active regions and the device isolation film and extending parallel to each other along a first horizontal direction; A first preliminary conductive layer is formed to fill at least a portion of each of the plurality of word line trenches; A first etching process is performed to remove the upper part of the first preliminary conductive layer and form a plurality of lower word line layers that fill the lower part of the plurality of word line trenches, wherein the first etching process is an anisotropic etching process. A second preliminary conductive layer is formed to cover the plurality of lower word line layers and fill the plurality of word line trenches; A second etching process is performed to remove the upper portion of the second preliminary conductive layer and form a plurality of upper word line layers that fill the portions of the plurality of word line trenches, wherein the second etching process is an anisotropic etching process. A third etching process is performed, which is an isotropic etching process and exhibits high etching selectivity for the plurality of lower word lines relative to the plurality of upper word lines; and Multiple buried insulating films are formed to cover the multiple lower word line layers and the multiple upper word line layers and fill the multiple word line trenches.

12. The method according to claim 11, wherein, At least one of the plurality of lower letter line layers includes a defect that protrudes upwards more than the other portions of the plurality of lower letter line layers, and The formation of the plurality of upper word lines includes: removing the upper portion of the second preliminary conductive layer, such that the defect in at least one of the plurality of lower word lines protrudes upward beyond the top surface of the plurality of upper word lines.

13. The method according to claim 12, wherein, Performing the third etching process includes: forming an electrode recess by removing at least a portion of the defects in at least one of the plurality of lower word line layers, and The formation of the plurality of buried insulating films includes: forming the plurality of buried insulating films such that at least one of the plurality of buried insulating films includes an extended insulating portion that fills the electrode groove and contacts at least one of the plurality of lower word line layers.

14. The method according to claim 13, wherein, After performing the third etching process, at least one of the plurality of lower word line layers includes a first protrusion projecting toward the first electrode recess, and at least one of the plurality of lower word line layers includes a second protrusion projecting toward the second electrode recess. Wherein, the horizontal width of the uppermost end of the first electrode groove is greater than the horizontal width of the uppermost end of the second electrode groove, and The second protrusion has a lower protrusion height than the first protrusion.

15. The method according to claim 13, wherein, After performing the third etching process, at least one of the plurality of lower word line layers includes a recess, the recess having a recessed top surface at a portion corresponding to the electrode recess, and The extended insulating portion fills the recessed portion.

16. The method according to claim 12, wherein, The first preliminary conductive layer comprises a material containing metal atoms, and The second preliminary conductive layer comprises a semiconductor material.

17. The method according to claim 16, wherein, Performing the third etching process includes: forming an electrode recess by removing at least a portion of the defects in at least one of the plurality of lower word line layers, and The method further includes forming a filling conductive layer comprising a semiconductor material and filling the electrode grooves before forming the plurality of buried insulating films.

18. A method for manufacturing a semiconductor memory device, the method comprising: A substrate is provided in which a plurality of active regions are defined by a device isolation film; Multiple word line trenches are formed, spanning the plurality of active regions and the device isolation film and extending parallel to each other along a first horizontal direction; A first preliminary conductive layer is formed to fill at least a portion of each of the plurality of word line trenches; A first etching process is performed to remove the upper portion of the first preliminary conductive layer and form a plurality of lower word line layers that fill the lower portion of the plurality of word line trenches, wherein the first etching process is an anisotropic etching process, and wherein at least one of the plurality of lower word line layers includes defects that protrude upwards more than other portions of the plurality of lower word line layers. A second preliminary conductive layer is formed to cover the plurality of lower word line layers and fill the plurality of word line trenches; A second etching process is performed to remove the upper portion of the second preliminary conductive layer and form a plurality of upper word line layers that fill the portions of the plurality of word line trenches, wherein the second etching process is an anisotropic etching process, wherein the defects in at least one of the plurality of lower word line layers protrude upward beyond the top surface of the plurality of upper word line layers, and wherein the plurality of lower word line layers and the plurality of upper word line layers constitute a plurality of word lines; A third etching process is performed, which is an isotropic etching process and has high etching selectivity for the plurality of lower word lines relative to the plurality of upper word lines, to form an electrode recess by removing at least a portion of the defects in at least one of the plurality of lower word lines. Multiple buried insulating films are formed to cover the multiple lower word line layers and the multiple upper word line layers and to fill the multiple word line trenches and the electrode grooves; Multiple bit lines extending along a second horizontal direction perpendicular to the first horizontal direction are formed on the multiple word lines, and multiple direct contact conductive patterns are formed to connect the multiple bit lines to the multiple active regions. A plurality of buried contacts are formed to fill the space between the plurality of bit lines and to connect to the plurality of active regions; Forming multiple bonding pads connected to the plurality of buried contacts; and Multiple capacitor structures are formed and connected to the plurality of bonding pads.

19. The method according to claim 18, wherein, The first preliminary conductive layer is formed of a metal, a conductive metal nitride, or a combination thereof, and The second preliminary conductive layer is formed of doped polycrystalline silicon.

20. The method according to claim 18, wherein, After the electrode recess is formed, at least one of the plurality of lower digit layers includes a protrusion that projects toward the electrode recess.

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