Semiconductor structure

Abstract

This application provides a semiconductor structure including a substrate, a first stacked layer, a second stacked layer, an isolation layer, a first channel via, and a groove. The first stacked layer, the isolation layer, and the second stacked layer are sequentially disposed on the substrate. The first stacked layer includes a plurality of alternating first dielectric layers and a plurality of first conductive layers. The second stacked layer includes a plurality of alternating second dielectric layers and a plurality of second conductive layers. The first channel via is located within the first stacked layer and has a first width. A first sidewall structure and a first conductive plug are sequentially disposed on the inner sidewall of the first channel via. The groove is located within the isolation layer and has a second width. A second sidewall structure and a contact pad are sequentially disposed on the inner sidewall of the groove. The groove is interconnected with the first channel via. The second width is greater than the first width. The first conductive plug and the contact pad are integrally formed. The first sidewall structure and the second sidewall structure are isolated from each other. The semiconductor structure provided in this application is used for data storage.

Description

[0001] This application is a divisional application. The original application has the application number 202410538397.3 and the original application date is April 30, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0003] With the development of semiconductor memory devices, the demand for semiconductor memory devices with high-density data storage cells is also growing. Therefore, three-dimensional memory with vertically stacked layers of multiple data storage cells has become a research hotspot.

[0004] The three-dimensional memory includes a substrate and several stacked structures disposed on the substrate. For example, a first stacked structure and a second stacked structure are stacked on the substrate, the upper first stacked structure includes a first through structure, and the lower second stacked structure includes a second through structure, with the top of the first through structure contacting and electrically connected to the bottom of the second through structure.

[0005] However, the electrical connection between the first and second through-structures of the current three-dimensional memory has poor reliability, which reduces the yield of the three-dimensional memory. Summary of the Invention

[0006] In view of the above problems, embodiments of this application provide a semiconductor structure that can improve the yield of three-dimensional memory.

[0007] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0008] A first aspect of this application provides a semiconductor structure comprising:

[0009] Substrate;

[0010] The first stacked layer includes a plurality of alternating first dielectric layers and a plurality of first conductive layers disposed on the substrate;

[0011] The second stacked layer includes a plurality of alternately arranged second dielectric layers and a plurality of second conductive layers disposed on the first stacked layer;

[0012] An isolation layer is located between the first stacked layer and the second stacked layer;

[0013] A first channel hole is located within the first stacked layer and has a first width, and a first sidewall structure and a first conductive plug are sequentially disposed on the inner sidewall of the first channel hole.

[0014] A groove, located within the isolation layer and having a second width, has a second sidewall structure and a contact pad sequentially disposed on the inner sidewall of the groove; wherein the groove is in communication with the first channel hole;

[0015] Wherein, the second width is greater than the first width, the first conductive plug and the contact pad are integrally formed, and the first conductive plug and the contact pad isolate the first sidewall structure and the second sidewall structure from each other.

[0016] A second aspect of this application provides a semiconductor structure, including:

[0017] Substrate;

[0018] A first stacked layer and an isolation layer are stacked on the substrate;

[0019] A T-shaped contact structure is disposed in the first stacked layer and the isolation layer. The T-shaped contact structure includes a lower part with a first width and an upper part with a second width. The first width is smaller than the second width, and the lower part and the upper part are integral structures.

[0020] The first sidewall structure is disposed on the lower sidewall of the T-shaped contact structure;

[0021] The second sidewall structure is disposed on the upper sidewall of the T-shaped contact structure;

[0022] The first sidewall structure and the second sidewall structure are discontinuous.

[0023] A third aspect of this application provides a semiconductor structure, including:

[0024] Substrate;

[0025] A first stacked layer and an isolation layer are stacked on the substrate;

[0026] An integral contact structure is disposed in the first stacked layer. The integral contact structure includes a lower part with a first width and an upper part with a second width, wherein the first width is smaller than the second width.

[0027] A first sidewall structure is disposed on the lower sidewall of the integral contact structure;

[0028] The second sidewall structure is disposed on the upper sidewall of the integral contact structure;

[0029] The projections of the first sidewall structure and the second sidewall structure do not overlap in the horizontal direction.

[0030] A fourth aspect of the embodiments of this application provides a semiconductor structure and a substrate;

[0031] A first stacked layer and an isolation layer are stacked on the substrate;

[0032] An integral contact structure is disposed in the first stacked layer and the isolation layer. The integral contact structure includes a lower part with a first width and an upper part with a second width. The first width is smaller than the second width, and the bottom surface of the upper part directly contacts the first stacked layer.

[0033] A first sidewall structure is disposed on the lower sidewall of the integral contact structure;

[0034] The second sidewall structure is disposed on the upper sidewall of the integral contact structure.

[0035] Compared with related technologies, the semiconductor structure provided in this application has the following advantages:

[0036] The semiconductor structure provided in this application includes a first stacked layer, a first through structure and a second through structure. The first through structure is disposed within the first stacked layer, and the top of the first through structure has a contact pad that completely covers it, and the bottom dimension of the contact pad is larger than the top dimension of the first through structure.

[0037] Furthermore, a second barrier layer is disposed around the contact pad, which isolates it from the first sidewall structure, the second sidewall structure, and part of the first stacked layer. The second through-structure is located above the contact pad and is electrically connected to the contact pad; that is, the first through-structure and the second through-structure are electrically connected through the contact pad.

[0038] In related technologies, the first and second through-hole structures of a three-dimensional memory are prone to misalignment, resulting in a small contact area between the first and second through-hole structures, or even no contact area between them, which affects the reliability of the electrical connection between the first and second through-hole structures.

[0039] However, in the semiconductor structure provided in this application embodiment, the bottom dimension of the contact pad is larger than the top dimension of the first through structure, which can increase the contact area between the first through structure and the second through structure, improve the reliability of the electrical connection between the first through structure and the second through structure, and thus improve the yield of the three-dimensional memory.

[0040] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions as described above, other technical problems that the semiconductor structure provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 1 ;

[0043] Figure 2 A schematic flowchart illustrating the semiconductor structure fabrication method provided in this application embodiment;

[0044] Figure 3 A detailed flowchart illustrating step S300 in the semiconductor structure fabrication method provided in this application embodiment;

[0045] Figures 4 to 15 A schematic diagram of the semiconductor structure fabrication method provided in the embodiments of this application;

[0046] Figure 16 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 2 .

[0047] Explanation of reference numerals in the attached figures:

[0048] 10-Substrate;

[0049] 11-Etching stop layer;

[0050] 20 - First stacked layer;

[0051] 21-Dielectric layer; 22-Conductive layer; 23-First channel via;

[0052] 30 - Isolation layer; 31 - Groove;

[0053] 40 - Mask layer;

[0054] 41 - First mask pattern; 42 - Second mask pattern;

[0055] 50 - Sidewall layer; 50a - First sidewall structure; 50b - Second sidewall structure;

[0056] 51-Metal oxide layer; 52-Third barrier layer;

[0057] 60 - Barrier material layer;

[0058] 61 - First barrier layer; 62 - Second barrier layer;

[0059] 70 - First through-hole structure; 71 - First conductive plug; 72 - Contact pad;

[0060] 80 - Second stacked layer;

[0061] 90 - Second through-hole structure; 91 - Second conductive plug;

[0062] 100-Semiconductor structure. Detailed Implementation

[0063] In related technologies, the electrical connection between the first and second through-structures of three-dimensional memory has poor reliability, resulting in low yield rates. The inventors have discovered that the reason for this problem is:

[0064] Three-dimensional memory typically includes a substrate and a first stacked structure and a second stacked structure stacked sequentially. The first stacked structure includes a first through-hole structure, and the second stacked structure includes a second through-hole structure. The top of the first through-hole structure and the bottom of the second through-hole structure are in contact and electrically connected. However, misalignment of the first and second through-hole structures is prone to occur during fabrication, resulting in a small contact area or even no contact area between the two structures, affecting the reliability of the electrical connection between the first and second through-hole structures.

[0065] To address the aforementioned technical problems, this application provides a semiconductor structure and its fabrication method. A contact pad completely covering the top of a first through-structure is provided, with the bottom dimension of the contact pad being larger than the top dimension of the first through-structure. A second barrier layer is provided around the contact pad, insulating it from the first sidewall structure, the second sidewall structure, and a portion of the first stacked layer. The second through-structure is located above the contact pad and is electrically connected to it.

[0066] With this configuration, the semiconductor structure provided in this application embodiment has a bottom dimension of the contact pad that is larger than the top dimension of the first through-structure, which can increase the contact area between the first through-structure and the second through-structure, improve the electrical connection reliability between the first through-structure and the second through-structure, and thus improve the yield of the three-dimensional memory.

[0067] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0068] like Figure 1 As shown, the semiconductor structure 100 provided in this embodiment can be a three-dimensional memory, which includes a substrate 10, which can be made of a semiconductor material. For example, the material used to fabricate the substrate 10 includes, but is not limited to, silicon, germanium, silicon-germanium, etc., and optionally the substrate 10 is made of single-crystal silicon. Other semiconductor elements may be included within the substrate 10.

[0069] A plurality of stacked layers are sequentially disposed on the substrate 10. For example, a first stacked layer 20 and a second stacked layer 80 are sequentially disposed on the substrate 10, that is, the second stacked layer 80 is located above the first stacked layer 20. Both the first stacked layer 20 and the second stacked layer 80 include a plurality of dielectric layers 21 and a plurality of conductive layers 22 disposed alternately, wherein the thickness of the dielectric layer 21 and the thickness of the conductive layer 22 may be the same or different.

[0070] It should be noted that the conductive layer 22 is made of a conductive material, including but not limited to tungsten, copper, aluminum, doped silicon, and / or silicides. The dielectric layer 21 is made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Of course, three or more stacked layers can be sequentially stacked on the substrate 10, the specific number depending on the actual number of conductive layers 22 stacked.

[0071] Each stacked layer is provided with a through structure. For example, the first stacked layer 20 is provided with a first through structure 70, which is disposed perpendicular to the first stacked layer 20, and the bottom end of the first through structure 70 extends to the surface of the substrate 10 or extends into the substrate 10.

[0072] The second stacked layer 80 is provided with a second through structure 90, which is perpendicular to the second stacked layer 80 and is located above the corresponding first through structure 70. The second through structure 90 and the first through structure 70 are staggered, and the bottom of the second through structure 90 is in contact with and electrically connected to the top of the corresponding first through structure 70.

[0073] For example, the first stacked layer 20 is provided with a first channel hole 23, which penetrates the first stacked layer 20, and the end of the first channel hole 23 near the substrate 10 can extend to the surface of the substrate 10 or the interior of the substrate 10. A first through-hole structure 70 is disposed in the first channel hole 23. The first through-hole structure 70 includes a first sidewall structure 50a, a first barrier layer 61, and a first conductive plug 71. The first sidewall structure 50a is disposed on the inner sidewall of the first channel hole 23, and the first barrier layer 61 is disposed on the inner sidewall of the first sidewall structure 50a, forming a filling space for the first conductive plug 71. The first conductive plug 71 is inserted into the filling space formed by the first barrier layer 61 and is in contact with the first barrier layer 61. The bottom end of the first conductive plug 71 passes through the bottom of the first barrier layer 61 and is in contact with and electrically connected to the substrate 10.

[0074] Furthermore, a second stacked layer 80 is disposed on the surface of the first stacked layer 20 away from the substrate 10. The second stacked layer 80 has a second channel hole that penetrates the second stacked layer 80. The second channel hole is staggered from the first channel hole 23, and the first channel hole 23 and the second channel hole are at least partially connected. A second through structure 90 is disposed within the second channel hole. The second through structure 90 has the same structure as the first through structure 70. For example, the second through structure 90 includes a second conductive plug 91, which can be electrically connected to the first conductive plug 71. This will not be described in detail here.

[0075] like Figure 16 As shown, in this embodiment of the application, the first through-structure 70 and the second through-structure 90 are arranged in a staggered manner. In order to ensure the reliability of the electrical connection between the first through-structure 70 and the second through-structure 90, the semiconductor structure 100 provided in this embodiment of the application further includes an isolation layer 30 and a plurality of contact pads 72, wherein the plurality of contact pads 72 are spaced apart in the isolation layer 30, each contact pad 72 is disposed on the top of the corresponding first through-structure 70, and the contact pad 72 covers the top of the first through-structure 70.

[0076] It is understood that the semiconductor structure provided in this application embodiment includes a first stacked layer 20 and a second stacked layer 80 thereon. The contact pad 72 is disposed on the top of the first through structure 70 and is located between the first stacked layer 20 and the second stacked layer 80. The top of the second through structure 90 is not provided with the contact pad 72. In other words, when the semiconductor structure includes two or more stacked layers, the contact pad 72 can be disposed between two adjacent stacked layers. The topmost stacked layer of the semiconductor structure does not need to be provided with the contact pad 72.

[0077] Furthermore, one side of the contact pad 72 is in contact with and electrically connected to at least a portion of the first conductive plug 71, and the other side of the contact pad 72 is electrically connected to at least a portion of the second conductive plug 91. That is, the contact pad 72 is used to electrically connect the first through structure 70 and the second through structure 90. The second through structure 90 is disposed on the contact pad 72, and at least a portion of the second through structure 90 contacts the contact pad 72.

[0078] For example, the isolation layer 30 is disposed on the side surface of the first stacked layer 20 away from the substrate 10 and covers the first stacked layer 20, that is, the isolation layer 30 is disposed between the first stacked layer 20 and the second stacked layer 80, and the isolation layer 30 has a certain thickness.

[0079] In this embodiment, the isolation layer 30 may be made of the same material as the dielectric layer 21 of the first stacked layer. For example, the isolation layer 30 may be made of an insulating material, and the insulating material for making the isolation layer 30 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above materials.

[0080] The isolation layer 30 has a plurality of grooves 31, each groove 31 being connected to a first channel hole 23. For example, the first channel hole 23 is centered with the corresponding groove 31, the bottom dimension of the groove 31 is larger than the dimension of the first channel hole 23, and the bottom of the groove 31 is connected to the first channel hole 23, forming a stepped hole structure between them.

[0081] In this embodiment, a plurality of contact pads 72 are provided within the isolation layer 30, and each contact pad 72 is disposed within a groove 31. The bottom dimension of the contact pad 72 is larger than the top dimension of the first through structure 70, and the contact pad 72 completely covers the first through structure 70, that is, the contact pad 72 completely covers the end face of the first conductive plug 71 and the first sidewall structure 50a.

[0082] To keep the contact pad 72 insulated from its surrounding structure and prevent leakage current between the contact pad 72 and its surrounding structure, the semiconductor structure 100 provided in this application embodiment further includes a second barrier layer 62. The second barrier layer 62 may be a titanium nitride layer. The second barrier layer 62 is disposed on the sidewall and bottom surface of the contact pad 72 and surrounds the contact pad 72.

[0083] Furthermore, the second barrier layer 62 is in contact with the first barrier layer 61, and the second barrier layer 62 and the first barrier layer 61 are an integral structure. The first barrier layer 61 is located between the first sidewall structure 50a and the first conductive plug 71, and the side portion of the first barrier layer 61 is in contact with the first sidewall structure 50a and the first conductive plug 71 respectively, and the bottom of the first barrier layer 61 is in contact with the substrate 10.

[0084] A portion of the second barrier layer 62 covers the inner surface of the second sidewall structure 50b and is located between the second sidewall structure 50b and the sidewall of the contact pad 72, that is, a portion of the second barrier layer 62 is in contact with the sidewalls of the second sidewall structure 50b and the contact pad 72 respectively.

[0085] A portion of the second barrier layer 62 covers the surface of the first stacked layer 20 exposed in the groove 31 and is located between the first stacked layer 20 and the bottom surface of the partial contact pad 72, that is, the portion of the second barrier layer 62 contacts the bottom surfaces of the portion of the first stacked layer 20 and the portion of the contact pad 72 respectively.

[0086] In related technologies, the first and second through-hole structures of three-dimensional memory are prone to misalignment, resulting in a small contact area between the first and second through-hole structures, or even no contact area between them, which affects the reliability of the electrical connection between the first and second through-hole structures.

[0087] However, in the semiconductor structure 100 provided in this application embodiment, the bottom dimension of the contact pad 72 is larger than the top dimension of the first through structure 70, which can increase the contact area of ​​the first through structure 70 and the second through structure 90, improve the reliability of the electrical connection between the first through structure 70 and the second through structure 90, and thus improve the yield of the three-dimensional memory.

[0088] Based on the above embodiments, in this application embodiment, the contact pad 72 and the first conductive plug 71 are configured as an integral structure. For example, both the first conductive plug 71 and the contact pad 72 are made of tungsten metal. During the manufacturing process, the first conductive plug 71 and the contact pad 72 are formed through a single deposition process to form an integral structure of the first conductive plug 71 and the contact pad 72. This configuration can improve manufacturing efficiency and shorten the manufacturing cycle.

[0089] Furthermore, in the embodiments of this application, the first sidewall structure 50a and the second sidewall structure 50b include the same material layer. For example, the sidewall layer 50 with the same material layer can be formed in a single process during the manufacturing process. This configuration can improve manufacturing efficiency and shorten the manufacturing cycle.

[0090] In one optional embodiment, the first sidewall structure 50a and the second sidewall structure 50b include a metal oxide layer 51 and a third barrier layer 52 disposed sequentially. The metal oxide layer 51 is made of a material including, but not limited to, a high-k dielectric material. The third barrier layer 52 is made of the same material as the first barrier layer 61 and the second barrier layer 62, which can all be made of titanium nitride.

[0091] For example, in the first sidewall structure 50a, a metal oxide layer 51 is disposed on the inner wall of the first channel hole 23, and a third barrier layer 52 is disposed on the metal oxide layer 51. It is understood that a second barrier layer 62 is disposed on the inner surface of the third barrier layer 52.

[0092] In the semiconductor structure 100 provided in this application embodiment, the contact pad 72, the first through-structure 70, and the second through-structure 90 are staggered. For example, in one optional embodiment, the contact pad 72 and the first through-structure 70 are directly opposite each other, and the second through-structure 90 and the contact pad 72 are staggered; or, in another optional embodiment, the contact pad 72 and the first through-structure 70 are staggered, and the second through-structure 90 and the contact pad 72 are staggered. This application embodiment does not limit this.

[0093] like Figure 1 As shown, the semiconductor structure 100 provided in this embodiment further includes:

[0094] Substrate 10.

[0095] The first stacked layer 20 and the isolation layer 30 are stacked on the substrate 10.

[0096] A T-shaped contact structure is disposed in the first stacked layer 20 and the isolation layer 30. The T-shaped contact structure includes a lower part with a first width and an upper part with a second width, the first width being smaller than the second width, and the lower part and the upper part being an integral structure. Specifically, the upper part is the portion of the T-shaped contact structure located in the isolation layer 30, that is, the upper part is the contact pad 72. The lower part is the portion of the T-shaped contact structure located in the first stacked layer 20, that is, the lower part is the first conductive plug 71.

[0097] The first sidewall structure is located on the lower sidewall of the T-shaped contact structure.

[0098] The second sidewall structure is located on the upper sidewall of the T-shaped contact structure.

[0099] The first sidewall structure and the second sidewall structure are discontinuous.

[0100] It should be noted that the substrate 10, the first stacked layer, the isolation layer 30, the first sidewall structure 50a and the second sidewall structure 50b can be referred to the above embodiments, and will not be described in detail here.

[0101] In one alternative embodiment, the T-shaped contact structure includes a barrier layer and a metal layer, with the barrier layer covering the outer peripheral surface and the bottom surface of the metal layer.

[0102] A first channel hole 23 is provided in the first stacked layer 20, and a groove 31 is provided in the isolation layer 30. The groove 31 and the first channel hole 23 are interconnected. The lower part is located in the first channel hole 23; in other words, the lower part is the first conductive plug 71. The upper part is located in the groove 31; in other words, the upper part is the contact pad 72. Figure 1 As shown, the semiconductor structure 100 provided in this embodiment further includes:

[0103] Substrate 10.

[0104] The first stacked layer 20 and the isolation layer 30 are stacked on the substrate 10.

[0105] An integral contact structure is disposed in the first stacked layer 20. The integral contact structure includes a lower part with a first width and an upper part with a second width, wherein the first width is smaller than the second width.

[0106] The first sidewall structure 50a is disposed on the sidewall of the lower part of the integral contact structure.

[0107] The second sidewall structure 50b is disposed on the upper sidewall of the integral contact structure.

[0108] The projections of the first sidewall structure 50a and the second sidewall structure 50b do not overlap in the horizontal direction.

[0109] It should be understood that the upper and lower parts of the integrated contact structure can be referred to the description of the above embodiment, and will not be repeated here.

[0110] like Figure 1 As shown, the semiconductor structure 100 provided in this embodiment further includes:

[0111] Substrate 10.

[0112] The first stacked layer 20 and the isolation layer 30 are stacked on the substrate 10.

[0113] An integral contact structure is disposed in the first stacked layer 20 and the isolation layer 30. The integral contact structure includes a lower part with a first width and an upper part with a second width. The first width is smaller than the second width, and the bottom surface of the upper part directly contacts the first stacked layer 20.

[0114] The first sidewall structure 50a is disposed on the sidewall of the lower part of the integral contact structure.

[0115] The second sidewall structure 50b is disposed on the upper sidewall of the integral contact structure.

[0116] It should be understood that the upper and lower parts of the integrated contact structure can be referred to the description of the above embodiment, and will not be repeated here.

[0117] like Figure 2 As shown in the embodiments of this application, a method for fabricating the semiconductor structure 100 is also provided, including the following steps:

[0118] First, step S100 is performed: a substrate 10 is provided; for example, the substrate 10 may be made of monocrystalline silicon and is used to protect and support the subsequently formed first stacked layer 20.

[0119] Next, step S200 is performed: a first stacked layer 20 and a covering isolation layer 30 are formed on the substrate 10. The structure formed in this step is as follows: Figure 4 As shown.

[0120] Specifically, before forming the first stacked layer 20 on the substrate 10, an etch stop layer 11 may be formed on the surface of the substrate 10. The etch stop layer 11 may be made of materials including but not limited to aluminum oxide. The etch stop layer 11 has a different etch selectivity than the first stacked layer 20. That is, the etch stop layer 11 can serve as a protective layer to control the etching rate and prevent the substrate 10 from being over-etched when the first stacked layer 20 is subsequently etched to form the first channel via 23.

[0121] After forming an etch stop layer 11 on the substrate 10, a first stacked layer 20 and an isolation layer 30 are sequentially formed on the etch stop layer 11. The first stacked layer 20 includes a dielectric layer 21 and a conductive layer 22 arranged alternately in sequence, and the bottommost dielectric layer 21 is in contact with the etch stop layer 11.

[0122] The isolation layer 30 is located on the surface of the first stacked layer 20 facing away from the substrate 10. For example, the dielectric layer 21 of the uppermost first stacked layer 20 is configured as the isolation layer 30; or, an insulating material is deposited on the dielectric layer 21 of the first stacked layer 20 to form the isolation layer 30, which is not limited in this embodiment. The following description uses the example of the dielectric layer 21 of the uppermost first stacked layer 20 being configured as the isolation layer 30.

[0123] For example, aluminum oxide is deposited on substrate 10 to form an etch stop layer 11; then, an insulating material and a conductive material are sequentially deposited on the etch stop layer 11 to form a dielectric layer 21 and a conductive layer 22, respectively, wherein the conductive material includes, but is not limited to, tungsten, copper, aluminum, doped silicon and / or silicides. The insulating material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0124] It should be noted that the isolation layer 30, as an insulating layer, can be made of the same material as the dielectric layer 21; chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods can be used in the process of fabricating the etch stop layer 11, the dielectric layer 21, and the conductive layer 22, and the embodiments of this application do not limit this.

[0125] Next, step S300 is performed: the isolation layer 30 and the first stacked layer 20 are etched to form a first channel hole 23 in the first stacked layer 20; and a groove 31 communicating with the first channel hole 23 is formed in the isolation layer 30, wherein the bottom width of the groove 31 is greater than the top width of the first channel hole 23.

[0126] Specifically, a first vertical etching is performed on the isolation layer 30 and the first stacked layer 20 to form a through-hole penetrating the first stacked layer 20 and the isolation layer 30. One end of the through-hole extends to the surface of the etching stop layer 11. Part of the through-hole is located within the first stacked layer 20, forming a first channel hole 23. Part of the through-hole is located within the isolation layer 30. Subsequently, a groove 31 communicating with the first channel hole 23 is configured. This structure is as follows: Figure 7 As shown.

[0127] A second vertical etching is performed on the isolation layer 30 to etch a portion of the isolation layer 30 around the via, forming a groove 31 within the isolation layer 30. The bottom width of the groove 31 is greater than the top width of the first channel hole 23, forming a stepped hole structure. This structure is as follows: Figure 9 As shown.

[0128] After forming the groove 31 in the isolation trench, the etch stop layer 11 is further etched so that the first channel hole 23 extends further to the surface or interior of the substrate 10; this structure is as follows Figure 11 As shown. It should be noted that the isolation layer 30 and the first stacked layer 20 can be etched using a dry etching process, while the etching stop layer 11 can be etched using a wet etching process. This application embodiment does not impose any restrictions on this.

[0129] After forming the first channel hole 23 and groove 31, step S400 is performed: a sidewall layer 50 is formed in the first channel hole 23 and groove 31. The structure formed in this step is as follows: Figure 12 As shown.

[0130] Specifically, the sidewall layer 50 includes a metal oxide layer 51 and a third barrier layer 52 disposed sequentially. A high-K dielectric material and titanium nitride are deposited sequentially in the first channel hole 23 and the first groove 31 to form a high-K dielectric layer and a titanium nitride layer, respectively. The high-K dielectric layer is configured as a metal oxide layer 51, and the titanium nitride layer is configured as a third barrier layer 52. The metal oxide layer 51 covers the inner wall of the first channel hole 23, and the third barrier layer 52 covers the metal oxide layer 51.

[0131] After the sidewall layer 50 is formed in the first channel hole 23 and the groove 31, step S500 is performed: the sidewall layer 50 is etched to form a first sidewall structure 50a disposed in the first channel hole 23 and a second sidewall structure 50b disposed in the groove 31.

[0132] Specifically, using the first channel hole 23 as the etching channel, the metal oxide layer 51 and the third barrier layer 52 located at the bottom of the first channel hole 23 are etched away, and a portion of the substrate 10 is exposed within the first channel hole 23. Additionally, a portion of the sidewall layer 50 located at the bottom of the groove 31 is etched to expose a portion of the first stacked layer 20 within the groove 31, forming a first sidewall structure 50a and a second sidewall structure 50b that do not contact each other. The structure formed in this step is as follows: Figure 13 As shown.

[0133] After forming the first sidewall structure 50a and the second sidewall structure 50b that do not contact each other, step S600 is performed: a barrier material layer 60 is formed in the groove 31 and the first channel hole 23, and the barrier material layer 60 covers the first sidewall structure 50a, the second sidewall structure 50b and the portion of the first stacked layer 20 exposed in the groove 31. The structure formed in this step is as follows: Figure 14 As shown.

[0134] Specifically, the groove 31 and the first channel hole 23 are used as deposition channels, and titanium nitride is deposited to form a barrier material layer 60. The barrier material layer 60 is continuous and covers the first sidewall structure 50a, the second sidewall structure 50b, the substrate 10 partially exposed to the first channel hole 23, and the first stacked layer 20 partially exposed in the groove 31.

[0135] It should be noted that the barrier material layer 60 also includes a first barrier layer 61 and a second barrier layer 62 in succession, wherein the first barrier layer 61 covers the third barrier layer 52 of the first sidewall structure 50a and covers the substrate exposed in the first channel hole 23; the second barrier layer 62 covers the second sidewall structure 50b and the surface of the first stacked layer 20 exposed in the groove.

[0136] After forming the barrier material layer 60 in the first channel hole 23 and the groove 31, step S700 is performed: a contact pad 72 and a first conductive plug 71 are formed in the groove 31 and the first channel hole 23, respectively. The first conductive plug 71, the first barrier layer 61, and the first sidewall structure 50a constitute the first through structure 70. The contact pad 72 completely covers the first through structure 70, and the bottom dimension of the contact pad 72 is larger than the top dimension of the first through structure 70. The structure formed in this step is as follows: Figure 15 As shown.

[0137] Specifically, using the first channel hole and groove 31 as deposition channels, metallic tungsten is deposited in the first channel hole 23 and groove 31, thereby forming a first conductive plug 71 in the first channel hole 23. The first barrier layer 61 surrounds and contacts the sidewall of the first conductive plug 71, and the bottom of the first conductive plug 71 contacts the first barrier layer 61. The first sidewall structure 50a, the first barrier layer 61 and the first conductive plug 71 constitute the first through structure 70.

[0138] A contact pad 72 is formed within the groove 31, wherein the contact pad 72 is located on top of the first conductive plug 71, and the two are integrally formed. The contact pad 72 completely covers the first through structure 70, and the bottom dimension of the contact pad 72 is larger than the top dimension of the first through structure 70.

[0139] This configuration increases the contact area between the subsequent second through-structure 90 and the contact pad 72. It should be noted that after the first conductive plug 71 and the contact pad 72 are formed, the top of the first through-structure 70 can be mechanically ground to make the contact pad 72 flat away from the surface of the first conductive plug 71.

[0140] After forming contact pads 72 and first conductive plugs 71 in the groove 31 and the first channel hole 23 respectively, step S800 can be performed: a second stacked layer 80 is formed on the first stacked layer 20. The second stacked layer 80 has a second through structure 90 that contacts a portion of the contact pads 72, and the first through structure 70, contact pads 72, and second through structure 90 are staggered. Further, the second through structure 90 includes a second conductive plug 91, and the second conductive plug 91 is at least partially in contact with the contact pads 72.

[0141] It should be noted that this step can be referred to in the example of the first stacked layer 20 and the formation of the first through structure 70 therein, and will not be repeated here. The structure formed by this step is as follows: Figure 1 As shown. It should be noted that the top of the second through structure 90 does not have a contact pad 72, so the process of making the contact pad 72 and related processes, such as the process of forming a groove on the top of the stacked layer, can be omitted.

[0142] Based on the above embodiments, such as Figure 3 As shown, in the preparation method provided in this application embodiment, step S300: etching the isolation layer 30 and the first stacked layer 20 includes:

[0143] Step S310: Form a first mask pattern 41 on the isolation layer 30. Specifically, a mask layer 40 is formed on the isolation layer 30, covering the isolation layer 30. The structure formed in this step is as follows: Figure 5 As shown. Further, the mask layer 40 is exposed and etched, and a first mask pattern 41 is formed on the isolation layer 30. The structure formed in this step is as follows. Figure 6 As shown.

[0144] Step S320: Use the first mask pattern 41 to etch the isolation layer 30 and the first stacked layer 20 to form the first channel hole 23.

[0145] Specifically, using the first mask pattern 41 of the mask layer 40, the isolation layer 30 and the first stacked layer 20 are vertically etched, and this etching can stop at the etch stop layer 11, thereby removing part of the isolation layer 30 and part of the first stacked layer 20 to form the first channel via 23; the structure formed by this step is as follows Figure 7 As shown.

[0146] Step S330: Etch the first mask pattern 41 to form the second mask pattern 42.

[0147] Specifically, the first mask pattern 41 is exposed and etched again to form the second mask pattern 42 on the isolation layer 30. The structure formed by this step is as follows: Figure 8 As shown.

[0148] Step S340: The isolation layer 30 is etched using the second mask pattern 42 to form a groove 31 communicating with the first channel hole 23 within the isolation layer 30. The structure formed in this step is as follows: Figure 9 As shown.

[0149] Specifically, the isolation layer 30 is partially etched using the second mask pattern 42 to form a groove 31 corresponding to the first channel hole 23 within the isolation layer 30, and the bottom of the groove 31 is connected to the first channel hole 23. This arrangement, using two mask patterns to form the groove 31 and the first channel hole 23, ensures the etching precision of both.

[0150] It should be noted that after completing step S340, the process also includes removing the second mask pattern 42 located on the isolation layer 30. The structure formed by this step is as follows: Figure 10 As shown.

[0151] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0152] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The first stacked layer includes a plurality of alternating first dielectric layers and a plurality of first conductive layers disposed on the substrate; The second stacked layer includes a plurality of alternately arranged second dielectric layers and a plurality of second conductive layers disposed on the first stacked layer; An isolation layer is located between the first stacked layer and the second stacked layer; A first channel hole is located within the first stacked layer and has a first width, and a first sidewall structure and a first conductive plug are sequentially disposed on the inner sidewall of the first channel hole. A groove, located within the isolation layer and having a second width, has a second sidewall structure and a contact pad sequentially disposed on the inner sidewall of the groove; wherein the groove is in communication with the first channel hole; Wherein, the second width is greater than the first width, the first conductive plug and the contact pad are integrally formed, and the first conductive plug and the contact pad isolate the first sidewall structure and the second sidewall structure from each other.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a first barrier layer and a second barrier layer. The first barrier layer is disposed between the first sidewall structure and the first conductive plug and is in contact with a portion of the substrate. The second barrier layer is disposed on the sidewall and bottom surface of the contact pad, and contacts the contact pad, the second sidewall structure and a portion of the first stacked layer, respectively.

3. The semiconductor structure according to claim 2, characterized in that, The first barrier layer and the second barrier layer are an integral structure.

4. The semiconductor structure according to claim 3, characterized in that, The first barrier layer is in contact with a portion of the bottom surface of the contact pad and the first conductive plug.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The second stacked layer is further provided with a second through structure, which is disposed on the contact pad and at least partially contacts the contact pad; The first sidewall structure, the first barrier layer disposed on the first sidewall structure, and the first conductive plug constitute a first through structure, wherein the bottom dimension of the contact pad is larger than the top dimension of the first through structure.

6. The semiconductor structure according to claim 5, characterized in that, The first through-structure, the contact pad, and the second through-structure are arranged in a staggered manner.

7. The semiconductor structure according to claim 1, characterized in that, The first sidewall structure and the second sidewall structure comprise the same material layer.

8. The semiconductor structure according to claim 7, characterized in that, The first sidewall structure and the second sidewall structure include a metal oxide layer and a third barrier layer disposed sequentially.

9. A semiconductor structure, characterized in that, include: Substrate; A first stacked layer and an isolation layer are stacked on the substrate; A T-shaped contact structure is disposed in the first stacked layer and the isolation layer. The T-shaped contact structure includes a lower part with a first width and an upper part with a second width. The first width is smaller than the second width, and the lower part and the upper part are integral structures. The first sidewall structure is disposed on the lower sidewall of the T-shaped contact structure; The second sidewall structure is disposed on the upper sidewall of the T-shaped contact structure; The first sidewall structure and the second sidewall structure are discontinuous.

10. The semiconductor structure according to claim 9, characterized in that, The T-shaped contact structure includes a barrier layer and a metal layer, with the barrier layer covering the outer peripheral surface and bottom surface of the metal layer.

11. The semiconductor structure according to claim 10, characterized in that, The first stacked layer is provided with a first channel hole, the isolation layer is provided with a groove, the groove and the first channel hole are interconnected, the lower part is located in the first channel hole, and the upper part is located in the groove; The first sidewall structure and the T-shaped contact structure, which are located within the first channel hole and are stacked sequentially, constitute the first through structure.

12. The semiconductor structure according to claim 11, characterized in that, The barrier layer located in the first channel hole constitutes a first barrier layer, the metal layer located in the first channel hole constitutes a first conductive plug, the barrier layer located in the groove constitutes a second barrier layer, and the metal layer located in the groove constitutes a contact pad. The first barrier layer is in contact with the first sidewall structure and a portion of the substrate, respectively; The second barrier layer contacts the contact pad, the second sidewall structure, and a portion of the first stacked layer.

13. The semiconductor structure according to claim 12, characterized in that, The bottom dimension of the contact pad is larger than the top dimension of the first through structure.

14. The semiconductor structure according to claim 13, characterized in that, The first barrier layer is in contact with a portion of the bottom surface of the contact pad.

15. The semiconductor structure according to claim 13 or 14, characterized in that, The semiconductor structure further includes a second stacked layer, and a second through-structure is disposed within the second stacked layer. The second through-structure is disposed on the contact pad and at least partially contacts the contact pad.

16. The semiconductor structure according to claim 15, characterized in that, The first through-structure, the contact pad, and the second through-structure are arranged in a staggered manner.

17. The semiconductor structure according to claim 15, characterized in that, Both the first stacked layer and the second stacked layer include alternating dielectric and conductive layers.

18. The semiconductor structure according to claim 9, characterized in that, The first sidewall structure and the second sidewall structure comprise the same material layer.

19. The semiconductor structure according to claim 18, characterized in that, The first sidewall structure and the second sidewall structure include a metal oxide layer and a third barrier layer disposed sequentially.

20. A semiconductor structure, characterized in that, include: Substrate; A first stacked layer and an isolation layer are stacked on the substrate; An integral contact structure is disposed in the first stacked layer. The integral contact structure includes a lower part with a first width and an upper part with a second width, wherein the first width is smaller than the second width. A first sidewall structure is disposed on the lower sidewall of the integral contact structure; The second sidewall structure is disposed on the upper sidewall of the integral contact structure; The projections of the first sidewall structure and the second sidewall structure do not overlap in the horizontal direction.

21. The semiconductor structure according to claim 20, characterized in that, The integrated contact structure includes a barrier layer and a metal layer, with the barrier layer covering the outer peripheral surface and bottom surface of the metal layer.

22. The semiconductor structure according to claim 21, characterized in that, The first stacked layer is provided with a first channel hole, the isolation layer is provided with a groove, the groove and the first channel hole are interconnected, the lower part is located in the first channel hole, and the upper part is located in the groove; The first sidewall structure and the integral contact structure, which are located within the first channel hole and are stacked sequentially, constitute the first through structure.

23. The semiconductor structure according to claim 22, characterized in that, The barrier layer located in the first channel hole constitutes a first barrier layer, the metal layer located in the first channel hole constitutes a first conductive plug, the barrier layer located in the groove constitutes a second barrier layer, and the metal layer located in the groove constitutes a contact pad. The first barrier layer is in contact with the first sidewall structure and a portion of the substrate, respectively; The second barrier layer contacts the contact pad, the second sidewall structure, and a portion of the first stacked layer.

24. The semiconductor structure according to claim 23, characterized in that, The first barrier layer contacts a portion of the bottom surface of the contact pad; and / or, the bottom dimension of the contact pad is larger than the top dimension of the first through-structure.

25. The semiconductor structure according to claim 23 or 24, characterized in that, The semiconductor structure further includes a second stacked layer, and a second through-structure is disposed within the second stacked layer. The second through-structure is disposed on the contact pad and at least partially contacts the contact pad.

26. The semiconductor structure according to claim 25, characterized in that, The first through-structure, the contact pad, and the second through-structure are arranged in a staggered manner.

27. The semiconductor structure according to claim 25, characterized in that, Both the first stacked layer and the second stacked layer include alternating dielectric and conductive layers.

28. The semiconductor structure according to claim 20, characterized in that, The first sidewall structure and the second sidewall structure comprise the same material layer.

29. The semiconductor structure according to claim 28, characterized in that, The first sidewall structure and the second sidewall structure include a metal oxide layer and a third barrier layer disposed sequentially.

30. A semiconductor structure, characterized in that, include: Substrate; A first stacked layer and an isolation layer are stacked on the substrate; An integral contact structure is disposed in the first stacked layer and the isolation layer. The integral contact structure includes a lower part with a first width and an upper part with a second width. The first width is smaller than the second width, and the bottom surface of the upper part directly contacts the first stacked layer. A first sidewall structure is disposed on the lower sidewall of the integral contact structure; The second sidewall structure is disposed on the upper sidewall of the integral contact structure.

31. The semiconductor structure according to claim 30, characterized in that, The integrated contact structure includes a barrier layer and a metal layer, with the barrier layer covering the outer peripheral surface and bottom surface of the metal layer.

32. The semiconductor structure according to claim 31, characterized in that, The first stacked layer is provided with a first channel hole, the isolation layer is provided with a groove, the groove and the first channel hole are interconnected, the lower part is located in the first channel hole, and the upper part is located in the groove; The first sidewall structure and the integral contact structure, which are located within the first channel hole and are stacked sequentially, constitute the first through structure.

33. The semiconductor structure according to claim 32, characterized in that, The barrier layer located in the first channel hole constitutes a first barrier layer, the metal layer located in the first channel hole constitutes a first conductive plug, the barrier layer located in the groove constitutes a second barrier layer, and the metal layer located in the groove constitutes a contact pad. The first barrier layer is in contact with the first sidewall structure and a portion of the substrate, respectively; The second barrier layer contacts the contact pad, the second sidewall structure, and a portion of the first stacked layer.

34. The semiconductor structure according to claim 33, characterized in that, The first barrier layer contacts a portion of the bottom surface of the contact pad; and / or, the bottom dimension of the contact pad is larger than the top dimension of the first through-structure.

35. The semiconductor structure according to claim 33 or 34, characterized in that, The semiconductor structure further includes a second stacked layer, and a second through-structure is disposed within the second stacked layer. The second through-structure is disposed on the contact pad and at least partially contacts the contact pad.

36. The semiconductor structure according to claim 35, characterized in that, The first through-structure, the contact pad, and the second through-structure are arranged in a staggered manner.

37. The semiconductor structure according to claim 35, characterized in that, Both the first stacked layer and the second stacked layer include alternating dielectric and conductive layers.

38. The semiconductor structure according to claim 30, characterized in that, The first sidewall structure and the second sidewall structure comprise the same material layer.

39. The semiconductor structure according to claim 38, characterized in that, The first sidewall structure and the second sidewall structure include a metal oxide layer and a third barrier layer disposed sequentially.

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