Nord flash memory device and method of manufacturing the same
By forming the first sidewall of the step and relocating the etching defect point during the fabrication process of the NORD flash memory device, the problem of third sidewall breakage and exposure is solved, device failure is avoided, and the normal operation of the device is ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-07-10
AI Technical Summary
Existing NORD flash memory devices suffer from problems such as the third sidewall tip breaking when the first sidewall etching process window is small, and the third sidewall tip being exposed after the word line polysilicon layer is ground and etched back, leading to device failure.
By defining a first window on the hard mask layer, forming a first isolation layer and a first sidewall, and performing a thinning process to form a step, the second sidewall and the third sidewall are then deposited sequentially to avoid etching process defects at the top corner of the control gate and to transfer them to the top corner of the hard mask layer.
The problem of the third sidewall breaking and being exposed at the top of the control grid was solved, avoiding short circuits between the control grid and the word lines and ensuring normal device operation.
Smart Images
Figure CN122373347A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a NORD flash memory device and its fabrication method. Background Technology
[0002] Flash memory is a type of non-volatile memory that retains data for an extended period even without a power supply, meaning data is not lost when power is off. Flash memory is primarily divided into two types: NORD and NAND, commonly referred to as NORD Flash and NAND Flash. NORD Flash, also known as coded flash memory, has become the mainstream non-volatile memory technology due to its characteristics such as direct code execution, high reliability, and fast read speed.
[0003] Figures 1A to 1F This is a schematic diagram showing the structural steps involved in the fabrication of a NORD flash memory process. For example... Figure 1A As shown, a gate oxide layer 101, a gate stack on the gate oxide layer 101, and a hard mask layer 105 on the gate stack are sequentially formed on the substrate 100. The gate stack includes, from bottom to top, a floating gate polysilicon layer 102, an inter-gate dielectric layer, and a control gate polysilicon layer 104. The inter-gate dielectric layer includes an ONO structure composed of a first oxide layer 103a, a nitride layer 103b, and a second oxide layer 103c stacked from bottom to top. First, the hard mask layer 105 is patterned (FGSN_ET) to define a first window 110. Then, as... Figure 1B As shown, a first sidewall 106 (FGSP DEP / ET) is formed on the sidewalls of the patterned hard mask layer 105, defining the second window 120. Next, as... Figure 1C and Figure 1D As shown, the control gate polysilicon layer 104 (CGPL_ET) and the inter-gate dielectric layer are etched along the second window 120. Next, as... Figure 1E As shown, a second side wall 107 and a third side wall 108 (OFFSET OX / SIN DEP&ET) are formed along the second window 120. Next, as... Figure 1F As shown, the floating gate polysilicon layer 102 and the gate oxide layer 101 (FGPL1_ET) are etched to form a word line window 130.
[0004] refer to Figure 2A , Figure 2B and Figure 2CAs shown, in the above manufacturing process, during the formation of the first sidewall 106, the etching process window is relatively small. If the over-etched portion (OE amount) is too small, the third sidewall 108 (OFFSET OX SIN) will easily be exposed after the subsequent formation of the control gate polysilicon layer undergoes chemical mechanical polishing (MPL_CMP). It will then be removed during the hard mask layer 105 removal (FGSN removal). Figure 2B As shown; this is generally improved by reducing CMP time, but the improvement is not significant. If there is too much over-etched area (OE amount), the sidewall of the first sidewall (FGSP) is relatively tilted. After the second sidewall 107 is formed (OFFSET OX_ET), the third sidewall (OFFSET OX SIN) 108 is prone to breakage, such as... Figure 2C As shown, this leads to device failure. Summary of the Invention
[0005] The purpose of this invention is to provide a NORD flash memory device and its manufacturing method to solve the problems of the third sidewall top being broken due to the small etching process window of the first sidewall and the exposure of the third sidewall top after the polysilicon layer of the word line is ground and etched back.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing a NORD flash memory device, comprising:
[0007] A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top;
[0008] Pattern the hard mask layer to define a first window;
[0009] A first isolation layer and a first sidewall located on the first isolation layer are formed within the first window, and a second window is defined.
[0010] The first sidewall is thinned so that a step is formed between the first sidewall and the isolation layer;
[0011] Etch the control gate polysilicon layer and the inter-gate dielectric layer along the second window;
[0012] A second sidewall and a third sidewall are formed sequentially, the second sidewall at least covering the sidewall of the control gate polysilicon layer, and the third sidewall covering the second sidewall, the step, and a portion of the first sidewall; and...
[0013] The floating gate polysilicon layer is etched to define the word line window.
[0014] Optionally, the isolation layer is deposited using the HTO process, and the first sidewall is deposited using the TEOS process.
[0015] Optionally, the deposition of the isolation layer using the HTO process and the deposition of the first sidewall using the TEOS process do not include RTO densification of the deposited isolation layer and the first sidewall.
[0016] Optionally, the wet etching rate of the first sidewall / the wet etching rate of the isolation layer is greater than 2.
[0017] Optionally, a gate oxide layer is formed on the substrate, and the gate stack is formed on the gate oxide layer.
[0018] Optionally, the inter-gate dielectric layer includes an ONO structure consisting of a first oxide layer, a nitride layer, and a second oxide layer stacked from bottom to top.
[0019] Optionally, after etching the floating gate polysilicon layer, the process further includes:
[0020] A tunneling oxide layer is formed on the sidewall of the character line window;
[0021] A polysilicon layer for word lines is filled into the word line window;
[0022] The polysilicon layer for the word lines is subjected to chemical mechanical polishing and etch-back.
[0023] Optionally, the isolation layer is L-shaped, and the thickness of the isolation layer is 200 angstroms to 300 angstroms.
[0024] Optionally, the isolation layer is an oxide layer, the first sidewall is an oxide layer, the second sidewall is an oxide layer, and the third sidewall is a nitrided layer.
[0025] In summary, this invention provides a NORD flash memory device and its fabrication method. A first window is formed by patterning a hard mask layer above the gate stack. An isolation layer and a first sidewall are formed within the first window using different deposition processes. A step is formed during the thinning process of the first sidewall using the etching ratio of the two. This shifts the location of weak points, which are prone to defects in the etching process, upwards during the deposition of the second and third sidewalls, rather than at the top corner of the control gate. This solves the problems of the third sidewall breaking at the top of the control gate due to the small etching window of the first sidewall and the exposure of the top of the third sidewall after the polysilicon layer of the word line is ground and etched back. This avoids short circuits between the control gate and the word line, thereby preventing device failure. Attached Figure Description
[0026] Figures 1A to 1F This is a schematic diagram of the structure corresponding to each step in the fabrication method of a NORD flash memory device;
[0027] Figures 2A to 2C Electron microscope image of a NORD flash memory device;
[0028] Figure 3 A schematic flowchart illustrating the fabrication method of a NORD flash memory device provided in an embodiment of the present invention;
[0029] Figures 4A to 4F This is a schematic diagram of the structure corresponding to each step in the fabrication method of a NORD flash memory device according to an embodiment of the present invention. Detailed Implementation
[0030] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.
[0031] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.
[0032] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.
[0033] Figure 3 Figure 1 shows a flowchart illustrating a method for fabricating a NORD flash memory device according to an embodiment of the present invention. The method for fabricating a NORD flash memory device according to this embodiment includes the following steps:
[0034] Step S01: Provide a semiconductor structure, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top;
[0035] Step S02: Pattern the hard mask layer, define a first window, and retain a portion of the thickness of the hard mask layer at the location of the first window;
[0036] Step S03: Form a first isolation layer and a first sidewall located on the first isolation layer within the first window, and define a second window;
[0037] Step S04: Thin the first sidewall so that a step is formed between the first sidewall and the isolation layer;
[0038] Step S05: Etch the control gate polysilicon layer and the inter-gate dielectric layer along the second window;
[0039] Step S06: Sequentially form a second sidewall and a third sidewall, wherein the second sidewall at least covers the sidewall of the control gate polysilicon layer, and the third sidewall covers the second sidewall, the step, and a portion of the first sidewall; and,
[0040] Step S07: Etch the floating gate polysilicon layer to define the word line window.
[0041] Figures 4A to 4F This is a schematic diagram showing the structural steps corresponding to each step in the fabrication method of a NORD flash memory device according to an embodiment of the present invention. Please refer to... Figure 3 As shown, and in combination Figures 4A to 4F This invention provides a detailed description of the fabrication method for the NORD flash memory device.
[0042] First, refer to Figure 2A As shown, steps S01 and S02 are performed to provide a semiconductor structure, which includes a substrate 200, a gate stack on the substrate 200, and a hard mask layer 205 on the gate stack. The gate stack includes, from bottom to top, a floating gate polysilicon layer 202, an inter-gate dielectric layer, and a control gate polysilicon layer 204. The hard mask layer 205 (FGSN_ET) is patterned, and a first window 210 is defined.
[0043] Specifically, the substrate 200 can be a silicon substrate, and the inter-gate dielectric layer includes an ONO structure composed of a first oxide layer 203a, a nitride layer 203b, and a second oxide layer 203c stacked from bottom to top. For example, the first oxide layer 203a and the second oxide layer 203c are silicon oxide layers, and the nitride layer 203b is a silicon nitride layer. The hard mask layer 205 is located on the control gate polysilicon layer 204, and the material of the hard mask layer 205 is at least one of silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbide nitride, and silicon oxynitride.
[0044] A gate oxide layer 201 is formed on the substrate 200, and the gate stack is located on the gate oxide layer 201. The gate oxide layer 201 can be formed by methods such as low-pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy. The material of the gate oxide layer 201 is silicon oxide to enhance the interfacial adhesion between layers.
[0045] Next, refer to Figure 4B As shown, step S03 is executed to form a first isolation layer 206 and a first sidewall 206b located on the first isolation layer 206a within the first window 210, and to define a second window 220.
[0046] Specifically, the isolation layer 206a and the first sidewall 206b are oxide layers, such as silicon dioxide layers, and the thickness of the isolation layer 206a is 200 angstroms to 300 angstroms. The isolation layer 206a can be deposited sequentially using a High Temperature Oxide (HTO) process, and the first sidewall 206b can be deposited using a TEOS process. Then, an L-shaped isolation layer 206a and a first sidewall 206b located on the L-shaped isolation layer 206a are formed by an etching process. It should be noted that the deposition of the isolation layer 206a using the HTO process and the deposition of the first sidewall 206b using the TEOS process do not include RTO densification treatment of the deposited isolation layer 206a and the first sidewall 206b. The wet etching rate of the isolation layer 206a and the first sidewall 206b without RTO densification is greater than 2, which makes it easy for the first sidewall 206b to form a step with the isolation layer 206a during the subsequent thinning process of the first sidewall 206b.
[0047] On the other hand, in this embodiment, the isolation layer 206a and the first sidewall 206b are formed by HTO deposition and TEOS process, which will not affect the opening size of the first window, nor will it affect the etching of the control gate, and the critical dimensions of subsequent processes will not be interfered with.
[0048] Next, refer to Figure 4C As shown, in step S04, the first sidewall 206b is thinned to form a step 209 between the first sidewall 206b and the isolation layer 206a. For example, the first sidewall 206b is thinned by wet cleaning. Since the isolation layer 206a and the first sidewall 206b are formed by different methods, their etching rates are different. The wet cleaning process increases the interface difference between the isolation layer 206a formed by the HTO process and the first sidewall 206b formed by the TEOS process.
[0049] Next, refer to Figure 4DAs shown, step S05 is performed, etching the control gate polysilicon layer 204 and the inter-gate dielectric layer along the second window 220 until the floating gate polysilicon layer 202 is exposed.
[0050] Next, continue to refer to Figure 4E As shown, in step S06, a second sidewall 207 (OFFSET OX) and a third sidewall 208 (OFFSET SIN) are formed sequentially. The second sidewall 207 at least covers the sidewall of the control gate polysilicon layer 204, and the third sidewall 208 covers the second sidewall 207, the step 209, and part of the first sidewall 206.
[0051] In the above steps, when the first sidewall 206b and the isolation layer 206a form a step 209, and the second sidewall 207 and the third sidewall 208 are deposited, the third sidewall (OFFSET SIN) 208 covers the step 209, shifting the position of the weak point that is prone to be generated by the etching process upwards, instead of the top corner of the control gate 204. Even if the third sidewall 208 breaks during the subsequent grinding and re-etching of the word line polysilicon layer, the break point is at the top corner of the retained hard mask layer 205, rather than the top corner of the selected gate, thereby avoiding a short circuit between the control gate and the word line.
[0052] Next, refer to Figure 4F As shown, step S07 is executed to etch the floating gate polysilicon layer 202 and define the word line window 230.
[0053] Furthermore, the method for fabricating the NORD flash memory device provided in this embodiment of the invention further includes: after etching the floating gate polysilicon layer 202, forming a tunneling oxide layer on the sidewall of the word line window 230; filling the word line window with a word line polysilicon layer; and performing chemical mechanical polishing and etch-back on the word line polysilicon layer.
[0054] Because this invention shifts the location of the weak point that is prone to occur in the etching process to the top corner of the third sidewall 208 instead of the top corner of the control gate 204 when forming the second sidewall 207 and the third sidewall 208, it solves the problem of the top of the third sidewall 208 (OFFSET SIN) being exposed when the word line polysilicon layer is chemically mechanically polished and etched back when the first sidewall 206 has too little etched portion (OE amount), and the problem of the third sidewall 208 (OFFSET SIN) breaking at the top of the control gate when the first sidewall 206 has too much etched portion (OE amount). In other words, it solves the problem of insufficient process window between the breakage of the OFFSET SIN top and the exposure of the OFFSET SIN top after MPL_CMP, without adding any additional process steps.
[0055] In summary, this invention provides a NORD flash memory device and its fabrication method. A first window is formed by patterning a hard mask layer above the gate stack. An isolation layer and a first sidewall are formed within the first window using different deposition processes. A step is formed during the thinning process of the first sidewall using the etching ratio of the two. This shifts the location of weak points, which are prone to defects in the etching process, upwards rather than at the top corner of the control gate during the deposition of the second and third sidewalls. This solves the problems of the third sidewall breaking at the top of the control gate due to the small etching window of the first sidewall and the exposure of the top of the third sidewall after the polysilicon layer of the word line is ground and etched back. This avoids short circuits between the control gate and the word line, thereby preventing device failure.
[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for fabricating a NORD flash memory device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top; Pattern the hard mask layer to define a first window; A first isolation layer and a first sidewall located on the first isolation layer are formed within the first window, and a second window is defined. The first sidewall is thinned so that a step is formed between the first sidewall and the isolation layer; Etch the control gate polysilicon layer and the inter-gate dielectric layer along the second window; A second sidewall and a third sidewall are formed sequentially, the second sidewall at least covering the sidewall of the control gate polysilicon layer, and the third sidewall covering the second sidewall, the step, and a portion of the first sidewall; and... The floating gate polysilicon layer is etched to define the word line window.
2. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The isolation layer is deposited using the HTO process, and the first sidewall is deposited using the TEOS process.
3. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The deposition of the isolation layer using the HTO process and the deposition of the first sidewall using the TEOS process do not include RTO densification of the deposited isolation layer and the first sidewall.
4. The method for fabricating a NORD flash memory device according to claim 3, characterized in that, The wet etching rate of the first sidewall / the wet etching rate of the isolation layer is greater than 2.
5. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, A gate oxide layer is formed on the substrate, and the gate stack is formed on the gate oxide layer.
6. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The inter-gate dielectric layer comprises an ONO structure consisting of a first oxide layer, a nitride layer, and a second oxide layer stacked from bottom to top.
7. The method for fabricating a NORD flash memory device according to claim 6, characterized in that, After etching the floating gate polysilicon layer, the process further includes: A tunneling oxide layer is formed on the sidewall of the character line window; A polysilicon layer for word lines is filled into the word line window; The polysilicon layer for the word lines is subjected to chemical mechanical polishing and etch-back.
8. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The isolation layer is L-shaped and has a thickness of 200 to 300 angstroms.
9. The method for manufacturing a NORD flash memory device according to claim 1, characterized in that, The isolation layer is an oxide layer, the first sidewall is an oxide layer, the second sidewall is an oxide layer, and the third sidewall is a nitrided layer.