Semiconductor element and method for manufacturing the same
By combining high-frequency diamond grinding wheels with plasma etching, the wafer warpage problem was solved, forming a TiSi-NiV-Ag drain electrode structure, which improved the wafer processing stability and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HON YOUNG SEMICON CORP
- Filing Date
- 2025-01-10
- Publication Date
- 2026-07-10
AI Technical Summary
As wafer thickness decreases, warpage becomes increasingly serious, affecting subsequent processes, transportation, and measurement. Existing technologies are unable to effectively solve wafer warpage and breakage problems.
High-grind diamond grinding wheels are used for grinding, combined with plasma etching to reduce or completely remove the damaged layer, and multilayer conductive layers are formed by deposition and annealing to repair the back side of the substrate, forming a TiSi-NiV-Ag drain electrode structure.
This effectively reduces stress accumulation on the back side of the substrate, lowers the risk of warpage, improves the yield of subsequent processes, and ensures wafer integrity.
Smart Images
Figure CN122373383A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] With the widespread application of power semiconductors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, and insulated-gate bipolar transistors (IGBTs), wafer thickness has been decreasing to reduce parasitic resistance and capacitance, thereby reducing overall power consumption and increasing integration density. Taking MOSFET technology as an example, the wafer must undergo a grinding process before entering the back-side etching process. However, the thinner the wafer, the more pronounced the warpage becomes due to stress accumulation, causing difficulties in subsequent processes, transportation, and measurement. Summary of the Invention
[0003] Some embodiments described herein provide a method for manufacturing a semiconductor device. The method includes: forming a device on a first side of a substrate; performing a polishing process on a second side of the substrate opposite to the first side to remove a portion of the substrate on the second side, wherein performing the polishing process forms a damage layer on the second side of the substrate, wherein the damage layer has a thickness; performing an etching process on the damage layer to reduce the thickness of the damage layer; and forming an electrode on the second side of the substrate, wherein forming the electrode includes: forming a first conductive layer on the second side of the substrate; forming a second conductive layer on the first conductive layer; and forming a third conductive layer on the second conductive layer.
[0004] Some embodiments described herein provide methods for manufacturing semiconductor devices, wherein a damaged layer has a non-zero thickness after an etching process is performed.
[0005] Some embodiments described herein provide methods for manufacturing semiconductor devices, wherein an etching process completely removes the damaged layer.
[0006] Some embodiments described herein provide methods for manufacturing semiconductor devices, wherein the polishing process is performed using a high-number diamond polishing wheel with an polishing pad having a particle size of 0.4 μm.
[0007] Some embodiments described herein provide a method for manufacturing a semiconductor device, wherein forming a first conductive layer includes: depositing a metal layer on a damaged layer; and performing an annealing process to silicide the metal layer into a metal silicide layer, wherein after the first conductive layer is formed, a second side of the substrate no longer has a damaged layer.
[0008] Some embodiments described herein provide methods for manufacturing semiconductor devices, wherein the metal layer is titanium, the metal silicide layer is titanium silicide, the second conductive layer is nickel vanadium, and the third conductive layer is silver.
[0009] Some embodiments described herein provide a semiconductor element comprising: a substrate; an element on a first side of the substrate; and an electrode on a second side of the substrate opposite to the first side, wherein the electrode comprises: a first conductive layer on the second side of the substrate, wherein the first conductive layer is a metal silicide; a second conductive layer on and in contact with the first conductive layer, wherein the second conductive layer is a metal alloy; and a third conductive layer on and in contact with the second conductive layer, wherein the third conductive layer is a pure metal.
[0010] Some embodiments described herein provide semiconductor devices in which the metal silicide is titanium, the metal alloy is nickel-vanadium, and the pure metal is silver.
[0011] Some embodiments described herein provide semiconductor devices in which the electrode is the drain electrode of the device.
[0012] Some embodiments described herein provide a semiconductor element that further includes a source electrode formed on a first side of a substrate. Attached Figure Description
[0013] The scope of the invention is best understood by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.
[0014] Figures 1 to 4 A cross-sectional view illustrating an intermediate stage of a semiconductor device process in some embodiments of the present invention is shown. Detailed Implementation
[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided objectives. Specific examples of elements and configurations are described below to simplify the content of the invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, the content of the invention may repeatedly refer to numbers and / or letters. This repetition is for simplicity and clarity and does not itself define the relationship between the various embodiments and / or configurations discussed.
[0016] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.
[0017] In this invention, a semiconductor device and a method for eliminating the damage layer (residual stress) on the semiconductor substrate of the semiconductor device caused by the polishing process are provided.
[0018] Figures 1 to 4 Cross-sectional views of intermediate stages of the semiconductor device 100 process in some embodiments of the present invention are illustrated. Please refer to... Figure 1 The semiconductor element 100 includes a semiconductor substrate 110. The substrate 110 may be made of any suitable material; in some embodiments, the substrate 110 is made of silicon carbide (SiC). In some embodiments, the semiconductor substrate 110 is an N-type semiconductor substrate.
[0019] like Figure 1 As shown, a P-type lightly doped region 119 is formed in the substrate 110. Specifically, a P-type lightly doped implantation can be performed on the substrate 110 to form a P-type lightly doped region 119 in the substrate 110.
[0020] like Figure 1 As shown, a P-type heavily doped region 116 is formed in the substrate 110. Specifically, P-type heavily doped implantation can be performed on the substrate 110 to form the P-type heavily doped region 116 in the substrate 110.
[0021] like Figure 1 As shown, an N-type heavily doped region 118 is formed in the substrate 110, and the N-type heavily doped region 118 is adjacent to the P-type heavily doped region 116. Specifically, N-type heavily doped implantation can be performed on the substrate 110 to form the N-type heavily doped region 118 in the substrate 110.
[0022] In addition, the P-type lightly doped region 119 contacts the bottom of the P-type heavily doped region 116 and the bottom of the N-type heavily doped region 118.
[0023] like Figure 1As shown, a gate dielectric layer 132 is formed on the substrate 110, and a gate layer 142 is formed on the gate dielectric layer 132. In some embodiments, the sidewalls of the gate dielectric layer 132 and the gate layer 142 may be aligned with each other. The gate dielectric layer 132 contacts the heavily doped N-type region 118, and the gate dielectric layer 132 covers the lightly doped P-type region 119 on the surface of the substrate 110. In this respect, the gate dielectric layer 132 may extend from one heavily doped N-type region 118 to another heavily doped N-type region 118.
[0024] Furthermore, a dielectric layer 150 can be formed on the gate dielectric layer 132 and the gate layer 142. Next, a source electrode 160 is formed in the dielectric layer 150. Specifically, the dielectric layer 150 can be formed on the gate dielectric layer 132 and the gate layer 142, covering the gate dielectric layer 132, the gate layer 142, and the substrate 110. Next, an opening is formed in the dielectric layer 150, and a source electrode 160 is formed in the opening. The source electrode 160 contacts the P-type heavily doped region 116 and the N-type heavily doped region 118.
[0025] Here, the P-type heavily doped region 116, the N-type heavily doped region 118, the P-type lightly doped region 119, the gate dielectric layer 132, and the gate layer 142 can be collectively referred to as a transistor element, wherein the transistor element and its source electrode 160 are formed on a first side (e.g., the front side) of the substrate 110. It should be understood that... Figure 1 The transistor elements shown are for illustrative purposes only, and the present invention is not limited thereto. In other embodiments, the semiconductor element 100 may have transistor elements with other structures.
[0026] Please refer to Figure 2 The semiconductor element 100 is flipped up and down. For example, it can be... Figure 1The structure of the substrate 110 is flipped, for example, by 180 degrees, so that the second side (e.g., the back side) of the substrate 110 faces upward. Next, subsequent processes, such as crystal back polishing and metallization, are performed on the back side of the substrate 110 of the semiconductor device 100. In some embodiments, a mechanical polishing process P1 is performed on the back side of the substrate 110 to thin the substrate 110 of the semiconductor device 100. For example, in some embodiments, the mechanical polishing process P1 can use a high-power diamond polishing wheel (e.g., the particle size of the polishing pad is about 0.4 μm) to polish the back surface of the substrate 110 to remove a portion of the back side of the substrate 110. However, the mechanical friction and thermal stress generated during polishing may cause a damaged layer 112D to form on the back side portion of the substrate 110. Defects such as micro-cracks or crystal dislocations in the damaged layer 112D will make the thinned semiconductor device 100 prone to significant warpage. Furthermore, if the stress accumulation on the back side of the substrate 110 of the semiconductor device 100 is too large, it may extend to the front side of the substrate 110, thereby affecting the devices on the front side of the substrate 110, or even causing wafer fracture, affecting the yield of subsequent processes.
[0027] like Figure 2 As shown, the damaged layer 112D has a thickness T1. In some embodiments, the thickness T1 may be less than 3.0 μm, for example, from about 0.3 μm to about 3.0 μm. Because the present invention uses a high-power diamond grinding wheel on the back side of the substrate 110, the thickness T1 of the damaged layer 112D can be reduced to the range described above. However, if a low-power diamond grinding wheel is used on the back side of the substrate 110, the thickness of the damaged layer 112D may be greater (e.g., equal to or greater than 3.0 μm), which will pose a risk of warping or cracking to the semiconductor device 100.
[0028] Please refer to Figure 3 An etching process P2 can be performed on the damaged layer 112D on the back side of the semiconductor device 100. In some embodiments, the etching process P2 can be a dry etching process, such as plasma etching. After performing the etching process P2, the damaged layer 112D has a thickness T2, which is a non-zero thickness and less than the thickness T1. In some embodiments, the thickness T2 can be approximately 1.0 μm to approximately 2.0 μm. In other embodiments, the damaged layer 112D can be completely removed, i.e. Figure 3 It no longer has the damaged layer 112D.
[0029] Please refer to Figure 4A first conductive layer 202 can be formed on the back side of the substrate 110 of the semiconductor element 100. In some embodiments, the first conductive layer 202 can be a metal silicide layer, such as titanium silicide (TiSi). For example, the metal silicide layer can be formed by depositing a metal layer (not shown) such as titanium (Ti) and then silicideting the metal layer into a metal silicide layer by an annealing process. In some embodiments, the annealing process can be a laser annealing process.
[0030] In some embodiments, the annealing process performed during the formation of the first conductive layer 202 not only silicides the metal layer on the back side of the semiconductor substrate 110 into a metal silicide layer, but also repairs the damaged layer 112D on the back surface of the semiconductor substrate 110. Therefore, after the formation of the first conductive layer 202, the back side of the substrate 110 no longer has the damaged layer 112D.
[0031] like Figure 2 As shown, in some embodiments, the repaired substrate 110 has a thickness T3, which ranges from about 95 μm to about 105 μm, for example, 100 μm.
[0032] In addition, such as Figure 4 As shown, a second conductive layer 204 can be deposited on the first conductive layer 202. In some embodiments, the second conductive layer 204 may contain a conductive material such as nickel vanadium (NiV). Next, a third conductive layer 206 is deposited on the second conductive layer 204. In some embodiments, the third conductive layer 206 may contain a conductive material such as silver (Ag). The stack of the first conductive layer 202, the second conductive layer 204, and the third conductive layer 206 on the back side of the semiconductor substrate 110 forms a drain electrode 200, wherein the drain electrode 200 is electrically connected to a transistor element on the front side of the substrate 110. In some embodiments, the stack of the first conductive layer 202, the second conductive layer 204, and the third conductive layer 206 is a TiSi-NiV-Ag structure.
[0033] In summary, the present invention provides embodiments in which a damaged layer on the back surface of a semiconductor substrate can be reduced or removed by using a high-repetition diamond grinding wheel and plasma etching, resulting in no stress accumulation on the surface of the semiconductor device and allowing subsequent processes to proceed. Furthermore, embodiments of the present invention provide a semiconductor device having a drain electrode formed by a stack of a first conductive layer, a second conductive layer, and a third conductive layer.
[0034] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will understand that the invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.
[0035] [Symbol Explanation]
[0036] 100: Semiconductor components
[0037] 110: Substrate
[0038] 112D: Damaged layer
[0039] 116: P-type heavily doped region
[0040] 118: N-type heavily doped region
[0041] 119: Lightly doped P-type region
[0042] 132: Gate dielectric layer
[0043] 142: Gate layer
[0044] 150: Dielectric layer
[0045] 160: Source electrode
[0046] 200: Drain electrode
[0047] 202: First conductive layer
[0048] 204: Second conductive layer
[0049] 206: Third conductive layer
[0050] P1, P2: Process
[0051] T1, T2, T3: Thickness.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Include: The element is formed on the first side of the substrate; A polishing process is performed on a second side of the substrate relative to the first side to remove a portion of the substrate on the second side, wherein the polishing process forms a damage layer on the second side of the substrate, wherein the damage layer has a thickness. An etching process is performed on the damaged layer to reduce its thickness; as well as An electrode is formed on the second side of the substrate, wherein forming the electrode includes: A first conductive layer is formed on the second side of the substrate; A second conductive layer is formed on the first conductive layer; as well as A third conductive layer is formed on the second conductive layer.
2. The method of claim 1, wherein the damaged layer has a non-zero thickness after the etching process is performed.
3. The method of claim 1, wherein the etching process completely removes the damaged layer.
4. The method of claim 1, wherein the grinding process is performed using a high-number diamond grinding wheel with a grinding pad having a particle size of 0.4 μm.
5. The method of claim 1, wherein forming the first conductive layer comprises: A metal layer is deposited on the damaged layer; and An annealing process is performed to silicide the metal layer into a metal silicide layer, wherein after the first conductive layer is formed, the second side of the substrate no longer has the damage layer.
6. The method according to claim 5, wherein the metal layer is titanium, the metal silicide layer is titanium silicide, the second conductive layer is nickel vanadium, and the third conductive layer is silver.
7. A semiconductor element, characterized in that, Include: substrate; Components, on the first side of the substrate; and An electrode is located on a second side of the substrate opposite to the first side, wherein the electrode comprises: A first conductive layer is disposed on the second side of the substrate, wherein the first conductive layer is a metal silicide; A second conductive layer is disposed on and in contact with the first conductive layer, wherein the second conductive layer is a metal alloy; and A third conductive layer is placed on and in contact with the second conductive layer, wherein the third conductive layer is a pure metal.
8. The semiconductor device according to claim 7, wherein the metal silicide is titanium, the metal alloy is nickel-vanadium, and the pure metal is silver.
9. The semiconductor device according to claim 7, wherein the electrode is the drain electrode of the device.
10. The semiconductor device of claim 9, further comprising forming a source electrode of the device on the first side of the substrate.