High electron mobility transistor with field plate

Abstract

The present disclosure relates to semiconductor structures, and more particularly to high electron mobility transistors with field plates and methods of manufacture. The structure includes a gate structure on a semiconductor substrate, a passivation layer adjacent the gate structure and over the semiconductor substrate, an insulator material over the passivation layer, and a field plate including a first portion in contact with the passivation layer and a second portion separated from the passivation layer by the insulator material.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more specifically to high electron mobility transistors with field plates and methods of manufacturing them. Background Technology

[0002] High electron mobility transistors (HEMTs) are field-effect transistors that contain a junction (i.e., a heterojunction) between two materials with different band gaps as a channel. HEMT transistors can operate at higher frequencies than ordinary transistors, such as up to millimeter-wave frequencies, and are used in high-frequency products such as cellular phones, satellite TV receivers, voltage converters, microwave and millimeter-wave communications, radio astronomy, power switching, and radar equipment. HEMTs can also be used in satellite receivers in low-power amplifiers. Summary of the Invention

[0003] In one aspect of this disclosure, a structure includes: a gate structure located on a semiconductor substrate; a passivation layer adjacent to the gate structure and located above the semiconductor substrate; an insulating material located above the passivation layer; and a field plate including a first portion in contact with the passivation layer and a second portion separated from the passivation layer by the insulating material.

[0004] In one aspect of this disclosure, a structure includes: a gate structure; a source region including a first ohmic contact adjacent to a first side of the gate structure; a drain region including a second ohmic contact adjacent to a second side of the gate structure; a passivation layer located between the gate structure and the drain region; a field plate including a first portion contacting a first portion of the passivation layer and a second portion separated from a second portion of the passivation layer; and an insulating material located between the second portion of the field plate and the second portion of the passivation layer.

[0005] In one aspect of this disclosure, a method includes: forming a gate structure on a semiconductor substrate; forming a passivation layer adjacent to and over the semiconductor substrate; forming an insulating material over the passivation layer; and forming a field plate including a first portion in contact with the passivation layer and a second portion separated from the passivation layer by the insulating material. Attached Figure Description

[0006] In the following detailed description, the present disclosure is described with reference to the accompanying drawings and non-limiting examples of exemplary embodiments thereof.

[0007] Figure 1 The structure and corresponding manufacturing process according to aspects of this disclosure are shown.

[0008] Figure 2The structure and corresponding manufacturing process according to other aspects of this disclosure are shown.

[0009] Figures 3A-3D Manufacturing according to aspects of this disclosure is shown. Figure 1 The manufacturing process of the structure shown. Detailed Implementation

[0010] This disclosure relates to semiconductor structures, and more specifically to high electron mobility transistors (HEMTs) with field plates and methods of fabrication thereof. More specifically, the high electron mobility transistor (HEMT) may be an e-type HEMT having a field plate near the top surface of an AlGaN stack (e.g., near the surface of the top AlGaN semiconductor layer). In embodiments, a portion of the field plate may be located above, below, or coincident with (e.g., planar) a portion of a dielectric material (e.g., AlxOy) near the surface of the top semiconductor layer. Advantageously, the field plate location provides improved off-state leakage, eliminates leakage paths, and allows adjustment of the d-mode pinch-off voltage without affecting other processes by positioning the field plate in different locations.

[0011] The structures disclosed herein can be fabricated using a variety of different tools and in a variety of ways. However, in general, methods and tools are used to form structures with micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating the structures of this disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned by photolithography on top of the wafer. Specifically, the fabrication of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film onto the mask. Furthermore, as is known in the art, a pre-cleaning process can be used to clean any contaminants from the etched surface. Additionally, as is known in the art, a rapid thermal annealing process can be used, where necessary, to drive in dopants or material layers.

[0012] Figure 1 The structure and corresponding manufacturing process according to aspects of this disclosure are illustrated. Structure 10 includes a semiconductor substrate 12. The semiconductor substrate 12 may be, for example, a GaN stack of semiconductor materials, more preferably, an AlGaN stack of semiconductor materials, as is known in the art.

[0013] With the aid of illustrative, non-limiting examples, an AlGaN stack of semiconductor materials may include a nucleation layer (e.g., AiN) formed on a Si semiconductor substrate, wherein one or more buffer layers are located between the AiN layer and the GaN semiconductor material. Those skilled in the art will understand that the nucleation layer helps to prevent Ga melt-back etching into Si and reduces interlayer diffusion of impurities into the channel layer. The Si semiconductor may preferably be a single-crystal Si material with a (111) orientation; however, other crystal orientations (e.g., (100), (110), or (001) crystal orientations) are also contemplated herein. The buffer layer may be a stepped-gradient interlayer and superlattice layer comprising one or more AlGaN layers, wherein the Al content gradually decreases from the bottom layer to the top layer. The GaN layer may be formed on the topmost layer of the AlGaN material. The GaN layer may act as a channel layer, wherein a 2D electron gas (2DEG) transition is located beneath the AlGaN material. Different semiconductor layers may be formed using epitaxial growth processes known in the art.

[0014] Figure 1 A gate structure 16 located on a semiconductor substrate 12 is also shown. For example, the gate structure 16 may comprise a doped GaN material 16a. In a more specific embodiment, the gate structure 16 comprises a p-doped GaN (pGaN) material 16a formed by conventional epitaxial growth processes utilizing in-situ doping, as known in the art. For example, the p-doperant may be magnesium (Mg). The gate structure 16 may also include a conductive material 16b (e.g., TiN material) layer formed on the doped GaN material 16a. For example, the conductive material 16b may be titanium nitride formed by conventional processes, as shown in the reference... Figure 3A As stated above.

[0015] A passivation layer 18 can be formed over the gate structure 16 and the semiconductor substrate 12. In an embodiment, the passivation layer 18 may be, for example, AlxOy deposited over the semiconductor substrate 12 after the formation of the gate structure 16. The passivation layer 18 can be deposited using a conventional blanket deposition process, as described in reference [reference missing]. Figure 3A As stated above.

[0016] Figure 1 The diagram also shows source and drain regions formed on the side of gate structure 16. In an embodiment, the source and drain regions may be ohmic contacts 14 formed on semiconductor substrate 12. In an embodiment, current flows between the source and drain regions (e.g., ohmic contacts 14), wherein gate structure 16 controls the current flow between the source and drain regions (e.g., ohmic contacts 14). Ohmic contacts 14 may be arranged in an interdigitated or other pattern, with gate structure 16 disposed therebetween. Ohmic contacts 14 may be any conductive material, such as aluminum, copper, gold, etc.

[0017] To form the ohmic contact 14, a specific metallization scheme is deposited on the semiconductor substrate 12 to form a low-resistance connection to a 2DEG (two-dimensional electron gas) channel, essentially allowing electrons to flow freely between the source and drain terminals (e.g., the ohmic contact 14), while the gate structure 16 controls the current flow through the channel region. This can be achieved by combining material selection, patterning, and annealing steps known in the art to ensure electrical contact while maintaining a Schottky barrier in the gate region to control current flow.

[0018] With a more specific example, the ohmic contact 14 can be formed using conventional photolithography, etching, and deposition methods known to those skilled in the art. For instance, the formation of the ohmic contact 14 may include a photoresist formed over an interlayer dielectric material 22 (e.g., silicon dioxide) above a passivation layer 18, which is exposed to energy (light) and developed using a conventional photoresist developer to form a pattern (opening). An etching process with selective chemical action, such as reactive ion etching (RIE), can be used to transfer the pattern from the photoresist to the interlayer dielectric material 22 and the passivation layer 18 to form one or more openings exposing the underlying semiconductor substrate 12. After the photoresist is removed by a conventional oxygen ashing process or other known stripping agents, a conductive material can be deposited using any conventional deposition process, such as a chemical vapor deposition (CVD) process. The conductive material can be a metal stack (e.g., Ti, Al, Ni, or Au).

[0019] The metal stack can be annealed at a controlled temperature to alloy with the semiconductor substrate 12, thereby forming a low-resistance ohmic contact 14. The annealing temperature and time are optimized to ensure good ohmic contact formation without damaging the device structure. Any residual material on the surface of the interlayer dielectric material can be removed or further patterned by conventional CMOS processes, such as chemical mechanical polishing (CMP) or etching processes (RIE).

[0020] Figure 1 A passivation layer 20 formed within the interlayer dielectric material 22 is also shown. In one embodiment, the passivation layer 20 may be an etch stop layer (ESL) that protects the underlying semiconductor substrate 12 from damage during the etching process. In another embodiment, the passivation layer 20 may be formed by conventional deposition processes (e.g., CVD) and subsequent conventional patterning processes (e.g., photolithography and etching processes). For example, the passivation layer 20 may be an alumina compound or silicon nitride.

[0021] like Figure 1As further shown, the passivation layer 20 may be located between the gate structure 16 and the ohmic contact 14 on the drain side of the structure. The passivation layer 20 may also be separated from the passivation layer 18, the ohmic contact 14, and the gate structure 16 by an interlayer dielectric material 22. In another embodiment, the passivation layer 20 may be planar.

[0022] Field plate 24 may be formed to partially coincide with passivation layer 20. In this and other configurations, field plate 24 may be a metallic material in direct contact with a portion of passivation layer 20 (e.g., AlxOy, where x and y are numerical values, such as Al2O3). The metallic material may be tantalum nitride deposited by a conventional deposition process (e.g., CVD) and then patterned using conventional photolithography and etching processes described herein. For example, using passivation layer 20 as an etch stop layer, an etch signal may be used to specify the time at which the etching process stops after a portion of passivation layer 20 has been removed by the etching process.

[0023] In a more specific embodiment, the bottom 24a of the field plate 24 may be flush with the passivation layer 20, wherein the remaining portion 24b of the field plate 24 lies above the passivation layer 20. In an alternative embodiment, the bottom 24a of the field plate 24 may be slightly recessed below the passivation layer 20, or located on top of the passivation layer (e.g., see...). Figure 2 The specific depth depends on the desired etching depth within the passivation layer 20. In any detailed configuration, the remaining portion 24b of the field plate 24 can be located above and parallel to the passivation layer 20. In an embodiment, an interlayer dielectric material 22 can be disposed between the remaining portion 24b of the field plate 24 and the passivation layer 20.

[0024] Those skilled in the art will recognize that the bottom 24a of the field plate 24 has a uniform bottom surface, and the junction of the field plate 24 between the bottom 24a and the remaining portion 24b includes a 90-degree profile 24c. More specifically, the 90-degree profile 24c may be located between vertical legs 24d extending between the bottom 24a and the remaining portion 24b and connecting to the bottom 24a and the remaining portion 24b. In an embodiment, the junction of the 90-degree profile between the bottom 24a and the vertical legs 24d may coincide (contact) with the passivation layer 20. In another embodiment, an interlayer dielectric material 22 may be disposed between the remaining portion 24b of the field plate 24 and between the passivation layers 20 and 18. This configuration will improve off-state leakage, reduce or eliminate leakage paths, provide higher dielectric field strength, and reduce weaknesses that may be present in conventional devices (e.g., breadloafing).

[0025] Figure 1A gate contact metal 26 is also shown connected to the gate structure 16 (more specifically, a conductive material 16b formed over a doped GaN material 16a). An ohmic contact 30 contacts the gate contact metal 26. A field contact metal (e.g., an ohmic contact) 28 may also be connected to a field plate 24. In embodiments, the gate contact metal 26, the ohmic contact 30, and the field contact metal 28 may be aluminum or copper formed by conventional deposition, patterning, and etching processes described herein.

[0026] Additional interlayer dielectric material 22 may be formed on top of interlayer dielectric material 2. Back-end process contacts (e.g., metal via contacts) 32 may be connected to ohmic contacts 14, 30, gate contact metal 26, and field contact 28. Metal wiring 34 is connected to back-end process contacts 32. Metal wiring 34 and back-end process contacts 32 may be formed by conventional photolithography, etching, and deposition methods already described herein, and therefore no further explanation is required to fully understand this disclosure.

[0027] Figure 2 Alternative structures according to aspects of this disclosure are shown. Figure 2 In structure 10a, the field plate 24 can be completely formed above the passivation layer 20. More specifically, the bottom 24a of the field plate 24 can contact the top surface of the passivation layer 20, wherein the remaining portion 24b of the field plate 24 lies above the passivation layer 20, as per [reference to...]. Figure 1 The intermediate layer, composed of interlayer dielectric material 22, is located between the remaining portion 24b of the field plate 24 and the passivation layer 20. In this way, the passivation layer 20 and the remaining portion 24b of the field plate 24 are isolated from each other, providing the advantages already described herein. Figure 2 The remaining features of structure 10a are similar to Figure 1 The structure is 10, therefore, no further explanation is required to fully understand this disclosure.

[0028] Figures 3A-3D Manufacturing process is shown Figure 1 The manufacturing process of the structure shown. Figure 3A In this embodiment, a gate structure 16 can be formed on the semiconductor substrate 12. In this embodiment, the gate structure includes a p-doped GaN material 16a and a conductive material 16b (e.g., titanium nitride) situated on top of the p-doped GaN material 16a. The p-doped GaN material 16a can be formed using an epitaxial growth process utilizing in-situ deposition followed by conventional patterning and etching processes.

[0029] Examples of various epitaxial growth process apparatuses that can be used in this application include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial growth can be performed using any known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. p-type dopants can be added to the precursor gas or gas mixture.

[0030] Conductive materials 16b (e.g., titanium nitride) can be formed using conventional processes. For example, conductive materials can be formed by CVD processes or PVD sputtering of TiN, in which a Ti sputtering target is used and Ti reacts in situ to become TiN.

[0031] A passivation layer 18 may be formed on the gate structure 16 and the semiconductor substrate 12. In an embodiment, the passivation layer 18 may be formed after the formation of the gate structure 16, for example, by blanket deposition of AlxOy (or other etch stop layers) on the semiconductor substrate 12. The passivation layer 18 may be deposited by, for example, CVD or atomic layer deposition (ALD) processes. In this way, the passivation layer 18 covers the gate structure 16 and the exposed portions of the semiconductor substrate 12.

[0032] exist Figure 3B In this process, an interlayer dielectric material 22 can be formed on the passivation layer 18. In embodiments, the interlayer dielectric material 22 can be formed by conventional deposition processes (e.g., CVD) followed by optional planarization processes. The interlayer dielectric material 22 can be an oxide material or a nitride material or a combination thereof. Preferably, the interlayer dielectric material 22 is selective to the passivation layer 20.

[0033] A passivation layer 20 can be formed on the interlayer dielectric material 22. In this way, the passivation layer 20 can be separated from the passivation layer 18 by the interlayer dielectric material 22. Figure 3B As shown, passivation layer 20 may be planar. Passivation layer 20 may be an etch stop layer containing a material selective to the interlayer dielectric material 22. For example, passivation layer 20 may be AlxOy. In a preferred embodiment, passivation layer 20 may be the same material as passivation layer 18. Passivation layer 20 may be formed by conventional blanket deposition processes (e.g., CVD or ALD processes) and subsequent conventional photolithography and etching processes already described herein. In an embodiment, passivation layer 20 may be formed between gate structure 16 and the drain region of the device.

[0034] exist Figure 3CIn this process, an additional interlayer dielectric material 22 can be formed on the passivation layer 20. A trench 100 can be formed in this interlayer dielectric material 22 to expose the underlying passivation layer 20. In an embodiment, the trench 100 can extend through the underlying passivation layer 20, such as... Figure 1 As shown, or located above passivation layer 22 (exposing passivation layer 22), such as Figure 2 As shown. The trench 100 can be formed by the conventional photolithography and etching processes described herein, therefore, no further explanation is required to fully understand this disclosure.

[0035] A field plate 16 can be formed in the trench 100 and on the surface of the interlayer dielectric material 22. In an embodiment, the field plate 16 can be formed by deposition of a portion of the passivation layer 20 (e.g., Figure 1 The edge of the etched passivation layer 20 shown or Figure 2 The passivation layer 20 shown is formed in direct contact with the conductive material on its top surface.

[0036] The conductive material can be tantalum nitride, deposited using conventional deposition processes (e.g., CVD or PVD / sputtering) and patterned using conventional photolithography and etching processes described herein. The bottom 24a of the field plate 24 can be flush with the passivation layer 20, as... Figure 1 As shown, or located above the passivation layer 20, such as Figure 2 As shown. Different configurations can be due to different etching depths in the passivation layer 20 and / or the interlayer dielectric material 22. In any configuration, the remaining portion 24b of the field plate 24 can be located above the passivation layer 20, coplanar with the passivation layer 20, and separated from the passivation layer 20 by the interlayer dielectric material 22. In this way, the interlayer dielectric material 22 can be uniform between the passivation layer 20 and the field plate 24.

[0037] Figure 3D The formation of an ohmic contact 14 and a gate contact metal 26 connected to a conductive material 16b of a gate structure 16 is illustrated. In embodiments, the ohmic contact 14 and the gate contact metal 26 can be formed in the same or different photolithography, etching, and deposition steps known in the art; therefore, no further explanation is required to fully understand this disclosure. Figure 1 As further shown, for example, ohmic contacts 28, 30, back-end process contact 32 and wiring structure 34 can be formed by conventional photolithography, patterning and etching processes known in the art as described herein, and therefore no further explanation is required to fully understand this disclosure.

[0038] These structures can be used in System-on-Chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes significantly less power and occupies a much smaller area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0039] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with one or both surface-mount or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0040] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: A gate structure located on a semiconductor substrate; A passivation layer, which is adjacent to the gate structure and located above the semiconductor substrate; An insulating material is located on the passivation layer; as well as The field plate includes a first portion in contact with the passivation layer and a second portion separated from the passivation layer by the insulating material.

2. The structure according to claim 1, wherein, The first portion of the field plate is flush with the passivation layer, and the second portion of the field plate is parallel to the passivation layer.

3. The structure according to claim 2, wherein, The edge of the first portion of the field plate coincides with the passivation layer.

4. The structure according to claim 3, wherein, The junction of the first and second portions of the field plate includes a 90-degree profile, and a dielectric material is located between the second portion of the field plate and the passivation layer.

5. The structure according to claim 1, wherein, The passivation layer is planar.

6. The structure according to claim 1, wherein, The passivation layer contains AlxOy.

7. The structure according to claim 1, wherein, The first portion of the field plate is located above and in contact with the passivation layer.

8. The structure according to claim 7, wherein, The second portion of the field plate is parallel to the passivation layer, wherein an interlayer dielectric material separates the second portion of the field plate from the passivation layer.

9. The structure according to claim 1, wherein, The semiconductor substrate is a stack of AlGaN materials, and the gate structure contains pGaN material.

10. The structure according to claim 1, wherein, The field plate is located between the gate structure and the drain region adjacent to the gate structure.

11. A structure comprising: Gate structure; The source region includes a first ohmic contact adjacent to a first side of the gate structure; The drain region includes a second ohmic contact adjacent to the second side of the gate structure; A passivation layer is located between the gate structure and the drain region; A field plate, comprising a first portion in contact with a first portion of the passivation layer and a second portion separated from a second portion of the passivation layer; as well as An insulating material is located between the second portion of the field plate and the second portion of the passivation layer.

12. The structure according to claim 11, wherein, The first portion of the field plate is flush with the first portion of the passivation layer, and the second portion of the field plate is located above and parallel to the second portion of the passivation layer.

13. The structure according to claim 12, wherein, The passivation layer comprises AlxOy, the field plate comprises a metallic material, and the insulator material comprises silicon dioxide.

14. The structure according to claim 13, further comprising a second passivation layer located above the gate structure and below the first passivation layer.

15. The structure according to claim 14, wherein, The first passivation layer and the second passivation layer are separated by the insulating material.

16. The structure according to claim 14, wherein, The second passivation layer contains AlxOy.

17. The structure according to claim 11, wherein, The first portion of the field plate is located on the first portion of the passivation layer, and the second portion of the field plate is located above the second portion of the passivation layer.

18. The structure according to claim 11, wherein, The gate structure includes a GaN high electron mobility transistor.

19. The structure according to claim 11, wherein, The edges of the first portion of the field plate include a consistent 90-degree profile.

20. A method comprising: A gate structure is formed on a semiconductor substrate; A passivation layer is formed adjacent to the gate structure and over the semiconductor substrate; An insulating material is formed on the passivation layer; as well as A field plate is formed comprising a first portion in contact with the passivation layer and a second portion separated from the passivation layer by the insulating material.

Images