Field effect transistor, power electronic system and method of manufacturing a field effect transistor

Abstract

This application relates to a field-effect transistor (FET), a power electronic system, and a method for fabricating a FET, comprising: an N+ type GaN substrate; an N- type GaN drift layer, a polarization-doped gradient layer, a channel layer, a barrier layer, and a gate structure sequentially stacked vertically on the N+ type GaN substrate, wherein the barrier layer has a first end and a second end opposite each other in the lateral direction, the first end and the second end being located inside the edge of the channel layer, and the barrier layer and the channel layer forming a heterojunction to form a 2DEG channel; a source layer formed on the channel layer and insulated from the gate structure, the source layer being in contact with the first end of the barrier layer and connected to the 2DEG channel; and a drain layer formed on the surface of the N+ type GaN substrate away from the N- type GaN drift layer, configured to be connected to an external circuit. This scheme can combine the high mobility and high-speed switching advantages of the lateral 2DEG channel with the high breakdown voltage and high power density advantages of the vertical drift region, and achieve a smooth and low-loss transition of electrons from lateral transport to vertical transport.

Description

Technical Field

[0001] This application belongs to the field of semiconductor devices, specifically relating to a field-effect transistor, a power electronic system, and a method for manufacturing a field-effect transistor. Background Technology

[0002] With the continuous development of technology, power semiconductor devices such as gallium nitride (GaN) field-effect transistors are gradually moving from high-end fields to the mass market, becoming one of the core driving forces for the development of a smart, efficient, and green world in the future.

[0003] GaN field-effect transistors (FETs) mainly include two types: lateral and vertical. Lateral GaN FETs utilize the high-mobility two-dimensional electron gas (2DEG) at the heterojunction between the barrier layer and the channel layer as a conductive channel, resulting in fast switching speeds and low on-resistance. However, their breakdown voltage depends on the lateral gate-drain spacing; increasing the breakdown voltage inevitably increases the chip area, leading to higher on-resistance per unit area and increased cost. Vertical GaN FETs can withstand voltage through a vertical drift region within the chip, achieving high breakdown voltage and high power density. However, the channel mobility of vertical GaN FETs is much lower than that of 2DEG, making it difficult for them to compete with lateral GaN FETs in terms of switching speed and on-resistance. Summary of the Invention

[0004] The purpose of this application is to provide a field-effect transistor, a power electronic system, and a method for fabricating a field-effect transistor, which can combine the advantages of high mobility and high-speed switching of the lateral 2DEG channel with the advantages of high voltage withstand and high power density of the vertical drift region, and achieve a smooth and low-loss transition of electrons from lateral transport to vertical transport.

[0005] To achieve the above objectives, this application provides a field-effect transistor, comprising:

[0006] N+ type GaN substrate; An N-type GaN drift layer, a polarization-doped gradient layer, a channel layer, a barrier layer, and a gate structure are sequentially stacked vertically on the N+ type GaN substrate. The barrier layer has a first end and a second end that are laterally opposite each other. The first end and the second end are located inside the edge of the channel layer. The barrier layer and the channel layer form a heterojunction to form a 2DEG channel. A source layer is formed on the channel layer and is insulated from the gate structure. The source layer is in contact with the first end of the barrier layer and is connected to the 2DEG channel. A drain layer, formed on the surface of the N+ type GaN substrate away from the N- type GaN drift layer, is configured to connect to an external circuit; wherein... The N-type GaN drift layer is configured to bear the high voltage applied by the drain layer to form a depletion region, and the polarization-doped gradient layer is configured to limit the high electric field peak in the depletion region. The polarization-doped gradient layer is configured to apply a vertical electric field force pointing towards the N+ type GaN substrate to electrons that move to the second end.

[0007] In some exemplary embodiments of this application, the polarization-doped gradient layer comprises an AlGaN material in which the Al composition increases in the direction away from the N-type GaN drift layer.

[0008] In some exemplary embodiments of this application, the Al composition of the polarization-doped gradient layer is continuous or stepped.

[0009] In some exemplary embodiments of this application, the Al composition of the polarization-doped gradient layer increases from 0 to 0.4.

[0010] In some exemplary embodiments of this application, the channel layer comprises a GaN material, and the barrier layer comprises an AlGaN material in which the Al composition remains constant within the layer.

[0011] In some exemplary embodiments of this application, the gate structure includes: A p-type GaN layer is formed on the upper surface of the barrier layer; A gate layer, formed on the upper surface of the P-type GaN layer, is configured to apply a gate voltage.

[0012] In some exemplary embodiments of this application, the gate structure is formed in the middle region of the barrier layer; The field-effect transistor further includes an insulating oxide layer that covers the area of ​​the barrier layer not covered by the gate structure, and also covers the area of ​​the channel layer not covered by the source layer and the barrier layer.

[0013] In some exemplary embodiments of this application, the surface of the source layer near the N+ type GaN substrate is closer to the N+ type GaN substrate than the surface of the barrier layer near the N+ type GaN substrate.

[0014] A second aspect of this disclosure provides a power electronic system comprising a plurality of field-effect transistors as described in any one of the preceding claims, the plurality of field-effect transistors being interconnected.

[0015] A third aspect of this disclosure provides a method for fabricating a field-effect transistor, comprising: Provide an N+ type GaN substrate; An N-type GaN drift layer, a polarization-doped gradient layer, a channel layer, a barrier layer, and a gate structure are formed vertically and stacked sequentially on the N+ type GaN substrate. The barrier layer has a first end and a second end that are laterally opposite each other. The first end and the second end are located inside the edge of the channel layer. The barrier layer and the channel layer form a heterojunction to form a 2DEG channel. A source layer is formed on the channel layer, the source layer is insulated from the gate structure, the source layer is in contact with the first end of the barrier layer, and is connected to the 2DEG channel; A drain layer is formed on the surface of the N+ type GaN substrate away from the N- type GaN drift layer, and the drain layer is configured to be connected to an external circuit; wherein... The N-type GaN drift layer is configured to bear the high voltage applied by the drain layer to form a depletion region, and the polarization-doped gradient layer is configured to limit the high electric field peak in the depletion region. Furthermore, the polarization-doped gradient layer is configured to apply a vertical electric field force pointing towards the N+ type GaN substrate to the electrons moving to the second end, so that the electrons at the second end move vertically to the drain layer.

[0016] This application has at least the following beneficial effects: This application achieves functional spatial partitioning of the lateral 2DEG channel and the vertical drift layer, allowing the switching speed and on-resistance of the field-effect transistor to be determined by the high mobility of the lateral channel, while the breakdown voltage is determined by the thickness of the vertical drift layer. This structural design enables high-frequency switching characteristics and high breakdown voltage characteristics to be achieved without compromise on the same chip. Furthermore, by employing a polarized doped gradient layer in conjunction with the second end (terminal) termination of the barrier layer, the built-in polarized electric field of the polarized doped gradient layer drives electrons to change their direction of motion, i.e., electrons change from lateral movement to vertical movement. This structural design avoids lattice damage and mobility degradation caused by high-energy injection, ensuring low resistance and high reliability in the current transition region from a structural perspective.

[0017] Furthermore, the polarization-doped gradient layer and the channel layer physically isolate the high-field vertical drift layer from the heterojunction. This design ensures that the electric field peak in the off state is clamped inside the vertical drift layer, and the heterojunction is in a low electric field environment, which fundamentally suppresses the current collapse effect and dynamic on-resistance degradation, and significantly improves the long-term reliability of the device.

[0018] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 This is a schematic diagram of the structure of a field-effect transistor described in one embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the electron flow direction of a field-effect transistor described in one embodiment of this application when it is in the on state.

[0023] Explanation of reference numerals in the attached figures: 10. N+ type GaN substrate; 11. N- type GaN drift layer; 12. Polarization doped gradient layer; 13. Channel layer; 14. Barrier layer; 14a. First end; 14b. Second end; 15. 2DEG channel; 16. Gate structure; 161. P-type GaN layer; 162. Gate layer; 17. Source layer; 18. Drain layer; 19. Insulating oxide layer. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0025] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0026] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0027] To address the drawbacks of lateral and vertical GaN field-effect transistors, the following solutions have been proposed in related technologies: Option 1: Discrete component cascade packaging By packaging a low-voltage enhancement-mode silicon MOSFET (metal-oxide-semiconductor field-effect transistor) with a high-voltage depletion-mode lateral GaN field-effect transistor in a common-source cascode package, this approach achieves normally-off operation. However, it introduces parasitic capacitance of the silicon device and reverse recovery loss of the parasitic diode, sacrificing the high-frequency potential of GaN. Furthermore, the multi-chip package introduces additional parasitic inductance.

[0028] Option 2: Direct stacking of lateral heterojunctions and vertical drift regions AlGaN (aluminum gallium nitride) / GaN heterojunctions are directly grown on the vertical drift region of GaN to form a top 2DEG channel. However, this simple stacking has two structural defects: one is a current transition bottleneck, namely, the two-dimensional electron gas is quantumly confined in the lateral potential well, lacking an effective structure to guide its vertical injection into the lower drift region, resulting in current congestion at the gate edge; the other defect is the electric field penetration problem, namely, the high electric field in the vertical drift region can penetrate to the thinner GaN layer above, causing electric field concentration in the heterojunction and exacerbating current collapse.

[0029] Option 3: Ion implantation of vertical conductive columns High-energy ion implantation is used to form N+ type vertical conductive pillars in the end region of 2DEG to guide the current downward. However, the lattice damage caused by ion implantation will severely degrade the carrier mobility in this region and introduce a large number of defect energy levels, leading to aggravated dynamic resistance degradation.

[0030] In summary, the above solutions lack a structural solution that can achieve an efficient transition from lateral to vertical current without compromising 2DEG mobility, while simultaneously achieving effective electric field shielding.

[0031] In order to achieve efficient transition from lateral to vertical current without compromising 2DEG mobility, and at the same time achieve effective electric field shielding, embodiments of this application provide a field-effect transistor, which may be a GaN field-effect transistor.

[0032] In some embodiments of this application, such as Figure 1 As shown, the field-effect transistor may include an N+ type GaN substrate 10 (i.e., a heavily doped N-type GaN substrate), an N- type GaN drift layer 11 (i.e., a lightly doped N-type GaN substrate), a polarization doped gradient layer 12, a channel layer 13, a barrier layer 14, a gate structure 16, a source layer 17, and a drain layer 18.

[0033] Specifically, an N-type GaN drift layer 11, a polarization-doped gradient layer 12, a channel layer 13, a barrier layer 14, and a gate structure 16 are sequentially stacked vertically on an N+ type GaN substrate 10. The barrier layer 14 may have a first end 14a and a second end 14b opposite each other in the lateral direction, and the first end 14a and the second end 14b of the barrier layer 14 are located inside the edge of the channel layer 13. The barrier layer 14 and the channel layer 13 form a heterojunction to form a 2DEG channel 15. A source layer 17 is formed on the channel layer 13 and is insulated from the gate structure 16. The source layer 17 is in contact with the first end 14a of the barrier layer 14 and is connected to the 2DEG channel 15. A drain layer 18 is formed on the surface of the N+ type GaN substrate 10 away from the N-type GaN drift layer 11 and is configured to be connected to an external circuit.

[0034] In this configuration, the N-type GaN drift layer 11 is configured to bear the high voltage applied by the drain layer 18 to form a depletion region, and the polarization-doped gradient layer 12 is configured to limit the high electric field peak to the depletion region; and the polarization-doped gradient layer 12 is configured to apply a vertical electric field force pointing towards the N+ type GaN substrate 10 to the electrons moving to the second end 14b, so that the electrons at the second end 14b move vertically to the drain layer 18.

[0035] In this embodiment, the 2DEG channel 15 formed by the barrier layer 14 and the channel layer 13 is a lateral channel. The lateral 2DEG channel 15 has extremely high electron mobility, typically reaching 1500-2000 cm² / V, far exceeding that of traditional silicon materials. This means that electrons encounter minimal resistance when moving within the channel, resulting in extremely low resistance for the field-effect transistor in the on-state. Furthermore, since the 2DEG channel 15 is spontaneously formed by the heterojunction polarization effect, the gate structure 16 has extremely strong control over it, enabling the device to turn on and off at extremely high frequencies (nanosecond-level response). In addition, the conductivity of the lateral channel relies on the polarization effect rather than chemical element doping, avoiding the scattering of electrons by impurity ions and further ensuring unimpeded electron movement laterally. In other words, the design of the lateral 2DEG channel 15 enables the field-effect transistor to have fast switching speeds and low on-resistance.

[0036] When electrons pass through the transverse 2DEG channel 15, the built-in electric field of the polarization-doped gradient layer 12 causes the electrons to turn rapidly, enter the N-type GaN drift layer 11 vertically and flow to the drain layer 18 on the back side. At this time, the voltage withstand capability of the field-effect transistor is mainly determined by the vertical drift layer thickness.

[0037] In traditional power semiconductor (such as silicon MOSFET devices or traditional lateral GaN devices) design, on-resistance and breakdown voltage are an irreconcilable contradiction: the higher the breakdown voltage, the longer the drift layer must be or the lower the doping level must be, leading to an exponential increase in resistance. This application, however, achieves a division of labor by combining the lateral 2DEG channel 15 with the polarization-doped gradient layer 12, enabling the lateral layer to handle high speed and the vertical layer to handle stability. This retains the high-frequency, low-resistance characteristics of the lateral GaN channel (fast operation and low resistance) while leveraging the high-voltage blocking advantages of the vertical structure (strong breakdown voltage and space-saving design). Ultimately, it achieves both high-frequency, high-efficiency and high-voltage, reliable characteristics on a single chip.

[0038] Furthermore, the polarization-doped gradient layer 12 is used in conjunction with the second end 14b (end) of the barrier layer 14 to terminate the electrons. The built-in polarization electric field of the polarization-doped gradient layer 12 drives the electrons to change their direction of motion, that is, the electrons change from horizontal movement to vertical movement. This structural design avoids lattice damage and mobility degradation caused by high-energy injection, and ensures low resistance and high reliability of the current transition region from a structural perspective.

[0039] In addition, the polarization-doped gradient layer 12 and the channel layer 13 physically isolate the high-field vertical drift layer from the heterojunction. This design allows the electric field peak in the off state to be clamped inside the vertical drift layer, and the heterojunction to be in a low electric field environment, which fundamentally suppresses the current collapse effect and dynamic on-resistance degradation, and significantly improves the long-term reliability of the device.

[0040] The following is combined with Figure 1 The specific structure of the field-effect transistor according to the embodiments of this disclosure will be described in detail.

[0041] The N+ type GaN substrate 10 can be understood as the physical foundation and support of the entire field-effect transistor, providing a low-resistance vertical current collection path for the field-effect transistor.

[0042] The drain layer 18 is formed on the lower surface of the N+ type GaN substrate 10, that is, located on the lower surface of the entire field-effect transistor, and is configured to connect to an external circuit. For example, the drain layer 18 can be made of a metallic material to ensure good conductivity. The drain layer 18 can be formed on the lower surface of the N+ type GaN substrate 10 after the structural layers on the N+ type GaN substrate 10 are fabricated, but it is not limited to this; it can also be formed on the lower surface of the N+ type GaN substrate 10 before the structural layers on the N+ type GaN substrate 10, depending on the specific requirements.

[0043] An N-type GaN drift layer 11 can be formed on the upper surface of an N+ type GaN substrate 10. When the field-effect transistor is in the blocking state, the N-type GaN drift layer 11 forms a space charge region to withstand the main blocking voltage applied between the drain layer 18 and the source layer 17. Furthermore, the thickness and doping concentration of the N-type GaN drift layer 11 determine the rated breakdown voltage of the field-effect transistor.

[0044] A polarization-doped gradient layer 12 can be formed on the upper surface of the N-type GaN drift layer 11 (i.e., the surface of the N-type GaN drift layer 11 away from the N+ type GaN substrate 10). A built-in vertical electric field can be generated within the polarization-doped gradient layer 12, with the electric field direction pointing downwards towards the N+ type GaN substrate 10. The built-in electric field within the polarization-doped gradient layer 12 not only induces the formation of a high-concentration three-dimensional electron gas (3DEG) within the layer through polarization, providing a low-resistance channel for vertical current, but also applies a downward vertical electric force to the transverse channel electrons reaching above it, driving the electrons to move towards the vertical drift layer.

[0045] For example, the polarization-doped gradient layer 12 may comprise AlGaN material with an Al composition that increases away from the N-type GaN drift layer 11. Since the polarization intensity of the AlGaN material is positively correlated with the Al composition, the spatial gradient of the Al composition can lead to a gradient distribution of polarization charge density within the polarization-doped gradient layer 12, thereby generating a built-in vertical electric field within the polarization-doped gradient layer 12, with the electric field direction pointing downwards towards the N+ type GaN substrate 10.

[0046] Among them, reference Figure 2 As shown, when an electron moves laterally along the 2DEG channel 15 to the end boundary (i.e., the second end 14b) of the barrier layer 14, the barrier layer 14 terminates, and the vertical quantum confinement of the electron is released. Simultaneously, the electron is exposed to the built-in vertical electric field generated by the underlying polarization-doped graded layer 12. Under the combined effect of the above structures, the electron naturally completes the transition from lateral transport to vertical transport at the end boundary of the barrier layer 14, entering the underlying polarization-doped graded layer 12 and the vertically arranged N-type GaN drift layer 11.

[0047] in, Figure 2 The bold black arrows in the middle indicate the direction of electron flow.

[0048] It should be understood that the polarization-doped gradient layer 12 is not limited to being made of the aforementioned materials; any material that can achieve the corresponding function is acceptable.

[0049] In some embodiments, the Al composition of the polarization-doped gradient layer 12 is continuously or stepwise, which results in stronger conductivity, lower resistance, higher withstand voltage, and greater durability without doping.

[0050] For example, the Al composition of the polarization-doped gradient layer 12 increases from 0 to 0.4, which achieves a good balance between strong polarization conductivity, high electron mobility and high-quality crystal growth. This ensures that the field-effect transistor has sufficient conductivity and voltage withstand capability, while preventing side effects such as electrons not being able to move (low mobility) and material cracking (poor reliability) caused by excessive aluminum content.

[0051] The channel layer 13 may be formed on the upper surface of the polarization-doped graded layer 12 (i.e., the surface of the polarization-doped graded layer 12 away from the N+ type GaN substrate 10). This channel layer 13 provides a high-quality carrier transport medium for 2DEG communication and acts as a physical buffer between the polarization-doped layer and the top heterojunction. For example, the channel layer 13 comprises GaN material. Specifically, the channel layer 13 in this embodiment may be a GaN channel layer 13.

[0052] A barrier layer 14 may be formed on the upper surface of the channel layer 13 (i.e., the surface of the channel layer 13 away from the N+ type GaN substrate 10). The barrier layer 14 may comprise an AlGaN material with a constant Al composition within the layer; specifically, in this embodiment, the barrier layer 14 may be an AlGaN barrier layer 14. Through a polarization effect, a high-mobility two-dimensional electron gas (2DEG) channel is induced below the heterojunction between the AlGaN barrier layer 14 and the unintentionally doped GaN channel layer 13.

[0053] It should be understood that the channel layer 13 and the barrier layer 14 are not limited to being made of the aforementioned materials; any material that can achieve the corresponding function is acceptable.

[0054] A gate structure 16 may be formed on the upper surface of the barrier layer 14 (i.e., the surface of the barrier layer 14 away from the N+ type GaN substrate 10). The gate structure 16 includes a P-type GaN layer 161 and a gate layer 162. The P-type GaN layer 161 may be formed on the upper surface of the barrier layer 14. Specifically, the P-type GaN layer 161 may be located in the gate control region above the AlGaN barrier layer 14. This layer, through its P-type conductivity, depletes the 2DEG in the region directly below it at zero gate voltage, thereby giving the field-effect transistor enhancement-mode (normally off) operation. The gate layer 162 may be formed on the upper surface of the P-type GaN layer 161 (i.e., the surface of the P-type GaN layer 161 away from the N+ type GaN substrate 10), and the gate layer 162 is configured to apply a gate voltage. For example, the gate layer 162 may be made of a metallic material to ensure good conductivity.

[0055] The source layer 17 can be formed on the upper surface of the channel layer 13 (i.e., the surface of the channel layer 13 away from the N+ type GaN substrate 10). After the barrier layer 14 is fabricated on the upper surface of the channel layer 13, the source layer 17 is formed through the barrier layer 14, and the channel layer 13 and the 2DEG channel 15 form a low-resistance electrical connection.

[0056] The source layer 17 is closer to the N+ GaN substrate 10 than the barrier layer 14 is to the N+ GaN substrate 10. In other words, the source layer 17 extends deeper downwards. It has a larger contact area and a tighter bond with the underlying conductive channel (2DEG channel 15), which can reduce the on-resistance and improve the current capability. When the field-effect transistor is subjected to high voltage (blocking state), the edge of the source layer 17 is usually the place where the electric field is most likely to concentrate. By extending the source layer 17 downwards, it is equivalent to forming a field plate or shielding effect inside the field-effect transistor. This structure can effectively stretch and disperse the electric field lines at the source edge, preventing the high electric field from concentrating at a sharp corner and causing the device to break down prematurely. This greatly improves the breakdown voltage and long-term reliability of the device. In addition, the source layer 17 extends downward, which makes the pinch-off region below the gate (i.e., the channel region not covered by the barrier layer 14) more precisely defined in the vertical direction. This allows the electron path from the source to the channel to be cut off more thoroughly and without dead ends when the gate is turned off. This ensures that the leakage current of the field-effect transistor is extremely low in the blocking state, the switching performance is more crisp and clean, and the energy waste caused by incomplete gate control is avoided.

[0057] For example, the source layer 17 may be made of a metallic material to ensure good electrical conductivity.

[0058] In some embodiments, the gate structure 16 is formed in the middle region of the barrier layer 14 (i.e., the gate control region above the barrier layer 14); the field-effect transistor also includes an insulating oxide layer 19, which covers the region of the barrier layer 14 not covered by the gate structure 16, and also covers the region of the channel layer 13 not covered by the source layer 17 and the barrier layer 14.

[0059] In this embodiment, the gate structure 16 is centered for more precise switching, and the insulating oxide layer 19 fully covers the entire surface of the field-effect transistor, thus providing comprehensive waterproofing, insulation, and passivation treatment. This not only prevents current erratic movement (preventing leakage and breakdown) but also protects the core conductive channel from damage, ensuring that the entire field-effect transistor is both safe and stable when operating at high voltage.

[0060] In some embodiments, the operating principle of a field-effect transistor may include: The conduction state of the field-effect transistor: When a forward bias voltage higher than the threshold voltage is applied to the gate metal, the depletion effect of the P-type GaN layer 161 on the two-dimensional electron gas below it is canceled out, and the 2DEG channel 15 below the gate layer 162 is turned on. Electrons are injected from the source layer 17 through the 2DEG channel 15 and migrate laterally along the interface between the AlGaN barrier layer 14 and the GaN channel layer 13 under the drive of the lateral electric field. After passing through the region below the gate structure 16, the electrons continue to move laterally along the 2DEG channel 15 until they reach the end boundary (i.e., the second end 14b) of the AlGaN barrier layer 14. At this boundary, the AlGaN barrier layer 14 terminates, and the vertical quantum confinement of the electrons is released. At this time, the electrons are in the built-in vertical electric field generated by the lower polarization-doped gradient layer 12. This electric field exerts an electric force on the electrons in the direction of the N+ type GaN substrate 10, driving the electrons to change their direction of motion from horizontal motion to vertical downward motion, and enter the polarization-doped gradient layer 12. The electrons continue to drift vertically to the N+ type GaN substrate 10 through the polarization-doped gradient layer 12 and the N- type GaN drift layer 11, and are finally collected by the bottom drain layer 18, completing the entire conduction current path.

[0061] The blocking state of the field-effect transistor: When the gate voltage is lower than the threshold voltage (typically zero bias), the P-type GaN layer 161 completely depletes the two-dimensional electron gas directly beneath it, and the lateral conductive channel is pinched off. The high voltage applied to the drain layer 18 is mainly borne by the underlying N-type GaN drift layer 11, forming a space charge depletion region within the N-type GaN drift layer 11. Since the lateral 2DEG channel 15 and the vertical drift layer are isolated by the polarization-doped gradient layer 12 and the GaN channel layer 13, the high electric field peak of the vertical depletion region is limited below the polarization-doped gradient layer 12 and cannot penetrate to the heterojunction interface of the AlGaN barrier layer 14 / GaN channel layer 13. This structural feature effectively suppresses the trapping of electrons by surface state traps, thereby significantly mitigating the dynamic on-resistance degradation phenomenon.

[0062] Based on the above, the field-effect transistor of this embodiment does not rely on complex additional structures. It achieves its beneficial effects only through the design of material sequence, composition distribution and the extension range of barrier layer 14. The structure is simple and has good design universality and process compatibility.

[0063] This disclosure also provides a power electronic system that may include multiple field-effect transistors (FETs) as described above, with the multiple FETs connected together. The power electronic system can balance high switching frequency, high voltage withstand capability, and low on-resistance. The power electronic system includes, but is not limited to: data center power supplies, on-board chargers, fast charging adapters, photovoltaic inverters, and industrial motor drives.

[0064] This disclosure also provides a method for fabricating a field-effect transistor, the structure of which is as follows: Figure 1 As shown, the method for fabricating a field-effect transistor includes steps S100, S200, S300, and S400.

[0065] In step S100, an N+ type GaN substrate 10 is provided.

[0066] In step S200, an N-type GaN drift layer 11, a polarization doped gradient layer 12, a channel layer 13, a barrier layer 14, and a gate structure 16 are formed on an N+ type GaN substrate 10 in a vertically stacked manner. The barrier layer 14 has a first end 14a and a second end 14b that are laterally opposite each other. The first end 14a and the second end 14b are recessed relative to the two sides of the channel layer 13. The barrier layer 14 and the channel layer 13 form a heterojunction to form a 2DEG channel 15.

[0067] Specifically, step S200 may include: first, epitaxially growing an N-type GaN drift layer 11 on an N+ type GaN substrate 10; then, epitaxially growing a polarization-doped gradient layer 12 on the N-type GaN drift layer 11; then, epitaxially growing a GaN channel layer 13 on the polarization-doped gradient layer 12; then, epitaxially growing an AlGaN barrier layer 14 on the GaN channel layer 13; then, depositing an insulating oxide layer 19 on the AlGaN barrier layer 14 using a mask process; then, depositing a P-type GaN layer 161 on the insulating oxide layer 19 using a mask process; and finally, depositing a metal layer 162 on the P-type GaN layer 161 using a mask process to form a gate layer 162.

[0068] In step S300, a source layer 17 is formed on the channel layer 13. For example, metal is deposited on the insulating oxide layer 19 using a mask process to form the source layer 17.

[0069] In step S400, a drain layer 18 is formed on the surface of the N+ type GaN substrate 10 away from the N- type GaN drift layer 11. For example, a source layer 17 is formed by depositing metal on the lower surface of the N+ type GaN substrate 10.

[0070] In this embodiment, during the fabrication of the field-effect transistor, the complex structure, including the N-type GaN drift layer 11, polarization-doped gradient layer 12, channel layer 13, barrier layer 14, P-type GaN layer 161, gate layer 162, and source layer 17, can be fabricated layer by layer on the upper surface of the N+ type GaN substrate using epitaxial growth and other processes. After all the fine structures on the upper surface of the N+ type GaN substrate are fabricated, the lower surface of the N+ type GaN substrate is thinned and polished, and finally, metal is deposited to form the drain layer 18.

[0071] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0072] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0073] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0074] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A field-effect transistor, characterized in that, include: N+ type GaN substrate; An N-type GaN drift layer, a polarization-doped gradient layer, a channel layer, a barrier layer, and a gate structure are sequentially stacked vertically on the N+ type GaN substrate. The barrier layer has a first end and a second end that are laterally opposite each other. The first end and the second end are located inside the edge of the channel layer. The barrier layer and the channel layer form a heterojunction to form a 2DEG channel. A source layer is formed on the channel layer and is insulated from the gate structure. The source layer is in contact with the first end of the barrier layer and is connected to the 2DEG channel. A drain layer, formed on the surface of the N+ type GaN substrate away from the N- type GaN drift layer, is configured to connect to an external circuit; wherein... The N-type GaN drift layer is configured to bear the high voltage applied by the drain layer to form a depletion region, and the polarization-doped gradient layer is configured to limit the high electric field peak in the depletion region. Furthermore, the polarization-doped gradient layer is configured to apply a vertical electric field force pointing towards the N+ type GaN substrate to the electrons that move to the second end.

2. The field-effect transistor according to claim 1, characterized in that, The polarization-doped gradient layer comprises AlGaN material in which the Al composition increases in the direction away from the N-type GaN drift layer.

3. The field-effect transistor according to claim 2, characterized in that, The Al composition of the polarization-doped gradient layer is either continuous or stepped.

4. The field-effect transistor according to claim 3, characterized in that, The Al composition of the polarization-doped gradient layer increases from 0 to 0.

4.

5. The field-effect transistor according to claim 1, characterized in that, The channel layer comprises GaN material, and the barrier layer comprises AlGaN material in which the Al composition remains constant within the layer.

6. The field-effect transistor according to claim 1, characterized in that, The gate structure includes: A p-type GaN layer is formed on the upper surface of the barrier layer; A gate layer, formed on the upper surface of the P-type GaN layer, is configured to apply a gate voltage.

7. The field-effect transistor according to claim 1, characterized in that, The gate structure is formed in the middle region of the barrier layer; The field-effect transistor further includes an insulating oxide layer that covers the area of ​​the barrier layer not covered by the gate structure, and also covers the area of ​​the channel layer not covered by the source layer and the barrier layer.

8. The field-effect transistor according to claim 1, characterized in that, The surface of the source layer near the N+ type GaN substrate is closer to the N+ type GaN substrate than the surface of the barrier layer near the N+ type GaN substrate.

9. A power electronic system, characterized in that, It includes a plurality of field-effect transistors as described in any one of claims 1 to 8, wherein the plurality of field-effect transistors are connected.

10. A method for fabricating a field-effect transistor, characterized in that, include: Provide an N+ type GaN substrate; An N-type GaN drift layer, a polarization doped gradient layer, a channel layer, a barrier layer, and a gate structure are formed on the N+ type GaN substrate in a vertically stacked manner. The barrier layer has a first end and a second end that are opposite each other in the lateral direction. The first end and the second end are recessed relative to the two sides of the channel layer. The barrier layer and the channel layer form a heterojunction to form a 2DEG channel. A source layer is formed on the channel layer, the source layer is insulated from the gate structure, the source layer is in contact with the first end of the barrier layer, and is connected to the 2DEG channel; A drain layer is formed on the surface of the N+ type GaN substrate away from the N- type GaN drift layer, and the drain layer is configured to be connected to an external circuit; wherein... The N-type GaN drift layer is configured to bear the high voltage applied by the drain layer to form a depletion region, and the polarization-doped gradient layer is configured to limit the high electric field peak in the depletion region. Furthermore, the polarization-doped gradient layer is configured to apply a vertical electric field force pointing towards the N+ type GaN substrate to the electrons moving to the second end, so that the electrons at the second end move vertically to the drain layer.

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