Method for improving nmos performance

Abstract

This application provides a method for improving the electrical properties of an NMOS transistor, comprising: Step 1, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming trenches in the interlayer dielectric layer; Step 2, forming a first work function metal layer within the trenches; Step 3, forming a second work function metal layer within the trenches located in the NMOS region of the substrate; Step 4, forming a third work function metal layer covering the second work function metal layer, wherein the stacked second and third work function metal layers constitute the NMOS work function metal layer, and the Al / Ti ratio of the third work function metal layer is less than the Al / Ti ratio of the second work function metal layer; Step 5, forming a metal gate within the trenches. This method increases the efficiency of aluminum diffusion without affecting production capacity, cavity environment, or TiAl layer thickness, thereby improving the electrical properties of the NMOS transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for improving the electrical properties of NMOS. Background Technology

[0002] In semiconductor manufacturing processes, NMOS uses an atomically deposited titanium aluminum (TiAl) layer as the work function metal layer. The work function of NMOS is adjusted by regulating the thickness of the TiAl layer or the Al / Ti ratio.

[0003] Increasing the thickness of the TiAl layer reduces the filling space for subsequent gate metal, causing defects such as voids, which affects electrical properties and yield. Increasing the Al / Ti ratio is often achieved by extending the infeed time and amount of Al-based precursor, but this method will cause negative effects such as reduced production capacity and a deteriorated cavity environment.

[0004] Limited by factors such as production capacity, trench filling space, and cavity environment, existing adjustment methods have very limited ability to adjust the work function of NMOS. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for improving the electrical properties of NMOS, in order to solve the problem of the limited ability of the prior art to regulate the work function of NMOS.

[0006] To achieve the above and other related objectives, this application provides a method for improving the electrical properties of NMOS, comprising: Step 1: Provide a substrate, and form an interlayer dielectric layer on the substrate, with trenches formed in the interlayer dielectric layer; Step two: Form the first work function metal layer within the trench; Step 3: Form a second work function metal layer in the trench located in the NMOS region of the substrate; Step 4: Form a third work function metal layer covering the second work function metal layer. The stacked second and third work function metal layers serve as the NMOS work function metal layers. The Al / Ti ratio of the third work function metal layer is less than that of the second work function metal layer. Step 5: Form a metal gate within the trench.

[0007] Preferably, the Al / Ti ratio of the second work function metal layer is greater than 4.5, and at most 5.0.

[0008] Preferably, the Al / Ti ratio of the third work function metal layer is less than 4.0, and the minimum is 3.0.

[0009] Preferably, before forming the first work function metal layer, the method further includes the step of sequentially forming a high dielectric constant dielectric layer and a capping layer on the sidewalls and bottom of the trench.

[0010] Preferably, the material of the coating layer includes titanium nitride.

[0011] Preferably, a deposition process is used to form a first work function metal layer, a second work function metal layer, and a third work function metal layer.

[0012] Preferably, the material of the first work function metal layer includes titanium nitride.

[0013] Preferably, the deposition process for forming the second work function metal layer and the third work function metal layer is atomic layer deposition.

[0014] Preferably, the total thickness of the second work function metal layer and the third work function metal layer is the same as the initial set thickness of the NMOS work function metal layer, and the time required to form the stacked second work function metal layer and the third work function metal layer is the initial set time for forming the NMOS work function metal layer.

[0015] Preferably, before forming the metal gate in the trench, the process further includes a step of forming a titanium nitride barrier layer covering the third work function metal layer using an atomic layer deposition process.

[0016] As described above, the method for improving the electrical properties of NMOS provided in this application has the following beneficial effects: it increases the efficiency of aluminum diffusion without affecting the production capacity, cavity environment, and TiAl layer thickness, thereby achieving the purpose of improving the electrical properties of NMOS. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 The flowchart shown is a method for improving the electrical properties of NMOS provided in an embodiment of this application. Figure 2 The graph shows the increase in Vt of NMOS based on the method for improving NMOS electrical properties provided in the embodiments of this application. Detailed Implementation

[0019] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0020] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0024] Please see Figure 1 The diagram illustrates a flowchart of a method for improving the electrical properties of NMOS provided in an embodiment of this application.

[0025] like Figure 1 As shown, the method for improving the electrical properties of NMOS includes the following steps: Step 1: Provide a substrate, and form an interlayer dielectric layer on the substrate, with trenches formed in the interlayer dielectric layer; Step two: Form the first work function metal layer within the trench; Step 3: Form a second work function metal layer in the trench located in the NMOS region of the substrate; Step 4: Form a third work function metal layer covering the second work function metal layer. The stacked second and third work function metal layers serve as the NMOS work function metal layers. The Al / Ti ratio of the third work function metal layer is less than that of the second work function metal layer. Step 5: Form a metal gate within the trench.

[0026] In step one, a substrate is provided. Optionally, the substrate may be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the substrate material may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material according to the type of device structure formed on the substrate, therefore the type of substrate should not limit the scope of protection of this invention.

[0027] Optionally, the material of the interlayer dielectric layer may include, but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).

[0028] For example, an interlayer dielectric layer is formed using a chemical vapor deposition process.

[0029] For example, the step of forming a trench in the interlayer dielectric layer includes: forming a photoresist layer on the interlayer dielectric layer by a coating process; exposing and developing the photoresist layer by a photolithography process to form a photoresist layer with a dummy gate pattern; using the photoresist layer with the dummy gate pattern as a mask, etching the exposed dummy gate by a plasma etching process to form a trench in the interlayer dielectric layer; and removing the photoresist layer with the dummy gate pattern by an ashing process.

[0030] In step two, before forming the first work function metal layer, a high dielectric constant (high k) dielectric layer and a capping layer are sequentially formed on the sidewalls and bottom of the trench. For example, the high k dielectric layer may be made of hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium dioxide (ZrO2), or hafnium zirconium oxide (HfZrOx), and the capping layer may be made of titanium nitride (TiN).

[0031] For example, a first work function metal layer is formed using a deposition process. This first work function metal layer serves as the work function metal layer of the PMOS metal gate device, and its material includes titanium nitride.

[0032] This deposition process can be carried out in a high-temperature environment, which can increase the molecular kinetic energy characteristics, enabling the deposition process to achieve higher step coverage and uniformity, thereby improving the electrical properties and yield of the formed first work function metal layer.

[0033] In step three, a second work function metal layer is first formed in the trench through a deposition process, and then the second work function metal layer located in the trench of the substrate PMOS region is removed through an etching process.

[0034] For example, the deposition process is an atomic layer deposition process.

[0035] In step four, a third work function metal layer is first formed in the trench through a deposition process, and then the third work function metal layer located in the trench of the substrate PMOS region is removed through an etching process.

[0036] For example, the deposition process is an atomic layer deposition process.

[0037] The stacked second and third work function metal layers serve as the work function metal layers of the NMOS metal gate device. Their material is TiAl, wherein the Al / Ti ratio of the second work function metal layer is greater than 4.5, with a maximum of 5.0; and the Al / Ti ratio of the third work function metal layer is less than 4.0, with a minimum of 3.0.

[0038] Compared to the third work function metal layer, the second work function metal layer has a larger Al / Ti ratio and is closer to the high-k dielectric layer, making downward diffusion of aluminum easier and thus better improving the NMOS electrical properties. Methods to increase the Al / Ti ratio include, but are not limited to, increasing the doping time / ratio of Al-based precursors.

[0039] Forming a third work function metal layer with a smaller Al / Ti ratio will protect the chamber environment and prevent an increase in particle sources due to excessive Al-based precursor incorporation.

[0040] Compared with the initial set thickness and time required to form a work function metal layer of an NMOS metal gate device in the prior art, the total thickness of the second work function metal layer and the third work function metal layer in the embodiment of this application is the same as the initial set thickness, and the time required to form the stacked second work function metal layer and the third work function metal layer remains unchanged.

[0041] In step five, before forming the metal gate in the trench, a titanium nitride barrier layer covering the third work function metal layer is formed using an atomic layer deposition process. The titanium nitride barrier layer is formed by the reaction of TiCl4 and NH3.

[0042] For example, the step of forming a metal gate includes: depositing a metal gate material layer on a substrate using a physical vapor deposition process, a chemical vapor deposition process, or a metal sputtering deposition process to fill the trench; and etching back the metal gate material layer to remove the metal gate material layer outside the trench region. For example, the etching back is plasma etching.

[0043] For example, the material of the metal gate includes tungsten.

[0044] like Figure 2 As shown, by implementing the method for improving the electrical properties of NMOS provided in the embodiments of this application, the threshold voltage (Vt) of NMOS located in different regions of the device is improved to varying degrees.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In summary, the method for improving NMOS electrical properties provided in this application increases aluminum diffusion efficiency without affecting production capacity, cavity environment, or TiAl layer thickness, thereby achieving the goal of improving NMOS electrical properties. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0047] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for improving the electrical properties of an NMOS transistor, characterized in that, The method includes: Step 1: Provide a substrate, and form an interlayer dielectric layer on the substrate, wherein trenches are formed in the interlayer dielectric layer; Step 2: Form a first work function metal layer within the trench; Step 3: Form a second work function metal layer in the trench located in the NMOS region of the substrate; Step 4: Form a third work function metal layer covering the second work function metal layer. The stacked second work function metal layer and the third work function metal layer serve as the NMOS work function metal layer. The Al / Ti ratio of the third work function metal layer is less than the Al / Ti ratio of the second work function metal layer. Step 5: Form a metal gate in the trench.

2. The method according to claim 1, characterized in that, The Al / Ti ratio of the second work function metal layer is greater than 4.5, with a maximum of 5.

0.

3. The method according to claim 1, characterized in that, The Al / Ti ratio of the third work function metal layer is less than 4.0, with a minimum of 3.

0.

4. The method according to claim 1, characterized in that, Before forming the first work function metal layer, the method further includes the step of sequentially forming a high dielectric constant dielectric layer and a capping layer on the sidewalls and bottom of the trench.

5. The method according to claim 4, characterized in that, The material of the coating layer includes titanium nitride.

6. The method according to claim 1, characterized in that, The first work function metal layer, the second work function metal layer, and the third work function metal layer are formed using a deposition process.

7. The method according to claim 1 or 6, characterized in that, The material of the first work function metal layer includes titanium nitride.

8. The method according to claim 6, characterized in that, The deposition process for forming the second work function metal layer and the third work function metal layer is atomic layer deposition.

9. The method according to claim 1, characterized in that, The total thickness of the second work function metal layer and the third work function metal layer is the same as the initial set thickness of the NMOS work function metal layer, and the time required to form the stacked second work function metal layer and the third work function metal layer is the initial set time for forming the NMOS work function metal layer.

10. The method according to claim 1, characterized in that, Before forming the metal gate in the trench, the process further includes forming a titanium nitride barrier layer covering the third work function metal layer using an atomic layer deposition process.

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