Semiconductor device

Abstract

A semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern and including a plurality of semiconductor patterns vertically spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns and including an inner electrode and an outer electrode, the inner electrode being disposed between a pair of adjacent semiconductor patterns and the outer electrode being disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns; and an inner spacer disposed between the inner electrode and the source / drain pattern, wherein the source / drain pattern includes a first semiconductor layer in contact with the plurality of semiconductor patterns, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0202918, filed on December 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] In this document, this disclosure relates to semiconductor devices, and more specifically, to semiconductor devices including field-effect transistors. Background Technology

[0003] Semiconductor devices comprise integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As semiconductor device dimensions and design rules continue to shrink, the miniaturization of MOSFETs is accelerating. However, as MOSFETs shrink, the operating characteristics of semiconductor devices may degrade. Therefore, various methods are being investigated to overcome the limitations imposed by the high integration density of semiconductor devices and to create semiconductor devices with improved electrical specificity. Summary of the Invention

[0004] Some example embodiments of this disclosure provide semiconductor devices with improved electrical characteristics.

[0005] The technical aspects of this invention are not limited to those described above, and other technical aspects not mentioned can be clearly understood by those skilled in the art from the following description.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern and including a plurality of semiconductor patterns vertically spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns, the gate electrode including an inner electrode and an outer electrode, the inner electrode being located between a pair of adjacent semiconductor patterns among the plurality of semiconductor patterns, and the outer electrode being located on the uppermost semiconductor pattern among the plurality of semiconductor patterns; and an inner spacer located between the inner electrode and the source / drain pattern, wherein the source / drain pattern includes a first semiconductor layer in contact with the plurality of semiconductor patterns, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, the inner spacer having a first tip length in a first direction, the first semiconductor layer having a second tip length in the first direction, and the second tip length being greater than the first tip length.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a PMOSFET region; an active pattern on the PMOSFET region; a channel pattern on the active pattern and including a plurality of semiconductor patterns vertically spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns, the gate electrode including an inner electrode and an outer electrode, the inner electrode being between a pair of adjacent semiconductor patterns among the plurality of semiconductor patterns, and the outer electrode being on the uppermost semiconductor pattern among the plurality of semiconductor patterns; a gate insulating layer between the gate electrode and adjacent semiconductor patterns; and an inner spacer between the source / drain pattern and the gate insulating layer surrounding the inner electrode, wherein the source / drain pattern includes a first semiconductor layer in contact with each of the plurality of semiconductor patterns, the inner spacer having a first horizontal width in a first direction, the first semiconductor layer having a second horizontal width in the first direction, and the second horizontal width being different from the first horizontal width.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first active pattern on a first active region of a substrate, and a second active pattern on a second active region of a substrate; an element separation layer filling a trench defining the first active pattern and the second active pattern; a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern vertically spaced apart from each other; a first source / drain pattern connected to the first channel pattern and a second source / drain pattern connected to the second channel pattern; a gate electrode on the first to third semiconductor patterns; a gate insulating layer between the first to third semiconductor patterns and the gate electrode; a first inner spacer between the gate insulating layer and the first source / drain pattern, and a second inner spacer between the gate insulating layer and the second source / drain pattern; a gate spacer on the sidewall of the gate electrode; and a gate capping pattern on the gate electrode. On the upper surface: an interlayer insulating layer on a gate cap pattern; an active contact penetrating the interlayer insulating layer to be electrically connected to each of the first source / drain pattern and the second source / drain pattern; a metal-semiconductor compound layer between the active contact and the first source / drain pattern, and between the active contact and the second source / drain pattern; a gate contact penetrating the interlayer insulating layer and the gate cap pattern to be electrically connected to the gate electrode; a first metal layer on the interlayer insulating layer, the first metal layer including power lines electrically connected to the active contact and the gate contact; and a second metal layer on the first metal layer, wherein the second metal layer includes a second wiring electrically connected to the first metal layer, the second active region is a PMOSFET region, the second source / drain pattern includes a first semiconductor layer in contact with the first semiconductor pattern to the third semiconductor pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, a second inner spacer having a silicon nitride-based insulating material, and the second source / drain pattern being spaced from the gate electrode by the second inner spacer.

[0009] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an active region on a substrate; forming a channel pattern by stacking a plurality of semiconductor patterns spaced apart from each other; forming a source / drain pattern on one side of the channel pattern such that the source / drain pattern is connected to the plurality of semiconductor patterns; forming a gate electrode on the plurality of semiconductor patterns, the gate electrode including an inner electrode and an outer electrode, the inner electrode being between a pair of adjacent semiconductor patterns among the plurality of semiconductor patterns, and the outer electrode being on the uppermost semiconductor pattern among the plurality of semiconductor patterns; and inserting an inner spacer between the inner electrode and the source / drain pattern, wherein forming the source / drain pattern includes: forming a first semiconductor layer in contact with the plurality of semiconductor patterns; forming a second semiconductor layer on the first semiconductor layer; and forming a third semiconductor layer on the second semiconductor layer, forming the inner spacer includes forming an inner spacer having a first tip length in a first direction, and forming the first semiconductor layer includes forming a first semiconductor layer having a second tip length in the first direction, the second tip length being less than the first tip length.

[0010] The formation of a third semiconductor layer can result in a germanium (Ge) concentration that is higher than that of the first and second semiconductor layers. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate some exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0012] Figures 1 to 3 This is a conceptual diagram of the logic units of a semiconductor device used to describe some exemplary embodiments of the concept according to the present invention;

[0013] Figure 4 It is a plan view used to describe an exemplary embodiment of a semiconductor device according to the concept of the present invention;

[0014] Figures 5A to 5D They are along Figure 4 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D';

[0015] Figure 6 It shows Figure 5B Enlarged view of an example embodiment of region M;

[0016] Figures 7A to 12D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention; and

[0017] Figures 13 to 17 It is used to describe the formation Figure 10B A magnified view of the method for region M. Detailed Implementation

[0018] Hereinafter, exemplary embodiments of the invention will be described in more detail with reference to the accompanying drawings, so as to further illustrate the concept of the invention.

[0019] As used herein, expressions such as “one of,” “one or more of,” “any one of,” “at least one of,” and “at least one selected from” modify the entire list of elements when following it, rather than individual elements within the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0020] Although the terms “identical,” “equal,” or “the same” are used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0021] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, the associated numerical values ​​are intended to include manufacturing or operational tolerances (e.g., ±10%) near said values. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended that precision of the geometry is not required, but tolerances of the shape are within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes.

[0022] Figures 1 to 3 This is a conceptual diagram used to describe the logic units of a semiconductor device according to some exemplary embodiments of the present invention.

[0023] refer to Figure 1 A single-height cell (SHC) can be configured. For example, a first power line M1_R1 and a second power line M1_R2 can be disposed on the substrate 100. The first power line M1_R1 can be a path providing the source voltage VSS (e.g., ground voltage). The second power line M1_R2 can be a path providing the drain voltage VDD (e.g., power supply voltage).

[0024] A single-height cell SHC can be defined between a first power line M1_R1 and a second power line M1_R2. The single-height cell SHC can include a first active region AR1 and a second active region AR2. Either the first active region AR1 or the second active region AR2 can be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 can be an NMOSFET region. In other words, the single-height cell SHC can have a structure with CMOS disposed between the first power line M1_R1 and the second power line M1_R2.

[0025] Each of the first active region AR1 and the second active region AR2 may have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as the first height HE1. The first height HE1 may be substantially the same as the distance (e.g., spacing) between the first electric field line M1_R1 and the second electric field line M1_R2.

[0026] A single-height SHC can constitute a logic unit. In this specification, a logic unit can represent a logic device that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic unit can include transistors used to construct the logic device and wiring connecting the transistors to each other.

[0027] refer to Figure 2 A dual-height cell (DHC) can be configured. For example, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 can be disposed on the substrate 100. The first power line M1_R1 can be disposed between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 can be a path providing the power supply voltage VSS.

[0028] The dual-height cell (DHC) can be defined between the second power line M1_R2 and the third power line M1_R3. The dual-height cell (DHC) can include two first active regions AR1 and two second active regions AR2.

[0029] One of the two second active regions AR2 can be adjacent to the second power line M1_R2. The other of the two second active regions AR2 can be adjacent to the third power line M1_R3. The two first active regions AR1 can be adjacent to the first power line M1_R1. In the plan view, the first power line M1_R1 can be located between the two first active regions AR1.

[0030] The length of the dual-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1The first height HE1 is approximately twice that of the second height. The two first active regions AR1 of the dual-height unit DHC can work together as a single active region.

[0031] According to the example embodiment, Figure 2 The dual-height cell (DHC) shown can be defined as a multi-height cell. Although not shown, a multi-height cell may include a tri-height cell whose height is approximately three times that of a single-height cell (SHC).

[0032] refer to Figure 3 The first single-height unit SHC1, the second single-height unit SHC2, and the double-height unit DHC can be disposed two-dimensionally on the substrate 100. The first single-height unit SHC1 can be disposed between the first electric field line M1_R1 and the second electric field line M1_R2. The second single-height unit SHC2 can be disposed between the first electric field line M1_R1 and the third electric field line M1_R3. The second single-height unit SHC2 can be adjacent to the first single-height unit SHC1 in the first direction D1.

[0033] The dual-height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0034] The separation structure DB can be disposed between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The active region of the dual-height unit DHC can be electrically separated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 through the separation structure DB.

[0035] Figure 4 This is a plan view used to describe an exemplary embodiment of a semiconductor device according to the present invention. Figures 5A to 5D They are along Figure 4 The cross-sectional views taken from lines A-A', B-B', C-C', and D-D'. Figure 6 It shows Figure 5B An enlarged view of an example embodiment of region M. Figure 4 and Figures 5A to 5D The semiconductor device shown is illustrated in more detail. Figure 1 An example of a single-height unit SHC.

[0036] refer to Figure 4 and Figures 5A to 5DA single-height cell (SHC) can be disposed on the substrate 100. Logic transistors constituting logic circuits can be disposed on the single-height cell (SHC). The substrate 100 can be a semiconductor substrate or a compound semiconductor substrate including silicon, germanium, silicon-germanium, etc. For example, the substrate 100 can be a silicon substrate.

[0037] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in a second direction D2. According to an example embodiment, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0038] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed on the substrate 100. The first active pattern AP1 may be disposed on a first active region AR1, and the second active pattern AP2 may be disposed on a second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically protruding portions that are part of the substrate 100.

[0039] A device separation layer ST may be disposed on substrate 100. The device separation layer ST may fill trench TR. The device separation layer ST may include a silicon oxide layer. The device separation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2, which will be described later.

[0040] A first channel pattern CH1 may be disposed on a first active pattern AP1. A second channel pattern CH2 may be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor patterns to the third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (e.g., third direction D3).

[0041] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon (e.g., single-crystal silicon). In an exemplary embodiment of the present invention, the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0042] Multiple first source / drain patterns SD1 can be disposed on a first active pattern AP1. Multiple first recesses RS1 can be formed on the first active pattern AP1. The first source / drain patterns SD1 can be disposed in the first recesses RS1 respectively. The first source / drain patterns SD1 can be impurity regions having a first conductivity type (e.g., N-type). A first channel pattern CH1 can be located between a pair of first source / drain patterns SD1. In other words, the stacked first semiconductor patterns to third semiconductor patterns SP1, SP2 and SP3 can connect a pair of first source / drain patterns SD1 to each other.

[0043] Multiple second source / drain patterns SD2 can be disposed on the second active pattern AP2. Multiple second recesses RS2 can be formed on the second active pattern AP2. The second source / drain patterns SD2 can be disposed in the second recesses RS2 respectively. The second source / drain patterns SD2 can be impurity regions having a second conductivity type (e.g., P-type). A second channel pattern CH2 can be located between a pair of second source / drain patterns SD2. In other words, the stacked first semiconductor patterns to third semiconductor patterns SP1, SP2 and SP3 can connect a pair of second source / drain patterns SD2 to each other.

[0044] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed in a selective epitaxial growth (SEG) process. For example, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at a height higher than the upper surface of the third semiconductor pattern SP3. As another example, the upper surface of at least one of the first source / drain pattern SD1 or the second source / drain pattern SD2 can be located at substantially the same height as the upper surface of the third semiconductor pattern SP3.

[0045] According to an exemplary embodiment of the present invention, the first source / drain pattern SD1 may include the same semiconductor element as the substrate 100 (e.g., Si). The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) with a lattice parameter larger than that of the semiconductor element (e.g., Si) of the substrate 100. Therefore, a pair of second source / drain patterns SD2 may apply compressive stress to the second channel pattern CH2 therebetween.

[0046] According to an exemplary embodiment of the present invention, the sidewalls of the second source / drain pattern SD2 may have a non-uniform indentation shape. In other words, the sidewalls of the second source / drain pattern SD2 may have a wave-like profile. The sidewalls of the second source / drain pattern SD2 may protrude toward the first to third semiconductor patterns SP1, SP2 and SP3 of the second channel pattern CH2.

[0047] Gate electrodes GE can be disposed on the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE can intersect the first channel pattern CH1 and the second channel pattern CH2 and can extend in the first direction D1. Each gate electrode GE can vertically overlap the first channel pattern CH1 and the second channel pattern CH2. Gate electrodes GE can be arranged at a first spacing in the second direction D2.

[0048] The gate electrode GE may include: a first internal electrode PO1 between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second internal electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3.

[0049] refer to Figure 5D The gate electrode GE can be disposed on the upper surface TS, the bottom surface BS, and the two sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. In other words, the transistor according to this example embodiment can be a three-dimensional field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET) or a gate-all-around field-effect transistor (GAAFET)), wherein the gate electrode GE surrounds its channel in three dimensions.

[0050] The first inner spacer ISP1 may be located on the first active region AR1 between the first source / drain pattern SD1 and the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the first source / drain pattern SD1, and the first inner spacer ISP1 may be located therebetween. The first inner spacer ISP1 may reduce or prevent leakage current from the gate electrode GE. For example, the first inner spacer ISP1 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0051] The second inner spacer ISP2 may be located on the second active region AR2 between the second source / drain pattern SD2 and the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the second source / drain pattern SD2, and the second inner spacer ISP2 may be located therebetween. The second inner spacer ISP2 may reduce or prevent the generation of leakage current and parasitic capacitance of the gate electrode GE. For example, the second inner spacer ISP2 may comprise at least one of silicon oxide, silicon nitride, or silicon oxynitride. For example, the second inner spacer ISP2 may comprise a silicon nitride-based insulating material. Reference will be made later. Figure 6The second inner spacer ISP2 according to the example embodiment is described in detail.

[0052] Return to reference Figure 4 and Figures 5A to 5D A pair of gate spacers GS can be respectively disposed on the two sidewalls of the outer electrode PO4 of the gate electrode GE. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The upper surface of the gate spacers GS can be higher than the upper surface of the gate electrode GE. The upper surface of the gate spacers GS can be coplanar with the upper surface of the first interlayer insulating layer 110, which will be described later. According to an example embodiment, the gate spacers GS can include at least one of SiCN, SiCON, or SiN. According to another example embodiment, the gate spacers GS can include a multilayer structure composed of at least two of SiCN, SiCON, or SiN.

[0053] A gate cap pattern GP may be disposed on the gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE in a first direction D1. The gate cap pattern GP may include a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described later. For example, the gate cap pattern GP may include at least one of SiON, SiCN, SiCON, or SiN.

[0054] The gate insulating layer GI may be located between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the upper surface TS, the bottom surface BS, and the two sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the upper surface of the device separation layer ST below the gate electrode GE.

[0055] According to exemplary embodiments of the present invention, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-dielectric layer. For example, the gate insulating layer GI may have a structure of stacked silicon oxide layers and high-dielectric layers. The high-dielectric layer may include a high-dielectric material having a higher dielectric constant than the silicon oxide layer. For example, the high-dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0056] According to another example embodiment, the semiconductor device may include a negative capacitance FET that uses a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric material layer having ferroelectric properties and / or a paraelectric material layer having paraelectric properties.

[0057] Ferroelectric material layers can have negative capacitance, and paraelectric material layers can have positive capacitance. For example, when at least two capacitors are connected in series and each capacitor has a positive capacitance value, the total capacitance becomes less than the capacitance of each individual capacitor. However, when at least one of the two or more capacitors connected in series has a negative capacitance value, the total capacitance can have a positive value and can be greater than the absolute value of the capacitance of each individual capacitor.

[0058] When a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric material layers can be increased. Utilizing this increase in total capacitance, transistors including ferroelectric material layers can exhibit a subthreshold swing (SS) of less than approximately 60 mV / decimal at room temperature.

[0059] The ferroelectric material layer can possess ferroelectric properties. For example, the ferroelectric material layer may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. Here, hafnium zirconium oxide may, for example, be hafnium oxide doped with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0060] The ferroelectric material layer may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the ferroelectric material included in the ferroelectric material layer.

[0061] When the ferroelectric material layer includes hafnium oxide, the dopants included in the ferroelectric material layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) or yttrium (Y).

[0062] When the dopant is aluminum (Al), the ferroelectric material layer may comprise approximately 3 at% to approximately 8 at% aluminum. Here, the dopant ratio may be the ratio of aluminum to the sum of hafnium and aluminum.

[0063] When the dopant is silicon (Si), the ferroelectric material layer may comprise about 2 at% to about 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may comprise about 2 at% to about 10 at% yttrium (Y). When the dopant is gadolinium (Gd), the ferroelectric material layer may comprise about 1 at% to about 7 at% gadolinium (Gd). When the dopant is zirconium (Zr), the ferroelectric material layer may comprise about 50 at% to about 80 at% zirconium (Zr).

[0064] The paraelectric material layer may have paraelectric properties. For example, the paraelectric material layer may include at least one of silicon oxide or a metal oxide having a high dielectric constant. For example, the metal oxide included in the paraelectric material layer may include at least one of hafnium oxide, zirconium oxide, or aluminum oxide, but the exemplary embodiments of the present invention are not limited thereto.

[0065] The ferroelectric material layer and the paraelectric material layer may contain the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when both the ferroelectric and paraelectric material layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric material layer is different from the crystal structure of the hafnium oxide in the paraelectric material layer.

[0066] The ferroelectric material layer can have a thickness suitable for exhibiting ferroelectric properties. For example, the ferroelectric material layer can have a thickness of about 0.5 nm to about 10 nm, but exemplary embodiments of the present invention are not limited thereto. Because each ferroelectric material can have a critical thickness at which it begins to exhibit ferroelectric properties, the ferroelectric material layer can have a different thickness depending on the ferroelectric material.

[0067] For example, the gate insulating layer GI may include a ferroelectric material layer. As another example, the gate insulating layer GI may include multiple ferroelectric material layers spaced apart from each other. The gate insulating layer GI may have a stacked structure in which multiple ferroelectric material layers and multiple paraelectric material layers are stacked alternately.

[0068] Return to reference Figure 4 and Figures 5A to 5D The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI to be adjacent to the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. By controlling the thickness and composition of the first metal pattern, the target threshold voltage of the transistor can be achieved. For example, the first inner electrode to the third inner electrode PO1, PO2, and PO3 of the gate electrode GE may be constituted by the first metal pattern made of work function metal.

[0069] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Furthermore, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0070] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), and tungsten (W). For example, the external electrode PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0071] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The upper surface of the first interlayer insulating layer 110 may be substantially coplanar with the upper surface of the gate cap pattern GP and the upper surface of the gate spacer GS. A second interlayer insulating layer 120 covering the gate cap pattern GP may be disposed on the first interlayer insulating layer 110. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. For example, the first to fourth interlayer insulating layers 110, 120, 130, and 140 may all comprise a silicon oxide layer.

[0072] A single-height element SHC may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in a second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. A single-height element SHC may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0073] A pair of separate structures DB, facing each other in the second direction D2, can be disposed on both sides of the single-height cell SHC. For example, the pair of separate structures DB can be disposed on the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The separate structures DB can extend parallel to the gate electrode GE in the first direction D1. The spacing between the separate structures DB and the adjacent gate electrode GE can be the same as the first spacing.

[0074] The separation structure DB can penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 to extend into the interior of the first active pattern AP1 and the second active pattern AP2. The separation structure DB can penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB can electrically separate the active region of a single-height unit SHC from the active region of another adjacent unit.

[0075] An active contact AC can be provided, which penetrates the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to electrically connect to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be respectively provided on both sides of the gate electrode GE. In a plan view, the active contact AC can have a strip-like form extending in the first direction D1.

[0076] The active contact AC can be a self-aligned contact. In other words, the active contact AC can be formed using a gate cap pattern GP and a gate spacer GS in self-alignment. For example, the active contact AC can at least partially cover the sidewalls of the gate spacer GS. Although not shown, the active contact AC can partially cover the upper surface of the gate cap pattern GP.

[0077] A metal-semiconductor compound layer SC (e.g., a silicide layer) may be located between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0078] A gate contact GC can be provided, which penetrates the second interlayer insulating layer 120 and the gate cap pattern GP, ​​to electrically connect to the gate electrode GE, respectively. In a plan view, the gate contact GC can be positioned to overlap with the first active region AR1 and the second active region AR2, respectively. For example, the gate contact GC can be located on the second active pattern AP2 (see...). Figure 5B ).

[0079] According to an exemplary embodiment of the present invention, reference is made to Figure 5B The upper part of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP can be lower than the bottom surface of the gate contact GC. In other words, due to the upper insulating pattern UIP, the upper surface of the active contact AC adjacent to the gate contact GC can become lower than the bottom surface of the gate contact GC. Therefore, electrical short circuits caused by contact between the gate contact GC and the adjacent active contact AC can be reduced or prevented.

[0080] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, or cobalt. The blocking pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The blocking pattern BM may include a metal layer and / or a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, or platinum nitride (PtN) layer.

[0081] The first metal layer M1 may be disposed in the third interlayer insulation layer 130. For example, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, and a first wiring M1_I. Each of the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0082] For example, the first power line M1_R1 and the second power line M1_R2 can be respectively set on the third boundary BD3 and the fourth boundary BD4 of the single-height unit SHC. The first power line M1_R1 can extend along the third boundary BD3 in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 in the second direction D2.

[0083] The first wiring M1_I of the first metal layer M1 can be disposed between the first power line M1_R1 and the second power line M1_R2. The first wiring M1_I of the first metal layer M1 can be arranged at a second spacing in the first direction D1. The second spacing can be smaller than the first spacing. The line width of each first wire M1_I can be smaller than the line width of each of the first power line M1_R1 and the second power line M1_R2.

[0084] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively. The active contact AC and the wirings of the first metal layer M1 may be electrically connected to each other through the first via VI1. The gate contact GC and the wirings of the first metal layer M1 may be electrically connected to each other through the first via VI1.

[0085] The wiring of the first metal layer M1 and the first via VI1 beneath it can be formed in separate processes. Each of the wiring of the first metal layer M1 and the first via VI1 can be formed in a single damascene process. The semiconductor device according to this example embodiment can be formed using a process for manufacturing semiconductor devices with a design rule of less than about 20 nm.

[0086] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second wirings M2_I. Each second wiring M2_I of the second metal layer M2 may have a linear or strip shape extending in the first direction D1. In other words, the second wirings M2_I may extend parallel to each other in the first direction D1.

[0087] The second metal layer M2 may further include a second via VI2 disposed below the second wiring M2_I. The wiring of the first metal layer M1 and the wiring of the second metal layer M2 can be electrically connected to each other through the second via VI2. For example, the wiring of the second metal layer M2 and the second via VI2 below it can be formed together by a dual damascene process.

[0088] The wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include the same conductive material or different conductive materials. For example, the wiring of the first metal layer M1 and the wiring of the second metal layer M2 may include at least one metallic material selected from aluminum, copper, tungsten, molybdenum, ruthenium, or cobalt. Although not shown, metal layers (e.g., M3, M4, M5, etc.) stacked on the fourth interlayer insulating layer 140 may be additionally provided. Each of the stacked metal layers may include wiring for routing between cells.

[0089] Reference Figure 6 The second channel pattern CH2, the second source / drain pattern SD2, and the second inner spacer ISP2 are described in more detail. (See reference) Figure 6 The second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are spaced apart from each other and stacked vertically. In an exemplary embodiment of the invention, the first to third semiconductor patterns SP1, SP2, and SP3 may have the same channel length. According to another exemplary embodiment, the uppermost third semiconductor pattern SP3 among the first to third semiconductor patterns SP1, SP2, and SP3 may have the shortest channel length. The lowermost first semiconductor pattern SP1 among the first to third semiconductor patterns SP1, SP2, and SP3 may have the longest channel length.

[0090] The channel length of each of the first to third semiconductor patterns SP1, SP2, and SP3 may be longer than the gate width of each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE, and the gate width of the outer electrode PO4 of the gate electrode GE. The channel length may be defined as a horizontal distance in the second direction D2, and the gate width may be defined as a horizontal distance in the second direction D2.

[0091] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include a concave sidewall. Therefore, the channel length of each of the first to third semiconductor patterns SP1, SP2, and SP3 may have a maximum length on its upper and lower surfaces and a minimum length at its center. Each of the first to third semiconductor patterns SP1, SP2, and SP3 may have a tip TP on its upper surface.

[0092] For example, the upper surface of the third semiconductor pattern SP3 may have a first length LI1 in the second direction D2, and the lower surface of the third semiconductor pattern SP3 may have a second length LI2 in the second direction D2. The first length LI1 and the second length LI2 may correspond to the maximum length. The outer electrode PO4 of the gate electrode GE may have a third length LI3 in the second direction D2, and the third inner electrode PO3 of the gate electrode GE may have a fourth length LI4 in the second direction D2. The third inner electrode PO3 and the gate insulating layer GI surrounding the third inner electrode PO3 may have a fourth length LI4 in the second direction D2.

[0093] Each of the first length LI1 and the second length LI2 can be greater than the third length LI3 and the fourth length LI4. The minimum length of the third semiconductor pattern SP3 in the second direction D2 can be equal to or greater than the third length LI3 and the fourth length LI4.

[0094] The second source / drain pattern SD2 may include a first semiconductor layer SEL1 in contact with the first to third semiconductor patterns SP1, SP2 and SP3, a second semiconductor layer SEL2 on the first semiconductor layer SEL1, and a third semiconductor layer SEL3 on the second semiconductor layer SEL2. The first semiconductor layer SEL1 may protrude toward each of the first to third semiconductor patterns SP1, SP2 and SP3, and may have a protruding side surface toward the corresponding semiconductor pattern in the first to third semiconductor patterns SP1, SP2 and SP3.

[0095] The first semiconductor layer SEL1 can also be disposed at the bottom of the second source / drain pattern SD2. The first semiconductor layer SEL1 disposed at the bottom can be located between the second active pattern AP2 and the second semiconductor layer SEL2.

[0096] The second source / drain pattern SD2 may include silicon germanium (SiGe). That is, the first semiconductor layer SEL1, the second semiconductor layer SEL2, and the third semiconductor layer SEL3 may all include silicon germanium (SiGe), but may have different germanium (Ge) concentrations.

[0097] The third semiconductor layer SEL3 may have a higher germanium (Ge) concentration than the first semiconductor layer SEL1 and the second semiconductor layer SEL2. The second semiconductor layer SEL2 may have a higher germanium (Ge) concentration than the first semiconductor layer SEL1. For example, the first semiconductor layer SEL1 may have a germanium (Ge) concentration of about 2 at% to about 8 at%, or about 4 at% to about 8 at%. The second semiconductor layer SEL2 may have a germanium (Ge) concentration of about 10 at% to about 20 at%, and the third semiconductor layer SEL3 may have a germanium (Ge) concentration of about 30 at% to about 70 at%.

[0098] The second inner spacer ISP2 can be located between the first to third inner electrodes PO1, PO2, and PO3 and the second source / drain pattern SD2. For example, the second inner spacer ISP2 can be located between the gate insulating layer GI surrounding the first to third inner electrodes PO1, PO2, and PO3 and the second semiconductor layer SEL2 and the third semiconductor layer SEL3 of the second source / drain pattern SD2. That is, the second source / drain pattern SD2 can be separated from the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE by the second inner spacer ISP2.

[0099] The second inner spacer ISP2 may have a first tip length WI1 in the second direction D2. The first tip length WI1 of the second inner spacer ISP2 may be defined as the distance in the second direction D2 from the tip TP of the second semiconductor pattern SP2 to a sidewall of the second inner spacer ISP2. For example, this sidewall may be a sidewall that contacts the gate insulating layer GI surrounding the third inner electrode PO3. The first semiconductor layer SEL1 may have a second tip length WI2 in the second direction D2. The second tip length WI2 of the first semiconductor layer SEL1 may be defined as the distance in the second direction D2 from the tip TP of the second semiconductor pattern SP2 to a side surface of the first semiconductor layer SEL1. This side surface may be a side surface that contacts the second semiconductor pattern SP2. The first tip length WI1 may be greater than the second tip length WI2.

[0100] The second inner spacer ISP2 may have a third tip length WI3 in the direction opposite to the second direction D2. The third tip length WI3 of the second inner spacer ISP2 may be defined as the distance from the tip TP of the second semiconductor pattern SP2 to another sidewall of the second inner spacer ISP2. For example, this other sidewall may be a sidewall in contact with the second semiconductor layer SEL2 or the third semiconductor layer SEL3. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may have a fourth tip length WI4 in the direction opposite to the second direction D2. The fourth tip length WI4 of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may be defined as the distance from the tip TP of the second semiconductor pattern SP2 to the inner surface of the second semiconductor layer SEL2. The fourth tip length WI4 may be greater than the third tip length WI3. The fourth tip length WI4 may be greater than the first tip length to the third tip lengths WI1, WI2, and WI3. The third tip length WI3 may be greater than the second tip length WI2. In other words, the inner surface of the second semiconductor layer SEL2 may be farther in the second direction D2 than the distance between one side surface of the second inner spacer ISP2 and the tip TP.

[0101] The second inner spacer ISP2 may have a first horizontal width WD1 in the second direction D2. The first horizontal width WD1 may be defined as the horizontal distance from one sidewall of the second inner spacer ISP2 to the other sidewall (as described above). The first semiconductor layer SEL1 may have a second horizontal width WD2 in the second direction D2. The second horizontal width WD2 may be defined as the horizontal distance from one side surface of the first semiconductor layer SEL1 to the other side surface (as described above). The second horizontal width WD2 may be the same as or different from the first horizontal width WD1. For example, the first horizontal width WD1 may be greater than the second horizontal width WD2. As another example, the second horizontal width WD2 may be from about 2 nm to about 6 nm.

[0102] The second inner spacer ISP2 may include a silicon nitride-based insulating material. This insulating material may include at least one selected from the group consisting of SiN, SiCN, SiOCN, and SiBCN. The second inner spacer ISP2 may include materials that are adjacent to the first inner spacer ISP1 (see [link to first inner spacer ISP1]). Figure 5A The same insulating material. For example, the second inner spacer ISP2 and the first inner spacer ISP1 (see...) Figure 5A It can include silicon nitride-based insulating materials, but it can also include different insulating materials.

[0103] Figures 7A to 12D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Figures 13 to 17 It is used to describe the formation Figure 10B A magnified view of the method for region M. For example, Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A Is with Figure 4 The cross-sectional view corresponding to line A-A'. Figure 9B , Figure 10B , Figure 11B and Figure 12B Is with Figure 4 The cross-sectional view corresponding to line B-B'. Figure 9C , Figure 10C , Figure 11C and Figure 12C Is with Figure 4 The cross-sectional view corresponding to line C-C'. Figure 7B , Figure 8B , Figure 11D and Figure 12D Is with Figure 4 The cross-sectional view corresponding to line D-D'.

[0104] refer to Figure 7A and Figure 7B A substrate 100 comprising a first active region AR1 and a second active region AR2 can be provided. Alternating stacked active layers ACL and sacrificial layers SAL can be formed on the substrate 100. The active layer ACL may comprise one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and the sacrificial layer SAL may comprise another of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0105] The sacrificial layer SAL can include a material that is etch-selective for the active layer ACL. For example, the active layer ACL can include silicon (Si), and the sacrificial layer SAL can include silicon germanium (SiGe). Each sacrificial layer SAL can have a germanium (Ge) concentration of about 10 at% to about 30 at%.

[0106] Mask patterns can be formed on the first active region AR1 and the second active region AR2 of the substrate 100, respectively. The mask patterns can have a linear or strip shape extending in the second direction D2.

[0107] The trench TR defining the first active pattern AP1 and the second active pattern AP2 can be formed by performing a patterning process using a mask pattern as an etching mask. The first active pattern AP1 can be formed on the first active region AR1. The second active pattern AP2 can be formed on the second active region AR2.

[0108] A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP may include alternately stacked active layers ACL and sacrificial layers SAL. The stacked pattern STP can be formed together with the first active pattern AP1 and the second active pattern AP2 during the patterning process.

[0109] A device separation layer ST that fills the trench TR can be formed. For example, an insulating layer covering the first active pattern AP1 and the second active pattern AP2 and the stacked pattern STP can be formed on the front surface of the substrate 100. The device separation layer ST can be formed by recessing the insulating layer until the stacked pattern STP is exposed.

[0110] The component separation layer ST may include an insulating material (e.g., a silicon oxide layer). The stacked pattern STP may be exposed above the component separation layer ST. In other words, the stacked pattern STP may protrude vertically above the component separation layer ST.

[0111] refer to Figure 8A and Figure 8B Sacrificial patterns PP intersecting the stacked pattern STP can be formed on the substrate 100. Each sacrificial pattern PP can be formed as a line or strip shape extending in a first direction D1. The sacrificial patterns PP can be arranged along a second direction D2 with a first spacing.

[0112] For example, forming a sacrificial pattern PP may include: forming a sacrificial layer on the front surface of a substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer may include polysilicon.

[0113] A pair of gate spacers GS can be formed on the two sidewalls of each sacrificial pattern PP. Forming the gate spacers GS may include: conformally forming a gate spacer layer on the front surface of the substrate 100, and anisotropically etching the gate spacer layer. In an exemplary embodiment of the present invention, the gate spacers GS may be a multilayer comprising at least two layers.

[0114] refer to Figures 9A to 9C A first groove RS1 can be formed in a stacked pattern STP on a first active pattern AP1. A second groove RS2 can be formed in a stacked pattern STP on a second active pattern AP2. During the formation of the first groove RS1 and the second groove RS2, the element separation layer ST on both sides of each of the first active pattern AP1 and the second active pattern AP2 can be further recessed (see [link to documentation]). Figure 9C ).

[0115] For example, the first recess RS1 can be formed by etching the stacked pattern STP on the first active pattern AP1 using a hard mask pattern MP and a gate spacer GS as an etch mask. The first recess RS1 can be formed between a pair of sacrificial patterns PP.

[0116] First semiconductor patterns to third semiconductor patterns SP1, SP2, and SP3 can be formed from the active layer ACL and stacked sequentially between adjacent first grooves RS1. The first semiconductor patterns to third semiconductor patterns SP1, SP2, and SP3 between adjacent first grooves RS1 can constitute a first channel pattern CH1.

[0117] For example, a first recess RS1 can be formed between sacrificial patterns PP, and the width of the first recess RS1 in the second direction D2 can become smaller in the direction closer to the substrate 100. The sacrificial layer SAL can be exposed by the first recess RS1. A process of selectively etching the exposed sacrificial layer SAL can be performed. This etching process can include a wet etching process that selectively removes only silicon and germanium. The first recessed region IDR can be formed by recessing each sacrificial layer SAL in the etching process.

[0118] A first inner spacer ISP1 can be formed to fill the first recessed region IDR. Forming the first inner spacer ISP1 may include: forming an insulating layer that fills the first recessed region IDR through a first groove RS1, and performing wet etching on the insulating layer exposed outside the first recessed region IDR. The insulating layer may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The first inner spacer ISP1 may be located between the first groove RS1 and the sacrificial layer SAL.

[0119] Refer again Figures 9A to 9C The second recess RS2 can be formed in a stacked pattern STP on the second active pattern AP2 in a process similar to that used to form the first recess RS1. The second recess region IDE can be formed by selectively etching the sacrificial layer SAL exposed by the second recess RS2. Due to the second recess region IDE, the second recess RS2 can have wavy inner sidewalls. A second inner spacer ISP2 can be formed on the second active pattern AP2 in the second recess region IDE. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recess RS2s can constitute a second channel pattern CH2. (Refer to...) Figures 10A to 10C as well as Figures 13 to 17 The formation of the second inner spacer ISP2 is described in detail.

[0120] refer to Figures 10A to 10CA first source / drain pattern SD1 can be formed in the first groove RS1. For example, an epitaxial layer filling the first groove RS1 can be formed by performing a SEG process using the inner sidewall of the first groove RS1 as a seed layer. The epitaxial layer can be grown using the first to third semiconductor patterns SP1, SP2, and SP3 exposed by the first groove RS1 and the substrate 100 as seed layers. For example, the SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0121] According to an exemplary embodiment of the present invention, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. During the formation of the first source / drain pattern SD1, impurities (e.g., phosphorus, arsenic, or antimony) that give the first source / drain pattern SD1 an N-type nature may be implanted in situ. Alternatively, impurities may be implanted into the first source / drain pattern SD1 after its formation.

[0122] A second source / drain pattern SD2 can be formed separately in the second groove RS2. For example, the second source / drain pattern SD2 can be formed by performing a SEG process that uses the inner sidewall of the second groove RS2 as a seed layer.

[0123] According to an exemplary embodiment of the present invention, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) with a lattice parameter larger than that of the semiconductor element of the substrate 100. During the formation of the second source / drain pattern SD2, impurities (e.g., boron, gallium, or indium) that give the second source / drain pattern SD2 a p-type shape may be implanted in situ. Alternatively, impurities may be implanted into the second source / drain pattern SD2 after its formation.

[0124] Figures 13 to 17 It is used to describe the formation Figure 9B Region M and Figure 10B A magnified view of the method for region M. (Reference) Figure 13 A second groove RS2 can be formed between the sacrificial patterns PP. The width of the second groove RS2 in the second direction D2 can be made smaller in the direction closer to the substrate 100. The second groove RS2 can be formed by partially removing the upper surface of the second active pattern AP2.

[0125] The sacrificial layer SAL can be exposed via a second recess RS2. A process for selectively etching the exposed sacrificial layer SAL can be performed. This etching process may include a wet etching process that selectively removes only silicon and germanium. Each sacrificial layer SAL can be recessed during the etching process to form a second recessed region IDE. Due to the second recessed region IDE, the sidewalls of the sacrificial layer SAL can be recessed.

[0126] refer to Figure 14 A preliminary insulating layer ISPL can be formed to fill the second recessed region IDE. Forming the preliminary insulating layer ISPL can be achieved by forming an ISPL that fills the second recessed region IDE through the second groove RS2. The preliminary insulating layer ISPL can be formed by performing a chemical vapor deposition (CVD) process. The preliminary insulating layer ISPL may include a silicon nitride-based insulating material. For example, the insulating material may include at least one selected from the group consisting of SiN, SiCN, SiOCN, and SiBCN.

[0127] refer to Figure 15 The second inner spacer ISP2 can be formed by wet etching of the initial insulating layer ISPL exposed outside the second recessed region IDE. The second active pattern AP2 and the second channel pattern CH2, excluding the initial insulating layer ISPL, can be formed without loss due to the etching selectivity of the wet etching process. The shape of one side surface of the second inner spacer ISPL formed by the wet etching process can correspond to the shape of the inner surface of the initial insulating layer ISPL. The second inner spacer ISP2 can be positioned between the second recess RS2 and the sacrificial layer SAL.

[0128] refer to Figure 16 After the second inner spacer ISP2 is formed, the first to third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 can be exposed by the second recess RS2. A process can be performed to selectively etch the first to third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 exposed by the second recess RS2. This etching process can include a wet etching process that selectively removes only silicon.

[0129] The first to third channel recesses CRS1, CRS2, and CRS3 can be formed by partially etching each of the first to third semiconductor patterns SP1, SP2, and SP3. For example, the first channel recess CRS1 can be formed by horizontally recessing the first semiconductor pattern SP1, the second channel recess CRS2 can be formed by horizontally recessing the second semiconductor pattern SP2, and the third channel recess CRS3 can be formed by horizontally recessing the third semiconductor pattern SP3. Due to the first to third channel recesses CRS1, CRS2, and CRS3, the second recess RS2 can have a wavy inner sidewall.

[0130] A first concave sidewall can be formed in a first semiconductor pattern SP1 via a first channel groove CRS1, a second concave sidewall can be formed in a second semiconductor pattern SP2 via a second channel groove CRS2, and a third concave sidewall can be formed in a third semiconductor pattern SP3 via a third channel groove CRS3. Due to the corresponding channel grooves in the first to third channel grooves CRS1, CRS2, and CRS3, each of the first to third semiconductor patterns SP1, SP2, and SP3 can have a tip TP on its upper surface.

[0131] For example, due to the third channel groove CRS3, the upper surface of the third semiconductor pattern SP3 can have a first length LI1, and due to the third channel groove CRS3, the lower surface of the third semiconductor pattern SP3 can have a second length LI2. The second length LI2 and the first length LI1 can be substantially the same.

[0132] refer to Figure 17 The SEG process can be performed using the second active pattern AP2 and the first to third semiconductor patterns SP1, SP2, and SP3 in the second groove RS2 as seed layers. Therefore, the first semiconductor layer SEL1 can be grown in the second groove RS2.

[0133] The first semiconductor layer SEL1 grown on the first to third semiconductor patterns SP1, SP2 and SP3 can fill the first to third channel recesses CRS1, CRS2 and CRS3. The first semiconductor layer SEL1 grown on the second active pattern AP2 can fill the lower part of the second recess RS2.

[0134] The first semiconductor layer SEL1 on the first semiconductor pattern to the third semiconductor patterns SP1, SP2 and SP3 can be... <111> More growth occurs in the direction of growth. Meanwhile, because the second inner spacer ISP2 is not used as a seed crystal, the first semiconductor layer SEL1 will not grow on the second inner spacer ISP2.

[0135] According to an exemplary embodiment of the present invention, even when the growth direction of the first semiconductor layer SEL1 is <111> In this orientation, the second semiconductor layer SEL2 can also be formed using first channel trenches to third channel trenches CRS1, CRS2, and CRS3 to cover all surfaces of the second inner spacer ISP2. By increasing the horizontal growth length of the first semiconductor layer SEL1 using first channel trenches to third channel trenches CRS1, CRS2, and CRS3, the time required for the second semiconductor layer SEL2 to completely cover the second inner spacer ISP2 can be ensured. That is, the second semiconductor layer SEL2 can cover the first semiconductor layer SEL1, the second inner spacer ISP2, and part of the gate spacer GS.

[0136] The second groove RS2 can be completely filled by performing a SEG process using the second semiconductor layer SEL2 as a seed layer. Therefore, a third semiconductor layer SEL3 can be grown in the second groove RS2. By sequentially forming the first semiconductor layer SEL1 and the second semiconductor layer SEL2, a third semiconductor layer SEL3 with a relatively high germanium (Ge) concentration can be formed to occupy a larger volume. That is, according to an exemplary embodiment of the present invention, the third semiconductor layer SEL3 with a relatively high germanium (Ge) concentration can occupy a larger volume in the second source / drain pattern SD2 compared to the first semiconductor layer SEL1 and the second semiconductor layer SEL2 with relatively low germanium (Ge) concentrations in the second source / drain pattern SD2.

[0137] Return to reference Figure 17 According to exemplary embodiments of the present invention, the second source / drain pattern SD2 can be formed by forming a first semiconductor layer SEL1 using first to third channel recesses CRS1, CRS2, and CRS3, and forming a second semiconductor layer SEL2 to completely cover the second inner spacer ISP2. Therefore, the generation of parasitic capacitance and leakage current caused by the second inner spacer ISP2 can be reduced or prevented. Thus, the method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention can guarantee improved electrical characteristics of the device.

[0138] refer to Figures 11A to 11D A first interlayer insulating layer 110 can be formed covering the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0139] The first interlayer insulating layer 110 can be planarized until the upper surface of the sacrificial pattern PP is exposed. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP can be completely removed during the planarization process. As a result, the upper surface of the first interlayer insulating layer 110 can be coplanar with the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS.

[0140] Exposed sacrificial pattern PP can be selectively removed. The outer region ORG exposing the first channel pattern CH1 and the second channel pattern CH2 can be formed by removing the sacrificial pattern PP (see [link to documentation]). Figure 11D Removing the sacrificial pattern PP can include wet etching using an etchant that selectively etches polysilicon.

[0141] The inner region IRG is formed by selectively removing the sacrificial layer SAL exposed through the outer region ORG (see [link]). Figure 11DFor example, the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 can be retained, and only the sacrificial layer SAL can be removed by performing an etching process that selectively etches the sacrificial layer SAL. This etching process can have a relatively high etching rate for silicon-germanium with a relatively high germanium concentration. For example, for silicon-germanium with a germanium concentration greater than about 10 at%, this etching process can have a relatively high etching rate.

[0142] The sacrificial SAL layer on the first active region AR1 and the second active region AR2 can be removed during the etching process. The etching process can be wet etching. The etchant used in the etching process can rapidly remove the sacrificial SAL layer with a relatively high germanium concentration.

[0143] Return to reference Figure 11D By selectively removing the sacrificial layer SAL, only the stacked first semiconductor patterns to the third semiconductor patterns SP1, SP2, and SP3 can be retained on each of the first active pattern AP1 and the second active pattern AP2. The first internal regions to the third internal regions IRG1, IRG2, and IRG3 can be formed respectively by removing the sacrificial layer SAL.

[0144] For example, a first internal region IRG1 can be formed between an active pattern AP1 or AP2 and a first semiconductor pattern SP1, a second internal region IRG2 can be formed between the first semiconductor pattern SP1 and a second semiconductor pattern SP2, and a third internal region IRG3 can be formed between the second semiconductor pattern SP2 and a third semiconductor pattern SP3.

[0145] Return to reference Figures 11A to 11D A gate insulating layer GI can be formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI can be formed around each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI can be formed in each of the first to third inner regions IRG1, IRG2, and IRG3. The gate insulating layer GI can be formed in the outer region ORG.

[0146] refer to Figures 12A to 12D A gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE may include: first inner electrodes PO1, PO2, and PO3 respectively formed in the first inner region to the third inner region IRG1, IRG2, and IRG3; and an outer electrode PO4 formed in the outer region ORG. The gate electrode GE can be recessed to reduce its height. A gate capping pattern GP can be formed on the recessed gate electrode GE.

[0147] Refer again Figures 5A to 5DA second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. Active contacts AC may be formed that penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to electrically connect to the first source / drain pattern SD1 and the second source / drain pattern SD2. Gate contacts GC may be formed that penetrate the second interlayer insulating layer 120 and the gate cap pattern GP to electrically connect to the gate electrode GE.

[0148] Each of forming the active contact AC and the gate contact GC may include: forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be formed conformally and may include a metal layer / metal nitride layer. The conductive pattern FM may include a low-resistance metal.

[0149] A separation structure DB can be formed on the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The separation structure DB can penetrate the gate electrode GE to extend from the second interlayer insulating layer 120 into the interior of the active pattern AP1 or AP2. The separation structure DB may include an insulating material (e.g., a silicon oxide layer or a silicon nitride layer).

[0150] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0151] In the semiconductor device of an exemplary embodiment of the present invention, an internal spacer can be formed between the source / drain pattern and the gate electrode on the PMOSFET region to reduce parasitic capacitance and leakage current generated on the PMOSFET element. Additionally, electrical short circuits between the gate electrode and the source / drain pattern can be reduced.

[0152] The source / drain pattern on the PMOSFET region may include multiple layers with different germanium concentrations to reduce parasitic capacitance and leakage current generated on the PMOSFET element, together with the inner spacer. In other words, the electrical characteristics of the semiconductor device according to an exemplary embodiment of the present invention can be improved.

[0153] While some exemplary embodiments of the inventive concept have been described, it will be understood that this disclosure should not be limited to these exemplary embodiments, and those skilled in the art can make various changes and modifications within the spirit and scope of the inventive concept claimed below. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and are not intended to limit this disclosure.

Claims

1. A semiconductor device, comprising: Substrate, including active patterning; The channel pattern is on the active pattern and includes a plurality of semiconductor patterns that are vertically spaced apart from each other. Source / drain patterns are connected to the plurality of semiconductor patterns; A gate electrode is provided on the plurality of semiconductor patterns. The gate electrode includes an inner electrode and an outer electrode. The inner electrode is located between a pair of adjacent semiconductor patterns among the plurality of semiconductor patterns, and the outer electrode is located on the uppermost semiconductor pattern among the plurality of semiconductor patterns. as well as An inner spacer, located between the inner electrode and the source / drain pattern, The source / drain pattern includes a first semiconductor layer in contact with the plurality of semiconductor patterns, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. The inner spacer has a first tip length in a first direction. The first semiconductor layer has a second tip length in the first direction, and The length of the first tip is greater than the length of the second tip.

2. The semiconductor device according to claim 1, wherein... The inner spacer has a third tip length in the direction opposite to the first direction. The first semiconductor layer and the second semiconductor layer have a fourth tip length in the opposite direction to the first direction, and The length of the fourth tip is greater than the length of the third tip.

3. The semiconductor device according to claim 2, wherein, The length of the fourth tip is greater than the lengths of the first tip, the second tip, and the third tip.

4. The semiconductor device according to claim 1, wherein The source / drain pattern comprises silicon-germanium (SiGe), and The germanium (Ge) concentration in the third semiconductor layer is higher than that in the first and second semiconductor layers.

5. The semiconductor device according to claim 4, wherein, The germanium (Ge) concentration in the second semiconductor layer is higher than that in the first semiconductor layer.

6. The semiconductor device according to claim 4, wherein The first semiconductor layer has a germanium (Ge) concentration of 2 at% to 8 at%. The second semiconductor layer has a germanium (Ge) concentration of 10 at% to 20 at%. The third semiconductor layer has a germanium (Ge) concentration of 30 at% to 70 at%.

7. The semiconductor device according to claim 1, wherein The first semiconductor layer of the source / drain pattern protrudes toward each of the plurality of semiconductor patterns, and The first semiconductor layer has a side surface that protrudes toward each of the plurality of semiconductor patterns.

8. The semiconductor device according to claim 1, wherein, Each of the plurality of semiconductor patterns includes a concave sidewall.

9. The semiconductor device according to claim 1, wherein The first semiconductor layer is also located between the active pattern and the second semiconductor layer, and The first semiconductor layer is at the bottom of the source / drain pattern.

10. The semiconductor device according to claim 1, wherein The uppermost semiconductor pattern among the plurality of semiconductor patterns has a first length on its uppermost surface in the first direction. The lower surface of the uppermost semiconductor pattern among the plurality of semiconductor patterns has a second length in the first direction. The external electrode has a third length in the first direction. The inner electrode has a fourth length in the first direction, and Each of the first length and the second length is greater than the third length and the fourth length.

11. The semiconductor device according to claim 10, wherein, The minimum length of the uppermost semiconductor pattern among the plurality of semiconductor patterns in the first direction is equal to or greater than each of the third length and the fourth length.

12. The semiconductor device according to claim 1, wherein, The inner spacer comprises a silicon nitride-based insulating material.

13. The semiconductor device according to claim 12, wherein, The silicon nitride-based insulating material includes at least one selected from the group consisting of SiN, SiCN, SiOCN, and SiBCN.

14. A semiconductor device, comprising: Substrate, including the PMOSFET region; An active pattern is present on the PMOSFET region; The channel pattern is on the active pattern and includes a plurality of semiconductor patterns that are vertically spaced apart from each other. Source / drain patterns are connected to the plurality of semiconductor patterns; A gate electrode is provided on the plurality of semiconductor patterns. The gate electrode includes an inner electrode and an outer electrode. The inner electrode is located between a pair of adjacent semiconductor patterns among the plurality of semiconductor patterns, and the outer electrode is located on the uppermost semiconductor pattern among the plurality of semiconductor patterns. A gate insulating layer is located between the gate electrode and adjacent semiconductor patterns. as well as An internal spacer is located between the source / drain pattern and the gate insulating layer surrounding the internal electrode. The source / drain pattern includes a first semiconductor layer in contact with each of the plurality of semiconductor patterns. The inner spacer has a first horizontal width in a first direction. The first semiconductor layer has a second horizontal width in the first direction, and The second horizontal width is different from the first horizontal width.

15. The semiconductor device according to claim 14, wherein, The first horizontal width is greater than the second horizontal width.

16. The semiconductor device according to claim 14, wherein, The second horizontal width is 2nm to 6nm.

17. The semiconductor device of claim 14, wherein The source / drain pattern further includes a second semiconductor layer on the first semiconductor layer and a third semiconductor layer on the second semiconductor layer. The upper surface of each of the plurality of semiconductor patterns includes a tip, and The inner surface of the second semiconductor layer is further from the tip in the first direction than one side surface of the inner spacer.

18. A semiconductor device, comprising: A first active pattern on a first active region of the substrate, and a second active pattern on a second active region of the substrate; The component separation layer is configured to fill the trenches defining the first active pattern and the second active pattern; The first channel pattern on the first active pattern and the second channel pattern on the second active pattern, each of the first channel pattern and the second channel pattern includes a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern that are vertically spaced apart from each other. A first source / drain pattern connected to the first channel pattern, and a second source / drain pattern connected to the second channel pattern; The gate electrode is located on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern; A gate insulating layer is located between the first semiconductor pattern, the second semiconductor pattern, the third semiconductor pattern, and the gate electrode; A first inner spacer between the gate insulating layer and the first source / drain pattern, and a second inner spacer between the gate insulating layer and the second source / drain pattern; Gate spacers are located on the sidewalls of the gate electrode. A gate capping pattern is present on the upper surface of the gate electrode; An interlayer insulating layer is present on the gate cap pattern; An active contact portion penetrates the interlayer insulation layer to be electrically connected to each of the first source / drain pattern and the second source / drain pattern; A metal-semiconductor compound layer is disposed between the active contact and the first source / drain pattern, and between the active contact and the second source / drain pattern; A gate contact portion penetrates the interlayer insulating layer and the gate capping pattern to be electrically connected to the gate electrode; A first metal layer is disposed on the interlayer insulating layer, the first metal layer including power lines electrically connected to the active contact and the gate contact; as well as A second metal layer is formed on top of the first metal layer. The second metal layer includes a second wiring electrically connected to the first metal layer. The second active region is the PMOSFET region. The second source / drain pattern includes a first semiconductor layer in contact with the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. The second inner spacer has a silicon nitride-based insulating material, and The second source / drain pattern is spaced apart from the gate electrode by the second inner spacer.

19. The semiconductor device according to claim 18, wherein, The silicon nitride-based insulating material includes at least one selected from the group consisting of SiN, SiCN, SiOCN, and SiBCN.

20. The semiconductor device of claim 18, wherein The second source / drain pattern includes silicon-germanium (SiGe). The germanium (Ge) concentration in the third semiconductor layer is higher than that in the first and second semiconductor layers. The second inner spacer has a first horizontal width in the first direction. The first semiconductor layer has a second horizontal width in the first direction, and The first horizontal width and the second horizontal width are the same.

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