Image sensor and method of manufacturing an image sensor

Abstract

An image sensor and a method of manufacturing the image sensor are provided. An image sensor according to embodiments of the present disclosure may include: a deep element isolation pattern disposed in a substrate doped with a dopant having a first conductivity type; a shallow element isolation pattern defining an active region including a terminal portion and a fin portion; a gate filling a gate recess formed in the shallow element isolation pattern to expose a portion of the fin portion; and a gate insulating layer, wherein the fin portion may include a channel region doped with a dopant having a second conductivity type, the terminal portion may include a side region doped with a dopant having a second conductivity type, and the side region may be vertically stacked with the gate.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0004378, filed on January 10, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to image sensors and methods for manufacturing image sensors. Background Technology

[0003] An image sensor is a semiconductor device that converts optical images into electrical signals. Recently, with the development of the computer and communications industries, the demand for image sensors with improved performance has increased in various fields such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, and medical miniature cameras. Image sensors can be classified into charge-coupled device (CCD) type and complementary metal-oxide-semiconductor (CMOS) type. CMOS image sensors have multiple pixels arranged in a two-dimensional pattern. Each pixel includes a photodiode (PD). The photodiode is used to convert incident light into an electrical signal. Summary of the Invention

[0004] This disclosure relates to providing an image sensor with transistors having improved electrical characteristics and a method for manufacturing the image sensor.

[0005] This disclosure may also relate to providing an image sensor with a transistor having improved transconductance and a method for manufacturing the image sensor.

[0006] This disclosure may also relate to providing an image sensor with a transistor that reduces parasitic resistance and a method for manufacturing the image sensor.

[0007] This disclosure may also relate to providing an image sensor with a transistor that reduces parasitic capacitance and a method for manufacturing the image sensor.

[0008] This disclosure may also relate to providing an image sensor including a junctionless transistor having a channel region with substantially uniform doping and a method of manufacturing the image sensor.

[0009] This disclosure may also relate to providing an image sensor having a transistor with an enlarged channel region and a method of manufacturing the image sensor.

[0010] This disclosure may also relate to providing an image sensor having a bulk channel region formed inside the fin and a method for manufacturing the image sensor.

[0011] This disclosure may also relate to providing an image sensor having a channel region formed by an isotropic doping process and a method for manufacturing the image sensor.

[0012] This disclosure may also relate to a method for manufacturing an image sensor in which the manufacturing process is simplified and the manufacturing cost is reduced.

[0013] An image sensor according to an embodiment of the present disclosure may include: a deep PD isolation pattern disposed in a substrate to define a group of photodiode regions, the substrate being doped with a dopant having a first conductivity type, each of the photodiode regions including at least one photodiode region; a shallow element isolation pattern filling a shallow trench recessed from a first surface of the substrate to define at least one active region in each of the photodiode regions, the active region including a terminal portion and a fin portion; a gate filling a gate recess formed in the shallow element isolation pattern to expose a portion of the fin portion; and a gate insulating layer between the gate and the exposed portion of the fin portion, wherein the fin portion may include a channel region formed in the exposed portion of the fin portion and doped with a dopant having a second conductivity type different from the first conductivity type, the terminal portion may include a side region defining a gate recess and doped with a dopant having a second conductivity type, and the side region may be vertically stacked with the gate.

[0014] The channel region can be uniformly doped with a dopant of a second conductivity type in the vertical direction.

[0015] The side regions can be uniformly doped with dopants having a second conductivity type.

[0016] The dopant concentration in the side region can be the same as that in the channel region.

[0017] The side region can extend in a direction that intersects with the longitudinal direction of the channel region.

[0018] The terminal portion may also include a source / drain region connected to the side region and doped with a dopant having a second conductivity type, and the source / drain region may not be vertically stacked with the gate.

[0019] The dopant concentration in the source / drain region can be higher than that in the side region.

[0020] The side region can be located between the source / drain region and the channel region, and the side region can connect the source / drain region and the channel region.

[0021] The side region may include an upper part connected to the source / drain region and a lower part located below the upper part, and the dopant concentration of the upper part may be greater than that of the lower part.

[0022] The gate may be doped with a dopant having a first conductivity type.

[0023] An image sensor according to an embodiment of the present disclosure may include: a deep PD isolation pattern disposed in a substrate to define a group of photodiode regions, the substrate being doped with a dopant having a first conductivity type, each of the photodiode regions including at least one photodiode region; a shallow element isolation pattern filling shallow trenches recessed from a first surface of the substrate to define at least one active region in each of the photodiode regions, the active region including a terminal portion and a fin portion; a gate filling a gate recess formed in the shallow element isolation pattern to expose a portion of the fin portion, the gate including a plurality of vertical portions spaced apart from each other in the gate recess; and a gate insulating layer between the gate and the exposed portion of the fin portion, wherein the fin portion may include a channel region formed in the exposed portion of the fin portion and doped with a dopant having a second conductivity type different from the first conductivity type, the terminal portion may include a source / drain region and a side region, the source / drain region being doped with a dopant having a second conductivity type, the side region being disposed between the fin and the source / drain region and doped with a dopant having a second conductivity type, and the dopant concentration of the side region may be smaller than the dopant concentration of the source / drain region.

[0024] The height of the upper end of the fin portion can be the same as the height of the first surface of the base, and the fin portion can separate the vertical portions from each other.

[0025] The height of the upper surface of the fin portion may be lower than the height of the first surface of the substrate, and the gate may include a horizontal portion connected to the vertical portion, and the height of the upper surface of the horizontal portion may be the same as the height of the first surface of the substrate.

[0026] The width of the fin portion, defined in the width direction of the channel region, can increase toward the first surface of the substrate.

[0027] A method of manufacturing an image sensor according to an embodiment of the present disclosure may include: patterning a first surface of a substrate to form a shallow trench defining an active region, the active region including a terminal portion and a fin portion; forming a shallow element isolation pattern filling the shallow trench; patterning the shallow element isolation pattern to form a gate recess exposing a side surface of the fin portion; performing an isotropic doping process to form a channel region in the fin portion through the upper surface and side surface of the fin portion; forming a gate insulating layer on the fin portion; and forming a gate filling the gate recess.

[0028] The steps of performing an isotropic doping process may include: conformally forming a doped film including a dopant on the upper surface and exposed side surface of the fin portion; and performing an annealing process to diffuse the dopant of the doped film into the fin portion.

[0029] The steps of performing isotropic doping may include: uniformly doping the upper surface and exposed side surfaces of the fin portion with a dopant in the plasma.

[0030] The method of manufacturing an image sensor may further include forming a source / drain region in a terminal portion, wherein the source / drain region may be doped with a dopant having the same conductivity type as the channel region.

[0031] The source / drain regions can be formed simultaneously with the channel region by performing an isotropic doping process.

[0032] The terminal portion may include a sidewall portion that defines a gate recess and connects to the fin portion. The side region may be formed in the sidewall portion by performing an isotropic doping process, and the side region may be doped with a dopant having the same conductivity type as the channel region. Attached Figure Description

[0033] Figure 1 This is a block diagram of an image sensor according to some embodiments of the present disclosure.

[0034] Figure 2 This is a circuit diagram of pixels included in a pixel array of an image sensor according to some embodiments of the present disclosure.

[0035] Figure 3 This is a circuit diagram of pixels included in a pixel array of an image sensor according to an embodiment of the present disclosure.

[0036] Figure 4 This is a plan view of an image sensor according to an embodiment of the present disclosure.

[0037] Figure 5 yes Figure 4 An enlarged plan view of a group of photodiode regions.

[0038] Figure 6A It is along Figure 5 A sectional view taken by line I-I'.

[0039] Figure 6B It is along Figure 5 The sectional view taken from line II-II'.

[0040] Figure 6C It is along Figure 5 The sectional view taken from line III-III'.

[0041] Figures 7A to 13A This is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the present disclosure, which is in contrast to... Figure 5 The sectional view corresponding to line I-I'.

[0042] Figures 7B to 13B , Figure 14A and Figure 15A A method for manufacturing an image sensor according to an embodiment of the present disclosure is shown, which is... Figure 5 The sectional view corresponding to line II-II'.

[0043] Figures 7C to 13C , Figure 14B and Figure 15B A method for manufacturing an image sensor according to an embodiment of the present disclosure is shown, which is... Figure 5 The sectional view corresponding to line III-III'.

[0044] Figure 16A This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line I-I'.

[0045] Figure 16B This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line II-II'.

[0046] Figure 16C This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line III-III'.

[0047] Figures 17A to 19A This is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the present disclosure.

[0048] Figures 17B to 19B This is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the present disclosure.

[0049] Figure 20A This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line I-I'.

[0050] Figure 20B This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line II-II'.

[0051] Figure 20C This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line III-III'.

[0052] Figure 21A This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line II-II'.

[0053] Figure 21B This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line III-III'.

[0054] Figure 22 This is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line I-I'.

[0055] Figure 23 This is an enlarged plan view of a group of photodiode regions of an image sensor according to an embodiment of the present disclosure. Detailed Implementation

[0056] In the following, embodiments of the present disclosure will be clearly and thoroughly described with reference to the accompanying drawings.

[0057] When referring to orientation, layout, location, shape, size, composition, quantity, or other measure, terms such as “same,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean completely (exactly) identical orientation, layout, location, shape, size, composition, quantity, or other measure, but are intended to cover nearly (approximately) identical orientation, layout, location, shape, size, composition, quantity, or other measure within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning unless the context or other statement indicates otherwise. For example, items described as “substantially same,” “substantially equal,” or “substantially plane” may be completely (exactly) identical, completely (exactly) equal, or completely (exactly) plane, or may be identical, equal, or plane within acceptable variations that may occur, for example, due to manufacturing processes.

[0058] Figure 1 This is a block diagram of an image sensor 10 according to some embodiments of the present disclosure.

[0059] Reference Figure 1 According to some embodiments of the present invention, the image sensor 10 may include a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output buffer (I / O buffer) 8.

[0060] Pixel array 1 may include a plurality of pixels arranged in a two-dimensional manner, and the pixels may convert optical signals into electrical signals. Pixel array 1 may be driven by a plurality of drive signals (e.g., pixel selection signals, reset signals, and / or charge transfer signals) sent from row driver 3. The converted electrical signals may be provided to CDS 6.

[0061] The row driver 3 can provide multiple driving signals to the pixel array 1 based on the decoding results from the row decoder 2, which are used to drive multiple pixels. When the pixels are arranged in a matrix, the driving signals can be provided on a row-by-row basis.

[0062] Timing generator 5 can provide timing signals and control signals to row decoder 2 and column decoder 4.

[0063] CDS 6 can receive electrical signals generated from pixel array 1, and can hold and sample the received signals. CDS 6 can double sample a specific noise level and a signal level caused by the electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0064] The ADC 7 can convert the analog signal corresponding to the difference level output from the CDS 6 into a digital signal and can output a digital signal.

[0065] I / O buffer 8 can latch digital signals and output the latched signals sequentially to the image signal processor (not shown) based on the decoding results from column decoder 4.

[0066] Figure 2 This is a circuit diagram of pixels included in a pixel array of an image sensor 10 according to some embodiments of the present disclosure.

[0067] Reference Figure 2 The pixel array may include multiple pixels PXL, and the pixels PXL may be arranged in a matrix. Each of the pixels PXL may be electrically connected to a pixel transistor, and the pixel transistor may include a transfer transistor and logic transistors RX, SEL, and SF. The logic transistors RX, SEL, and SF may include a reset transistor RX, a select transistor SEL, and a source follower transistor SF. In addition, each of the pixels PXL may include a photodiode PD, and the photodiode PD may be electrically connected (e.g., via the transfer transistor) to a floating diffusion region FD. In some embodiments, each of the pixels PXL may also include a transfer gate TG of the transfer transistor.

[0068] A photodiode (PD) generates and accumulates photocharge in proportion to the amount of light incident from the outside. A PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. A transfer transistor transfers the photocharge generated from the PD to a floating diffusion region (FD). The transfer gate (TG) of the transfer transistor may be connected to a transfer gate line (TGL). The floating diffusion region (FD) receives and accumulates the photocharge generated from the PD.

[0069] The gate of the source follower transistor SF can be connected to the floating diffusion region FD. The drain terminal of the source follower transistor SF can be connected to the power supply voltage line V that can receive the power supply voltage. pix The source follower transistor SF can be controlled based on the amount of photocharge accumulated in the floating diffusion region FD. The source follower transistor SF can convert a signal corresponding to the amount of input photocharge into a voltage signal.

[0070] The reset transistor RX periodically resets the charge accumulated in the floating diffusion region FD. The gate of the reset transistor RX can be connected to the reset gate line RGL. The source terminal of the reset transistor RX can be connected to the floating diffusion region FD, and the drain terminal of the reset transistor RX can be connected to the power supply voltage line V. pix When the reset transistor RX is turned on, the power supply voltage supply line V... pix The power supply voltage can be applied to the floating diffusion region FD through the reset transistor RX. For example, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be released by the power supply voltage, thereby resetting the floating diffusion region FD.

[0071] The source follower transistor SF can be used as a source follower buffer amplifier. The source follower transistor SF amplifies the potential change in the floating diffuse region FD and outputs the amplified potential change to the output line V. OUT .

[0072] The gate of the select transistor SEL can be connected to the select gate line SGL. The drain terminal of the select transistor SEL can be connected to the source terminal of the source follower transistor SF, and the source terminal of the select transistor SEL can be connected to the output line V. OUT The selection transistor SEL for the pixel PXL to be read out row by row can be selected by a selection signal applied through the corresponding selection gate line SGL. When the selection transistor SEL is turned on, the potential change amplified by the source follower transistor SF can be output to the output line V through the selection transistor SEL. OUT .

[0073] Figure 3This is a circuit diagram of pixels included in a pixel array of an image sensor 10 according to an embodiment of the present disclosure.

[0074] Reference Figure 3 A pixel array may include multiple pixel groups (PXGs), and each pixel group (PXG) may include multiple pixels. A circuit diagram of a pixel group (PXG) is shown in... Figure 3 middle.

[0075] Reference Figure 3 In one embodiment, the pixel group PXG may include four pixels (i.e., first pixels to fourth pixels). The first to fourth pixels may each include a first transmission gate to a fourth transmission gate TG1, TG2, TG3, and TG4, and a first photodiode to a fourth photodiode PD1, PD2, PD3, and PD4. The transmission gates TG1, TG2, TG3, and TG4 of the first to fourth transmission transistors may be connected to the first to fourth transmission gate lines TGL1, TGL2, TGL3, and TGL4, respectively. The first to fourth pixels may share the previously disclosed reset transistor RX, source follower transistor SF, and select transistor SEL.

[0076] exist Figure 3 In one embodiment, the pixel group PXG comprises four pixels, but the embodiments of this disclosure are not limited thereto. The number of pixels in the pixel group PXG can be varied. For example, the number of pixels in the pixel group PXG can be eight.

[0077] Figure 4 This is a plan view of an image sensor 10 according to an embodiment of the present disclosure. Figure 5 yes Figure 4 An enlarged plan view of a group of photodiode regions. Figure 6A It is along Figure 5 A sectional view taken by line I-I'. Figure 6B It is along Figure 5 The sectional view taken from line II-II'. Figure 6C It is along Figure 5 The sectional view taken from line III-III'.

[0078] Reference Figures 4 to 6C A deep PD isolation pattern (or deep element isolation pattern) DTI may be disposed in the substrate 100 to define a plurality of photodiode region groups PDRG, each of the photodiode region groups PDRG including at least one (e.g., a plurality) photodiode region PDR. Furthermore, the deep PD isolation pattern DTI may extend into each of the photodiode region groups PDRG to define a photodiode region PDR. For example, the deep PD isolation pattern DTI may also be disposed between photodiode region PDRs.

[0079] The substrate 100 may have a first surface and a second surface opposite to the first surface. The first surface of the substrate 100 may be the front surface of the substrate 100, and the second surface of the substrate 100 may be the back surface of the substrate 100.

[0080] In one embodiment, a deep PD isolation pattern (DTI) may extend through the substrate 100. For example, the deep PD isolation pattern (DTI) may fill a deep trench extending through the substrate 100. The deep PD isolation pattern (DTI) may be arranged in a basic grid shape in a plan view. Each of the photodiode regions (PDRs) may be a portion of the substrate 100 surrounded by the deep PD isolation pattern (DTI).

[0081] Shallow element isolation patterns (STIs) may be disposed in the substrate 100 to define at least one (e.g., multiple) active regions in each of the photodiode region groups (PDRGs). The shallow element isolation patterns (STIs) may fill shallow trenches (TRs) recessed from a first surface of the substrate 100. For example, the shallow element isolation patterns (STIs) may be disposed in the substrate 100 and may be adjacent to the first surface of the substrate 100. Each of the active regions may be a portion of the substrate 100 surrounded by the shallow element isolation patterns (STIs) in a plan view (i.e., a portion of the photodiode region (PDR) surrounded by the shallow element isolation patterns (STIs) in a plan view).

[0082] Multiple active regions may include a first active region ATR1, a second active region ATR2, a third active region ATR3, and a fourth active region ATR4. A source follower transistor SF may be located in the first active region ATR1, and a transfer transistor may be located in the second active region ATR2. A reset transistor RX may be located in the third active region ATR3, and a select transistor SEL may be located in the fourth active region ATR4. For example, a source follower gate SFG may be located in the first active region ATR1, and a transfer gate TG may be located in the second active region ATR2. A reset gate RSG may be located in the third active region ATR3, and a select gate SLG may be located in the fourth active region ATR4.

[0083] In some embodiments, the first active region ATR1 may be located in any one of the photodiode regions PDR in each of the photodiode region groups PDRG. (See also...) Figure 5 In one embodiment, each of the photodiode region group PDRG may include a first photodiode region to a fourth photodiode region PDR1, PDR2, PDR3 and PDR4, and the first active region ATR1 may be defined in the first photodiode region PDR1.

[0084] In some embodiments, the second active region ATR2 may be defined in each of the photodiode regions PDRs in each of the photodiode region groups PDRG. For example, as Figure 5 As shown, the second active region ATR2 may be defined in each of the first photodiode regions PDR1 to the fourth photodiode regions PDR4. In this case, the transfer gate TG may be disposed on each of the second active regions ATR2. In one embodiment, the second active region ATR2 of each of the photodiode region groups PDRG may extend and be connected to each other.

[0085] The third active region ATR3 may be defined in another photodiode region PDR of each of the photodiode region groups PDRG, and the fourth active region ATR4 may be defined in yet another photodiode region PDR of each of the photodiode region groups PDRG. For example, as Figure 5 As shown, the third active region ATR3 may be defined in the second photodiode region PDR2, and the fourth active region ATR4 may be defined in the fourth photodiode region PDR4. In one embodiment, an additional transistor may be disposed in another active region defined in the third photodiode region PDR3. The additional transistor may be a dummy transistor or a transistor performing an additional function (e.g., a double-conversion gain transistor).

[0086] A floating diffusion region FD may be disposed in the second active region ATR2 on one side of the transmission gate TG. The floating diffusion region FD of each of the photodiode regions PDR (e.g., PDR1 to PDR4) may extend along the second active region ATR2 and be connected to each other.

[0087] A photodiode (PD) can be disposed in each of the photodiode regions (PDRs). A first region of substrate 100 (i.e., the first region of each of the photodiode regions (PDRs)) can be doped with an impurity having a first conductivity type, and a second region of substrate 100 (i.e., the second region of each of the photodiode regions (PDRs)) can be doped with an impurity having a second conductivity type different from the first conductivity type. One of the first and second conductivity types can be P-type (also called p-type), and the other of the first and second conductivity types can be N-type (also called n-type). For example, the first conductivity type can be P-type, and the second conductivity type can be N-type. Therefore, the first and second regions of substrate 100 can be PN-junctioned to form a photodiode. The floating diffusion region (FD) can be doped with an impurity having the second conductivity type. In semiconductor technology, if a semiconductor contains both p-type and n-type impurities, the conductivity type of the semiconductor is determined by the concentration of which type of impurity is greater. Therefore, if a semiconductor contains both p-type and n-type impurities, the net conductivity type is determined by the dominant impurity concentration. As used herein, a semiconductor region of “first conductivity type” means that the dominant impurity in the semiconductor region is (or is) a first conductivity type impurity. As used herein, the “concentration of first conductivity type” (or “doping concentration”) in the semiconductor region refers to the net concentration of impurities in the semiconductor region (i.e., (amount of first conductivity type impurity minus amount of second conductivity type impurity) / volume of the semiconductor region).

[0088] The first active region ATR1 may include a terminal portion TP and a fin portion FP. The fin portion FP may extend through the shallow element isolation pattern STI. Therefore, a portion of the fin portion FP may protrude from the shallow element isolation pattern STI.

[0089] A gate recess GR may be formed in a shallow element isolation pattern (STI). The gate recess GR may be formed by recessing one surface of the shallow element isolation pattern (STI). The gate recess GR may be defined by a fin portion FP, a terminal portion TP (e.g., a side region SR of the terminal portion TP, which will be described below), and the shallow element isolation pattern (STI). A portion of the fin portion FP may be exposed by the gate recess GR. The portion of the fin portion FP exposed by the gate recess GR may correspond to the upper portion of the fin portion FP (e.g., the exposed portion of the fin portion FP).

[0090] The fin portion FP may include a channel region CH doped with a dopant. The channel region CH may be formed in the portion of the fin portion FP exposed by the gate recess GR (i.e., the upper part (exposed portion) of the fin portion FP). For example, the channel region CH may be formed in the portion of the fin portion FP that protrudes from the shallow element isolation pattern STI.

[0091] The channel region CH may be doped with a dopant having a second conductivity type different from the first conductivity type. For example, the channel region CH may be substantially uniformly doped with a dopant having the second conductivity type. For example, the channel region CH may be substantially uniformly doped with a dopant having the second conductivity type along the depth direction of the channel region CH. The depth direction of the channel region CH may correspond to a third direction DR3. The third direction DR3 may be referred to as the up-down direction or the vertical direction.

[0092] The remaining portion of the fin portion FP may correspond to the lower portion (e.g., the unexposed portion). The remaining portion of the fin portion FP may be located in a shallow element isolation pattern (STI). The remaining portion of the fin portion FP may be substantially undoped. The remaining portion of the fin portion FP may be connected to the substrate 100. The remaining portion of the fin portion FP may connect the substrate 100 and the upper portion (exposed portion) of the fin portion FP.

[0093] The terminal portion TP may include a source / drain region SD doped with a dopant having a second conductivity type. The conductivity type of the source / drain region SD may be the same as that of the channel region CH. Therefore, a junctionless transistor can be provided. A junctionless transistor may include a channel region CH and a source / drain region SD doped with the same conductivity type as described above. The junctionless transistor may also include a gate electrode configured to control the flow of current between the source and drain. For example, the source / drain region SD, the side region SR (described below), the channel region CH, and the source follower gate SFG may form a junctionless transistor.

[0094] The terminal portion TP may include a first terminal portion TP1 disposed on one side of the fin portion FP and a second terminal portion TP2 disposed on the other side of the fin portion FP. The source / drain region SD may include a first source / drain region 120 on the first terminal portion TP1 and a second source / drain region 140 on the second terminal portion TP2. The first source / drain region 120 may be disposed on a portion of the first terminal portion TP1. The second source / drain region 140 may be disposed on a portion of the second terminal portion TP2.

[0095] The source / drain region SD may not be vertically stacked with the source follower gate SFG. For example, the source / drain region SD may be positioned outside the source follower gate SFG in a plan view.

[0096] The first source / drain region 120 may include an upper region 122 and a lower region 124. The upper region 122 may be adjacent to a surface of the substrate 100, and the lower region 124 may be disposed below the upper region 122. Similarly, the second source / drain region 140 may include an upper region 142 and a lower region 144. The upper region 142 may be adjacent to the aforementioned surface of the substrate 100, and the lower region 144 may be disposed below the upper region 142.

[0097] Terminal portion TP may include a sidewall portion SW connected to fin portion FP. For example, first terminal portion TP1 may include a first sidewall portion SW1 connected to fin portion FP, and second terminal portion TP2 may include a second sidewall portion SW2 connected to fin portion FP.

[0098] The terminal portion TP may also include a side region SR disposed in the sidewall portion SW. The side region SR may be disposed between the source / drain region SD and the channel region CH. For example, the side region SR may include a first side region SR1 disposed in the first sidewall portion SW1 and a second side region SR2 disposed in the second sidewall portion SW2.

[0099] The side region SR can be doped with a dopant having a second conductivity type. The side region SR can be substantially uniformly doped with a dopant having a second conductivity type. For example, the side region SR can be substantially uniformly doped with dopant in the depth direction. Therefore, the side region SR can connect the source / drain region SD and the channel region CH.

[0100] The dopant concentration in the side region SR can be substantially the same as the dopant concentration in the channel region CH. For example, the dopant concentration in the side region SR at the boundary where the side region SR and the channel region CH meet can be substantially the same as the dopant concentration in the channel region CH. Therefore, the dopant concentration does not change across the boundary region between the side region SR and the channel region CH (i.e., the dopant concentration across the boundary region between the side region SR and the channel region CH is the same). The dopant concentration in the side region SR can be smaller than the dopant concentration in the source / drain region SD. For example, the dopant concentration in the source / drain region SD can be larger than the dopant concentration in the side region SR.

[0101] The side region SR may include upper SR11 and SR21 connected to the source / drain region SD. The side region SR may also include lower SR12 and SR22 positioned below the upper SR11 and SR21 on the third-direction DR3. The upper SR11 and SR21 of the side region SR may be directly connected to the upper regions 122 and 142 of the source / drain region SD, respectively. The upper SR11 and SR21 of the side region SR may also be directly connected to the lower regions 124 and 144 of the source / drain region SD, respectively. The dopant concentration of the upper SR11 and SR21 of the side region SR may be greater than the dopant concentration of the lower SR12 and SR22 of the side region SR.

[0102] The side region SR can be vertically stacked with the source follower gate SFG. For example, on the third-direction DR3, the side region SR can be disposed below the horizontal portion 320 of the source follower gate SFG. Furthermore, on the third-direction DR3, the side region SR can also be disposed below the gate spacer GS formed on the side surface of the horizontal portion 320 of the source follower gate SFG.

[0103] Side regions SR1 and SR2 may be spaced apart from each other in the longitudinal direction (or "longitudinal direction") of the channel region CH. Side regions SR1 and SR2 may be located on one side and the other side of the fin portion FP, respectively. Side regions SR1 and SR2 may extend in directions intersecting the longitudinal direction of the channel region CH. For example, the longitudinal direction of the channel region CH may be defined as a second direction DR2, and side regions SR1 and SR2 may extend in a first direction DR1 orthogonal to the second direction DR2. The first direction DR1 and the second direction DR2 may be referred to as horizontal directions (e.g., first horizontal direction and second horizontal direction, respectively). A third direction DR3 is orthogonal to the first direction DR1 and the second direction DR2.

[0104] The source follower gate SFG may fill the gate recess GR. The source follower gate SFG may include a vertical portion 340 that fills the gate recess GR and a horizontal portion 320 connected to the vertical portion 340.

[0105] The vertical portion 340 may be disposed between the fin portion FP and the shallow element isolation pattern STI. In one embodiment, the vertical portion 340 may also be disposed between the fin portions FP. In some embodiments, the vertical portions 340 may be spaced apart from each other in the gate recess GR.

[0106] The vertical portion 340 can be positioned between the side regions SR1 and SR2. The shallow element isolation pattern STI can be positioned below the vertical portion 340.

[0107] The horizontal portion 320 may be disposed above the fin portion FP. The horizontal portion 320 may cover a portion of the shallow element isolation pattern STI. The horizontal portion 320 may be disposed above the side region SR. The horizontal portion 320 may be vertically stacked with the side region SR, but may not be vertically stacked with the source / drain region SD.

[0108] The source follower gate (SFG) may include a polysilicon gate doped with a dopant having a first conductivity type, or a metal gate having a work function substantially equivalent to that of the polysilicon gate.

[0109] The gate insulating layer GI can be disposed between the source follower gate SFG and the fin portion FP (e.g., the exposed portion of the fin portion FP). The gate insulating layer GI can conformally cover the inner surface of the gate recess GR. The gate insulating layer GI can also be disposed between the source follower gate SFG and the shallow element isolation pattern STI. The gate insulating layer GI can also be disposed between the source follower gate SFG and the terminal portion TP. For example, the gate insulating layer GI can also be disposed between the source follower gate SFG and the sidewall portion SW in which the side region SR is disposed.

[0110] A gate spacer GS may be disposed on the side surface of the horizontal portion 320 of the source follower gate SFG. The gate spacer GS may be disposed above the side region SR. The edge of the gate spacer GS may be vertically aligned (e.g., coplanar) with the edge of the source / drain region SD. Furthermore, the edge of the gate spacer GS may be vertically aligned with the edge of the side region SR.

[0111] Figures 7A to 13A This is a cross-sectional view illustrating a method of manufacturing an image sensor 10 according to an embodiment of the present disclosure, which is in contrast to... Figure 5 The sectional view corresponding to line I-I'. Figures 7B to 13B , Figure 14A and Figure 15A This illustrates a method for manufacturing an image sensor 10 according to an embodiment of the present disclosure, which is related to... Figure 5 The sectional view corresponding to line II-II'. Figures 7C to 13C , Figure 14B and Figure 15B This illustrates a method for manufacturing an image sensor 10 according to an embodiment of the present disclosure, which is related to... Figure 5 The sectional view corresponding to line III-III'.

[0112] Reference Figures 7A to 7C A substrate 100 can be prepared. The substrate 100 can be a semiconductor substrate including silicon (Si), germanium (Ge), silicon-germanium (Si-Ge), etc., or it can be a compound semiconductor substrate. For example, the substrate 100 can be a silicon substrate.

[0113] A shallow trench TR can be formed by patterning a first surface of substrate 100 to define a first active region ATR1. For example, a first mask pattern MP1 covering the first active region ATR1 can be formed on the first surface of substrate 100. The first mask pattern MP1 may have a first opening OP1 defining the shallow trench TR. The first mask pattern MP1 can be used as an etching mask to perform an etching process on the first surface of substrate 100. The etching process may include a front-side anisotropic etching process. Thus, the first active region ATR1 can be formed.

[0114] The first active region ATR1 may include terminal portions TP and fin portions FP. Multiple fin portions FP may be formed. Terminal portions TP may be formed in pairs. Fin portions FP may be disposed between a pair of terminal portions TP1 and TP2, and the pair of terminal portions TP1 and TP2 may be connected.

[0115] Each of the photoelectric conversion regions PR can be formed in each of the photodiode regions. For example, the photoelectric conversion region PR can be formed using an ion implantation process. In some embodiments, the first mask pattern MP1 can be removed (e.g., after forming the photoelectric conversion region PR).

[0116] Reference Figure 8A and Figure 8B An insulating layer (not shown) may be formed on a first surface of the substrate 100 in which a shallow trench TR is formed. The insulating layer (not shown) may include silicon oxide.

[0117] An insulating layer (not shown) may fill the shallow trench TR and cover the first surface of the substrate 100. The insulating layer (not shown) may be planarized until the upper surface of the substrate 100 is exposed. The planarization of the insulating layer may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. As a result, a shallow element isolation pattern STI may be formed. The upper surface of the shallow element isolation pattern STI may be coplanar with the upper surface of the substrate 100 (specifically, the upper surface of the first active region ATR1).

[0118] Reference Figure 9A and Figure 9B A second mask pattern MP2 can be formed on the shallow element isolation pattern STI. The second mask pattern MP2 may have a second opening OP2 defining a gate recess GR. The second mask pattern MP2 can be used as an etching mask to perform an etching process on the shallow element isolation pattern STI. The etching process may include a front-side anisotropic etching process. The etch ions used in the etching process may have etch selectivity relative to the substrate 100. Therefore, the shallow element isolation pattern STI exposed through the second opening OP2 can be etched, and the first active region ATR1 of the substrate 100 can be retained.

[0119] A gate recess GR can be formed by recessing one surface of the shallow element isolation pattern STI through an etching process. The gate recess GR can expose a portion of the first active region ATR1. For example, the gate recess GR can expose the side surface of the fin portion FP. Furthermore, the gate recess GR can expose the side surface of the terminal portion TP. As a result, the gate recess GR can be defined by the fin portion FP, the terminal portion TP, and the shallow element isolation pattern STI. In some embodiments, the second mask pattern MP2 can be removed (e.g., after forming the gate recess GR).

[0120] Reference Figures 10A to 11C An isotropic doping process can be performed on the first surface of the substrate 100 in which the gate recess GR is formed. The isotropic doping process may include plasma-assisted doping (PLAD), spin-on dopant (SOD), chemical vapor deposition (CVD) and diffusion processes, and single-layer doping (MLD).

[0121] By performing an isotropic doping process, the channel region CH can be formed in the fin portion FP.

[0122] Furthermore, by performing isotropic doping, the source / drain region SD can be formed in the terminal portion TP. By performing isotropic doping, the source / drain region SD can be formed simultaneously with the channel region CH.

[0123] Furthermore, by performing isotropic doping, the side region SR can be formed in the sidewall portion SW. The side region SR can also be formed simultaneously with the source / drain region SD and the channel region CH by performing isotropic doping.

[0124] Since the source / drain region SD, the side region SR, and the channel region CH are formed together through an isotropic doping process, the conductivity type of the source / drain region SD, the conductivity type of the side region SR, and the conductivity type of the channel region CH can be the same.

[0125] Reference Figures 10A to 10C In one embodiment, a doped film DL may be conformally formed on a first surface of the substrate 100 in which a gate recess GR is formed. The doped film DL may include a dopant. The dopant may have a second conductivity type different from the first conductivity type. For example, the doped film DL may be conformally formed on the portion of the fin portion FP exposed through the gate recess GR. The doped film DL may be conformally formed on the side and top surfaces of the exposed portion of the fin portion FP.

[0126] Furthermore, a doped film DL can be formed on the inner surface of the defined gate recess GR of the shallow element isolation pattern STI. Additionally, a doped film DL can be conformally formed on the upper and side surfaces of the terminal portion TP. The side surface of the terminal portion TP may correspond to one surface of the sidewall portion.

[0127] Reference Figures 11A to 11C An annealing process can be performed to diffuse the dopant included in the doped film DL into the first active region ATR1. Additionally, an annealing process can be performed to activate the diffused dopant.

[0128] For example, a channel region CH can be formed in the exposed portion of the fin portion FP by performing an annealing process. Dopant can diffuse into the exposed portion of the fin portion FP. Since the doped film DL is conformally formed on the side and top surfaces of the exposed portion of the fin portion FP, the diffused dopant can be uniformly distributed throughout the exposed portion of the fin portion FP. Therefore, the formed channel region CH can have a substantially uniform dopant concentration. For example, the dopant concentration can be substantially uniform (e.g., substantially the same) throughout the entire channel region CH.

[0129] Since the doped film DL is formed on the portion of the fin portion FP exposed by the gate recess GR, the channel region CH can be formed substantially within the exposed portion of the fin portion FP. The remaining portion of the fin portion FP located in the shallow device isolation pattern STI (e.g., the unexposed portion) can be substantially undoped. However, depending on the process conditions of the annealing process, the channel region CH can extend toward the remaining portion of the fin portion FP.

[0130] The source / drain region SD can be formed in a portion of the terminal portion TP by performing an annealing process. For example, the dopant included in the doped film DL formed on the terminal portion TP can be diffused into that portion of the terminal portion TP by the annealing process, and the source / drain region SD can be formed in the terminal portion TP. Since the doped film DL is conformally formed on the terminal portion TP, the diffused dopant can be uniformly distributed in that portion of the terminal portion TP. Therefore, the formed source / drain region SD can have a substantially uniform dopant concentration.

[0131] Furthermore, by performing an annealing process, a side region SR can be formed in another portion of the terminal portion TP. This other portion of the terminal portion TP may correspond to the sidewall portion SW. The side region SR is disposed between the source / drain region SD and the channel region CH, and can connect the source / drain region SD and the channel region CH.

[0132] An annealing process can diffuse the dopant in the doped film DL formed on the sidewall portion SW into the sidewall portion SW, forming a side region SR within the sidewall portion SW. Since the doped film DL is conformally formed on the sidewall portion SW, the diffused dopant can be uniformly distributed within the sidewall portion SW. Therefore, the formed side region SR can have a substantially uniform dopant concentration.

[0133] After the channel region CH is formed, the remaining portion of the doped film DL can be removed. Therefore, the upper and side surfaces of the fin portion FP, where the channel region CH is formed, can be exposed again. Furthermore, the upper and side surfaces of the terminal portion TP can also be exposed again.

[0134] Alternatively, in one embodiment, an isotropic doping process can be performed using a PLAD process. In this case, the dopant in the plasma diffuses into the fin portion FP through the upper surface and exposed side surfaces, and the diffused dopant is uniformly distributed within the fin portion FP. Therefore, the channel region CH can be formed in the fin portion FP. Similarly, source / drain regions SD and side regions SR with uniform dopant concentrations can be formed together with the channel region CH using a PLAD process.

[0135] Reference Figures 12A to 12C A gate insulating layer GI may be conformally formed on a first surface of the substrate 100 in which a gate recess GR is formed. The gate insulating layer GI may include silicon oxide, silicon nitride, or silicon oxynitride.

[0136] The gate insulating layer GI can be conformally formed on a first surface of the substrate 100. For example, the gate insulating layer GI can be conformally formed on the upper surface and side surface of the exposed first active region ATR1. The gate insulating layer GI can be conformally formed on the upper surface of the fin portion FP and the side surface of the fin portion FP exposed by the gate recess GR. The gate insulating layer GI can also be conformally formed on the upper surface and side surface of the terminal portion TP. The gate insulating layer GI can also be formed on one surface of the sidewall portion SW. The gate insulating layer GI can also be formed on the shallow element isolation pattern STI.

[0137] Reference Figures 13A to 13C A conductive layer 310 may be formed on a first surface of the substrate 100 on which a gate insulating layer GI is formed. The conductive layer 310 may fill the gate recess GR. The conductive layer 310 may cover the first surface of the substrate 100. The conductive layer 310 may comprise polysilicon or metal. The polysilicon may be doped with a dopant having a first conductivity type.

[0138] Reference Figure 14A and Figure 14B The source follower gate SFG can be formed by etching the conductive layer 310. For example, a third mask pattern MP3 can be formed on the conductive layer 310. The third mask pattern MP3 can define the source follower gate SFG. The third mask pattern MP3 can be used as an etching mask to perform an etching process on the conductive layer 310. The etching process can include a front-side anisotropic etching process. Therefore, the portion of the conductive layer 310 exposed by the third mask pattern MP3 can be etched, and the source follower gate SFG can be formed. After the source follower gate SFG is formed, the third mask pattern MP3 can be removed.

[0139] During the etching process, the gate insulating layer GI can also be etched. However, the etch ions used in the etching process can be etch-selective relative to the shallow element isolation pattern STI. Therefore, the gate insulating layer GI can be etched, but the shallow element isolation pattern STI can be retained.

[0140] Reference Figure 15A and Figure 15B A gate spacer GS can be formed on the side surface of the formed source follower gate SFG. The gate spacer GS may include silicon oxide, silicon nitride, or silicon oxynitride.

[0141] After the gate spacer GS is formed, a blocking mask BM can be formed. The blocking mask BM can cover the source follower gate SFG and the gate spacer GS. For example, the blocking mask BM can be disposed on the upper surface of the source follower gate SFG and the upper surface of the gate spacer GS.

[0142] After forming the barrier mask BM, the source / drain regions SD can be formed. For example, a doping process can be performed on the first surface of the substrate 100 in which the source follower gate SFG is formed. The doping process can be anisotropic doping. For example, the doping process can include an ion implantation process.

[0143] By performing a doping process, source / drain regions SD can be formed in the terminal portion TP. The doping process implants a dopant with a second conductivity type into the terminal portion TP. In this case, the dopant may not be implanted into the source follower gate SFG due to the barrier mask BM and the gate spacer GS. For example, the barrier mask BM and the gate spacer GS can be used as ion barriers. Therefore, the source follower gate SFG formed from polysilicon doped with a dopant with a first conductivity type may not be doped with a dopant with a second conductivity type.

[0144] The source / drain region SD can be aligned with the gate spacer GS. For example, the edge of the source / drain region SD can be vertically aligned with the edge of the gate spacer GS. Furthermore, the side region SR formed below the gate spacer GS can be left undoped.

[0145] After the source / drain region SD is formed, the blocking mask BM can be removed. Therefore, the upper surface of the source follower gate SFG and the upper surface of the gate spacer GS can be exposed.

[0146] The source / drain region (SD) can be extended in the depth direction through doping processes. For example, the source / drain region SD can be extended on the third-direction DR3. As a result, the source / drain region SD formed by isotropic doping can be referred to as the upper region of the source / drain region SD, and the source / drain region SD can be extended from the upper region to the lower region by anisotropic doping processes. The source / drain region SD formed by anisotropic doping can be superimposed on the upper region.

[0147] Figure 16A This is a cross-sectional view of an image sensor 10a according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line I-I'. Figure 16B This is a cross-sectional view of an image sensor 10a according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line II-II'. Figure 16C This is a cross-sectional view of an image sensor 10a according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line III-III'.

[0148] Most of the components and materials constituting the image sensor 10a described below are the same as those referenced above. Figures 1 to 6C The components and materials of the image sensor 10 described are substantially the same or similar. Therefore, for ease of explanation, the differences from the image sensor 10 described above will be mainly described.

[0149] Reference Figures 16A to 16C The fin portion FPa may be recessed. The height (level) of the upper end of the fin portion FPa may be lower than the height of one surface of the shallow element isolation pattern STI. Furthermore, the height of the upper end of the fin portion FPa may be lower than the height of the first surface of the substrate 100. However, the channel region CHa may still be formed in the portion of the fin portion FPa that protrudes from the shallow element isolation pattern STI (e.g., the exposed portion of the fin portion FPa).

[0150] The source follower gate SFGa may include a vertical portion 340 and a horizontal portion 320a, and may be disposed in a shallow element isolation pattern (STI). For example, the source follower gate SFGa may be buried in a shallow element isolation pattern (STI).

[0151] Therefore, the parasitic capacitance generated between the source follower gate SFGa and another adjacent gate can be reduced.

[0152] Furthermore, the parasitic capacitance generated between the source follower gate SFGa and the adjacent contact pattern can be reduced.

[0153] For example, the height of the upper end of the source follower gate SFGa on the third-direction DR3 can be substantially the same as the height of a surface of the shallow element isolation pattern STI. Furthermore, the height of the upper end of the source follower gate SFGa can be substantially the same as the height of the first surface of the substrate 100.

[0154] The upper surface of the horizontal portion 320a may be substantially coplanar with the surface of the shallow element isolation pattern STI. For example, the height of the upper surface of the horizontal portion 320a may be substantially the same as the height of the surface of the shallow element isolation pattern STI. Furthermore, the upper surface of the horizontal portion 320a may be substantially coplanar with the first surface of the substrate 100. For example, the height of the upper surface of the horizontal portion 320a may be substantially the same as the height of the first surface of the substrate 100. Furthermore, the upper surface of the horizontal portion 320a may be substantially coplanar with one surface of the terminal portion TPa. For example, the height of the upper surface of the horizontal portion 320a may be substantially the same as the height of one surface of the terminal portion TPa.

[0155] The gate insulating layer GI can be placed between the horizontal portion 320a and the terminal portion TPa. The gate insulating layer GI can also be placed between the horizontal portion 320a and the sidewall portion SWa. The gate insulating layer GI can also be placed between the horizontal portion 320a and the side region SR.

[0156] Since the horizontal portion 320a of the source follower gate SFGa is disposed in the shallow element isolation pattern STI, the gate spacer GS can be omitted. In this case, the sidewall portion SWa forming the side region SR can be disposed below the horizontal portion 320a. The edges of the source / drain region SD and the edges of the horizontal portion 320a can be vertically aligned. For example, the edges of the source / drain region SD can be substantially coplanar with the edges of the horizontal portion 320a on the third-direction DR3.

[0157] Figures 17A to 19A This is a cross-sectional view illustrating a method for manufacturing an image sensor 10a according to an embodiment of the present disclosure. Figures 17B to 19B This is a cross-sectional view illustrating a method for manufacturing an image sensor 10a according to an embodiment of the present disclosure.

[0158] Reference Figure 17A and Figure 17B In one embodiment, a portion of the fin portion FPa may be etched together during the process of forming the gate recess GR. The etch ions used in the etching process may have etch selectivity relative to the fin portion FPa. For example, the etch rate of the shallow element isolation pattern STI via etch ions may be greater than the etch rate of the fin portion FPa via etch ions. For example, the etch rate of the shallow element isolation pattern STI via etch ions may be about five times or more than the etch rate of the fin portion FPa via etch ions.

[0159] Therefore, the height of the upper end of the fin portion FPa can be reduced during the process of forming the gate recess GR.

[0160] However, to prevent the entire terminal portion TPa from being etched during the process of forming the gate recess GR, a second mask pattern MP2 can also be formed on the terminal portion TPa. However, the second mask pattern MP2 can be formed on the portion of the terminal portion TPa where the source / drain region SD will be formed, and the remaining portion of the terminal portion TPa can be exposed. The remaining portion of the terminal portion TPa can correspond to the sidewall portion SWa. Therefore, when the shallow element isolation pattern STI is etched, the first gate recess GR1 can be formed, and when the remaining portion of the terminal portion TPa is etched, the second gate recess GR2 can be formed.

[0161] The height of the bottom surface of the second gate recess GR2 can be approximately the same as the height of the upper end of the fin portion FPa. The height of the upper end of the sidewall portion SWA can be approximately the same as the height of the upper end of the fin portion FPa.

[0162] Reference Figure 18A and Figure 18B A gate insulating layer GI can be conformally formed on a first surface of the substrate 100 in which the first gate recess GR1 and the second gate recess GR2 are formed. The gate insulating layer GI can also be conformally formed on the upper surface and exposed side surface of the fin portion FPa. Furthermore, the gate insulating layer GI can be conformally formed on the upper surface and side surface of the terminal portion TPa.

[0163] Reference Figure 19A and Figure 19B A conductive layer 310a may be formed on a first surface of the substrate 100 on which a gate insulating layer GI is formed. The conductive layer 310a may fill a first gate recess GR1 and a second gate recess GR2. The conductive layer 310a may cover the first surface of the substrate 100. The conductive layer 310a may comprise polysilicon or metal. The polysilicon may be doped with a dopant having a first conductivity type.

[0164] Subsequently, the conductive layer 310a can be patterned to form the source follower gate SFGa.

[0165] Figure 20A This is a cross-sectional view of an image sensor 10b according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line I-I'. Figure 20B This is a cross-sectional view of an image sensor 10b according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line II-II'. Figure 20C This is a cross-sectional view of an image sensor 10b according to an embodiment of the present disclosure, which is... Figure 5The sectional view corresponding to line III-III'.

[0166] Most of the components and materials constituting the image sensor 10b described below are the same as those referenced above. Figures 1 to 6C The components and materials of the image sensor 10 described are substantially the same or similar. Therefore, for ease of explanation, the differences from the image sensor 10 described above will be mainly described.

[0167] Reference Figures 20A to 20C The horizontal portion 320 of the source follower gate SFGb can be omitted. In this case, the vertical portions 340 can be spaced apart from each other. Fin portions FP can be disposed between the vertical portions 340 to disconnect the vertical portions 340 from each other. Each of the contact patterns (not shown) can be connected to each of the vertical portions 340 and can be electrically connected to each other. Therefore, electrical signals can be applied to the vertical portions 340 simultaneously.

[0168] The height of the upper end of the vertical portion 340 can be substantially the same as the height of the upper end of the shallow element isolation pattern STI. The height of the upper end of the vertical portion 340 on the third-direction DR3 can also be substantially the same as the height of the upper end of the fin portion FP. The height of the upper end of the vertical portion 340 can also be substantially the same as the height of the first surface of the substrate 100.

[0169] Therefore, the parasitic capacitance generated between the source follower gate SFGb and another adjacent gate can be reduced.

[0170] Furthermore, the parasitic capacitance generated between the source follower gate SFGb and the adjacent contact pattern can also be reduced.

[0171] Figure 21A This is a cross-sectional view of an image sensor 10c according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line II-II'. Figure 21B This is a cross-sectional view of an image sensor 10c according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line III-III'.

[0172] Most of the components and materials constituting the image sensor 10c described below are the same as those referenced above. Figures 1 to 6C The components and materials of the image sensor 10 described are substantially the same or similar. Therefore, for ease of explanation, the differences from the image sensor 10 described above will be mainly described.

[0173] Reference Figure 21A and Figure 21BThe source / drain region SDc can be formed using an isotropic doping process. For example, the source / drain region SDc can be doped together with the channel region CH using an isotropic doping process. In this case, both the source / drain region SDc and the channel region CH can be doped with high concentrations of dopant. Therefore, the dopant concentration of the source / drain region SDc can be substantially the same as the dopant concentration of the channel region CH.

[0174] The side region SR can also be doped together with the channel region CH and the source / drain region SDc through isotropic doping processes.

[0175] Therefore, a method for manufacturing image sensors with simplified manufacturing processes and reduced manufacturing costs can be provided.

[0176] Figure 22 This is a cross-sectional view of an image sensor 10d according to an embodiment of the present disclosure, which is... Figure 5 The sectional view corresponding to line I-I'.

[0177] Most of the components and materials constituting the image sensor 10d described below are the same as those referenced above. Figures 1 to 6C The components and materials of the image sensor 10 described are substantially the same or similar. Therefore, for ease of explanation, the differences from the image sensor 10 described above will be mainly described.

[0178] Reference Figure 22 The fin portion FPd may have an inverted trapezoidal cross-sectional shape. For example, the fin portion FPd may have a width defined in the width direction of the channel, and the width of the fin portion FPd may increase towards the upper side of the fin portion FPd. The width of the fin portion FPd may decrease towards the lower side of the fin portion FPd. The width of the fin portion FPd may increase towards the first surface of the substrate 100, and may decrease towards the second surface of the substrate 100 as the fin portion FPd (e.g., along the third direction DR3) moves away from the first surface of the substrate 100.

[0179] Figure 23 This is an enlarged plan view of a photodiode region group PDRGe of an image sensor 10e according to an embodiment of the present disclosure.

[0180] Reference Figure 23 The structure of a Fin-FET applied to a source follower transistor according to some embodiments of this disclosure can also be applied to a transfer transistor, a reset transistor, or a select transistor. For example, the structure of a Fin-FET according to some embodiments of this disclosure can be applied to at least one of a source follower transistor, a transfer transistor, a reset transistor, and a select transistor. For example, as... Figure 23As shown, the gate structure of a Fin-FET according to some embodiments of this disclosure can be applied to at least one of the source follower gate SFG of a source follower transistor, the transport gate TGa of a transport transistor, the reset gate RSGa of a reset transistor, and the select gate SLGa of a select transistor. In some embodiments, such as Figure 23 As shown, the additional transistor (e.g., a dual-conversion gain transistor) disposed in the third photodiode region PDR3 may also have a structure substantially the same as or similar to the structure of a Fin-FET according to some embodiments of the present disclosure, but is not limited thereto.

[0181] Therefore, a transfer transistor, reset transistor, or select transistor with a junctionless transistor structure can be provided.

[0182] According to embodiments of this disclosure, a channel region having a substantially uniform dopant concentration can be formed in the fin portion via an isotropic doping process. Therefore, the area of ​​the channel region can be increased, and the width of the channel can be substantially increased. Consequently, the electrical characteristics of the transistor can be improved, and an image sensor with enhanced performance can be provided.

[0183] Furthermore, according to embodiments of this disclosure, a junctionless transistor can be provided because the channel region in the fin portion is doped with a dopant having the same conductivity type as the source / drain regions. Therefore, traps between the fin portion and the gate dielectric layer can be avoided, thereby improving the electrical characteristics of the transistor. For example, the transconductance of the transistor can be enhanced.

[0184] Furthermore, according to embodiments of this disclosure, an image sensor with a transistor exhibiting reduced parasitic resistance can be provided, due to a side region located between the source / drain region and the channel region and doped with a dopant having the same conductivity type as the source / drain region and the channel region. Therefore, an image sensor with enhanced performance can be provided.

[0185] Furthermore, according to embodiments of this disclosure, since the side regions are doped using an isotropic doping process, the dopant concentration in the side regions can be formed substantially uniformly. Therefore, the area of ​​the side regions can be increased.

[0186] Furthermore, according to embodiments of this disclosure, parasitic capacitance generated between the gate and the contact or between gates can be reduced due to the gate being buried in a shallow element isolation pattern. Therefore, an image sensor with enhanced performance can be provided.

[0187] Furthermore, according to embodiments of this disclosure, since the channel region and the source / drain region are formed together through an isotropic doping process, a method for manufacturing an image sensor with a simplified manufacturing process and reduced manufacturing cost can be provided.

[0188] Furthermore, according to embodiments of this disclosure, since the channel region and the source / drain region are formed together by isotropic doping, a method for manufacturing an image sensor with a simplified manufacturing process and reduced manufacturing cost can be provided.

[0189] The foregoing description describes specific embodiments for implementing this disclosure. In addition to the embodiments described above, this disclosure will also include embodiments that can be easily bypassed or modified. Furthermore, this disclosure will also include techniques that can be easily implemented by modifying the embodiments. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined not only by the appended claims, but also by the equivalents of the claims of this disclosure.

Claims

1. An image sensor, comprising: A deep element isolation pattern is disposed in a substrate to define a group of photodiode regions, the substrate being doped with a dopant having a first conductivity type, each of the photodiode regions including at least one photodiode region; Shallow element isolation pattern, filling shallow trenches recessed from a first surface of the substrate, to define at least one active region in each of the photodiode region groups, the active region including terminal portions and fin portions; The gate fills a gate recess formed in a shallow element isolation pattern, and the gate recess exposes a portion of the fin portion. as well as A gate insulating layer is located between the gate and the exposed portion of the fin. in, The fin portion includes a channel region formed in the exposed portion of the fin portion and is doped with a dopant having a second conductivity type different from the first conductivity type. The terminal portion includes a side region that defines a gate recess and is doped with a dopant having a second conductivity type. The side regions are stacked vertically with the gate.

2. The image sensor according to claim 1, wherein, The channel region is uniformly doped with a dopant of a second conductivity type in the vertical direction.

3. The image sensor according to claim 2, wherein, The side regions are uniformly doped with dopants of a second conductivity type.

4. The image sensor according to claim 3, wherein, The dopant concentration in the side region is the same as that in the channel region.

5. The image sensor according to claim 1, wherein, The lateral region extends in a direction that intersects with the longitudinal direction of the channel region.

6. The image sensor according to claim 1, wherein, The terminal portion also includes a source / drain region, which is connected to the side region and is doped with a dopant having a second conductivity type. The source / drain regions are not vertically stacked with the gate, and The source / drain region, side region, channel region, and gate form a junctionless transistor.

7. The image sensor according to claim 6, wherein, The dopant concentration in the source / drain region is greater than that in the side region.

8. The image sensor according to claim 6, wherein, The side region is located between the source / drain region and the channel region, and The side region connects the source / drain region and the channel region.

9. The image sensor according to claim 7, wherein, The lateral region includes: The upper part connects to the source / drain region; and The lower part is positioned below the upper part, and The dopant concentration in the upper part is greater than that in the lower part.

10. The image sensor according to any one of claims 1 to 9, wherein, The gate is doped with a dopant having a first conductivity type.

11. An image sensor, comprising: A deep element isolation pattern is disposed in a substrate to define a group of photodiode regions, the substrate being doped with a dopant having a first conductivity type, each of the photodiode regions including at least one photodiode region; Shallow element isolation pattern, filling shallow trenches recessed from a first surface of the substrate, to define at least one active region in each of the photodiode region groups, the active region including terminal portions and fin portions; The gate fills a gate recess formed in a shallow element isolation pattern to expose a portion of the fin portion. The gate includes a plurality of vertical portions spaced apart from each other in the gate recess. as well as A gate insulating layer is located between the gate and the exposed portion of the fin. in, The fin portion includes a channel region formed in the exposed portion of the fin portion and is doped with a dopant having a second conductivity type different from the first conductivity type. The terminal portion includes: The source / drain regions are doped with dopants having a second conductivity type; and A side region, disposed between the fin portion and the source / drain region, is doped with a dopant having a second conductivity type. The dopant concentration in the side region is lower than or the same as that in the source / drain region.

12. The image sensor according to claim 11, wherein, The upper end of the fin is positioned at the same height as the first surface of the base, and The fins separate the vertical sections from each other.

13. The image sensor according to claim 11, wherein, The height of the upper surface of the fin is lower than the height of the first surface of the base. The gate also includes a horizontal portion connected to the vertical portion, and The height of the upper surface of the horizontal portion is the same as the height of the first surface of the base.

14. The image sensor according to any one of claims 11 to 13, wherein, The width of the fin portion, defined in the width direction of the channel region, increases toward the first surface of the substrate.

15. A method for manufacturing an image sensor, the method comprising: The first surface of the substrate is patterned to form shallow trenches defining an active region, which includes a terminal portion and a fin portion. Forming a shallow element isolation pattern that fills the shallow trench; The shallow element isolation pattern is patterned to form a gate recess that exposes the side surface of the fin portion; An isotropic doping process is performed to form a channel region in the fin portion through the upper and side surfaces of the fin portion; A gate insulating layer is formed on the fin portion; as well as A gate is formed to fill the gate depression.

16. The method according to claim 15, wherein, The steps involved in performing an isotropic doping process include: A doped film, including a dopant, is conformally formed on the upper surface and exposed side surfaces of the fin portion; and An annealing process is performed to allow the dopant in the doped film to diffuse into the fin portion.

17. The method according to claim 15, wherein, The steps of performing the isotropic doping process include: uniformly doping the upper surface and exposed side surfaces of the fin with a dopant in plasma.

18. The method according to any one of claims 15 to 17, wherein the method further comprises: Source / drain regions are formed in the terminal section. in, The source / drain regions are doped with dopants that have the same conductivity type as the channel regions.

19. The method according to claim 18, wherein, The source / drain regions are formed simultaneously with the channel region through the steps of performing isotropic doping processes.

20. The method according to claim 18, wherein, The terminal portion includes a sidewall portion that defines a gate recess and connects to the fin portion. The side regions are formed in the sidewall portions by performing isotropic doping processes. The side regions are doped with dopants having the same conductivity type as the channel regions, and The source / drain region, side region, channel region, and gate form a junctionless transistor.

Images