Etching method of side wall
By performing stepwise cleaning and pre-coating of the etching equipment cavity, a stable and uniform process environment is constructed, which solves the problem of low device reliability and yield caused by sidewall etching and achieves higher etching accuracy and uniformity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICONDUCTOR MANUFACTURING (WUXI) LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-10
AI Technical Summary
In semiconductor manufacturing processes, when etching equipment is running other processes, sidewall etching can lead to low device reliability and yield, especially in the 55nm process, where poor wafer batch uniformity can cause abnormal device parameters.
A step-by-step cleaning method is adopted for the cavity. First, nitrogen trifluoride gas is used to remove inorganic byproducts, then oxygen is used to remove organic byproducts. Then, a pre-coating is deposited on the inner wall of the cavity to build a stable and uniform process cavity environment, followed by sidewall etching.
This improved the perpendicularity of the sidewall etching profile and the accuracy of critical dimensions, thereby enhancing the reliability and yield of the device products and resolving the issue of abnormal device parameters.
Smart Images
Figure CN122373706A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a sidewall etching method. Background Technology
[0002] Sidewalls are dielectric isolation structures formed around the gate of semiconductor devices to precisely control the source and drain doping regions and suppress short-channel effects and parasitic capacitance. As semiconductor manufacturing processes have advanced to below 90 nanometers (nm), composite sidewall structures composed of multiple thin film layers are typically used to meet the performance and reliability requirements of devices in smaller sizes.
[0003] Taking the fabrication process of a 55 nm chip as an example, in the process of etching the sidewalls of transistors, active gases and materials are deposited on the inner wall of the chamber to form a stable coating. When the etching equipment runs other processes to etch the sidewalls, due to changes in the state of the reaction chamber, the plasma cannot consume enough of the chamber coating and instead consumes the wafer, resulting in smaller critical dimensions of the wafer sidewalls and poor batch uniformity. In the Wafer Acceptance Test (WAT), the saturation drain current (Is) of the device is measured. dsat An abnormality in this parameter reduces the reliability and yield of the device product. Summary of the Invention
[0004] This application provides a sidewall etching method that can solve the problem of low device reliability and yield when etching equipment is running other processes before sidewall etching in related technologies.
[0005] This application provides a sidewall etching method, including: A pretreatment operation is performed on the process cavity of the etching equipment, the pretreatment operation including at least one cavity cleaning step and at least one cavity inner wall pre-coating deposition step; A substrate is transferred into the process cavity, a gate structure is formed on the substrate, the gate structure includes a gate and a gate dielectric layer formed between the gate and the substrate, a first sidewall dielectric layer is formed on the surface of the gate structure and the substrate, and a second sidewall dielectric layer is formed on the first sidewall dielectric layer. Etching is performed within the process chamber to expose the top of the gate structure and the substrate surface around the gate structure. The first sidewall dielectric layer and the second sidewall dielectric layer around the gate structure constitute the sidewalls.
[0006] In some embodiments, the cavity cleaning step includes: The first cleaning is performed using a gas containing nitrogen trifluoride under first pressure and first power conditions; The second cleaning is performed using a gas containing oxygen under second pressure and second power conditions.
[0007] In some embodiments, the first pressure ranges from 200mt to 300mt.
[0008] In some embodiments, the first power ranges from 1000W to 1500W.
[0009] In some embodiments, the flow rate of the nitrogen trifluoride gas does not exceed 700 sccm.
[0010] In some embodiments, the second pressure ranges from 10 mt to 20 mt.
[0011] In some embodiments, the second power ranges from 1000W to 1500W.
[0012] In some embodiments, the flow rate of the oxygen gas does not exceed 200 sccm.
[0013] In some embodiments, the cavity inner wall pre-coating deposition step includes: The pre-coating is formed on the inner wall of the cavity by reacting a gas containing oxygen and silicon tetrachloride under a third pressure and a third power condition.
[0014] In some embodiments, the pre-coating includes an oxide coating.
[0015] In some embodiments, the flow ratio of oxygen to silicon tetrachloride is 1:4 to 4:1.
[0016] In some embodiments, the total flow rate of the oxygen and the silicon tetrachloride does not exceed 150 sccm.
[0017] In some embodiments, the value range of the third pressure is 10mt to 20mt.
[0018] In some embodiments, the value of the third power ranges from 1000W to 1500W.
[0019] The technical solution of this application has at least the following advantages: By employing a stepwise cleaning chamber to sequentially remove inorganic and organic byproducts, a pre-coated uniform silicon oxide layer is deposited. This systematically constructs a stable, uniform, and highly controllable initial environment for the sidewall etching process chamber. Subsequent etching improves the perpendicularity of the sidewall profile after sidewall etching, enhances the accuracy and uniformity of critical dimensions after etching, and ultimately improves the reliability and yield of the device products. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 This is a flowchart of a sidewall etching method provided in an exemplary embodiment of this application.
[0022] Figures 2 to 3 This is a cross-sectional schematic diagram of the etching process of the sidewall provided in an exemplary embodiment of this application.
[0023] Figure 4 and Figure 5 This is a test result diagram of a pattern obtained by etching a sidewall using an exemplary embodiment of this application. Detailed Implementation
[0024] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0025] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0027] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0028] refer to Figure 1 The diagram illustrates a flowchart of an etching method for a sidewall provided in an exemplary embodiment of this application, the method comprising: Step S1: Perform a pretreatment operation on the process cavity of the etching equipment. The pretreatment operation includes at least one cavity cleaning step and at least one cavity inner wall pre-coating deposition step.
[0029] The cavity cleaning step is used to remove etching byproducts (including organic and / or inorganic byproducts) from the cavity, and the pre-coating deposition step is used to form a pre-coating on the inner wall of the cavity to avoid excessive consumption of material on the substrate.
[0030] For example, the cavity cleaning step may include: step S11, using a gas containing nitrogen trifluoride (NF3) under a first pressure and a first power condition to perform a first cleaning, which is mainly used to remove inorganic by-products in the cavity; step S12, using a gas containing oxygen under a second pressure and a second power condition to perform a second cleaning, which is mainly used to remove organic by-products in the cavity.
[0031] Optionally, the first pressure ranges from 200 millitorr (mt) to 300 mt (e.g., it could be 250 mt); optionally, the first power ranges from 1000 watt (W) to 1500 W; optionally, the flow rate of nitrogen trifluoride gas does not exceed 700 standard cubic centimeters per minute (sccm).
[0032] Optionally, the second pressure ranges from 10 to 20 mt (for example, it can be 15 mt); optionally, the second power ranges from 1000 W to 1500 W; optionally, the oxygen gas flow rate does not exceed 200 sccm.
[0033] For example, the pre-coating deposition step on the inner wall of the cavity may include: step S13, using a gas containing oxygen (O2) and silicon tetrachloride (SiCl4), reacting under a third pressure and a third power condition to generate the pre-coating on the inner wall of the cavity.
[0034] For example, the pre-coating includes an oxide coating. Optionally, the flow ratio of oxygen to silicon tetrachloride is 1:4 to 4:1 (e.g., it can be 2:1); optionally, the total flow rate of oxygen and silicon tetrachloride does not exceed 150 sccm; optionally, the third pressure ranges from 10 ms to 20 ms; optionally, the third power ranges from 1000 W to 1500 W.
[0035] The etching equipment executes steps S11, S12 and S13 sequentially through a preset program (recipe), enabling the equipment to construct a stable, uniform, and highly controllable initial environment for the process chamber when performing sidewall etching for other processes.
[0036] Step S2: The substrate is transferred into the process cavity, and a gate structure is formed on the substrate. The gate structure includes a gate and a gate dielectric layer formed between the gate and the substrate. A first sidewall dielectric layer is formed on the surface of the gate structure and the substrate, and a second sidewall dielectric layer is formed on the first sidewall dielectric layer.
[0037] After the preprocessing operation is completed, the substrate placed in the storage cavity can be transferred to the process cavity by a robotic arm.
[0038] refer to Figure 2 The diagram shows a cross-sectional schematic of a semiconductor structure 100 transferred into a process cavity. The semiconductor structure 100 includes: a substrate 110 (typically in the form of a wafer), a gate structure 120 formed on the substrate 110, the gate structure 120 including a gate dielectric layer 121 and a gate 122 located above the gate dielectric layer 121, a first sidewall dielectric layer 130 and a second sidewall dielectric layer 140 on the sidewalls of the gate structure 120 and the surface of the substrate 110.
[0039] For example, substrate 110 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon substrate on which an epitaxial layer has been grown. The material of gate dielectric layer 121 may include silicon oxide (SiO2), silicon oxynitride (SiON), or hafnium oxide (HfO2). The material of gate 122 may include polysilicon, metal, or a combination thereof. First sidewall dielectric layer 130 and second sidewall dielectric layer 140 may have different etch selectivity ratios; typical material combinations include, but are not limited to: first sidewall dielectric layer 130 comprising silicon oxide (SiO2), and second sidewall dielectric layer 140 comprising silicon nitride (Si3N4); or, first sidewall dielectric layer 130 comprising silicon nitride (Si3N4), and second sidewall dielectric layer 140 comprising silicon oxide (SiO2). First sidewall dielectric layer 130 and second sidewall dielectric layer 140 together constitute the etchable stack layer for forming sidewalls.
[0040] Step S3: Etching is performed in the process chamber to expose the top of the gate structure and the substrate surface around the gate structure. The first sidewall dielectric layer and the second sidewall dielectric layer around the gate structure constitute the sidewall.
[0041] refer to Figure 3 The diagram shows a cross-sectional view of the etched semiconductor structure 100. The top and peripheral substrate surfaces of the gate structure 120 are exposed and etched, and the first sidewall dielectric layer 130 and the second sidewall dielectric layer 140 on the periphery of the gate structure 120 form sidewalls.
[0042] Optionally, after completing the sidewall etching step, the substrate may undergo source / drain ion implantation, metal silicide formation, or metal interconnection steps. This process method can be used to manufacture devices including, but not limited to, metal-oxide-semiconductor transistors, complementary metal-oxide-semiconductor transistors, or floating-gate transistors.
[0043] An exemplary application scenario of this application is the sidewall etching of a 55nm process high threshold voltage N-type MOSFET (HVTN) device.
[0044] refer to Figure 4 and Figure 5 The diagram shows a comparison of wafer measurement results between embodiments of this application and comparative examples (not using embodiments of this application). Figure 4 The horizontal axis represents the sample numbers in chronological order, with dashed lines as intervals. The left side of the dashed line represents the Etch Process Detection (EPD) time of the sample prepared in the embodiments of this application, and the right side of the dashed line represents the EPD time of the sample prepared in the comparative example. Figure 5The left and right sides of the dashed lines represent the I values of HVTN devices prepared using the methods of the embodiments and comparative examples of this application during WAT testing, respectively. dsat Data. Table 1 shows the critical dimensions of the sidewalls of the first wafers (the first wafer after sidewall etching following other processes in the etching equipment) prepared in the embodiments and comparative examples of this application. It can be seen that after adopting the method of the embodiments of this application, the EPD time is longer, especially for the first wafer, and the critical dimensions of the sidewalls are larger, meaning that the critical dimensions of the sidewalls prepared in the same batch have better uniformity; dsat Lower data indicates improved reliability and yield of the device products.
[0045] Table 1. Critical dimension test data of the sidewall of the first wafer HVTN device Key dimensions of the sidewall Target size 93.4nm Examples of this application 94.1nm Comparative Example 91.0nm This invention employs a step-by-step cleaning chamber to sequentially remove inorganic and organic byproducts, followed by the deposition of a pre-coated uniform silicon oxide layer. This systematically constructs a stable, uniform, and highly controllable initial environment for the sidewall etching process chamber before etching. This improves the perpendicularity of the sidewall profile after sidewall etching, enhances the accuracy and uniformity of critical dimensions after etching, and ultimately improves the reliability and yield of the device products.
[0046] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for etching sidewalls, characterized in that, include: A pretreatment operation is performed on the process cavity of the etching equipment, the pretreatment operation including at least one cavity cleaning step and at least one cavity inner wall pre-coating deposition step; A substrate is transferred into the process cavity, and a gate structure is formed on the substrate. The gate structure includes a gate and a gate dielectric layer formed between the gate and the substrate. A first sidewall dielectric layer is formed on the surface of the gate structure and the substrate, and a second sidewall dielectric layer is formed on the first sidewall dielectric layer. Etching is performed within the process chamber to expose the top of the gate structure and the substrate surface around the gate structure. The first sidewall dielectric layer and the second sidewall dielectric layer around the gate structure constitute the sidewalls.
2. The method according to claim 1, characterized in that, The cavity cleaning steps include: The first cleaning is performed using a gas containing nitrogen trifluoride under first pressure and first power conditions; The second cleaning is performed using a gas containing oxygen under second pressure and second power conditions.
3. The method according to claim 2, characterized in that, The first pressure ranges from 200mt to 300mt.
4. The method according to claim 3, characterized in that, The first power value ranges from 1000W to 1500W.
5. The method according to claim 4, characterized in that, The flow rate of the nitrogen trifluoride gas does not exceed 700 sccm.
6. The method according to claim 2, characterized in that, The second pressure ranges from 10mt to 20mt.
7. The method according to claim 6, characterized in that, The second power value ranges from 1000W to 1500W.
8. The method according to claim 7, characterized in that, The flow rate of the oxygen gas does not exceed 200 sccm.
9. The method according to claim 1, characterized in that, The pre-coating deposition step on the inner wall of the cavity includes: The pre-coating is formed on the inner wall of the cavity by reacting a gas containing oxygen and silicon tetrachloride under a third pressure and a third power condition.
10. The method according to claim 9, characterized in that, The pre-coating includes an oxide coating.
11. The method according to claim 10, characterized in that, The flow ratio of oxygen to silicon tetrachloride is 1:4 to 4:
1.
12. The method according to claim 11, characterized in that, The total flow rate of the oxygen and the silicon tetrachloride shall not exceed 150 sccm.
13. The method according to claim 12, characterized in that, The value range of the third pressure is 10mt to 20mt.
14. The method according to claim 13, characterized in that, The value range of the third power is 1000W to 1500W.