A soaker active cooling pellet and a method of making the same

Abstract

This invention relates to the technical field of chip manufacturing, and mainly discloses a homogenized active cooling chip and its preparation method. The chip includes a microchannel layer with microfluidic channels and a first interconnect unit, the first interconnect unit having a deformation region; an electrical interconnect layer covering the lower surface of the microchannel layer; and a thermal expansion layer covering the lower surface of the electrical interconnect layer, containing a second interconnect unit that connects the first interconnect unit to the active chip. This invention solves the problem that existing chip heat exchange structures with uniform and dense reinforcement to meet the potential local high heat flux density heat sources lead to a significant increase in flow resistance and energy waste.

Description

Technical Field

[0001] This invention relates to the technical field of chip manufacturing, and in particular to a homogenized active cooling die and its preparation method. Background Technology

[0002] Integrated chip technology is one of the main paths to improve chip computing power in the post-Moore's Law era. Through a new design paradigm of "decomposition-combination-integration," it drives the evolution of chips towards higher integration levels in three dimensions, and is a key method for my country to fabricate high-performance chips across process nodes. However, on the one hand, due to the continuous development of chip technology, the average power consumption and local hotspot heat flux density of a single chip are increasing, reaching 800W / cm² in the 7nm process. 2 Micrometer-scale localized hot spots, with an average heat flux density on the chip approaching 150 W / cm². 2 On the other hand, as chips evolve from 2D planar layouts to 3D three-dimensional layouts, the heat dissipation requirements of chips on the vertical projected area increase significantly for the same total power consumption. Furthermore, the heat dissipation path of chips far from heat dissipation devices is lengthened, and parasitic thermal resistance increases. Therefore, remote heat dissipation methods based on layer-by-layer heat transfer can no longer meet the heat dissipation requirements of high-power, highly integrated 3D integrated chips.

[0003] In recent years, microchannel near-junction cooling, which involves creating microchannels on the back substrate of a chip to directly introduce fluid heat dissipation, has attracted attention due to its ability to significantly reduce thermal resistance and effectively address the problem of heat accumulation in high-power chips. However, traditional microchannel near-junction cooling methods integrate the microchannels with the substrate of the active heat-generating chip, forcing an increase in chip thickness. On the one hand, due to the needs of integration technology, current 3D integrated chips are developing towards thinner thicknesses, with single-layer chip thicknesses reduced to below 100μm. Integrating heat dissipation fluid microchannels at this thickness will lead to a sharp increase in flow resistance, a decrease in heat dissipation efficiency, and an increase in the pump power required for heat dissipation, resulting in a significant decrease in economy and energy efficiency. If the chip substrate thickness is increased to the thickness required for setting up microchannels, such as 300μm, the area of ​​through-silicon vias (TSVs) used for 3D electrical interconnects will increase due to the requirements of their fabrication process (consistent TSV aspect ratio), leading to a significant increase in the area of ​​passive regions required for electrical interconnects, thereby squeezing the area of ​​the active layer and resulting in a decrease in chip performance for the same chip area. On the other hand, incorporating microchannel fabrication processes into active chip manufacturing processes will severely impact the yield of active chips and significantly increase costs. Therefore, traditional near-junction heat dissipation methods for substrate-integrated microchannels cannot balance the conflicting demands of high power and high integration density in three-dimensional integrated chips.

[0004] Therefore, there is an urgent need to develop a new microchannel heat dissipation method suitable for high-power, highly integrated 3D integrated chips. Furthermore, the following technical problems encountered in the integration of microchannels and TSVs must be addressed in its fabrication process: (1) Traditional near-junction microchannels use conventional hydrophilic bonding methods in their bonding and sealing processes. Due to the limitations of their process principles, a micron-thickness buried silica layer will form at the bonding interface, and voids are prone to exist at the bonding interface. Voids will affect the bonding reliability and lead to failure. The buried silica layer will hinder subsequent TSV fabrication processes such as etching, sputtering, and electroplating, resulting in the failure of the heat dissipation structure and electrical interconnect integration.

[0005] (2) The height of the microchannel must meet the requirements of heat dissipation and heat exchange efficiency, so the volume of the TSV will increase with its height. For example, when the aspect ratio of the TSV is set to 8:1 in current mature processes, if the depth of the TSV increases to 400μm, its diameter needs to reach 50μm; in contrast, the diameter of the TSV in a conventional 3D chip is 5-10μm. Since the thermal expansion coefficients of the conductive metal (e.g., copper) filled in the TSV are very different from those of silicon, large-volume TSVs will be subject to greater thermal stress in the high-temperature annealing process of TSV fabrication and in high-temperature application scenarios during service, which may eventually lead to risks such as TSV expansion, heat exchange structure rupture or chip failure.

[0006] (3) Different heat distributions will appear in different functional areas of the chip. With the development of advanced process technology, the heat flux density of local hot spots will increase. For example, in the 7nm process, a local heat source with a heat density of nearly 800W / cm2 will appear in a certain position of the computing core area. The non-uniformly distributed heat source will affect the chip performance and even its service life. Summary of the Invention

[0007] Therefore, the technical problem to be solved by the present invention is that existing chips have unsatisfactory heat dissipation efficiency when dealing with unevenly distributed local heat sources.

[0008] The above-mentioned technical problems are solved by the following technical solution: The present invention proposes a heat-equalizing active cooling core, which includes a microchannel layer, in which a microfluidic groove and a first interconnection unit are disposed, wherein a deformation region is formed in the first interconnection unit; an electrical interconnection layer, which is disposed on the lower surface of the microchannel layer; and a thermal expansion layer, which is disposed on the lower surface of the electrical interconnection layer, wherein a second interconnection unit is disposed inside the thermal expansion layer, and the second interconnection unit connects the first interconnection unit and the active core.

[0009] In a preferred embodiment of the active cooling core of the present invention: a bonding preparation layer and a first bonding layer are sequentially deposited on the lower surface of the electrical interconnect layer, and a second bonding layer is deposited on the top of the thermal expansion layer, wherein the second bonding layer is bonded to the first bonding layer.

[0010] In a preferred embodiment of the heat-equalizing active cooling core of the present invention: interconnecting holes are formed in the thermal expansion layer, and the second interconnecting unit is disposed in the interconnecting holes.

[0011] In a preferred embodiment of the heat-equalizing active cooling core of the present invention: a first pad and a first welding area are provided on the upper surface of the microchannel layer, and an insulating ring is provided between the first pad and the first welding area; a second pad and a second welding area are provided on the lower surface of the thermal expansion layer, and the insulating ring isolates the second pad and the second welding area; the first pad is fixed to the top of the first interconnect unit, and the second pad is fixed to the bottom of the second interconnect unit.

[0012] In a preferred embodiment of the heat-equalizing active cooling core of the present invention: the top end of the second interconnect unit and the bottom end of the first interconnect unit are connected through the internal circuitry of the electrical interconnect layer.

[0013] In a preferred embodiment of the heat-equalizing active cooling core of the present invention: the first interconnecting unit and the second interconnecting unit are coaxially arranged; or, the first interconnecting unit and the second interconnecting unit are staggered.

[0014] In a preferred embodiment of the heat-equalizing active cooling core of the present invention: fluid inlet and outlet are provided at the corresponding positions of the microfluidic groove in the first welding zone.

[0015] To solve the above-mentioned technical problems, the present invention also proposes the following technical solution: a method for preparing a homogenized active cooling chip, comprising the following steps: spin-coating photoresist on the upper surface of a first silicon wafer, forming a microfluidic trench on the first silicon wafer after standard photolithography and deep silicon etching, and removing the remaining photoresist; wherein, a bonding region is formed in the area of ​​the first silicon wafer outside the microfluidic trench; surface activation is performed on the bonding region and the upper surface of the second silicon wafer to form a first activation region and a second activation region respectively, bonding the first activation region and the second activation region, sealing and forming a microchannel layer; thinning the upper surface of the microchannel layer, etching the bonding region and... A first deposition hole is formed; an insulating layer, a barrier layer, and a first seed layer are deposited sequentially within the first deposition hole, followed by electrochemical deposition and annealing to form the first interconnect unit. The first interconnect unit is filled with a soft adhesive and chemically mechanically polished down to the insulating layer. A barrier layer and a second seed layer are deposited sequentially on the insulating layer on the upper surface of the microchannel layer. After electrochemical deposition of the second seed layer, chemically mechanically polishing is performed, followed by patterning using standard photolithography. Then, a first pad, an insulating ring, and a first soldering area are etched. A fluid inlet and outlet are formed on the first soldering area, and the depth of the fluid inlet and outlet is etched to... At the location of the insulating layer, a core preform is formed; a carrier sheet is temporarily bonded to the upper surface of the first pad using a temporary bonding method, and the lower surface of the microchannel layer is thinned to expose the metal at the lower end of the first interconnect unit. An electrical interconnect layer is prepared on the lower surface of the microchannel layer, and a bonding preparation layer is deposited on the lower surface of the electrical interconnect layer; simultaneously, a thermal expansion layer is epitaxially grown on the third silicon wafer; the first bonding layer and the second bonding layer are simultaneously prepared on the bonding preparation layer and the thermal expansion layer, respectively, and after surface activation, they are bonded together. The third silicon wafer is then thinned and polished to completely remove the thermal expansion layer; a hard mask is prepared on the lower surface of the thermal expansion layer, and etched after a standard photolithography process. A hard mask is used, and the thermal expansion layer is etched according to the pattern formed by etching the hard mask until the electrical interconnect metal is exposed, forming interconnect holes in the thermal expansion layer; an insulating layer, a barrier layer, and a third seed layer are deposited in the interconnect holes using the same method as for preparing the first pad; the third seed layer is electrochemically deposited until it fills the interconnect holes and forms the second interconnect unit; the lower end face of the deposited second interconnect unit is thinned by chemical mechanical polishing, and a second pad, an insulating ring, and a second soldering area are prepared; the carrier sheet is debonded, and the fluid inlet and outlet in the first soldering area are etched to the position where they communicate with the microfluidic channel in the microchannel layer, forming a homogenized active cooling core.

[0016] In a preferred embodiment of the preparation method of the homogenizing active cooling core of the present invention: the bonding preparation layer is made of silicon dioxide with a surface roughness of less than 0.5 nm; the thermal expansion layer is made of diamond with a surface roughness of less than 0.8 nm.

[0017] In a preferred embodiment of the preparation method of the homogenizing active cooling core of the present invention: the first bonding layer and the second bonding layer are made of silicon dioxide and have a thickness of 10nm~30nm.

[0018] In a preferred embodiment of the method for preparing the homogenized active cooling core of the present invention: when preparing the interconnect hole, Si3N4 is deposited on the surface of the thermal expansion layer by chemical vapor deposition, then patterned by standard photolithography, and then Si3N4 is etched by dry etching technology to transfer the pattern to the Si3N4 layer. After removing the resist, Si3N4 is used as an etching mask for the thermal expansion layer; at least one of ICP etching technology or ultraviolet nanosecond laser method is used to etch the thermal expansion layer, and the silicon dioxide layer is etched by dry etching until the interconnect metal is exposed to form the interconnect hole.

[0019] The beneficial effects of this invention are as follows: 1. Unlike typical design methods that open channels on active substrates, this invention adopts a modular approach of "disassembling and then reassembling," completely decoupling the microchannels from the active core. A new diamond thermal expansion layer and standardized electrical interconnects are added, reconstructing the active core into an actively cooled core consisting of a "microchannel layer + electrical interconnect layer + thermal expansion layer." Through the integration of standardized pad interfaces for fluid and electrical signals, it ensures both the thinness of the active core, high vertical interconnect density, and high active layer area utilization. Furthermore, the dual-mode layout of the thermal expansion layer for heat dissipation and the microfluidic trenches adapts to non-uniform heat source scenarios, achieving "one core for multiple uses" and significantly improving core reusability.

[0020] 2. Surface activation bonding technology is adopted to avoid the formation of silica layer and voids on the bonding surface during the sealing of microchannels (characterized by no silica and void rate ≤0.1%). At the same time, the bonding structure and parameters are optimized for the diamond thermal expansion layer to adapt to the requirements of layered bonding. While ensuring the reliability of bonding, the heat conduction path is further shortened and the thermal resistance between the thermal expansion layer and the microchannel layer is reduced.

[0021] 3. To address the thermal stress issue, this invention proposes a hollow metal interconnect column, namely the first interconnect unit, which is filled with soft adhesive within a hollow structure. Based on this, a second interconnect unit is coaxially or staggeredly configured with a diamond thermal expansion layer for heat homogenization, forming a dual protection of "structural buffering + heat homogenization and cooling." This effectively prevents electrical performance failure or heat exchange structure damage caused by non-uniform heat sources during hot annealing and high-temperature service.

[0022] 4. To solve the bonding thermal resistance problem of "modular" integration, this invention proposes "large-area bonding metal". Based on this, a second welding zone is designed in conjunction with a thermal expansion layer, and a vacuum insulation ring ensures electrical insulation. The large-area bonding metal, combined with the high thermal conductivity of diamond, further reduces the thermal resistance of the bonding layer and avoids heat accumulation under non-uniform heat sources. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention. Wherein: Figure 1 An overall cross-sectional view of the homogenized active cooling core is shown; Figure 2 The diagram shows the location distribution of the bonding preparation layer, the first bonding layer, and the second bonding layer within the homogenized active cooling core. Figure 3 A cross-sectional view of the second interconnected unit of the homogenized active cooling core is shown; Figure 4 A detailed cross-sectional view of the homogenized active cooling core is shown; Figure 5 The fluid inlet and outlet distribution diagram of the homogenized active cooling core is shown; Figure 6 A cross-sectional view showing the distribution of microfluidic channels within the homogenizing active cooling core is shown. Figure 7 A cross-sectional view of the first deposition hole of the homogenized active cooling core particle is shown; Figure 8 This diagram illustrates the formation process of the first interconnecting unit in the homogenized active cooling core. Figure 9 A radial cross-sectional view of the first interconnected unit of the homogenized active cooling core is shown. Figure 10 A schematic diagram showing the ratio of pads to insulating rings in a heat-equalizing active cooling core is shown. Figure 11 The distribution diagrams of the first and second activation zones of the homogenized active cooling core particles are shown. Figure 12 A schematic diagram of the core pellet embryo structure is shown; Figure 13 The bonding region distribution of the homogenized active cooling core particles is shown; Figure 14 A flow chart of the microchannel layer fabrication process for homogenized active cooling core particles is shown; Figure 15 A flow chart of the core pellet preparation process for homogenized active cooling core pellets is shown. Figure 16 The remaining preparation process flow diagram of the homogenized active cooling core particle is shown; Figure 17 A diagram showing the bonding of the homogenized active cooling core particles is presented; Figure 18 The image shows a high-precision ultrasonic scanning result of the microfluidic channel; Figure 19 The diagram shows the bonding situation between the first and second activation regions; Figure 20 The image shows an actual etched wafer with grooved and microneedle-ribbed microchannel heat transfer enhancement structures; Figure 21 An enlarged view of the deformation zone of the homogenized active cooling core particle is shown; Figure 22 The packaging structure of the vapor chamber active cooling chip and the three-dimensional integrated chip is shown. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0025] The terminology used in this invention is that which is currently widely used in the art in consideration of the function of the invention; however, these terms may vary according to the intent of those skilled in the art, precedent, or new technology in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the invention. Therefore, the terms used in this specification should not be construed as simple names, but rather based on their meanings and the overall description of the invention.

[0026] Example 1

[0027] Reference Figures 1 to 22 The first embodiment of the present invention provides a homogeneous active cooling core (CC), whose core function is to solve the problems of low reusability, insufficient thermal shock resistance and energy waste caused by non-uniform heat sources in three-dimensional integrated chips. Through the "homogeneous heat dissipation" layered design and the "interconnection" integration process, uniform heat conduction, efficient heat dissipation and electrical interconnection between the upper and lower layers of the three-dimensional chip are achieved.

[0028] The active cooling core CC includes a microchannel layer 100, which serves as the core carrier for heat dissipation. At least one set of microfluidic grooves A are formed in the microchannel layer 100 for the flow of cooling fluids, such as deionized water or fluorinated liquid, to remove heat. An interconnection region D is provided on the microchannel layer 100, which is used to prepare an electrical interconnection structure.

[0029] The interconnection area D is located within the microfluidic channel A area or between microfluidic channels A. Furthermore, the location of the interconnection area D has been optimized for spatial compatibility, and it can be flexibly located within the microfluidic channel A area, such as the reserved area on the side wall or bottom of the channel, or in the gap area between microfluidic channels A, which avoids occupying extra space and ensures that the subsequent interconnection structure and heat dissipation channel do not interfere with each other.

[0030] The first interconnect unit 200, namely the through silicon via (TSV), is responsible for transmitting electrical signals. The first interconnect unit 200 is located in the interconnect area D and is vertically connected to the upper and lower surfaces of the microchannel layer 100 to realize cross-layer electrical interconnection.

[0031] The first interconnect unit 200 has a deformation zone B, which is a hollow metal structure. The hollow structure is filled with soft adhesive to relieve the thermal stress caused by the difference in thermal expansion coefficients between the first interconnect unit 200 and the microchannel layer 100, and to prevent structural cracking or electrical performance failure.

[0032] The electrical interconnect layer 300 is disposed on the lower surface of the microchannel layer 100. Its main function is to realize the electrical connection between the first interconnect unit 200 and the second interconnect unit 401, while avoiding electrical signal interference.

[0033] A thermal expansion layer 400 is disposed on the lower surface of the electrical interconnect layer 300. The thermal expansion layer 400 is made of diamond and can quickly distribute the local hot spot heat of the active chip to the entire microchannel layer 100, thereby alleviating local thermal stress concentration. A second interconnect unit 401 is disposed inside the thermal expansion layer 400. The second interconnect unit 401 connects the first interconnect unit 200 and the active chip, so as to realize the transmission of electrical signals from the active chip to the first interconnect unit 200. Preferably, the first interconnect unit 200 and the second interconnect unit 401 can be arranged coaxially to ensure the shortest electrical signal transmission path and reduce parasitic resistance.

[0034] Several sets of microfluidic channels A are interconnected, or several sets of microfluidic channels A are relatively independent.

[0035] Furthermore, a bonding preparation layer 301 and a first bonding layer 302 are sequentially deposited on the lower surface of the electrical interconnect layer 300. The bonding preparation layer 301 is made of silicon dioxide with a surface roughness of less than 0.5 nm to ensure bonding flatness. It mainly serves as insulation and transition, and is the basis for the epitaxial growth of the first bonding layer 302. A second bonding layer 402 is deposited on the top of the thermal expansion layer 400. The second bonding layer 402 is bonded to the first bonding layer 302. Both the first bonding layer 302 and the second bonding layer 402 are made of silicon dioxide with a thickness of 10 nm to 30 nm. This ensures bonding reliability, and the nanometer-level thickness also ensures thermal conductivity efficiency.

[0036] Furthermore, a first deposition hole D1 for preparing the first interconnect unit 200 is formed in the interconnect region D. The radial cross-sectional shape of the first deposition hole D1 is circular. The circular structure can make the subsequent coating thickness more uniform and reduce stress concentration points.

[0037] The first deposition hole D1 has an insulating layer, a barrier layer, and a first seed layer deposited sequentially from the hole wall toward the axis. The first interconnect unit 200 is formed by electrochemical deposition of the first seed layer. An interconnect hole 403 is formed in the thermal expansion layer 400. The aspect ratio of the interconnect hole 403 is adapted to the first deposition hole D1 and is compatible with existing etching processes. The second interconnect unit 401 is disposed in the interconnect hole 403. Its fabrication process is the same as that of the first interconnect unit 200 to ensure electrical performance and structural consistency.

[0038] Specifically, the insulating layer is preferably silicon dioxide or silicon nitride to achieve electrical insulation between the first interconnect unit 200 and the microchannel layer 100; the barrier layer is preferably TiN or TaN to prevent metal ions from diffusing and contaminating the silicon substrate; the first seed layer is preferably Cu or Au to provide a conductive substrate for subsequent electrochemical deposition; the first interconnect unit 200 is formed by growing the first seed layer through an electrochemical deposition process, which can ensure the density of metal filling and reduce interconnect resistance.

[0039] The prototype of the first interconnect unit 200 is a blind hole structure with one end open and the other end closed. A deformation zone B is formed inside the first interconnect unit 200 at the open end. Soft glue is then filled in to further optimize the stress buffering effect. After the first interconnect unit 200 is completed, it is a solid structure with both ends closed and the interior filled with soft glue. The deformation zone B is sealed inside the first interconnect unit 200.

[0040] The length of the first interconnect unit 200 is greater than the thickness of the microchannel layer 100. The first pad 201 is fixedly provided on the protruding end at its top. The protruding end design can ensure that the pad forms a stable connection with the surface of the microchannel layer 100, and at the same time facilitates docking with the upper active chip.

[0041] The microchannel layer 100 has a first pad 201 and a first soldering area 203 on its upper surface. The first pad 201 is used to transmit electrical signals, and the first soldering area 203 provides a large area of ​​metal contact for bonding the core to the upper active core structure, thereby reducing the bonding thermal resistance. An insulating ring 201a is provided between the first pad 201 and the first soldering area 203. The insulating ring 201a is an annular vacuum groove to prevent short circuits between the electrical signals and the bonding area.

[0042] The lower surface of the thermal expansion layer 400 is provided with a second pad 202 and a second soldering area 204. The second pad 202 is directly connected to the electrical signal interface of the active chip, and the second soldering area 204 is bonded to the heat dissipation area of ​​the active chip. Similarly, the second pad 202 and the second soldering area 204 are isolated by an insulating ring 201a.

[0043] The first pad 201 is fixed to the top of the first interconnect unit 200, and the second pad 202 is fixed to the bottom of the second interconnect unit 401. The top of the second interconnect unit 401 and the bottom of the first interconnect unit 200 are connected through the internal circuit of the electrical interconnect layer 300, forming a complete electrical interconnect path of "second pad 202 - second interconnect unit 401 - electrical interconnect layer 300 - first interconnect unit 200 - first pad 201". At the same time, heat can be efficiently dissipated through the path of "active core particle - second soldering area 204 - thermal expansion layer 400 - second bonding layer 402 - first bonding layer 301 - electrical interconnect layer 300 - microchannel layer 100 - microfluidic groove A", realizing the separation of "electrical-thermal" paths and that they do not interfere with each other.

[0044] The surface of the first pad 201 is flush with the surface of the first welding area 203, and the surface of the second pad 202 is flush with the surface of the second welding area 204. The flush design can ensure uniform force during bonding and avoid bonding voids or poor contact caused by height differences.

[0045] The first welding zone 203 has a fluid inlet and outlet at the corresponding position of the microfluidic tank A. The fluid inlet and outlet are precisely connected to the microfluidic tank A to ensure smooth flow of cooling fluid.

[0046] An insulating medium E is provided between the first welding area 203 and the microchannel layer 100. The insulating medium E is also provided between the thermal expansion layer 400 and the second welding area 204. The insulating medium E is preferably silicon dioxide. The insulating medium E can further enhance the electrical insulation between the welding area and the microchannel layer 100 and the thermal expansion layer 400, and at the same time improve the structural stability of the welding area.

[0047] The thickness of the first interconnect unit 200 on one side is β, and the aperture of the deformation region B is α. The ratio of β to α ranges from 1:10 to 2:5. This ratio range has been optimized through mechanical and electrical simulations: it ensures that the first interconnect unit 200 has a small integrated resistance to support the electrical interconnection function, and it also ensures that the deformation region B has sufficient space to buffer thermal stress, avoiding insufficient buffering due to an excessively small ratio or structural fragility due to an excessively large ratio.

[0048] The thickness of the insulating ring 201a on one side is φ, and the outer diameter of the first pad 201 and the second pad 202 is γ. The ratio of φ to γ ​​is in the range of 1:10 to 3:10. This ratio can minimize the space occupied by the insulating ring 201a while ensuring the insulation effect, so as to reserve a larger area for the welding area and reduce the bonding thermal resistance.

[0049] Example 2

[0050] Reference Figures 1 to 22This is the second embodiment of the present invention. Unlike the first embodiment, this embodiment provides a method for preparing homogenized active cooling core particles (CC). This method is designed around "layered preparation, precise bonding, and homogenization-interconnection synergy," taking into account both process compatibility and performance stability. Specifically, it includes the following steps: Photoresist is spin-coated onto the surface of the first silicon wafer. After a standard photolithography process (including photoresist coating, pre-baking, exposure, development, and post-baking) and deep silicon etching, a microfluidic groove A with a preset pattern is formed on the first silicon wafer. After etching, a special photoresist remover solution is used to remove the remaining photoresist to ensure that there are no residual impurities on the inner wall of the microfluidic groove A, so as to avoid affecting the subsequent cooling fluid flow or bonding quality.

[0051] Among them, the first silicon wafer region outside the microfluidic trench A forms the bonding region Q. The bonding region Q is reserved for the subsequent fabrication of the first interconnect unit 200 (TSV). Its area and position need to be planned in advance according to the layout of the microfluidic trench A and the electrical interconnection requirements.

[0052] It should be noted that the area of ​​interconnect region D is smaller than the area of ​​bonding region Q. Interconnect region D is the area where the first interconnect unit 200 is located, and bonding region Q is the area where the first silicon wafer and the second silicon wafer are bonded. Therefore, the area of ​​bonding region Q is larger than that of interconnect region D.

[0053] Surface activation is performed on the bonding region Q and the upper surface of the second silicon wafer (used to seal the microfluidic groove A to form a closed flow channel) to form the first activation region H1 and the second activation region H2 respectively. The first activation region H1 and the second activation region H2 are bonded together to seal and form a microchannel layer 100, thus avoiding the silicon dioxide buried layer formed in the traditional Si-Si direct bonding process.

[0054] Specifically, the first activation region H1 and the second activation region H2 are tightly bonded together through a bonding process to achieve the sealing of the microfluidic groove A and form a complete microchannel layer 100. The sealing effect directly affects whether the cooling fluid leaks, so the bonding process parameters must be strictly controlled to avoid voids.

[0055] It should be noted that, due to the use of the above-mentioned microchannel etching and bonding methods, the presence of buried silicon dioxide layers on the bonding surface can be avoided, which is beneficial for the etching of the first deposition hole D1 and the subsequent filling of the conductive metal layer.

[0056] The upper surface of the microchannel layer 100 is thinned by a combination of mechanical grinding and chemical polishing to achieve the design requirements for the thickness of the microchannel layer 100. In this embodiment, the thickness is preferably 150~400μm. The bonding region Q is etched using DRIE (deep silicon etching) process to form the first deposition hole D1. The etching process needs to control the etching rate and perpendicularity to ensure that the aspect ratio of the first deposition hole D1 meets the requirements of the subsequent coating.

[0057] An insulating layer, a barrier layer, and a first seed layer are deposited sequentially in the first deposition hole D1 using sputtering or PECVD (plasma-enhanced chemical vapor deposition) processes. The thickness of each layer needs to be precisely controlled to balance insulation, anti-diffusion, and conductivity. Electrochemical deposition is then performed based on the first seed layer to grow and form the first interconnect unit 200. After deposition, the first interconnect unit 200 is filled with a soft adhesive. During the filling process, air bubbles must be avoided to ensure stress buffering effect.

[0058] After the soft adhesive is filled and cured, the upper surface of the microchannel layer 100 is thinned and polished using a chemical mechanical polishing (CMP) process to remove excess soft adhesive outside the deformation area until the insulating medium E is exposed. Then, a barrier layer and a second seed layer are deposited sequentially on the insulating layer on the upper surface of the microchannel layer 100. After electrochemical deposition of the second seed layer, chemical mechanical polishing is performed to make the surface flatness meet the bonding requirements (typically surface roughness <0.5nm). Subsequently, after patterning by a standard photolithography process, the first pad 201, the insulating ring 201a, and the first welding area 203 are etched. The pad pattern needs to match the active chip pads to be connected later. Fluid inlets and outlets are opened on the first welding area 203. The depth of the fluid inlets and outlets is etched to the position of the insulating layer without penetrating the microchannel layer 100 to form the chip preform M.

[0059] The carrier sheet is temporarily bonded to the upper surface of the first pad 201 using a temporary bonding method, providing mechanical strength support for the subsequent thinning of the lower surface of the microchannel layer 100. The lower surface of the microchannel layer 100 is thinned to a preset thickness, exposing the lower metal of the first interconnect unit 200. An electrical interconnect layer 300 is fabricated on the lower surface of the microchannel layer 100 using a damask or double damask process. The internal metal circuit material is the same as that of the first interconnect unit 200 to ensure electrical conductivity. A bonding preparation layer 301 is deposited on the lower surface of the electrical interconnect layer 300. The bonding preparation layer 301 is made of silicon dioxide and has a surface roughness of less than 0.5 nm. At the same time, a thermal expansion layer 400 is fabricated on the third silicon wafer (as a thermal expansion layer substrate) using an epitaxial growth process. The thermal expansion layer 400 is made of diamond and has a surface roughness of less than 0.8 nm.

[0060] In the temporary bonding method, thermally release adhesive or water-soluble adhesive is preferably used as the temporary bonding medium, and the carrier sheet is preferably made of glass or silicon wafer.

[0061] Furthermore, a first bonding layer 302 and a second bonding layer 402 are simultaneously prepared on the bottom surface of the bonding preparation layer 301 and the upper surface of the thermal expansion layer 400, respectively. Both the first bonding layer 302 and the second bonding layer 402 are silicon dioxide with a thickness of 10nm~30nm, prepared by sputtering process to ensure uniform thickness. The first bonding layer 302 and the second bonding layer 402 are surface activated. After bonding, the third silicon wafer is thinned and polished. The silicon material is gradually removed by mechanical polishing, thereby preserving the complete thermal expansion layer 400.

[0062] A mask is prepared on the lower surface of the thermal expansion layer 400. After a standard photolithography process, the hard mask is etched, and the thermal expansion layer 400 is etched according to the pattern formed by etching the hard mask, until the metal of the electrical interconnect layer 300 is exposed. Interconnect holes 403 are formed in the thermal expansion layer 400. The Si3N4 mask is used and prepared by chemical vapor deposition. The thickness is 50~100nm and the etching resistance is strong.

[0063] The specific steps for etching the thermal expansion layer 400 in the mask area are as follows: First, the mask is patterned using a standard photolithography process. Then, at least one of ICP etching technology or ultraviolet nanosecond laser method is used to etch the thermal expansion layer 400. Finally, the underlying silicon dioxide layer (the exposed portion of the bonding preparation layer 301) is etched using a dry etching method until the metal of the electrical interconnect layer 300 is exposed, forming interconnect holes 403.

[0064] An insulating layer (with the same material as the insulating layer in the first deposition hole D1), a barrier layer (with the same material as the barrier layer mentioned above), and a third seed layer (with the same material as the first seed layer and a thickness of 200~500nm) are deposited in the interconnect hole 403 using the same method as for the preparation of the first interconnect unit 200. The third seed layer is electrochemically deposited until it fills the interconnect hole 403 and forms the second interconnect unit 401. The preparation conditions are: copper methanesulfonate solution, current density 0.3~0.6ASD, deposition time 15~30min, and temperature 25℃, to ensure the compactness and conductivity of the second interconnect unit 401.

[0065] Parasitic copper is formed on the surface of thermally extended layer 400 after chemical mechanical polishing, grinding thinning, and electrochemical deposition to a final thickness of 200-500nm while ensuring a surface roughness of <0.5nm. The second pad 202, insulating ring 201a, and second welding area 204 are prepared using the same photolithography and etching process as the first pad 201, ensuring the consistency of the structure and size of the upper and lower pads for subsequent integration.

[0066] The carrier sheet is debonded by heating or dissolving the temporary bonding medium, and the fluid inlet and outlet in the first welding area 203 are further etched to the position where it connects with the microfluidic groove A in the microchannel layer 100. The etching depth is adjusted according to the thickness of the microchannel layer 100 to ensure unobstructed fluid flow, and finally a homogenized active cooling core CC is formed.

[0067] Specifically, in this embodiment, both the first and second silicon wafers are double-polished silicon wafers with a surface roughness of less than 0.5nm. The high flatness of the surface is the basis for ensuring that subsequent bonding is void-free and the microfluidic groove A is accurately sized.

[0068] The photoresist spin-coated on the surface of the first silicon wafer is AZ4620. This type of photoresist has high resolution and good etching resistance, making it suitable for the fine patterning of microfluidic trench A. The spin-coating speed of the spin coater is 2500 r / min, and the spin-coating time is 30 s. These parameters allow the photoresist thickness to be uniformly controlled within the range of 2~3 μm. After spin-coating, the photoresist is baked at 100℃ for 5 min to remove the solvent in the photoresist and enhance the adhesion between the photoresist and the silicon wafer. The designed microchannel structure pattern is exposed using a photolithography machine. The exposure dose needs to be adjusted according to the photoresist thickness. After exposure, development is performed to remove the photoresist in the unexposed areas, forming the pattern of microfluidic trench A.

[0069] Furthermore, the designed microchannel structure pattern is exposed and developed using a photolithography machine, and then heated to 110°C and held for 5 minutes to further enhance the etching resistance of the photoresist.

[0070] Microchannels are etched using deep silicon etching, with a depth range of 50~300μm. The specific depth needs to be determined based on heat dissipation requirements: deeper etching is chosen when the heat flux density is high (to increase the channel volume), and shallower etching is chosen when the heat flux density is low (to reduce material consumption). After etching, acetone and isoacetone solutions are used for photoresist removal and cleaning. The two solutions can dissolve the photoresist matrix and residual small molecules respectively, ensuring thorough photoresist removal.

[0071] Specifically, the first activation region H1 and the second activation region H2 are prepared using the following steps. The core of this process is to remove the surface oxide layer and impurities to form a highly active surface to achieve silica-free bonding: First, the etched first and second silicon wafers are ultrasonically cleaned sequentially for 10 minutes each with acetone, anhydrous ethanol, and deionized water, and then dried with nitrogen gas for later use. It should be noted that nitrogen gas must be used to dry the wafers after each cleaning step to avoid cross-contamination. Acetone is used to remove photoresist residue, anhydrous ethanol is used to remove acetone, and deionized water is used to remove water-soluble impurities, ultimately ensuring that there is no organic matter or particulate contamination on the surface of the silicon wafers.

[0072] Next, the cleaned first and second silicon wafers are placed on the fixtures inside the cavity. These fixtures are professional-grade and ensure the wafers are flat and securely fixed. The cavity is then sealed and evacuated to a vacuum level of 10. -6 The Pa level and high vacuum can prevent air molecules from forming voids at the bonding interface and prevent secondary oxidation of the surface.

[0073] Then, the bonding region of the first silicon wafer and the upper surface of the second silicon wafer are activated using an Ar ion beam for 180s to 420s. The Ar ion beam energy is 0.6 to 1keV. The Ar ions remove the natural oxide layer (silicon dioxide) on the surface of the silicon wafer through physical bombardment and form a fresh Si active layer on the surface, laying the foundation for subsequent bonding. The beam current and irradiation time must be matched: when the beam current is high, the time should be shortened to avoid excessive bombardment that would cause surface roughness; when the beam current is low, the time should be extended to ensure that the oxide layer is completely removed.

[0074] Finally, the first and second silicon wafers are bonded together by applying pressure from above and below using a bonding machine. The bonding time is 250 seconds and the bonding pressure is 0.6~1.2 MPa. The combination of pressure and time can promote the formation of Si-Si bonds, ensure the bonding strength, and at the same time avoid excessive pressure that could cause the silicon wafer to crack or the microfluidic channel A to deform. Thus, the bonding of the first and second silicon wafers is completed, forming the microchannel layer 100.

[0075] Furthermore, the first interconnect unit 200 is prepared by electrochemical deposition. The first interconnect unit 200 is made of metal, and the metal is at least one of Cu and Au. Cu has the advantages of high conductivity (low resistivity) and low cost, and is suitable for general electrical interconnection scenarios. Au has excellent corrosion resistance and reliability, and is suitable for high-requirement scenarios, such as automotive or aerospace chips.

[0076] Electrochemical deposition is performed on the first deposition hole D1 using an electroplating bath. The electrochemical deposition solution is copper methanesulfonate, which has the characteristics of high stability and low toxicity. The deposited Cu grains are fine and dense. The current density is 0.3~0.6 ASD. Too low a current density will result in slow deposition speed and low efficiency, while too high a current density will easily lead to rough coating and pinholes. The electrochemical deposition time is 15~30 minutes. The specific time is determined according to the depth, diameter and electroplating thickness of the first deposition hole D1 to ensure the density and conductivity of the metal in the first deposition hole D1. The temperature is 25℃ to avoid changes in solution composition or damage to the silicon wafer caused by high temperature.

[0077] After electrochemical deposition, the first interconnect unit 200 is annealed in a vacuum environment. The core purpose of annealing is to eliminate the internal stress generated during the deposition process and improve the density and conductivity of the coating. The specific steps are as follows: the silicon wafer is heated from room temperature to 400°C in a vacuum furnace at a slow heating rate of 5°C / min. The slow heating can avoid the additional stress caused by sudden temperature changes. After holding at 400°C for 30 to 90 minutes, it is allowed to cool naturally. The holding time needs to be adjusted according to the coating thickness. When the coating is thick, the holding time is extended to ensure that the stress is fully released. After the holding time is completed, it is allowed to cool naturally to room temperature to avoid stress re-accumulation caused by rapid cooling.

[0078] The deformation zone B is filled with a vacuum-assisted filling process to seal and fill it with a soft adhesive. The soft adhesive is one of the following: benzocyclobutene resin (BCB), polydimethylsiloxane (PDMS), and epoxy resin. BCB has excellent high temperature resistance and insulation properties, making it suitable for high-temperature service scenarios. PDMS has good elasticity and excellent stress buffering effect, making it suitable for scenarios with frequent thermal cycling. Epoxy resin has high bonding strength and low cost, making it suitable for general scenarios.

[0079] The filling process consists of three steps: First, the adhesion promoter AP3000 is filled into the deformation zone B through a 2-minute vacuum treatment to enhance the bonding force between the soft adhesive and the metal. The vacuum environment ensures that the promoter fully penetrates to the bottom of the deformation zone B. Then, the adhesive is spin-coated at 500 rpm for 6 seconds and 3000 rpm for 40 seconds on a spin coater, and then baked at 95°C for 10 minutes to form a thin adhesion promoter layer. Baking removes the solvent in the promoter.

[0080] Then, in a vacuum chamber, the flexible adhesive is filled into the deformation zone B of the metal in the through-silicon via. The vacuum environment can prevent air bubbles from entering. The initially thick flexible adhesive layer is thinned and smoothed by spin coating at 500 rpm for 6 seconds and at 1000 rpm for 40 seconds, ensuring that the flexible adhesive fills the deformation zone B evenly.

[0081] Finally, the flexible adhesive is cured in a nitrogen environment at 250℃ for 60-120 minutes. The nitrogen environment can prevent the flexible adhesive from oxidizing. The curing time needs to be adjusted according to the type of flexible adhesive to ensure complete curing and to exert a stress buffering effect.

[0082] Furthermore, during the process of depositing the insulating layer in the first deposition hole D1, by controlling the sputtering angle and range, the insulating layer covers the upper surface of the microchannel layer 100 to form the insulating medium E. This design can reduce a separate process of depositing the insulating medium E, simplify the process flow, and at the same time ensure the continuity and consistency of the insulating layer.

[0083] Specifically, the first pad 201 and the first welding area 203 are prepared by the following method: a second seed layer is further sputtered on the upper surface of the insulating medium E. The second seed layer grows and completely covers the surface of the insulating medium E and communicates with the metal in the first deposition hole D1. The metal layer formed after electrochemical deposition is thinned by chemical mechanical polishing to a final thickness of 200-500 nm and the surface roughness is ensured to be <0.5 nm. Subsequently, an insulating ring 201a is coaxially formed at the corresponding position of the first deposition hole D1 by photolithography and etching processes. The insulating ring 201a is an annular vacuum groove. The metal area inside the insulating ring 201a is defined as the first pad 201, and the metal area outside the insulating ring 201a is defined as the first welding area 203. The insulating ring 201a makes the first pad 201 insulated from the external vacuum.

[0084] After thinning the lower surface of the microchannel layer 100 to expose the metal at the lower end of the first interconnect unit 200, the electrical interconnect layer 300 is prepared by damask or double damask process.

[0085] The first bonding layer 302 and the second bonding layer 402 are bonded by the following process: In a high-cleanliness vacuum environment, a layer of silicon dioxide is sputtered on the bottom surface of the bonding preparation layer 301 and the upper surface of the heat transfer layer to form the first bonding layer 302 and the second bonding layer 402, respectively. Then, the core blank M with the second bonding layer 402 and the thermal expansion layer 400 are placed on a fixture inside the cavity, the cavity is sealed, and the cavity is evacuated to a vacuum level of 10. -7 The process involves applying pressure to the top of the second bonding layer 402 and the bottom of the first bonding layer 302 using an Ar ion beam. The irradiation time is 300s to 500s, and the Ar ion beam energy is 0.8 to 1.2keV. Finally, the core preform and the heat transfer layer are bonded together under pressure. The bonding time is 400 to 800s, and the bonding pressure is 1.4 to 2.5MPa. This completes the bonding of the thermal expansion layer 400 and the electrical interconnect layer 300.

[0086] Furthermore, interconnect holes 403 are etched on the lower surface of the thermal expansion layer 400 using photolithography and etching processes. The interconnect holes 403 can be coaxially or misaligned with the first deposition hole D1. A third seed layer is deposited on the insulating dielectric E surface of the lower surface of the electrical interconnect layer 300. The third seed layer on the lower surface is electrochemically deposited. The third seed layer grows and fills the interconnect holes 403, then passes through the interconnect holes 403 and extends to cover the insulating dielectric E surface of the lower surface. The parasitic copper formed on the surface of the thermal expansion layer after electrochemical deposition is thinned using chemical mechanical polishing to a final thickness of 200-500 nm and ensuring a surface roughness of <0.5 nm. The second pad 202, insulating ring 201a, and second soldering area 204 are prepared using the same photolithography and etching processes as the preparation of the first pad 201, ensuring the consistency of the upper and lower pad structures and dimensions to adapt to subsequent integration.

[0087] Before the second and third seed layers completely cover the upper surface of the microchannel layer 100 and the lower surface of the thermal expansion layer 400, a barrier layer is sputtered on the upper and lower surfaces of the microchannel layer 100 using magnetron sputtering. The barrier layer is used to enhance the bonding force between the first seed layer and the insulating medium E, prevent the seed layer from falling off during subsequent processes or service, and prevent Cu atoms from diffusing into the silicon layer during high-temperature processing or high-temperature applications.

[0088] The barrier layer is made of at least one of Cr and Ti, with a thickness of 20-30 nm. Cr has strong adhesion to silicon and the insulating layer, while Ti has excellent anti-diffusion properties. If the thickness is too thin, the adhesion will be insufficient, while if it is too thick, it may affect the conductivity or increase the thermal resistance. The second and third seed layers covering the upper and lower surfaces of the microchannel layer 100 are made of at least one of Cu and Au, with a thickness of 200-500 nm. This thickness can ensure that the conductivity of the seed layer meets the requirements of electrochemical deposition, while avoiding surface flatness problems caused by excessive thickness.

[0089] The remaining structure is the same as that in Example 1.

[0090] Example 3

[0091] Reference Figures 1 to 22 This is the third embodiment of the present invention. This embodiment differs from the second embodiment in that it provides a packaging method for a vapor chamber active cooling chip and a three-dimensional integrated chip. This method focuses on "low-resistance bonding, high-efficiency integration, and heat dissipation-electrical interconnection synergy." Its core is to integrate the vapor chamber active cooling chip CC and the active chip 500 through a standardized interface. It includes the aforementioned vapor chamber active cooling chip CC and its preparation method, and further includes the following steps:

[0092] The first pad 201 and the second pad 202 are bonded and integrated with the fluid pads and electrical signal interface pads of the active core 500 to be dissipated on the upper and lower layers respectively by the high vacuum surface activation bonding method.

[0093] Specifically, the high vacuum environment can prevent voids from forming at the bonding interface and improve the vacuum insulation of the insulating ring 201a. The surface activation treatment can remove the oxide layer and impurities on the surface of the pads, ensuring direct metal-to-metal bonding and significantly reducing bonding resistance and thermal resistance.

[0094] Furthermore, during bonding, it is necessary to ensure that the first pad 201 is precisely aligned with the electrical signal interface pad of the active core 500 (to achieve electrical interconnection), the first soldering area 203 is aligned with the fluid pad and mechanical support pad of the active core 500 (to ensure unobstructed cooling fluid pathways), the second pad 202 is aligned with the electrical signal interface pad of the lower active core 500, and the second soldering area 204 is aligned with the mechanical support pad of the lower active core 500, ultimately forming a three-dimensional stacked structure of "active core - heat dissipation active cooling core - active core", achieving coordinated heat dissipation and electrical interconnection of multiple cores.

[0095] The remaining structure is the same as that in Example 2.

[0096] Finally, it should be noted that the methods and devices described in detail above are merely embodiments, and those skilled in the art can modify these embodiments in different ways as long as they do not depart from the scope of the present invention.

Claims

1. A homogenizing active cooling core (CC), characterized in that: include, A microchannel layer (100) is provided therein, which has a microfluidic groove (A) and a first interconnection unit (200), and a deformation region (B) is provided in the first interconnection unit (200); An electrical interconnect layer (300) is disposed on the lower surface of the microchannel layer (100); A thermal expansion layer (400) is disposed on the lower surface of the electrical interconnect layer (300), and a second interconnect unit (401) is disposed inside the thermal expansion layer (400). The second interconnect unit (401) connects the first interconnect unit (200) and the active chip.

2. The heat-equalizing active cooling core according to claim 1, characterized in that: The lower surface of the electrical interconnect layer (300) is sequentially deposited with a bonding preparation layer (301) and a first bonding layer (302), and the top of the thermal expansion layer (400) is deposited with a second bonding layer (402), which is bonded to the first bonding layer (302).

3. The homogenizing active cooling core according to claim 1 or 2, characterized in that: The thermal expansion layer (400) has an interconnect hole (403) and the second interconnect unit (401) is disposed in the interconnect hole (403).

4. The homogenizing active cooling core according to claim 1 or 2, characterized in that: The microchannel layer (100) has a first pad (201) and a first welding area (203) on its upper surface, and an insulating ring (201a) is provided between the first pad (201) and the first welding area (203). The lower surface of the thermal expansion layer (400) is provided with a second pad (202) and a second welding area (204), and the insulating ring (201a) isolates the second pad (202) and the second welding area (204). The first pad (201) is fixed to the top of the first interconnect unit (200), and the second pad (202) is fixed to the bottom of the second interconnect unit (401).

5. The heat-equalizing active cooling core particle according to claim 4, characterized in that: The top of the second interconnect unit (401) is connected to the bottom of the first interconnect unit (200) through the internal wiring of the electrical interconnect layer (300).

6. The homogenizing active cooling core according to any one of claims 1, 2 and 5, characterized in that: The first interconnection unit (200) and the second interconnection unit (401) are coaxially arranged; Alternatively, the first interconnection unit (200) and the second interconnection unit (401) may be misaligned.

7. The homogenizing active cooling core according to claim 5, characterized in that: The first welding area (203) has a fluid inlet and outlet at the corresponding position of the microfluidic channel (A).

8. A method for preparing a homogenized active cooling core (CC), characterized in that: Includes the following steps, Photoresist is spin-coated onto the upper surface of the first silicon wafer. After standard photolithography and deep silicon etching, a microfluidic trench (A) is formed on the first silicon wafer, and the remaining photoresist is removed. The first silicon wafer region outside the microfluidic groove (A) forms a bonding region (Q); Surface activation is performed on the bonding region (Q) and the upper surface of the second silicon wafer to form a first activation region (H1) and a second activation region (H2) respectively. The first activation region (H1) and the second activation region (H2) are bonded together and sealed to form a microchannel layer (100). The upper surface of the microchannel layer (100) is thinned, the bonding region (Q) is etched and a first deposition hole (D1) is formed; an insulating layer, a barrier layer and a first seed layer are deposited in the first deposition hole (D1) in sequence, electrochemical deposition is performed, and an annealing process is performed to form the first interconnect unit (200). The first interconnect unit (200) is filled with soft adhesive and chemically mechanically polished to the insulating layer. A barrier layer and a second seed layer are deposited sequentially on the insulating layer on the upper surface of the microchannel layer (100). After electrochemical deposition of the second seed layer, chemical mechanical polishing is performed, and after patterning by standard photolithography, the first pad (201), the insulating ring (201a), and the first welding area (203) are etched. A fluid inlet and outlet are opened on the first welding area (203), and the depth of the fluid inlet and outlet is etched to the position of the insulating layer to form a core preform (M). The carrier sheet is temporarily bonded to the upper surface of the first pad (201) by a temporary bonding method, and the lower surface of the microchannel layer (100) is thinned to expose the metal at the lower end of the first interconnect unit (200). An electrical interconnect layer (300) is prepared on the lower surface of the microchannel layer (100), and a bonding preparation layer (301) is deposited on the lower surface of the electrical interconnect layer (300). At the same time, a thermal expansion layer (400) is epitaxially grown on the third silicon wafer. A first bonding layer (302) and a second bonding layer (402) are simultaneously prepared on the bonding preparation layer (301) and the thermal expansion layer (400), respectively. After surface activation, they are bonded together. The third silicon wafer is then thinned and ground to completely remove the bonding layer. A hard mask is prepared on the lower surface of the thermal expansion layer (400), and the hard mask is etched after a standard photolithography process. The thermal expansion layer (400) is etched according to the pattern formed by etching the hard mask until the metal of the electrical interconnect layer (300) is exposed, and interconnect holes (403) are formed in the thermal expansion layer (400). An insulating layer, a barrier layer and a third seed layer are deposited in the interconnect hole (403) using the same method as the preparation of the first pad (201). The third seed layer is electrochemically deposited until it fills the interconnect hole (403) and forms the second interconnect unit (401). The lower end face of the deposited second interconnect unit (401) is thinned by chemical mechanical polishing, and a second pad (202), an insulating ring (201a), and a second welding area (204) are prepared. Debond the carrier sheet and etch the fluid inlet and outlet in the first welding area (203) to the position where it communicates with the microfluidic groove (A) in the microchannel layer (100) to form a homogenized active cooling core (CC).

9. The method for preparing the homogenized active cooling core according to claim 8, characterized in that: The bonding preparation layer (301) is made of silicon dioxide and has a surface roughness of less than 0.5 nm. The thermal expansion layer (400) is made of diamond and has a surface roughness of less than 0.8 nm.

10. The method for preparing the homogenized active cooling core according to claim 8 or 9, characterized in that: The first bonding layer (302) and the second bonding layer (402) are made of silicon dioxide and have a thickness of 10nm~30nm.

11. The method for preparing homogenized active cooling core particles according to claim 10, characterized in that: When preparing the interconnect hole (403), Si3N4 is deposited on the surface of the thermal expansion layer (400) by chemical vapor deposition. Then, after patterning by standard photolithography, Si3N4 is etched by dry etching technology to transfer the pattern to the Si3N4 layer. After removing the resist, Si3N4 is used as the etching mask of the thermal expansion layer (400). The thermally extended layer (400) is etched using at least one of ICP etching technology or ultraviolet nanosecond laser method, and the silicon dioxide layer is etched to the interconnect metal exposure using dry etching method to form the interconnect hole (403).

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