Power semiconductor package including stacked FET dies and method of manufacturing the same

Abstract

A power semiconductor package includes: a power electronics substrate including a first side and an opposing second side; a first FET die including a first side and an opposing second side, the first FET die being disposed on the power electronics substrate; a second FET die including a first side and an opposing second side, the second FET die being disposed on top of the first side of the first FET die; a first conductive layer disposed between the first FET die and the second FET die and electrically connecting the first FET die and the second FET die to each other; an encapsulation body encapsulating the first FET die and the second FET die; a first metal clip including a first portion and a second portion; and a first connector electrically connecting a control electrode on the first side of the first FET die to the first metal clip.

Description

Technical Field

[0001] This disclosure relates to power semiconductor packaging, and more particularly to a power semiconductor package and a method for manufacturing such a power semiconductor package, said power semiconductor package comprising a first field-effect transistor die and a second field-effect transistor die stacked on top of each other. Background Technology

[0002] Power semiconductor packages can be configured to operate with high currents (e.g., up to 500 A or even higher) and / or high voltages (e.g., up to 1200 V or even higher). A power semiconductor package can, for example, be a discrete power device configured to block high voltages and / or conduct high currents between two load electrodes provided by external contacts of the power semiconductor package. Such devices can be configured for use in many different automotive, industrial, and domestic applications. A specific application of such devices is the main inverter for electric motors. The electrical performance characteristics of such devices can depend on the size of the power transistor chip or die implemented within the device. However, larger dies also increase the overall cost of such power semiconductor packages, thus potentially limiting the expected cost for a given performance level or die coverage area. Improved power semiconductor packages, and improved methods for manufacturing them, can help address these and other issues. Summary of the Invention

[0003] Various aspects relate to a power semiconductor package, including: a power electronic substrate, the power electronic substrate including a first side and an opposing second side; a first FET die, the first FET die including a first side and an opposing second side, the first FET die being disposed on the power electronic substrate such that the first side of the first FET die faces away from the power electronic substrate and the second side of the first FET die faces the first side of the power electronic substrate; a second FET die, the second FET die including a first side and an opposing second side, the second FET die being disposed on top of the first side of the first FET die such that the second side of the second FET die faces the first FET die; a first conductive layer, the first... A conductive layer is disposed between the first FET die and the second FET die and electrically connects the first FET die and the second FET die to each other; an encapsulation body encapsulates the first FET die and the second FET die; a first metal clip includes a first portion and a second portion, wherein the first portion is disposed on a first side of the second FET die and electrically connected to a first power electrode on the first side of the second FET die, and wherein the second portion is laterally disposed beside the first FET die and the second FET die; and a first connector electrically connects a control electrode on the first side of the first FET die to the first metal clip.

[0004] Various aspects relate to a method for manufacturing a power semiconductor package, the method comprising: providing a power electronic substrate, the power electronic substrate including a first side and an opposing second side; disposing a first field-effect transistor (FET) die including the first side and the opposing second side on the power electronic substrate, such that the first side of the first FET die faces away from the power electronic substrate and the second side of the first FET die faces the first side of the power electronic substrate; disposing a second FET die including the first side and the opposing second side on top of the first side of the first FET die, such that the second side of the second FET die faces the first FET die; and disposing a second FET die between the first FET die and the first... A first conductive layer is disposed between two FET dies, thereby electrically connecting the first FET die and the second FET die to each other; the first FET die and the second FET die are encapsulated by an encapsulation body; a first metal clip including a first portion and a second portion is provided; the first portion of the first metal clip is disposed on a first side of the second FET die and electrically connected to a first power electrode on the first side of the second FET die, and the second portion is disposed laterally next to the first FET die and the second FET die; and a first connector is used to electrically connect a control electrode on the first side of the first FET die to the first metal clip.

[0005] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and examining the accompanying drawings. Attached Figure Description

[0006] The present disclosure is illustrated in the accompanying drawings by way of example and not limitation, wherein the same reference numerals refer to similar or identical elements. Elements in the drawings are not necessarily drawn to scale relative to each other. Features of various illustrated examples can be combined unless mutually exclusive.

[0007] Figure 1A and Figure 1B Plan view and cross-sectional view of an exemplary power semiconductor package are shown, the power semiconductor package including a first FET die and a second FET die stacked on top of each other and electrically connected to each other.

[0008] Figure 2 It shows that it can be used Figure 1A and Figure 1B An exemplary common-emitter common-base circuit / common-source common-gate circuit implemented using a semiconductor package.

[0009] Figure 3A plan view of another exemplary power semiconductor package is shown, including a first FET die through a fourth FET die, wherein the first FET die and the third FET die, as well as the second FET die and the fourth FET die, are connected in parallel.

[0010] Figure 4 A plan view of another exemplary semiconductor package is shown, which is related to... Figure 3 Similar to power semiconductor packaging, but in which the control electrodes of the first FET die and the third FET die are aligned with... Figure 3 In power semiconductor packages, they are connected to metal clips in different ways.

[0011] Figure 5 A plan view of another exemplary semiconductor package is shown, in which the stacked body of FET dies is aligned with... Figure 3 Different arrangements in power semiconductor packages.

[0012] Figure 6 A cross-sectional view of another exemplary power semiconductor package is shown, wherein a metal clip is coupled to a substrate portion, and wherein the substrate portion is exposed from the encapsulation body to provide external contacts for the power semiconductor package.

[0013] Figure 7 A plan view of another exemplary power semiconductor package is shown, wherein the connector that connects the control electrodes of the first FET die and the third FET die to the metal clip is part of the metal clip itself.

[0014] Figure 8 This is a flowchart of an exemplary method for manufacturing a power semiconductor package. Detailed Implementation

[0015] In the following detailed description, known structures and elements are illustrated schematically to facilitate the description of one or more aspects of this disclosure. For this purpose, directional terms such as “top,” “bottom,” “left,” “right,” “upper,” and “lower” are used with reference to the orientation of the described figures. Because the components of this disclosure can be positioned in a variety of different orientations, directional terms are used only for illustrative purposes. It should be understood that other examples can be utilized, and structural or logical changes can be made.

[0016] Additionally, while specific features or aspects may be disclosed with respect to only one of several embodiments, such features or aspects may be combined with one or more other features or aspects of other embodiments as may be desired and advantageous for any given or particular application, unless otherwise specifically indicated or unless technically limited. Furthermore, to the extent that the terms “include,” “have,” “with,” or other variations thereof are used in the detailed description or claims, such terms are intended to be inclusive rather than encompassing, similar to the term “comprise.” The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical or electrical contact, or whether they are not in direct contact with each other; intermediate elements or layers may be provided between elements that are “bonded,” “attached,” or “connected.” However, elements that are “bonded,” “attached,” or “connected” may also be in direct contact with each other. Furthermore, the term “exemplary” is intended only as an example and not as best or optimal.

[0017] A semiconductor die may have contact pads (or electrodes) that allow electrical contact with an integrated circuit included in the semiconductor die. Electrodes may be disposed on two main surfaces of the semiconductor die. They may include one or more electrode metal layers of semiconductor material applied to the semiconductor die. The electrode metal layers may be fabricated to have any desired geometry and any desired material composition. For example, they may include materials selected from or in the group consisting of: Cu, Ni, NiSn, Au, Ag, Pt, Pd, alloys of one or more of these metals, conductive organic materials, or conductive semiconductor materials.

[0018] In several examples, layers or stacks of layers are applied to each other or materials are applied to or deposited onto the layers. It should be understood that any such terms “applied” or “deposited” are intended to encompass all kinds and techniques of applying layers to each other. In particular, they are intended to cover techniques that apply layers as a whole at once (e.g., lamination) as well as techniques that deposit layers in a sequential manner (e.g., sputtering, coating, molding, CVD, etc.).

[0019] High-efficiency power semiconductor packaging and efficient methods for manufacturing power semiconductor packages can, for example, reduce material consumption, ohmic losses, chemical waste, etc., and thus achieve energy and / or resource savings. As specified in this specification, improved power semiconductor packaging and improved methods for manufacturing power semiconductor packages can therefore at least indirectly contribute to green technology solutions, i.e., provide climate-friendly solutions that mitigate energy and / or resource use.

[0020] Figure 1AA plan view of the power semiconductor package 100 is shown, and Figure 1B The power semiconductor package 100 is shown along... Figure 1A The cross-sectional view of line A-A' in the diagram. The power semiconductor package 100 includes a power electronic substrate 110, a first field-effect transistor (FET) die 120, a second FET die 130, a first conductive layer 140, an encapsulation body 150, a first metal clip 160, and a first connector 170.

[0021] The power semiconductor package 100 can be configured as a discrete power device. A discrete power device is a single packaged device configured to block high voltages and / or conduct high currents between two load electrodes. For example, the power semiconductor package 100 can be configured to operate at voltages of 100 V or higher, or 250 V or higher, or 600 V or higher, or 1.2 kV or higher. The power semiconductor package 100 can, for example, be configured to conduct currents of 10 A or greater, or 50 A or greater, or 100 A or greater, or 500 A or greater.

[0022] The power semiconductor package 100 can be configured for any suitable application, such as automotive, industrial, or residential applications. According to a specific example, the power semiconductor package 100 can be part of the main inverter for an electric motor (e.g., the electric motor of an electric vehicle). For example, multiple power semiconductor packages 100 can be electrically connected in three half-bridges to provide three-phase power for the electric motor.

[0023] The power electronics substrate 110 includes a first side 111 and an opposing second side 112. The power electronics substrate 110 can be any suitable type of substrate, such as direct-bonded copper (DBC), direct-bonded aluminum (DBA), active metal brazing (AMB), insulated metal substrate (IMS), leadframe, etc. Figure 1A and Figure 1B In the example shown, the power electronics substrate 110 includes a single pad on which the first FET die 120 and the second FET die 130 are disposed. However, the power electronics substrate 110 may also include multiple pads. For example, the first FET die 120 and the second FET die 130 may be disposed on one of the pads, and one or more additional pads may be configured as external power contacts of the power semiconductor package 100.

[0024] The first FET die 120 includes a first side 121 and an opposing second side 122. Furthermore, the first FET die 120 is disposed on a power electronics substrate 110 such that the first side 121 of the first FET die 120 faces away from the power electronics substrate 110, and the second side 122 of the first FET die 120 faces the first side 111 of the power electronics substrate 110.

[0025] The first FET die 120 can have any suitable size. The first FET die 120 can include or be composed of any suitable semiconductor material. For example, the first FET die 120 can include or be composed of Si, SiC, or GaN as an active semiconductor material. The first FET die 120 can include a first power electrode disposed on a first side 121 and a second power electrode disposed on a second side 122. Figure 1A and Figure 1B (Not shown in the image). The first power electrode can be, for example, a drain electrode or an emitter electrode, and the second power electrode can be a source electrode or a collector electrode. According to another example, the first power electrode can be a source electrode or a collector electrode, and the second power electrode can be a drain electrode or an emitter electrode.

[0026] Furthermore, the first FET die 120 includes a control electrode 120-1, such as a gate electrode, disposed on a first side 121. The control electrode 120-1 is electrically connected to a first metal clip 160 via a first connector 170. Figure 1A In the example shown, the first connector 170 is a bonding wire. However, the first connector 170 could also be a contact clip, band, or portion (finger) of the first metal clip 160 itself.

[0027] The second FET die 130 includes a first side 131 and an opposing second side 132. Furthermore, the second FET die 130 is disposed on top of the first side 121 of the first FET die 120, such that the second side 132 of the second FET die 130 faces the first FET die 120. The second FET die 130 may, for example, comprise or be composed of any semiconductor material mentioned above with respect to the first FET die 120. According to a specific example, the first FET die 120 is a wide-bandgap semiconductor material, specifically, but not limited to, a SiC or GaN die, and the second FET die 130 is a Si die. Specifically, the first FET die 120 may be a depletion-mode FET, and the second FET die 130 may be an enhancement-mode MOSSEF. The first FET die 120 and the second FET die 130 may be connected in a cascode configuration, as described above. Figure 2 The explanation given.

[0028] The second FET die 130 may include a first power electrode, a second power electrode, and a control electrode in the same manner as explained above regarding the first FET die 120. Specifically, the second power electrode on the second side 122 of the first FET die 120 may be electrically connected to the power electronics substrate 110, the first power electrode on the first side 121 of the first FET die 120 may be electrically connected to the second power electrode of the second FET die 130, and the first power electrode of the second FET die 130 may be electrically connected to the first metal clip 160.

[0029] A first conductive layer 140 is disposed between the first FET die 120 and the second FET die 130, particularly between the first side 121 of the first FET die 120 and the second side 132 of the second FET die 130. Furthermore, the first conductive layer 140 electrically connects the first FET die 120 and the second FET die 130 to each other.

[0030] The first conductive layer 140 may include or be composed of any suitable conductive material. For example, the first conductive layer 140 may include or be composed of a solder layer, a sintered layer, or a conductive adhesive layer. According to an example, the power semiconductor package 100 may include one or more additional conductive layers. For example, additional conductive layers may be present between the first FET die 120 and the power electronics substrate 110 and / or between the second FET die 130 and the first metal clip 160. The one or more additional conductive layers may include or be composed of the same material as the first conductive layer 140.

[0031] like Figure 1A and Figure 1B As shown in the example, when viewed from above the first side 131 of the second FET die 130, the second FET die 130 may have a smaller coverage area than the first FET die 120. The first conductive layer 140 may completely or almost completely cover the second side 132 of the second FET die 130 (particularly the second power electrode disposed on the second side 132).

[0032] Encapsulation body 150 encapsulates the first FET die 120 and the second FET die 130. Encapsulation body 150 may also at least partially cover the power electronics substrate 110 and the first metal clip 160. For example... Figure 1B As shown, the second side 112 of the power electronics substrate 110 may be at least partially exposed from the encapsulation body 150, for example, to couple the second side 112 to a heat sink.

[0033] According to the example, the encapsulation body 150 includes or is composed of a molded body. Such a molded body can be manufactured using any suitable molding technique, such as compression molding, injection molding, or transfer molding. According to another example, the encapsulation body 150 includes or is composed of a plastic frame encapsulating an internal volume, wherein a first FET die 120 and a second FET die 130 are arranged within the internal volume, and wherein the internal volume is at least partially filled with potting material.

[0034] The encapsulation body 150 may have a first side 151, an opposing second side 152, and a lateral side 153 connecting the first side 151 and the second side 152. The power semiconductor package 100 may have any suitable size and any suitable shape. For example, when viewed from above the first side 151 of the encapsulation body 150, the power semiconductor package 100 may have a substantially rectangular or square shape. A rectangular power semiconductor package 100 may, for example, have a longer side (e.g., about 43 mm) ranging from about 30 mm to about 50 mm and a shorter side (e.g., about 15 mm) ranging from about 10 mm to about 20 mm.

[0035] The first metal clip 160 includes a first portion 160-1 and a second portion 160-2, wherein the first portion 160-1 is disposed on a first side 131 of the second FET die 130, and wherein the second portion 160-2 is laterally disposed beside the first FET die 120 and the second FET die 130. Furthermore, the first portion 160-1 is electrically connected to a first power electrode on the first side 131 of the second FET die 130.

[0036] like Figure 1A and Figure 1B As shown, the first portion 160-1 and the second portion 160-2 may be parts of a monolithic unit (i.e., the first metal clip 160). The first metal clip 160 may include or be composed of any suitable metal or metal alloy, and may include or be composed of Al or Cu, for example. The first metal clip 160 may, for example, be deposited on the second FET die 130 as part of the clip frame, and fabricating the power semiconductor package 100 may include slicing the first metal clip 160 from the clip frame.

[0037] according to Figure 1A and Figure 1B In the example shown, the second portion 160-2 of the first metal clip is at least partially exposed from the encapsulation body 150 (in particular, from one of the sides 153 of the encapsulation body 150) to provide external contacts for the power semiconductor package 100. However, the second portion 160-2 may also be coupled to a portion of the power electronics substrate 110, and this substrate portion is exposed from the encapsulation body 150 and provides external contacts.

[0038] Figure 2 A common-emitter common-base / common-source common-gate circuit 200 can be implemented in a power semiconductor package 100 using a first FET die 120 and a second FET die 130. As described above, the first FET die 120 can be a depletion-mode FET die of the common-emitter common-base / common-source common-gate circuit 200, and the second FET die 130 can be an enhancement-mode FET die of the common-emitter common-base / common-source common-gate circuit 200, particularly a MOSFET die. The gate of the first FET die 120 can be connected to the source of the second FET die 130, particularly via a first connector 170, such as... Figure 1A As shown.

[0039] The common-emitter common-base circuit / common-source common-gate circuit 200 may include a source contact 201, a drain contact 202, and a gate contact 203 that can be exposed from the encapsulation body 150 of the power semiconductor package 100.

[0040] High-power applications typically have higher electrical performance requirements compared to low-power applications, such as maximum current and maximum voltage. These requirements may necessitate increasing the size of the power transistor die in devices rated for high-power applications, which in turn may increase the cost of such devices. A power semiconductor package 100 including a common-emitter / common-base circuit / common-source / common-gate circuit 200 can provide excellent electrical characteristics while requiring a relatively small die area. Specifically, compared to using only an enhancement-mode transistor die, when using the common-emitter / common-base circuit / common-source / common-gate circuit 200 in the power semiconductor package 100, the product R... DSon A might be better, for example, 30% or even 40% better, where R... DSon A is the resistance between the drain and source of the transistor when it is turned on, and A is the die area.

[0041] Figure 3 A plan view of another power semiconductor package 300 is shown, which may be similar to or the same as power semiconductor package 100, with the differences described below.

[0042] The power semiconductor package 300 includes all the components described with respect to the power semiconductor package 100, and the power semiconductor package 300 further includes a third FET die 310 and a fourth FET die 320.

[0043] Similar to the first FET die 120, the third FET die 310 includes a first side and an opposing second side. The third FET die 310 is disposed on the power electronics substrate 110 such that the first side of the third FET die 310 faces away from the power electronics substrate 110, and the second side of the third FET die 310 faces the first side 111 of the power electronics substrate 110. Furthermore, the third FET die 310 is laterally disposed on the power electronics substrate 110 next to the first FET die 120.

[0044] Similar to the second FET die 130, the fourth FET die 320 includes a first side and an opposing second side, wherein the fourth FET die 320 is disposed on top of the first side of the third FET die 310 such that the second side of the fourth FET die 320 faces the third FET die 310. Furthermore, a second conductive layer is disposed between the third FET die 310 and the fourth FET die 320, and electrically connects the third FET die 310 and the fourth FET die 320 to each other in a manner similar to that used to connect the first FET die 120 and the second FET die 130 via the first conductive layer 140.

[0045] The first FET die 120 and the third FET die 310 are connected in parallel via a power electronics substrate 110, and the second FET die 130 and the fourth FET die 320 are connected in parallel via a first metal clip 160. According to the example, both the first FET die 120 and the third FET die 310 are depletion-mode FET dies, and the second FET die 130 and the fourth FET die 320 are enhancement-mode FET dies of a common-emitter common-base circuit / common-source common-gate circuit 200.

[0046] According to the example, the power semiconductor package 300 may include additional FET dies connected in parallel with the first FET die 120 and the second FET die 130, respectively, in order to further improve the electrical characteristics of the power semiconductor package 300.

[0047] The third FET die 310 may be the same type of die as the first FET die 120, and the fourth FET die 320 may be the same type of die as the second FET die 130. Furthermore, the second conductive layer may have the same material and the same thickness as the first conductive layer.

[0048] According to the example, the power electronics substrate 110 of the power semiconductor package 300 includes a first conductive pad 110-1 and a second conductive pad 110-2, which are separated from each other by the dielectric material of the power electronics substrate 110 and / or the encapsulation body 150. First FET dies to fourth FET dies 120-120 are disposed on the first conductive pad 110-1, and a control electrode 130-1 on a first side 131 of a second FET die 130 is electrically connected to the second conductive pad 110-2 via a second connector 172. Similar to the first FET die 120, the control electrode of a third FET die 310 can be connected to a first metal clip 160 via a third connector 174, and similar to the second FET die 130, the control electrode of a fourth FET die 320 can be connected to the second conductive pad 110-2 via a fourth connector 176. The second, third, and fourth connectors 172-176 can be connectors of the same type as the first connector 170.

[0049] The first metal clip 160 of the power semiconductor package 300 spans the second conductive pad 110-2. This specifically means that the first metal clip 160 does not physically contact the second conductive pad 110-2, and there is no direct electrical connection between the first metal clip 160 and the second conductive pad 110-2 in the absence of an intermediate transistor.

[0050] The power semiconductor package 300 may include a first external contact 330, a second external contact 332, and a third external contact 334 exposed from the encapsulation body 150. For example... Figure 3 As shown in the specific example, the first external contact 330 and the third external contact 334 may be exposed from a first side of the side 153 of the encapsulation body 150, and the second external contact 332 may be exposed from the opposite second side of the side 153. The first external contact 330 and the second external contact 332 may be power contacts of the power semiconductor package 300, and the third external contact 334 may be a control contact, particularly a gate contact of the power semiconductor package 300. For example, the first external contact 330 may be a source contact, and the second external contact may be a drain contact of the power semiconductor package 300 (e.g., a drain contact of a common-emitter common-base circuit / cascode circuit 200). According to another example, the source and drain contacts are reversed.

[0051] The second external contact 332 can be connected to the power electrodes on the second side of the first FET die 120 and the third FET die 310 via the first conductive pad 110-1. The second external contact 332 may include or be composed of a second metal clip. The second metal clip may include a first portion and a second portion, wherein the first portion is disposed on the first side 111 of the power electronics substrate 110, and wherein the second portion is exposed from the encapsulation body 150.

[0052] like Figure 3 As shown, the third external contact 334 can be connected to the gate electrodes of the second FET die 130 and the fourth FET die 320. Specifically, the control electrode 130-1 of the second FET die 130 can be connected to the third external contact 334 via the second conductive pad 110-2. The third contact 334 may, for example, include or be composed of a third metal clip, which may, for example, be part of the same clip frame as the first metal clip 160.

[0053] Figure 4 A plan view of another power semiconductor package 400 is shown, which may be similar to or the same as power semiconductor package 300, with the differences described below.

[0054] Specifically, in power semiconductor package 300, the first connector 170 and the third connector 174 are attached to a first portion 160-1 of the first metal clip 160. Conversely, in power semiconductor package 400, the first connector 170 and the third connector 174 are attached to a second portion 160-2 of the first metal clip. Figure 4 As shown, the power semiconductor package 400 may include a fifth connector 178 that connects the second conductive pad 110-2 to the third external contact 334.

[0055] Figure 5 A plan view of another power semiconductor package 500 is shown, which may be similar to or the same as power semiconductor package 300 or 400, with the differences described below.

[0056] Specifically, in power semiconductor package 500, the stack of first FET die 120, second FET die 130, third FET die 310, and fourth FET die 320 is arranged along a direction perpendicular to the side 153 extending from its exposed first external contact 330. On the other hand, in power semiconductor packages 300 and 400, the stack of FET dies is arranged along a direction parallel to the side 153 extending from its exposed first external contact 330. Furthermore, the power electronics substrate 110 of power semiconductor package 500 does not necessarily include a second conductive pad 110-2. This specific arrangement of the FET die stack of power semiconductor package 500 makes it relatively simple to directly attach the second connector 172 and the fourth connector 176 to the third external contact 334 without requiring the use of a second conductive pad for redistribution purposes.

[0057] Figure 6A cross-sectional view of another power semiconductor package 600 is shown, which may be similar to or the same as any of power semiconductor packages 100 to 500, with the differences described below.

[0058] Specifically, in the power semiconductor package 600, the second portion 160-2 of the first metal clip 160 is not exposed from the encapsulation body 150 and does not form external contacts of the power semiconductor package 600. Instead, the second portion 160-2 is coupled to a substrate portion 114, which may be part of a power electronics substrate 110. The substrate portion 114 is exposed from the encapsulation body 150 and provides the first external contact 330.

[0059] Figure 7 A plan view of another power semiconductor package 700 is shown, which may be similar to or the same as any of the power semiconductor packages 100 to 600, with the differences described below.

[0060] Specifically, in the power semiconductor package 700, the first connector 170 and the third connector 174, which connect the control electrodes of the first FET die 120 and the third FET die 310 to the first metal clip 160, are portions of the first metal clip 160, such as fingers. In other words, the first connector 170 and the third connector 174 form the third and fourth portions of the first metal clip 160, respectively, wherein the first to fourth portions are portions of a monolithic unit.

[0061] Figure 8 This is a flowchart of an exemplary method 800 for manufacturing a power semiconductor package. Method 800 can be used, for example, to manufacture any of power semiconductor packages 100 to 700.

[0062] Method 800 includes: at 801, providing a power electronics substrate including a first side and an opposing second side; at 802, disposing a first FET die including the first side and the opposing second side on the power electronics substrate, such that the first side of the first FET die faces away from the power electronics substrate and the second side of the first FET die faces the first side of the power electronics substrate; at 803, disposing a second FET die including the first side and the opposing second side on top of the first side of the first FET die, such that the second side of the second FET die faces the first FET die; at 804, disposing a first FET die and a second FET die together... The process of distributing a first conductive layer between FET dies and thereby electrically connecting the first FET die and the second FET die to each other includes, at 805, providing a first metal clip including a first portion and a second portion; at 806, distributing the first portion of the first metal clip over a first side of the second FET die and electrically connecting the first portion to a first power electrode on the first side of the second FET die, and laterally distributing the second portion next to the first FET die and the second FET die; and at 807, using a first connector to electrically connect a control electrode on the first side of the first FET die to the first metal clip. The process may further include the step of encapsulating the first FET die and the second FET die with an encapsulation body.

[0063] According to an example, method 800 includes: electrically connecting a first FET die and a second FET die such that the first FET die and the second FET die form a common-emitter common-base circuit / common-source common-gate circuit. According to an example, connecting a first portion of a first metal clip to a first power electrode on a first side of the second FET die includes: soldering or sintering the first portion to the first power electrode. According to an example, process 805 of encapsulating the first FET die and the second FET die includes: molding the first FET die and the second FET die, the first metal clip, the first conductive layer, the first connector, and a first side of a power electronics substrate. Example

[0064] The following sections use specific examples to further explain power semiconductor packaging and methods for manufacturing power semiconductor packages.

[0065] Example 1 is a power semiconductor package comprising: a power electronic substrate including a first side and an opposing second side; a first FET die including a first side and an opposing second side, the first FET die being disposed on the power electronic substrate such that the first side of the first FET die faces away from the power electronic substrate and the second side of the first FET die faces the first side of the power electronic substrate; a second FET die including a first side and an opposing second side, the second FET die being disposed on top of the first side of the first FET die such that the second side of the second FET die faces the first FET die; and a first conductive layer. An electrical layer is disposed between the first FET die and the second FET die and electrically connects the first FET die and the second FET die to each other; an encapsulation body encapsulates the first FET die and the second FET die; a first metal clip includes a first portion and a second portion, wherein the first portion is disposed on a first side of the second FET die and electrically connected to a first power electrode on the first side of the second FET die, and wherein the second portion is laterally disposed beside the first FET die and the second FET die; and a first connector electrically connects a control electrode on the first side of the first FET die to the first metal clip.

[0066] Example 2 is a power semiconductor package according to Example 1, wherein the first FET is a depletion-type junction FET, and / or wherein the second FET is an enhancement-type FET, particularly a metal-oxide-semiconductor field-effect transistor.

[0067] Example 3 is a power semiconductor package according to Example 1 or 2, wherein the first FET die comprises or is composed of a wide-bandgap semiconductor material, particularly SiC or GaN, and the second FET die comprises or is composed of Si.

[0068] Example 4 is a power semiconductor package according to one of the preceding examples, wherein, when viewed from above the first side of the second FET die, the second FET die has a smaller coverage area compared to the first FET die.

[0069] Example 5 is a power semiconductor package according to one of the preceding examples, further comprising: a third FET die including a first side and an opposing second side, the third FET die being laterally disposed on the power electronics substrate next to the first FET die such that the first side of the third FET die faces away from the power electronics substrate and the second side of the third FET die faces the first side of the power electronics substrate; a fourth FET die including a first side and an opposing second side, the fourth FET die being disposed on top of the first side of the third FET die such that the second side of the fourth FET die faces the third FET die; a second conductive layer disposed between the third FET die and the fourth FET die and electrically connecting the third FET die and the fourth FET die to each other, wherein the first FET die and the third FET die are connected in parallel through the power electronics substrate, and wherein the second FET die and the fourth FET die are connected in parallel through the first metal clip.

[0070] Example 6 is a power semiconductor package according to one of the foregoing examples, wherein the drain electrode on a first side of the first FET die is connected to the source electrode on a second side of the second FET die via the first conductive layer, or wherein the source electrode on the first side of the first FET die is connected to the drain electrode on the second side of the second FET die via the first conductive layer.

[0071] Example 7 is a power semiconductor package according to one of the foregoing examples, wherein a first end of the first connector is attached to the first portion of the first metal clip.

[0072] Example 8 is a power semiconductor package according to one of Examples 1 to 6, wherein a first end of the first connector is attached to the second portion of the first metal clip.

[0073] Example 9 is a power semiconductor package according to one of the preceding examples, wherein the second portion is exposed from the encapsulation body and forms the external power contacts of the power semiconductor package.

[0074] Example 10 is a power semiconductor package according to one of the foregoing examples, further comprising: a second metal clip including a first portion and a second portion, wherein the first portion is disposed on a first side of the power electronics substrate and electrically connected via the power electronics substrate to a power electrode on a second side of the first FET die, and wherein the second portion is exposed from the encapsulation body, wherein the second portion of the first metal clip is exposed from a first side of the encapsulation body, and the second portion of the second metal clip is exposed from an opposite second side of the encapsulation body.

[0075] Example 11 is a power semiconductor package according to one of the preceding examples, wherein the first connector is a bonding wire.

[0076] Example 12 is a power semiconductor package according to one of Examples 1 to 10, wherein the first connector is a third portion of the first metal clip, and wherein the first portion, the second portion and the third portion are portions of a monolithic unit.

[0077] Example 13 is a power semiconductor package according to one of the foregoing examples, wherein the power electronics substrate includes a first conductive pad and a second conductive pad, wherein a first FET die and a second FET die are disposed on the first conductive pad, wherein a control electrode on a first side of the second FET die is electrically connected to the second conductive pad via a second connector, and wherein a first metal clip spans the second conductive pad.

[0078] Example 14 is a power semiconductor package according to one of Examples 1 to 12, further comprising: a third metal clip exposed from the package body, wherein a control electrode on a first side of the second FET die is electrically connected to the third metal clip such that the connection between the control electrode and the third metal clip does not include any conductive pads of the power electronics substrate.

[0079] Example 15 is a method for manufacturing a power semiconductor package, the method comprising: providing a power electronic substrate, the power electronic substrate including a first side and an opposing second side; disposing a first junction field-effect transistor (FET) die including the first side and the opposing second side on the power electronic substrate, the first FET die such that the first side of the first FET die faces away from the power electronic substrate and the second side of the first FET die faces the first side of the power electronic substrate; disposing a second FET die including the first side and the opposing second side on top of the first side of the first FET die, such that the second side of the second FET die faces the first FET die; and disposing a second FET die on top of the first side of the first FET die, the second side of the second FET die facing the first FET die; and disposing a second FET die on top of the first side of the first FET die. A first conductive layer is disposed between the second FET dies, thereby electrically connecting the first FET die and the second FET die to each other; the first FET die and the second FET die are encapsulated by an encapsulation body; a first metal clip including a first portion and a second portion is provided; the first portion of the first metal clip is disposed on a first side of the second FET die and electrically connected to a first power electrode on the first side of the second FET die, and the second portion is laterally disposed next to the first FET die and the second FET die; and a first connector is used to electrically connect a control electrode on the first side of the first FET die to the first metal clip.

[0080] Example 16 is the method according to Example 15, wherein the first FET die comprises or is composed of a wide-bandgap semiconductor material, particularly SiC or GaN, and the second FET die comprises or is composed of Si.

[0081] Example 17 is the method according to Example 15 or 16, wherein the first FET die and the second FET die are electrically connected such that the first FET die and the second FET die form a common-emitter common-base circuit / common-source common-gate circuit.

[0082] Example 18 is a method according to one of Examples 15 to 17, wherein connecting the first portion of the first metal clip to the first power electrode on a first side of the second FET die includes: welding or sintering the first portion to the first power electrode.

[0083] Example 19 is a method according to one of Examples 15 to 18, wherein the encapsulation includes molding over the first FET die and the second FET die, the first metal clip, the first conductive layer, the first connector, and a first side of the power electronics substrate.

[0084] Example 20 is an apparatus comprising a unit for performing the method according to any one of Examples 15 to 19.

[0085] While specific examples have been shown and described herein, it will be understood by those skilled in the art that various alternatives and / or equivalent implementations may be made in place of the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

[0086] It should be noted that the methods and apparatuses, including their preferred embodiments as outlined in this document, can be used independently or in combination with other methods and apparatuses disclosed in this document. Furthermore, features outlined in the context of the apparatus also apply to the corresponding methods, and vice versa. Moreover, all aspects of the methods and apparatuses outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0087] It should be noted that the description and accompanying drawings only illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that embody the principles of the invention and are included within its spirit and scope, although not explicitly described or shown herein. Furthermore, all examples and embodiments outlined in this document are intended primarily for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing the principles, aspects, and embodiments of the invention and their specific examples are intended to cover their equivalents.

Claims

1. A power semiconductor package (100), comprising: A power electronics substrate (110) includes a first side (111) and an opposite second side (112). A first field-effect transistor (FET) die (120) includes a first side (121) and an opposing second side (122). The first FET die (120) is disposed on the power electronic substrate (110) such that the first side (121) of the first FET die (120) faces away from the power electronic substrate (110), and the second side (122) of the first FET die (120) faces the first side (111) of the power electronic substrate (110). The second FET die (130) includes a first side (131) and an opposite second side (132). The second FET die (130) is disposed on top of the first side (121) of the first FET die (120) such that the second side (132) of the second FET die (130) faces the first FET die (120). A first conductive layer (140) is disposed between the first FET die (120) and the second FET die (130) and electrically connects the first FET die (120) and the second FET die (130) to each other; Encapsulation body (150) encapsulates the first FET die (120) and the second FET die (130). A first metal clip (160) includes a first portion (160-1) and a second portion (160-2), wherein the first portion (160-1) is disposed on a first side (131) of the second FET die (130) and electrically connected to a first power electrode on the first side (131) of the second FET die (130), and wherein the second portion (160-2) is laterally disposed beside the first FET die (120) and the second FET die (130); and The first connector (170) electrically connects the control electrode on the first side (121) of the first FET die (120) to the first metal clip (160).

2. The power semiconductor package (100) according to claim 1, wherein, The first FET is a depletion-type junction FET, and / or the second FET is an enhancement-type FET, particularly a metal-oxide-semiconductor field-effect transistor.

3. The power semiconductor package (100) according to claim 1 or 2, wherein, The first FET die (120) comprises or is composed of a wide-bandgap semiconductor material, particularly SiC or GaN, and the second FET die (130) comprises or is composed of Si.

4. The power semiconductor package (100) according to any one of the preceding claims, wherein, When viewed from above the first side (131) of the second FET die (130), the second FET die (130) has a smaller coverage area compared to the first FET die (130).

5. The power semiconductor package (300) according to any one of the preceding claims further comprises: A third FET die (310) includes a first side and an opposite second side. The third FET die (310) is laterally arranged on the power electronics substrate (110) next to the first FET die (120), such that the first side of the third FET die (310) faces away from the power electronics substrate (110), and the second side of the third FET die (310) faces the first side (111) of the power electronics substrate (110). A fourth FET die (320) includes a first side and an opposing second side, the fourth FET die (320) being disposed on top of the first side of the third FET die (310) such that the second side of the fourth FET die (320) faces the third FET die (310). A second conductive layer is disposed between the third FET die (310) and the fourth FET die (320), and electrically connects the third FET die (310) and the fourth FET die (320) to each other. The first FET die (120) and the third FET die (310) are connected in parallel through the power electronics substrate (110), and the second FET die (130) and the fourth FET die (320) are connected in parallel through the first metal clip (160).

6. The power semiconductor package (100) according to any one of the preceding claims, wherein, The drain electrode on the first side (121) of the first FET die (120) is connected to the source electrode on the second side (132) of the second FET die (130) via the first conductive layer (140), or The source electrode on the first side (121) of the first FET die (120) is connected to the drain electrode on the second side (132) of the second FET die (130) via the first conductive layer (140).

7. The power semiconductor package (100) according to any one of the preceding claims, wherein, The first end of the first connector (170) is attached to the first portion (160-1) of the first metal clip (160).

8. The power semiconductor package (100) according to any one of claims 1 to 6, wherein, The first end of the first connector (170) is attached to the second part (160-2) of the first metal clip (160).

9. The power semiconductor package (300) according to any one of the preceding claims, wherein, The second part (160-2) is exposed from the encapsulation body (150) and forms the external power contact (330) of the power semiconductor package (300).

10. The power semiconductor package (300) according to any one of the preceding claims further comprises: The second metal clip (332) includes a first portion and a second portion, wherein the first portion is disposed on a first side (111) of the power electronics substrate (110) and electrically connected via the power electronics substrate (110) to a power electrode on a second side (122) of the first FET die (120), and wherein the second portion is exposed from the encapsulation body (150). The second portion (160-2) of the first metal clip (160) is exposed from the first side (153) of the encapsulation body (150), and the second portion of the second metal clip (332) is exposed from the opposite second side (153) of the encapsulation body (150).

11. The power semiconductor package (100) according to any one of the preceding claims, wherein, The first connector is a bonding wire.

12. The power semiconductor package (700) according to any one of claims 1 to 10, wherein, The first connector (170) is the third part of the first metal clip (160), wherein the first part, the second part and the third part are parts of a monolithic unit.

13. The power semiconductor package (300) according to any one of the preceding claims, wherein, The power electronics substrate (110) includes a first conductive pad (110-1) and a second conductive pad (110-2), wherein the first FET die (120) and the second FET die (130) are disposed on the first conductive pad (110-1). The control electrode on the first side (131) of the second FET die (130) is electrically connected to the second conductive pad (110-2) via the second connector (172), and the first metal clip (160) spans the second conductive pad (110-2).

14. The power semiconductor package (500) according to any one of claims 1 to 12, further comprising: The third metal clip (334) is exposed from the encapsulation body (150). The control electrode on the first side (131) of the second FET die (130) is electrically connected to the third metal clip (334), such that the connection between the control electrode and the third metal clip (334) does not include any conductive pads of the power electronics substrate (110).

15. A method (800) for manufacturing a power semiconductor package, the method (800) comprising: A power electronics substrate (801) is provided, the power electronics substrate comprising a first side and an opposing second side; A first junction field-effect transistor die, including a first side and an opposite second side, is arranged (802) on the power electronic substrate such that the first side of the first FET die faces away from the power electronic substrate and the second side of the first FET die faces the first side of the power electronic substrate. A second FET die comprising a first side and an opposite second side is arranged on the top of the first side of the first FET die (803), such that the second side of the second FET die faces the first FET die; A first conductive layer (804) is disposed between the first FET die and the second FET die, thereby electrically connecting the first FET die and the second FET die to each other; Provided (805) a first metal clip comprising a first part and a second part; The first portion of the first metal clip is arranged (806) on the first side of the second FET die, and the first portion is electrically connected to the first power electrode on the first side of the second FET die, and the second portion is arranged laterally next to the first FET die and the second FET die. as well as The control electrode on the first side of the first FET die is electrically connected (807) to the first metal clip using the first connector.

16. The method (800) according to claim 15, wherein, The first FET die comprises or is composed of a wide-bandgap semiconductor material, particularly SiC or GaN, and the second FET die comprises or is composed of Si.

17. The method (800) according to claim 15 or 16, wherein, The first FET die and the second FET die are electrically connected, so that the first FET die and the second FET die form a common emitter common base circuit / common source common gate circuit.

18. The method according to any one of claims 15 to 17, wherein, Connecting the first portion of the first metal clip to the first power electrode on the first side of the second FET die includes welding or sintering the first portion to the first power electrode.

19. The method (800) according to any one of claims 15 to 18, further comprising: Encapsulating the first FET die and the second FET die with an encapsulation body, wherein the encapsulation includes molding on the first FET die and the second FET die, the first metal clip, the first conductive layer, the first connector, and a first side of the power electronics substrate.

Images