Detecting errors within data path circuitry of a memory device

Abstract

A memory device includes core circuitry having memory cells and write data path circuitry coupled to the core circuitry. The write data path circuitry determines a second parity bit based on a second signal and a poison bit. The second signal and the poison bit are determined by processing a first data signal. Furthermore, the write data path circuitry detects a first error within the second signal based on a comparison between the first parity bit and the second parity bit, and outputs a first error signal including the first error.

Description

Technical Field

[0001] Examples of this disclosure generally relate to error detection within a memory device, and more specifically, to detecting errors in signals processed within the read and write data path circuitry of the memory device. Background Technology

[0002] Memory systems employ various data integrity schemes to mitigate errors in signals sent to and from memory devices and / or to protect data as it is transmitted to and from memory devices. Data integrity schemes include the use of Error Correcting Codes (ECC) and / or Cyclic Redundancy Check (CRC) procedures. An ECC scheme can be an inline ECC scheme that uses memory within the corresponding memory device to store the ECC codes. ECC codes are used to detect errors within the data of the corresponding memory transaction when read and write commands are executed. A CRC procedure is used to detect bit changes within the data signal. The CRC procedure detects changes at different points along the data path. Summary of the Invention

[0003] In one example, a memory device includes core circuitry having memory cells and write data path circuitry coupled to the core circuitry. The write data path circuitry determines a first parity bit based on a first signal and a second parity bit based on a second signal and a poison bit. The second signal and poison bit are determined by processing the first data signal. Furthermore, the write data path circuitry detects a first error within the second signal based on a comparison between the first parity bit and the second parity bit, and outputs a first error signal including the first error.

[0004] In one example, a memory device includes core circuitry having memory cells and read data path circuitry coupled to the core circuitry. The read data path circuitry determines a first parity bit based on a first signal, a poison bit, and a severity bit. The poison bit and severity bit are determined according to the first signal. Furthermore, the read data path circuitry determines a second parity bit based on a second signal. The second signal is generated by processing the first signal. The read data path circuitry also detects a first error within the second signal based on a comparison between the first parity bit and the second parity bit; and Attached Figure Description

[0005] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting the scope of the description.

[0006] Figure 1 This is a block diagram of a memory system.

[0007] Figure 2A This is a block diagram of the write data path circuit of the memory system.

[0008] Figure 2B This is a block diagram of the write data path circuit of the memory system.

[0009] Figure 3 It is a timing diagram of memory commands within the write data path circuit of the memory system.

[0010] Figure 4 It is a timing diagram of back-to-back memory commands within the write data path circuit of the memory system.

[0011] Figure 5A This is a block diagram of the data read path circuit of the memory system.

[0012] Figure 5B This is a block diagram of the data read path circuit of the memory system.

[0013] Figure 6 A flowchart illustrating a method for detecting errors within a data path circuit is provided.

[0014] Figure 7 A flowchart illustrating a method for detecting errors within a data path circuit is provided. Detailed Implementation

[0015] A memory system comprises memory devices coupled to a host device. When signals are transmitted between the host device and the memory device, data integrity procedures are used to mitigate errors within the signals. For example, a memory system may employ error-correcting code (ECC) and cyclic redundancy check (CRC) procedures as data integrity procedures. Furthermore, in some examples, data masking schemes and read-modify-write operations are used for data integrity.

[0016] In the ECC process, to ensure data integrity of signals from the host device to the memory device, an ECC code is generated and transmitted from the host device. The ECC code is stored in the memory device. Therefore, using this ECC process, memory resources are used to store the ECC code, thereby reducing the amount of available data that can be stored or increasing the cost of the memory device due to the increased size of the memory device to support the storage of the ECC code.

[0017] In the CRC process, errors within the data signal are detected at specific points along the data path circuit. However, the values ​​of bits within the data signal may change before or after the CRC process completes. These changes may not be detected by the CRC process. Therefore, errors that were not detected by the CRC process may exist in the signal output to the host device or memory device. Furthermore, the use of CRC bits increases the number of memory cells within the memory device, thereby increasing the cost of the memory device.

[0018] The memory device described below uses a data path CRC circuit to detect and mitigate errors within the corresponding data path circuitry. In one example, the data path CRC circuit includes CRC (DPCRC) generation and DPCRC verification circuitry for detecting and mitigating errors within the corresponding data path circuitry during both write and read operations. As a signal propagates within the corresponding data path, the data path CRC circuit uses one or more parity bits to detect and / or mitigate errors within the corresponding signal. In one example, the data path CRC circuit generates one or more parity bits. The use of parity bits maintains data integrity within the write and read data path circuitry without significantly increasing the size and cost of the memory device and / or the complexity and cost of the host device's memory controller. The use of the data path CRC circuit allows data integrity to be used by a large number of memory controllers, and specifically with memory controllers that do not include other types of data integrity processes. Furthermore, the proposed method does not increase storage-related costs because the additional memory cells are not used to store ECC bits or codes generated by the host device.

[0019] Figure 1 A memory system 100 is illustrated. The memory system 100 includes a memory device 110 and a host device 120. The memory system 100 is an integrated circuit (IC) device. The memory system 100 includes one or more IC chips. For example, the memory device 110 is part of a first one or more IC chips, and the host device 120 is part of a second one or more IC chips.

[0020] The host device 120 includes a memory controller circuit 122 and a processing device 124. The processing device 124 is a central processing unit (CPU) or a graphics processing unit (GPU), etc.

[0021] Memory device 110 is dynamic random access memory (DRAM). In one example, the memory device is a double data rate (DDR) memory device. In another example, the memory device is a graphics DDR (GDDR) memory device. In other examples, memory device 110 is a high bandwidth memory (HBM) device. An HBM device comprises vertically stacked memory device chips.

[0022] The memory device 110 includes core circuitry 112, input / output circuitry 114, and data path circuitry 116. Core circuitry 112 includes memory cells (e.g., bit cells), bit lines, word lines, sense amplifier circuitry, row decoder circuitry, and / or column decoder circuitry, etc.

[0023] Input / output circuitry 114 includes receiver circuitry for receiving signals from memory controller circuitry 122 and transmitter circuitry for sending signals to memory controller circuitry 122. Input / output circuitry 114 may be physical layer (PHY) circuitry. In one or more examples, input / output circuitry 114 includes one or more buffers and / or other circuit elements to facilitate signal reception and transmission.

[0024] Data path circuit 116 includes write data path circuitry and read data path circuitry. Data path circuit 116 is coupled between core circuit 112 and input / output circuit 114. Data path circuit 116 transmits signals from core circuit 112 to input / output circuit 114 and performs one or more of the decoding, encoding, ECC, and CRC processes. In one or more examples, as described in more detail below, data path circuit 116 includes data path CRC circuit 118. Data path CRC circuit 118 detects and mitigates errors within data path circuit 116. In one or more examples, data path CRC circuit 118 includes DPCRC generator circuitry and / or DPCRC check circuitry. In one example, a first data path CRC circuit 118 is included within the write data path circuitry of data path circuit 116, and / or a second data path CRC circuit 118 is included within the read data path circuitry of data path circuit 116. In one example, data path CRC circuit 118 is coupled to core circuit 112. For example, the data path CRC circuit 118 is coupled to the core circuit 112 via the data path circuit 116 to detect errors within the data path circuit 116.

[0025] In one or more examples, data integrity protection is lacking in at least a portion of the data path circuitry of memory device 110. In one example, an on-die ECC scheme of memory device 110 protects data within core circuitry 112 from erroneous bit flips, and a CRC write / read check scheme of memory device 110 protects data as corresponding signals are transmitted to and / or from core circuitry 112 and / or host device 120. However, bit flips, errors, or other stimuli that cause changes in values ​​within signals may occur between the on-die ECC circuitry and the CRC write / read check circuitry, resulting in undetected or unmitigated read or write errors. In one or more examples, bit flips occurring in signals between the CRC write / read check circuitry of the data path circuitry and the on-die ECC circuitry of the data path circuitry may be incorporated into the generated ECC code (e.g., a checksum). In an example where the signal received by the host device has an error, the ECC code generated by the host device from the signal will also have an error. In the above examples, the data path CRC circuitry 118 detects and mitigates the above-mentioned example errors within data path circuitry 116.

[0026] Figure 2 illustrates an example block diagram of the write data path circuit 200 of the memory system 100. The write data path circuit 200 is... Figure 1 The data path circuit 116 is a part of the memory device 110. The write data path circuit 200 is included within the memory device 110. The write data path circuit 200 may be included in an IC device and / or die shared with the core circuit 112 and / or the input / output circuit 114. The write data path circuit 200 transmits data within signals received by the input / output circuit 114 from the host device 120 (e.g., the memory controller circuit 122 of the host device 120) to the core circuit 112 based on a write command provided by the host device 120. The write command includes the address of the data to be written within the core circuit 112.

[0027] The write data path circuit 200 includes decoder circuits 210 to 216, CRC write verification circuit 218, scrambler circuit 220, on-die ECC circuit 222, DPCRC generator circuit 224, and DPCRC verification circuit 226. The DPCRC generator circuit 224 and DPCRC verification circuit 226 form the data path CRC circuit (e.g., data path CRC circuit 118).

[0028] In one example, the input of decoder circuit 210 is coupled to the output of input / output circuit 114, and the output of decoder circuit 210 is coupled to the input of CRC write-check circuit 218. One or more outputs of CRC write-check circuit 218 are coupled to the inputs of decoder circuits 212, 214, and 216. One output of CRC write-check circuit 218 is coupled to input / output circuit 114.

[0029] One or more outputs of the DPCRC generator circuit 224 are coupled to the DPCRC verification circuit 226. The outputs of the decoder circuits 212 and 214 are coupled to the input scrambler circuit 220. The output of the scrambler circuit 220 is coupled to the inputs of the DPCRC verification circuit 226, the on-die ECC circuit 222, and the core circuit 112. The output of the decoder circuit 216 is coupled to the inputs of the on-die ECC circuit 222 and the DPCRC verification circuit 226. The output of the on-die ECC circuit 222 is coupled to the input of the core circuit 112. One or more outputs of the DPCRC verification circuit are coupled to the input / output circuit 114.

[0030] The host device 120 outputs signal 260 to the input / output circuit 114. Signal 260 is a Pulse Amplitude Modulation 3 (PAM-3) signal. In other examples, signal 260 may have more or fewer three levels, or a different communication protocol than PAM-3. In one example, signal 260 has 176 symbols. In other examples, signal 260 has more or fewer than 176 symbols.

[0031] Input / output circuit 114 outputs signal 231 to the inputs of decoder circuit 210 and DPCRC generator circuit 224. Signal 231 corresponds to signal 260. Signal 231 includes one or more data symbols and one or more CRC symbols. In one example, signal 231 includes 164 data symbols and 12 CRC symbols. Signal 233, including CRC symbols, is received by decoder circuit 210. Decoder circuit 210 decodes the CRC symbols of signal 233 to generate signal 234. In one example, signal 234 has 18 bits. Signal 234 is received by CRC write-verification circuit 218 as CRC data. CRC write-verification circuit 218 also receives signal 232.

[0032] Signal 234 is used to perform a CRC check on signal 232. For example, the data symbol of signal 232 is used to generate CRC data by the CRC write-check circuit 218. This CRC data is compared with the CRC data of signal 234. If the data match, no error is reported in signal 231. If the data do not match, an error is reported in signal 231.

[0033] The CRC write check circuit 218 outputs an error signal 250. Error signal 250 is combined with error signal 249 output by the DPCRC check circuit 226 and output as error signal 251 to input / output circuit 114, which in turn outputs to host device 120. The value of error signal 250 indicates whether the CRC write check circuit 218 or the DPCRC check circuit 226 detected an error. In one example, the value of error signal 250 indicates the type of error. In one or more examples, a value of zero indicates a CRC write check error, and a value of one indicates no error. In other examples, other values ​​can be used to indicate other types of errors. In one example, if the CRC check fails, an error report is sent back to host device 120 via an error output pin. In one example, the error could be a write CRC (WRCRC) error (indicated by a value of 0), a command address parity check error (indicated by a value of -1), and no error (indicated by a value of 1). The previous example is for the PAM-3 signaling protocol. In other examples, values ​​greater than or less than three can be used to report an error or no error. Furthermore, values ​​can be used in different ways to report errors or no errors.

[0034] In one example, error signal 251 is a PAM-3 signal. In other examples, other communication protocols may be used to convey error signal 251.

[0035] DPCRC generator circuit 224 receives signal 232. In one example, DPCRC generator circuit 224 receives signal 232 based on the assumption that signal 232 is error-free. DPCRC generator circuit 224 generates an error check signal 236 from the bits of signal 232. Error check signal 236 includes one or more parity bits determined based on the bits of signal 232. In another example, error check signal 236 includes one or more CRC codes determined based on the bits of signal 232.

[0036] DPCRC generator circuit 224 generates an error check signal 236 from the symbols of signal 232. In one example, the error check signal 236 is generated as one or more parity bits based on the number of ones or zeros within signal 232. In one example, the parity bit of the error check signal 236 can be a value of zero or one (or another value). In one example, if the number of ones (or zeros) within signal 232 is odd, the parity bit value is zero, and if the total number of ones (or zeros) in signal 232 is even, the parity bit value is one. In other examples, other methods may be used to determine the parity bit.

[0037] Signal 232 is also received by decoder circuits 212, 214, and 216. Decoder circuit 212 receives a first symbol of signal 232, decoder circuit 214 receives a second symbol of signal 232, and decoder circuit 216 receives one or more third symbols of signal 232. In an example where signal 232 has 164 symbols, decoder circuit 212 receives 161 symbols, decoder circuit 214 receives two symbols, and decoder circuit 216 receives one symbol. The symbol received by decoder circuit 216 in signal 239 corresponds to the poison bit and / or severity bit.

[0038] Decoder circuit 212 decodes the symbol of signal 237 to generate data signal 240. Decoder circuit 214 decodes the symbol of signal 238 to generate data signal 241. Furthermore, decoder circuit 216 decodes the symbol of signal 239 to generate poison bit 244 and severity bit of signal 246.

[0039] Scrambler circuit 220 receives signal 242 as a combination of signals 240 and 241, and generates signal 243. In one example, signal 240 has 253 bits, signal 241 has 3 bits, and signal 242 has 256 bits. Furthermore, signal 243 has 256 bits. Scrambler circuit 220 inverts or randomizes one or more values ​​within signal 242 to generate signal 243.

[0040] On-die ECC circuit 222 receives signal 243 and signal 244, which includes a poison bit and / or a severity bit, and generates an ECC code based on signals 243 and 244. The ECC code of signal 245 is output to and stored in core circuit 112. In one or more examples, on-die ECC circuit 222 generates an ECC code (e.g., a checksum) 245 based on signal 243 and stores the ECC code of signal 245 in core circuit 112. The DPCRC check circuit 226 receives signals 243, 244, and 246. Signal 246 is the severity bit. In one example of a write command, signal 246 has a value of zero.

[0041] DPCRC check circuit 226 generates one or more parity bits from signals 243, 244, and 246. In one example, an error signal corresponding to error check signal 236 is generated by DPCRC check circuit 226. In the example where error check signal 236 is one or more parity bits, the error signal generated by DPCRC check circuit 226 is one or more parity bits. The one or more parity bits are generated based on signals 243, 244, and 246 as described above with respect to DPCRC generator circuit 224. Parity bits can be zero or one, and are based on the number of zeros or ones in signals 243, 244, and 246. In the example where error check signal 236 is a CRC code, the error signal generated by DPCRC check circuit 226 is a CRC code. The CRC code is generated as described above.

[0042] If the error signal (e.g., parity bit or CRC code) determined by the DPCRC check circuit 226 matches the error check signal 236 (e.g., parity bit or CRC code) (e.g., having the same value), no error is detected and no error is reported via error signal 249. For example, a value of zero is reported to the host device 120 to indicate that no error was detected. If an error is detected, a value of one is reported to the host. The error is reported as a DPCRC error. In other examples, the values ​​assigned to error and no error may be reversed, or other values ​​may be used to report different types of errors.

[0043] The error detection method described herein determines whether a bit is flipped in the signal between the DPCRC generator circuit 224 and the DPCRC check circuit 226. If a bit is flipped, the parity bit determined by the DPCRC generator circuit 224 and the DPCRC check circuit 226 are different, and an error is reported. In one example, based on the detected error, the transmission of the data signal 260 is retried. For example, the data signal 260 is retransmitted from the host device 120 to the core circuit 112 via the write data path circuit 200 and the input / output circuit 114.

[0044] In one example, a single parity bit is generated by DPCRC check circuit 226 and DPCRC generator circuit 224. In other examples, more than one parity bit may be used. In one example, the number of parity bits can be programmable.

[0045] Figure 2B An example block diagram of the write data path circuit 270 of the memory system 100 is shown. The write data path circuit 270 is... Figure 1The data path circuit 116 is a part of the memory device 110. The write data path circuit 270 is included within the memory device 110. The write data path circuit 270 may be included in an IC device and / or die shared with the core circuit 112 and / or the input / output circuit 114. The write data path circuit 270 transmits data within signals received by the input / output circuit 114 from the host device 120 (e.g., the memory controller circuit 122 of the host device 120) to the core circuit 112 based on a write command provided by the host device 120.

[0046] The write data path circuit 270 is configured to be similar to Figure 2A The write data path circuit 200. For example, the write data path circuit 270 includes decoder circuits 210 to 216, CRC write check circuit 218, scrambler circuit 220, on-die ECC circuit 222, DPCRC generator circuit 224, and DPCRC check circuit 226. Compared to the write data path circuit 200, the write data path circuit 270 also includes encoder circuits 271 to 273 and descrambler circuit 274. Furthermore, in the write data path circuit 270, one or more inputs of the DPCRC check circuit 226 are coupled to the outputs of the encoder circuits 271 to 273. In one example, the DPCRC generator circuit 224 and the DPCRC check circuit 226 form a data path CRC circuit (e.g., Figure 1 (Data path CRC circuit 118).

[0047] The input of descrambler circuit 274 is coupled to the output of scrambler circuit 220 and receives signal 243 from scrambler circuit 220. Descrambler circuit 274 descrambles (e.g., inverts the function performed by descrambler circuit 274) signal 243 to generate signal 275. Signal 275 comprises 256 bits.

[0048] The inputs of encoder circuits 271 and 272 are coupled to the output of descrambler circuit 274. Encoder circuit 271 receives signal 276, which includes a first portion of the bits of signal 275, and encoder circuit 272 receives signal 277, which includes a second portion of the bits of signal 275. The number of bits in signal 276 is greater than the number of bits in signal 277. In one example, signal 276 includes 253 bits, and signal 277 includes 3 bits. In other examples, signals 276 and 277 may have other numbers of bits. Encoder circuit 271 encodes the bits of signal 276 to generate symbols for signal 278. Signal 278 may include 161 symbols. Encoder circuit 272 encodes the bits of signal 277 to generate symbols for signal 279. Signal 279 may include 2 symbols.

[0049] The input of encoder circuit 273 is coupled to the output of decoder circuit 216 and receives signal 244. Encoder circuit 273 also receives a severity bit. In one example of a write command, the severity bit has a value of 0. Encoder circuit 273 encodes signal 244 and the severity bit into symbols of signal 280. In one example, signal 280 includes one or more symbols.

[0050] Signals 278, 279, and 280 are combined into signal 281, which is received by DPCRC check circuit 226. In one example, DPCRC check circuit 226 receives each of 278, 279, and 280 and internally combines these signals. DPCRC check circuit 226 functions as described above to generate an error signal, which is compared with an error check signal 236 generated by DPCRC generator circuit 224 to determine whether an error exists in signal 243.

[0051] Error signals 249 and 250 are combined as described above and output as error signal 251 as described above.

[0052] Figure 3 Timing diagram 300 is illustrated. Timing diagram 300 is used for... Figure 2A Write data path circuit 200 or Figure 2B The write data path circuit 270 processes write commands (e.g., write command m). Timing diagram 300 includes a clock signal CK, a write clock signal WCK, row command CA, column command CA, a data signal DQ, a data enable signal DQE, and an error signal 251. Furthermore, the timing diagram indicates write latency (WL) timing, WRCRC2ERR, DPCRC2ERR, and CAPAR2ERR. Write latency (WL) indicates the time difference (e.g., number of cycles) from when the write command is initiated until data is available for writing. Figure 3 In the example, WL represents the four cycles of the clock signal CK.

[0053] WRCRC2ERR is from data available (e.g., received) Figure 2A The data signal 260) is written to the host device (e.g., Figure 1 The time it takes for the host device 120 to be notified of the presence of errors in the data sent for the corresponding transaction. The WRCRC2ERR timing corresponds to the CRC check circuit (e.g., written to the data path circuit 200) of the CRC check circuit. Figure 2A Error checking is performed by the CRC write-verification circuit 218. Figure 3In the example, the WRCRCERR timing is four cycles of the clock signal CK. In one example of the write command m, an indication is output at time T9 regarding whether the CRC write verification circuit 218 detected an error. The value of the error signal 251 indicates whether the CRC write verification circuit 218 detected an error.

[0054] DCRC2ERR is from data available (e.g., received) Figure 2A When the data signal 260 is received by the DPCRC verification circuit (e.g., Figure 2A The time elapsed when the DPCRC check circuit 226 detects or does not detect an error. At time T11, the error signal 251 includes an indication of whether the DPCRC check circuit 226 has detected an error.

[0055] In one example, the timing DPCRC2ERR is six cycles of the clock signal CK. Therefore, the delay associated with DPCRC2ERR is equal to the delay associated with WRCRC2ERR. Thus, when error signal 251 is shared between CRC write check circuit 218 and DPCRC check circuit 226, host device 120 is able to determine the origin of the error within error signal 251.

[0056] In one or more examples, when an error signal is output via a common output (e.g., a common line and / or pin), timing is used to determine the type of error. For example, at time T9, an error related to the CRC check circuitry (e.g., WRCRC2ERR) is reported. Reference Figure 1 As shown in Figure 2, host device 120 receives error signal 251 and determines the type of error based on timing. At time T9, host device 120 determines that error signal 251 was reported by CRC write-check circuit 218 and corresponds to an error at CRC write-check circuit 218. At time T11, host device 120 determines that error signal 251 corresponds to an error at DPCRC check circuit 226.

[0057] Figure 4 An example of a write data path circuit is shown (e.g., Figure 2A The timing diagram of the write data path circuit 200 (400) is shown in Figure 400. Figure 3Compared to timing diagram 300, which includes a single write command, timing diagram 400 is used for two write commands, such as write command m and write command n. Write commands m and n occur sequentially, back-to-back. Timing diagram 400 includes a clock signal CK, a write clock signal WCK, a row command CA, a column command CA, a data signal DQ, a data enable signal DQE, and an error signal 251. Furthermore, timing diagram 400 indicates the write latency (WL) timing for each write command, the WRCRC2ERR for each write command, the DPCRC2ERR for the first write command (e.g., write command m), and the CAPAR2ERR associated with the parity check of the write commands.

[0058] When write commands m and n are issued back-to-back (without any other commands issued in between), the reporting time associated with an error (e.g., DPCRC2ERR) from DPCRC check circuit 226 for the first write command (e.g., write command m) and the reporting time associated with an error (e.g., WRCRC2ERR-2) from CRC write check circuit 218 for the second write command (e.g., write command n) both occur at time T11. Therefore, the host device (e.g., host device 120) cannot determine the source of the error, e.g., whether it originates from CRC write check circuit 218 or DPCRC check circuit 226. Furthermore, parity checking is performed for each instruction in each cycle of the clock signal CK. The timing of the parity check output is indicated by CAPAR2ERR. As can be seen in timing diagram 400, the parity check output occurs at time T11. Therefore, if an error is reported to the host device 120 via error signal 251 at time T11 through parity check, the host device 120 cannot determine whether the error is based on a parity check error or is output by CRC write check circuit 218 and DPCRC check circuit 226.

[0059] An indication that an error was reported at time T11 is provided to host device 120 via error signal 251. Based on the indication of the error at time T11, host device 120 retryes memory commands m and n, because host device 120 cannot determine which memory command the error corresponds to. For example, the error signal is transmitted via a common output (e.g., Figure 1The timing of the output error signal 251 (from the common output pin of the memory device 110) is used to determine the type of error. For example, at timing T9, an error related to the CRC write check circuit 218 and associated with WRCRC2ERR is reported via error signal 251. The host device 120 receives error signal 251 and determines the type of error based on the timing. For example, at time T9, the host device 120 determines that error signal 251 was reported by the CRC write check circuit 218 and corresponds to an error detected by the CRC write check circuit 218. At time T11, the host device 120 determines that error signal 251 includes an error detected by the DPCRC check circuit 226.

[0060] In one example, host device 120 receives error signal 251 at time T11. Based on the error signal received at time T11, host device 120 retryes the first memory command and the second memory command because host device 120 cannot determine whether the error was detected by DPCRC check circuit 226 and associated with memory command m (e.g., the first write memory command), whether the error was detected by CRC write check circuit 218 and associated with memory command n (e.g., the second write memory command), or whether it is a parity error associated with memory command m or memory command n.

[0061] In one example, a method includes: receiving a first error signal from a memory device; comparing the first error signal with timing data associated with a write data path circuitry within the memory device. Furthermore, the method includes determining that the first error signal includes a first error detected by cyclic redundancy check (CRC) circuitry within the write data path circuitry.

[0062] In one example, a method includes receiving a first signal from read data path circuitry of a memory device, and generating a first cyclic redundancy check (CRC) code from the first signal. Furthermore, the method includes determining an error within the first signal based on the first CRC code. This error is associated with an output detected by a data path CRC (DPCRC) check circuitry within the read data path circuitry.

[0063] Figure 5A Examples Figure 1 An example block diagram of the read data path circuit 500 of the memory system 100. The read data path circuit 500 is... Figure 1The data path circuit 116 is a part of the memory device 110. The read data path circuit 500 is included within the memory device 110. The read data path circuit 500 may be included in an IC device and / or die shared with the core circuit 112 and / or the input / output circuit 114. The read data path circuit 500 transmits data signals received from the core circuit 112 to the input / output circuit 114 and the host device 120 (e.g., the memory controller circuit 122 of the host device 120) based on a read command issued by the host device 120.

[0064] The data path reading circuit 500 includes encoder circuits 510, 514, 515, and 516, a read CRC (RDCRC) update circuit 511, a DPCRC check circuit 512, a CRC read check circuit 513, a descrambler circuit 517, an on-die ECC circuit 518, and a DPCRC generator circuit 519. In one example, the DPCRC check circuit 512 and the DPCRC generator circuit 519 form the data path CRC circuit (e.g., Figure 1 (Data path CRC circuit 118).

[0065] The output of core circuit 112 is coupled to the inputs of the DPCRC generator circuit, descrambler circuit 517, and on-die ECC circuit 518. The output of descrambler circuit 517 is coupled to the inputs of encoder circuits 514 and 515. Furthermore, the output of descrambler circuit 517 is coupled to the input of on-die ECC circuit 518, and the output of on-die ECC circuit 518 is coupled to descrambler circuit 517. The output of on-die ECC circuit 518 is coupled to the input of DPCRC generator circuit 519. The output of DPCRC generator circuit 519 is coupled to DPCRC verification circuit 512. The outputs of encoder circuits 514, 515, and 516 are coupled to the inputs of CRC verification circuit, DPCRC verification circuit, and encoder circuit 510. The output of CRC read verification circuit 513 is coupled to the input of RDCRC update circuit 511. The output of DPCRC verification circuit 512 is coupled to the input of RDCRC update circuit 511. The output of RDCRC update circuit 511 is coupled to the input of encoder circuit 510. The output of encoder circuit 510 is coupled to the input of input / output circuit 114. The output of input / output circuit 114 is coupled to the input of host device 120.

[0066] The core circuit 112, based on the read command received from the host device 120, outputs a data signal 520 to the descrambler circuit 517, the on-die ECC circuit 518 and the DPCRC generator circuit 519, and outputs an ECC code signal 521 to the on-die ECC circuit 518.

[0067] Data signal 520 corresponds to a read command received from host device 120. For example, the read command indicates the address to be read from core circuit 112, and core circuit 112 outputs the corresponding data as data signal 520 and outputs the ECC code via signal 521.

[0068] Descrambler circuit 517 generates signal 523 using data signal 520 and poison bit 524 received from ECC circuit 518 on the die. In one example, output descrambler circuit 517 descrambles data signal 520 to generate signal 523. Signal 523 is split into signals 526 and 527. Signal 526 has more bits than signal 527. In the example where signal 523 has 256 bits, signal 526 has 253 bits, and signal 527 has three bits.

[0069] Encoder circuit 514 receives signal 526 and encodes the data of signal 526 to generate signal 529. Signal 529 includes symbols. Encoder circuit 514 generates symbols from the data bits of signal 526. In the example where the signal has 253 bits, signal 529 has 161 symbols.

[0070] Encoder circuit 515 receives signal 527 and encodes the data of signal 527 to generate signal 530. Signal 530 includes a symbol. Encoder circuit 515 generates the symbol from the data bits of signal 527. In the example where the signal has three bits, signal 530 has two symbols.

[0071] The on-die ECC circuit 518 receives signals 520 and 521 and generates a poison bit 524. Signal 521 includes one or more ECC codes. The on-die ECC circuit 518 generates the poison bit 524 and the severity bit 525 from the ECC codes of data signals 520 and 521.

[0072] In one example, the on-die ECC circuit 518 detects errors within the data signal 520 based on the ECC code of signal 521. If an error is detected, the on-die ECC circuit 518 may request the data signal to be retransmitted from core circuit 112 and / or the on-die ECC circuit 518 may correct the error based on the ECC code. In another example, the on-die ECC circuit 518 does not correct detected errors. In one or more examples, the on-die ECC circuit 518 generates a severity bit 525 based on whether an error is detected in the data signal 520. For example, the severity bit 525 has a value of zero (or one) when an error is detected in the data signal 520, and a value of one (or zero) when an error is detected in the data signal 520. In other examples, other values ​​may be used to indicate whether an error has been detected.

[0073] Encoder circuit 516 receives poison bit 524 and severity bit 525 from on-die ECC circuit 518, and generates signal 531 from poison bit 524 and severity bit 525. Signal 531 has one symbol. Signals 529, 530, and 531 are combined into signal 533. The number of symbols in signal 533 corresponds to the number of combinations of symbols in signals 529, 530, and 531. Signal 533 is received by CRC read check circuit 513 and DPCRC check circuit 512, and is output to encoder circuit 510.

[0074] The DPCRC generator circuit 519 receives the data signal 520 from the core circuit 112. The DPCRC generator circuit 519 also receives a poison bit 524 from the on-die ECC circuit 118, and a severity bit 525 from the on-die ECC circuit 518. Therefore, in this example, the DPCRC generator circuit 519 receives the bits associated with the data signal 520, as well as the poison bit 524 and the read bit 525 associated with the read command. The DPCRC generator circuit 519 receives each data bit from the data bits propagated through the read data path circuit 500 to generate the output signal 537.

[0075] The DPCRC generator circuit 519 generates an error check signal 532 based on the data signal 520, the poison bit 524, and the severity bit 525. In one example, the error check signal 532 is a parity bit and is generated based on the number of ones or zeros in the data signal 520, the poison bit 524, and the severity bit 525. For example, if the number of ones is odd, the parity bit has a value of one (or zero). Furthermore, if the number of ones is even, the parity bit has a value of zero (or one). In another example, the error check signal 532 is a CRC code and is generated from the signal bits 520, 524, and 525.

[0076] DPCRC check circuit 512 receives signal 533 and error check signal 532. DPCRC check circuit 512 generates an error check signal from signal 533 and compares the generated error check signal with the parity bit of signal 533 received from DPCRC generator circuit 519. If the error check signals match (e.g., have the same value), it is determined that there is no error in signal 533. If the error check signals differ from each other (e.g., have different values), an error is determined in signal 533. The error check signal generated by DPCRC check circuit 512 can be a parity bit or a CRC code. The error check signal generated by DPCRC check circuit 512 corresponds to error check signal 532. For example, if error check signal 532 includes a parity bit, then the error check signal generated by DPCRC check circuit 512 includes a parity bit. Furthermore, if error check signal 532 includes a CRC code, then the error check signal generated by DPCRC check circuit 512 includes a CRC code.

[0077] An error in signal 533 corresponds to a difference between signal 533 and signals 520, poison bit 524, and severity bit 525. For example, the value of error indicator signal 533 differs from the values ​​of signals 520, poison bit 524, and severity bit 525. The error occurs between the output of on-die ECC circuit 518 and the input of CRC read verification circuit 513.

[0078] In one example, the DPCRC check circuit 512 outputs an error signal 538 to the host device 120 indicating that an error has occurred. The error signal 538 can be a single bit (or more) signal. A value of zero (or one) indicates that an error was detected, and a value of one (or zero) indicates that no error was detected. In other examples, other values ​​can be used to indicate whether an error was detected or not. Based on the indication of an error, the read command can be repeated. For example, the core circuit 112 can be instructed to retransmit signals 520 and 521. In another example, the error signal 538 is output to the RDCRC update circuit 511.

[0079] CRC read verification circuit 513 is connected to the output of encoder circuits 514 to 516. The output of CRC read verification circuit 513 is coupled to the input of RDCRC update circuit 511. Furthermore, the output of DPCRC verification circuit 512 is connected to the input of RDCRC update circuit 511. In one or more examples, RDCRC update circuit 511 is optional. In such an example, the output of DPCRC verification circuit 512 is output to input / output circuit 114 and host device 120. Furthermore, in such an example, the output of CRC read verification circuit 513 is coupled to encoder circuit 510. In examples including RDCRC update circuit 511, RDCRC update circuit 511 is coupled to the output of CRC read verification circuit 513 and the output of DPCRC verification circuit 512.

[0080] The CRC read verification circuit 513 generates signal 534 from signal 533. Signal 534 includes a CRC code (e.g., CRC data) with one or more bits. In one example, signal 533 has 164 symbols, and signal 534 has 18 bits of CRC data. Signal 534 is output by the CRC read verification circuit 513.

[0081] The RDCRC update circuit 511 receives signal 534 from the CRC read verification circuit 513. Additionally, the RDCRC update circuit 511 receives an error signal 538 from the DPCRC verification circuit 512. The RDCRC update circuit 511 updates signal 534 based on the value of error signal 538 (e.g., regardless of whether error signal 538 indicates an error). For example, if error signal 538 indicates an error (e.g., has a value of one or zero), the RDCRC update circuit 511 updates (e.g., changes) one or more bit values ​​within signal 534. Furthermore, if error signal 538 does not indicate an error (e.g., has a value of zero or one), the RDCRC update circuit 511 does not update (e.g., does not change) one or more bit values ​​in signal 534. Changing bit values ​​includes changing a bit value from zero to one or from one to zero.

[0082] The signal 535 output by the RDCRC update circuit 511 is received by the encoder circuit 510. The encoder circuit 510 generates the signal 536 from the signal 535. The encoder circuit 510 encodes the bits in the signal 535 into symbols to generate the signal 535.

[0083] Signals 535 and 533 are combined to generate signal 537, which is output to input / output circuitry 114 and then to host device 120. To detect errors within the received signal 539, host device 120 (e.g., memory controller circuitry 122) generates a CRC code from signal 539. If signal 534 is updated to indicate that DPCRC check circuitry 512 has detected an error, then signal 537 (or 538) differs from signals 533 and 534. Therefore, the CRC code generated by the host from signal 539 differs from the CRC code of signal 534 generated from signal 533. Host device 120 determines that an error exists within signal 539 because the CRC code generated from signal 539 differs from the CRC code of signal 534 generated from signal 533. In one example, host device 120 performs error checking by generating a CRC code from signal 539. Based on the CRC code not matching the expected CRC code (e.g., the CRC code of signal 534), host device 120 indicates an error.

[0084] Signal 539 is output as a PAM-3 signal. In other examples, signal 539 may have more or fewer three levels, or a different communication protocol than pulse amplitude modulation.

[0085] Figure 5B Examples Figure 1 An example block diagram of the read data path circuit 550 of the memory system 100. The read data path circuit 550 is... Figure 1 The data path circuit 116 is a part of the memory device 110. The read data path circuit 550 is included within the memory device 110. The read data path circuit 550 may be included in an IC device and / or die shared with the core circuit 112 and / or the input / output circuit 114. The read data path circuit 550 transmits data signals received from the core circuit 112 to the input / output circuit 114 and the host device 120 (e.g., the memory controller circuit 122 of the host device 120) based on a read command issued by the host device 120.

[0086] The data path circuit 550 is configured to be similar to Figure 5A The data read path circuit 500. For example, the data read path circuit 550 includes encoder circuits 510, 514, 515, and 516, a read CRC (RDCRC) update circuit 511, a DPCRC check circuit 512, a CRC read check circuit 513, a descrambler circuit 517, an on-die ECC circuit 518, and a DPCRC generator circuit 519. Figure 5ACompared to the read data path circuit 500, the read data path circuit 550 further includes decoder circuits 540 to 542 and a scrambler circuit 543. Furthermore, the inputs of the decoder circuits 540 to 542 are coupled to the outputs of the encoder circuits 514 to 516. The input of the scrambler circuit 543 is coupled to the outputs of the decoder circuits 540 to 541, and the input of the DPCRC check circuit 512 is coupled to the outputs of the scrambler circuit 543 and the decoder circuit 542. In one or more examples, the DPCRC check circuit 512 and the DPCRC generator circuit 519 are used for the data path CRC circuit (e.g., ...). Figure 1 (Data path CRC circuit 118).

[0087] Decoder circuit 540 receives signal 544, which includes a first portion of the symbols of signal 533, and decodes the symbols of signal 544 to generate signal 547, which includes one or more bits. Decoder circuit 541 receives signal 545, which includes a second portion of the symbols of signal 533, and decodes the symbols of signal 545 to generate signal 548, which includes one or more bits. Decoder circuit 542 receives signal 546, which includes a third portion of the symbols of signal 533, and decodes the symbols of signal 546 to generate signal 549, which includes one or more bits. In one example, the number of symbols in signal 544 is greater than the number of symbols in signal 545, and the number of symbols in signal 545 is greater than the number of symbols in signal 546. Furthermore, the number of bits in signal 547 is greater than the number of bits in signal 548, and the number of bits in signal 548 is greater than the number of bits in signal 549. In one example, signal 544 includes 161 symbols, signal 545 includes 2 symbols, and signal 546 includes one symbol. In addition, signal 547 includes 253 bits, signal 548 includes 3 bits, and signal 549 includes 2 bits. Signal 549 includes a toxicity bit and a severity bit.

[0088] Signals 547 and 548 are received by scrambler circuit 543, which scrambles the bits of signals 547 and 548 to generate signal 551. In one example, signals 547 and 548 are combined before or after being received by scrambler circuit 543. Signal 551 is received by DPCRC check circuit 512.

[0089] The DPCRC check circuit 512 also receives signal 549 and error check signal 532. The DPCRC check circuit 512 generates an error check signal from signals 551 and 549, and compares this error check signal with error check signal 532 to determine whether an error exists in the corresponding data signal of the read data path circuit 550. In one example, the DPCRC check circuit 512 generates an error check signal with one or more parity bits. In another example, the DPCRC check circuit 512 generates an error check signal with one or more CRC codes. As described above, the DPCRC check circuit 512 outputs an error signal 538 to the host device 120 (e.g., via input / output circuit 114) and / or outputs an error signal 538 to the RDCRC update circuit 511.

[0090] Figure 6 A flowchart illustrating a method 600 for determining errors within a data path circuit, based on one or more examples, is shown. In one example, method 600 consists of... Figure 2A Write data path circuit 200 or Figure 2B The write data path circuit 270 is executed.

[0091] At 610 of method 600, the first parity bit is determined based on the data signal. In one example, the DPCRC generator circuit (e.g., Figure 2A or Figure 2B The DPCRC generator circuit 224 determines the error check signal 236 (e.g., parity bit) based on signal 231, as described above. Figure 2A and / or Figure 2B As described. In one example, 610 of method 600 is optional. For example, 610 of method may be omitted from method 600. In this example, the first parity bit is determined outside the DPCRC generator circuitry. For example, the first parity bit may be received from a host device (e.g., host device 120) or another device or circuit element outside the DPCRC generator circuitry. The first parity bit may be received as part of a data signal or another signal provided (e.g., by the host device or another device or circuit element outside the DPCRC generator circuitry) to the data path circuitry.

[0092] At 620 of method 600, the second parity bit is determined based on the second signal and the poison bit. In one example, the DPCRC check circuit (e.g., Figure 2A or Figure 2B The DPCRC check circuit 226 determines one or more parity bits based on the poison bit 244 and the signal 243, as described above. Figure 2A and / or Figure 2B As described.

[0093] At 630 of method 600, a first error is detected in the second signal based on the first parity bit and the second parity bit. In one example, a DPCRC check circuit (e.g., Figure 2A or Figure 2B The DPCRC check circuit 226 detects errors based on the parity bit, as mentioned above. Figure 2A and / or Figure 2B As described.

[0094] At 640 of method 600, the output includes a first error signal indicating the first error. In one example, the path data circuit is written (e.g., ...). Figure 2A Write data path circuit 200 or Figure 2B The write data path circuit 270) outputs an error signal 251, as mentioned above regarding... Figure 2A and / or Figure 2B As described.

[0095] Figure 7 A flowchart illustrating a method 700 for determining errors within a data path circuit, based on one or more examples, is shown. In one example, method 700 consists of... Figure 5A The data reading path circuit 500 or Figure 5B The write data path circuit 570 is executed.

[0096] At 710 of method 700, the first parity bit is determined based on the first signal, the poison bit, and the severity bit. In one example, the DPCRC generator circuit (e.g., Figure 5A or Figure 5B The DPCRC generator circuit 519 determines the error check signal 532 (e.g., one or more parity bits) based on signal 520, poison bit 524, and severity bit 525, as described above. Figure 5A and / or Figure 5B As described. In one example, at least a portion of 710 of method 700 is optional and may be omitted from method 700. For example, the first parity bit may be determined and provided to the data path circuit outside the data path circuit. In one example, the first parity bit is determined outside the DPCRC generator circuit. For example, the first parity bit may be received from a host device (e.g., host device 120), core circuitry, or another device or circuit element outside the DPCRC generator circuitry. The first parity bit may be received as part of a data signal or another signal provided (e.g., provided by the host device, core circuitry, or another device or circuit element outside the DPCRC generator circuitry) to the data path circuitry.

[0097] At 720 of method 700, the second parity bit is determined based on the second signal. In one example, the DPCRC check circuit (e.g., Figure 5A or Figure 5B The DPCRC check circuit 512 determines one or more parity bits based on signal 533, as described above. Figure 5A and / or Figure 5B As described.

[0098] At 730 of method 700, a first error is detected in the second signal based on the first parity bit and the second parity bit. In one example, a DPCRC check circuit (e.g., Figure 5A or Figure 5B The DPCRC check circuit 512 detects errors based on the parity bit, as mentioned above. Figure 5A and / or Figure 5B As described.

[0099] At 740 of method 700, the output includes a first error signal indicating the first error. In one example, the path data reading circuit (e.g., Figure 5A The data reading path circuit 500 or Figure 5B The data path reading circuit 550 outputs an error signal 538, as mentioned above. Figure 5A and / or Figure 5B As described.

[0100] The above-described technology may also be described in one or more of the following non-limiting embodiments.

[0101] Example 1. A memory device, the memory device comprising: a core circuit including memory cells; and a write data path circuit coupled to the core circuit and configured to: determine a second parity bit based on a second signal and a poison bit, wherein the second signal and the poison bit are determined by processing a first signal; detect a first error in the second signal based on the first parity bit and the second parity bit; and output a first error signal including the first error.

[0102] Example 2. The memory device according to Example 1, wherein the data path circuit is further configured to determine the first parity bit based on the first signal.

[0103] Example 3. The memory device according to Example 1, wherein the write data path circuit is further configured to: detect a second error in the first signal based on a comparison of the first signal with a cyclic redundancy check (CRC) code; and output a second error signal including the second error.

[0104] Example 4. The memory device according to Example 3, wherein the write data path circuit is further configured to combine the first error signal with the second error signal to generate an output error signal, wherein the output error signal is output to the host device.

[0105] Example 5. The memory device according to Example 4, wherein the host device is configured to: receive an output error signal including the first error signal; and determine, based on timing information associated with a write data path, that the output error signal includes the first error signal.

[0106] Example 6. The memory device according to Example 1, wherein the write data path circuitry includes: a first decoder circuitry configured to generate a CRC value based on a first symbol of an input signal received from a host device, wherein the input signal includes a second symbol associated with data to be written to the core circuitry.

[0107] Example 7. The memory device according to Example 6, wherein the write data path circuit further includes: a CRC write check circuit configured to detect a third error in the input signal based on the second symbol and the CRC value; and a data path CRC (DPCRC) generator circuit configured to receive a first signal including the second symbol of the input signal, and determine the first parity bit based on the second symbol of the input signal.

[0108] Example 8. The memory device according to Example 7, wherein the write data path circuit further includes: a decoder circuit configured to generate a data signal and the poison bit from the second symbol of the input signal; a scrambler circuit configured to generate the second signal based on the data signal; and an on-die error correction code (ECC) circuit configured to detect a fourth error in the second signal based on the poison bit.

[0109] Example 9. The memory device according to Example 8, wherein the write data path circuit further includes: a DPCRC check circuit, the DPCRC check circuit being configured to: receive the second signal, the poison bit and the severity bit from the scrambler circuit; determine the second parity bit based on the second signal, the poison bit and the severity bit; and output the first error signal to the host device.

[0110] Example 10. The memory device according to Example 9, wherein the write data path circuit further includes: a descrambler circuit and an encoder circuit, the encoder circuit being configured to receive the second signal, the poison bit, and the severity bit from the descrambler circuit, and determine a third signal and a fourth signal; and a DPCRC check circuit, the DPCRC check circuit being configured to: receive the third signal and the fourth signal from the descrambler circuit and the encoder circuit; determine the second parity bit from the third signal and the fourth signal; and output the first error signal to the host device.

[0111] Example 11. A memory device comprising: a core circuit including memory cells; and a read data path circuit coupled to the core circuit and configured to: determine a first parity bit based on a first signal, a poison bit, and a severity bit, wherein the poison bit and the severity bit are determined according to the first signal; detect a first error in a second signal based on the first parity bit and a second parity bit, wherein the second signal is generated by processing the first signal; and output a first error signal including the first error.

[0112] Example 12. The memory device according to Example 11, wherein the read data path circuit is further configured to determine the second parity bit based on the second signal.

[0113] Example 13. The memory device according to Example 11, wherein the read data path circuit is further configured to: generate a cyclic redundancy check (CRC) code based on the second signal; and update the CRC code based on the first error signal.

[0114] Example 14. The memory device according to Example 13, wherein the read data path circuit is further configured to output the first error signal to the host device.

[0115] Example 15. The memory device according to Example 11, wherein the read data path circuitry includes: a descrambler circuit configured to generate a third signal from the first signal; a first encoder circuit and a second encoder circuit configured to generate a first symbol signal and a second symbol signal from the third signal; an error correction code (ECC) circuit configured to determine the severity bit; a third encoder circuit configured to generate a third symbol signal from the poison bit and the severity bit, wherein the first symbol signal, the second symbol signal, and the third symbol signal are combined into the second signal; and a CRC circuit configured to generate a CRC code from the third symbol signal.

[0116] Example 16. The memory device according to Example 15, wherein the read data path circuit further includes: a data path CRC (DPCRC) generator circuit configured to receive the first signal, the poison bit, and the severity bit, and determine the first parity bit based on the first signal, the poison bit, and the severity bit; and a DPCRC verification circuit configured to: receive the first parity bit and the second signal; determine the second parity bit based on the second signal; detect the first error in the second signal based on a comparison between the first parity bit and the second parity bit; and output the first error signal.

[0117] Example 17. The memory device according to Example 16, wherein the read data path circuit further includes: a read (CRC) update circuit, the read (CRC) update circuit being configured to receive the CRC code and the first error signal and update the value of the CRC code based on the first error signal, and wherein the read data path circuit is further configured to output an output signal to a host device, the output signal including the updated CRC code, wherein the host device is configured to detect an error in the output signal based on the CRC code generated from the output signal.

[0118] Example 18. The memory device according to Example 14, wherein the read data path circuit further includes: a decoder circuit and a scrambler circuit configured to receive the first signal, the poison bit, and the severity bit, and generate a third signal and a fourth signal; a data path CRC (DPCRC) generator circuit configured to receive the third signal and the fourth signal, and determine the first parity bit based on the third signal and the fourth signal; and a DPCRC check circuit configured to: receive the first parity bit and the second signal; determine the second parity bit based on the second signal; detect the first error in the second signal based on a comparison between the first parity bit and the second parity bit; and output the first error signal.

[0119] Example 19. A memory system comprising: a host device including memory controller circuitry; and a memory device coupled to the host device, the memory device including: a core circuit including memory cells; and a write data path circuit coupled to the core circuitry and configured to: determine a second parity bit from a second signal and a first poison bit, wherein the second signal and the first poison bit are determined by processing a first signal received from the memory controller circuitry; detect a first error within the second signal based on the first parity bit and the second parity bit; and output a first error signal including the first error to the host device.

[0120] Example 20. The memory system according to Example 19, wherein the memory device further includes: a read data path circuit coupled to the core circuit and configured to: determine a third parity bit based on a fifth signal, a second poison bit, and a second severity bit, wherein the second poison bit and the second severity bit are determined from a fourth signal; detect a second error within the fifth signal based on the third parity bit and the fourth parity bit; and output a second error signal including the second error to the host device.

[0121] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. A memory device, the memory device comprising: The core circuit includes a memory unit; and A write data path circuit, which is coupled to the core circuit and configured as follows: A second parity bit is determined from a second signal and a poison bit, wherein the second signal and the poison bit are determined by processing a first signal; The first error in the second signal is detected based on the first parity bit and the second parity bit. as well as The output includes a first error signal for the first error.

2. The memory device of claim 1, wherein the data path circuitry is further configured to determine the first parity bit based on the first signal.

3. The memory device of claim 1, wherein the write data path circuit is further configured to: The second error within the first signal is detected by comparing the first signal with the Cyclic Redundancy Check (CRC) code; and The output includes a second error signal for the second error.

4. The memory device of claim 3, wherein the write data path circuitry is further configured to combine the first error signal and the second error signal to generate an output error signal, wherein the output error signal is output to the host device.

5. The memory device of claim 4, wherein the host device is configured to: Receive an output error signal including the first error signal; and Based on timing information associated with the written data path, it is determined that the output error signal includes the first error signal.

6. The memory device of claim 1, wherein the write data path circuit comprises: A first decoder circuit is configured to generate a CRC value based on a first symbol of an input signal received from a host device, wherein the input signal includes a second symbol associated with data to be written to the core circuit.

7. The memory device of claim 6, wherein the write data path circuitry further comprises: A CRC write-verification circuit is configured to detect a third error in the input signal based on the second symbol and the CRC value. and A data path CRC (DPCRC) generator circuit is configured to receive a first signal including the second symbol of the input signal, and to determine the first parity bit based on the second symbol of the input signal.

8. The memory device of claim 7, wherein the write data path circuitry further comprises: A decoder circuit configured to generate a data signal and the poison bit from the second symbol of the input signal; A scrambler circuit configured to generate the second signal based on the data signal; and An on-die error correction code (ECC) circuit is configured to detect a fourth error within the second signal based on the poison bit.

9. The memory device of claim 8, wherein the write data path circuitry further comprises: DPCRC check circuit, wherein the DPCRC check circuit is configured as follows: Receive the second signal, the poison bit, and the severity bit from the scrambler circuit; The second parity bit is determined based on the second signal, the toxicity bit, and the severity bit; and The first error signal is output to the host device.

10. A memory device, the memory device comprising: The core circuit includes a memory unit; and A data read path circuit, coupled to the core circuit and configured as follows: A first parity bit is determined based on a first signal, a poison bit, and a severity bit, wherein the poison bit and the severity bit are determined according to the first signal; A first error is detected in a second signal based on the first parity bit and the second parity bit, wherein the second signal is generated by processing the first signal; and The output includes a first error signal for the first error.

11. The memory device of claim 10, wherein the read data path circuit is further configured to determine the second parity bit based on the second signal.

12. The memory device of claim 10, wherein the read data path circuit is further configured to: Generate a Cyclic Redundancy Check (CRC) code based on the second signal; and The CRC code is updated based on the first error signal.

13. The memory device of claim 10, wherein the read data path circuit comprises: A descrambler circuit, the descrambler circuit being configured to generate a third signal from the first signal; A first encoder circuit and a second encoder circuit are configured to generate a first symbol signal and a second symbol signal from the third signal. An error correction code (ECC) circuit, the error correction code (ECC) circuit being configured to determine the severity bit; A third encoder circuit is configured to generate a third symbol signal from the poison bit and the severity bit, wherein the first symbol signal, the second symbol signal and the third symbol signal are combined into the second signal; and A CRC circuit, configured to generate a CRC code from the third symbol signal.

14. The memory device of claim 13, wherein the read data path circuit further comprises: A data path CRC (DPCRC) generator circuit, configured to receive the first signal, the poison bit, and the severity bit, and determine the first parity bit based on the first signal, the poison bit, and the severity bit; and DPCRC check circuit, wherein the DPCRC check circuit is configured as follows: Receive the first parity bit and the second signal; The second parity bit is determined based on the second signal; The first error in the second signal is detected based on the comparison between the first parity bit and the second parity bit; as well as Output the first error signal.

15. The memory device of claim 11, wherein the read data path circuit further comprises: A decoder circuit and a scrambler circuit are configured to receive the first signal, the poison bit, and the severity bit, and generate a third signal and a fourth signal. and A data path CRC (DPCRC) generator circuit, configured to receive the third signal and the fourth signal, and determine the first parity bit based on the third signal and the fourth signal; and DPCRC check circuit, wherein the DPCRC check circuit is configured as follows: Receive the first parity bit and the second signal; The second parity bit is determined based on the second signal; The first error in the second signal is detected based on the comparison between the first parity bit and the second parity bit; as well as Output the first error signal.

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