A MOSFET device structure and method of fabricating the same

Abstract

This invention provides a MOSFET device structure and its fabrication method. The MOSFET device structure, from bottom to top, includes a substrate layer, a drain N-type electrode, and a bottom-up N-type electrode. + Type gallium nitride layer, first N ‑ Type-2 gallium nitride layer, second N ‑ Gallium nitride (GaN) layer, P-type GaN substrate and source N + Type-2 gallium nitride layer, second N ‑ Gallium nitride (GaN) layer, P-type GaN substrate and source N + The combined structure of the type gallium nitride layer has a trench structure arranged along the thickness direction, and in the position corresponding to the trench structure, the first N ‑ near the second N-type gallium nitride layer ‑ One side of the type gallium nitride layer has ion-implanted P + The well region also includes a source, drain, and gate, with the source located at source N. + At the gallium nitride layer, the drain is located at the drain N. + At the gallium nitride layer, the gate is located in the trench structure. The MOSFET device structure provided by this invention balances high voltage withstand capability with normal conduction characteristics, thereby improving the overall performance and reliability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology and relates to a MOSFET device structure and its fabrication method. Background Technology

[0002] Trench MOSFETs are widely used in power semiconductor devices due to their high channel density and low on-resistance. In traditional silicon-based trench MOSFET structures, the electric field distribution at the boundary between the drift region and the trench bottom is extremely uneven when the device is in the blocking state. Due to the curvature effect at the trench bottom, the electric field lines are severely concentrated here, forming significant electric field spikes. This electric field concentration effect makes the trench bottom the weakest region most susceptible to breakdown, limiting the device's breakdown voltage and severely impacting its long-term reliability.

[0003] To alleviate electric field concentration at the bottom of the trench, existing silicon-based technologies typically employ a structure that introduces a P-type implantation region (i.e., a P-pillar or P-type shielding layer) below the trench bottom. This P-type region forms a PN junction with the N-type drift region. Under reverse bias, the depletion region expands, effectively modulating the electric field distribution and reducing the electric field spike at the trench bottom. This, in turn, improves the device's breakdown voltage without significantly sacrificing on-resistance. This technology relies on mature ion implantation and high-temperature annealing activation processes, enabling high activation rates and high precision P-type doping in silicon materials.

[0004] Vertical gallium nitride (GaN) power devices offer higher breakdown voltage, smaller size, lower parasitic capacitance, and better switching efficiency compared to planar devices. They are also unaffected by surface conditions and possess avalanche breakdown capability. GaN trench MOSFETs are among the most mainstream GaN vertical transistors, boasting advantages such as high threshold voltage and high current density. However, for GaN-based MOSFET devices, it is difficult to directly form a p-well region through efficient ion implantation activation, unlike Si or SiC. This is primarily because the activation efficiency of P-type doping (e.g., magnesium Mg) in gallium nitride is extremely low, and the required activation temperature is extremely high (typically exceeding 1200℃). Conventional ion implantation followed by annealing is insufficient to achieve efficient and uniform P-type region activation. Furthermore, high-temperature annealing processes can cause irreversible damage to the material surface morphology and the formed heterojunction structure. Therefore, the technique of forming a P-type shielding layer at the bottom of the trench through ion implantation, as used in silicon (Si) or silicon carbide (SiC) based devices, cannot be directly adopted in GaN-based trench MOSFET structures.

[0005] To address the aforementioned issues with GaN devices, existing solutions typically involve ion implantation and activation on a conventional SBD epitaxial structure, followed by secondary epitaxy of p-GaN and N⁺-GaN, and then completing the conventional fabrication process for trench MOSFETs. However, if only secondary epitaxy of p-GaN and N⁺-GaN is performed... + -GaN, the strong depletion effect of the p-well makes it difficult for the device to form a continuous electron enrichment layer, cutting off the carrier transport path from the source region to the drift region, resulting in the device being unable to conduct normally.

[0006] Therefore, how to enable GaN-based trench MOSFET structures to balance high voltage withstand capability and normal conduction, thereby improving the overall performance and reliability of the devices, is a technical problem that urgently needs to be solved. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a MOSFET device structure and its fabrication method. The MOSFET device structure provided by the present invention, in the first N... - Based on the type gallium nitride layer, a second N-type layer was then set. - The p-type gallium nitride layer can provide an effective N-type conduction channel for the device while maintaining sufficient shielding of the electric field at the bottom of the trench from the p-well. This balances high voltage withstand capability with normal conduction characteristics, thereby improving the overall performance and reliability of the device.

[0008] To achieve this objective, the present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a MOSFET device structure, wherein the MOSFET device structure comprises, from bottom to top, a substrate layer, a drain N-type electrode, and a bottom-to-top layer. + Type gallium nitride layer, first N - Type-2 gallium nitride layer, second N - Gallium nitride (GaN) layer, P-type GaN substrate and source N + Gallium nitride layer,

[0010] The second N - Gallium nitride (GaN) layer, P-type GaN substrate and source N + The combined structure of the type gallium nitride layer has a trench structure arranged along the thickness direction, and at the position corresponding to the trench structure, the first N - near the second N-type gallium nitride layer - One side of the type gallium nitride layer has ion-implanted P + Type-shaped trap region;

[0011] The MOSFET device structure further includes a source, a drain, and a gate, with the source located at source N. + At the gallium nitride layer, the drain is located at the drain N. +At the gallium nitride layer, the gate is located at the trench structure.

[0012] Preferably, the substrate layer and the drain N + A buffer layer is also provided between the gallium nitride layers.

[0013] Optionally, the buffer layer can be a single-layer structure or a multi-layer composite structure.

[0014] Preferably, the substrate layer comprises a sapphire substrate and / or a gallium nitride substrate.

[0015] Preferably, the drain is located at the drain N. + The surface of the gallium nitride layer on the side away from the substrate layer.

[0016] Preferably, the first N - The thickness of the gallium nitride layer is ≥5μm.

[0017] Preferably, the P + The depth of the trap region is 300nm~600nm.

[0018] Preferably, the second N - The thickness of the gallium nitride layer is 300nm~600nm.

[0019] Preferably, the first N - The doping concentration of the type gallium nitride layer is greater than that of the second N-type layer. - Doping concentration of the gallium nitride layer.

[0020] Preferably, the groove width perpendicular to the thickness direction is smaller than the corresponding P. + Width of the trap region.

[0021] Preferably, the P + The trap region includes P-type pits implanted with Mg ions. + Type-shaped trap region.

[0022] Preferably, the source N + The gallium nitride layer has a through-hole disposed along its thickness direction, and the source electrode is located at the through-hole and extends to the source N. + The surface of the gallium nitride layer.

[0023] Preferably, a gate dielectric layer is further disposed between the gate and the trench structure.

[0024] Preferably, the MOSFET device structure further includes a passivation layer that covers the surface of all exposed gallium nitride layers.

[0025] In a second aspect, the present invention provides a method for fabricating a MOSFET device structure as described in the first aspect, the method comprising the following steps:

[0026] (1) Gallium nitride epitaxial growth is performed on one side of the substrate to form a drain N-type electrode that is stacked sequentially. + Type GaN layer and first N - Gallium nitride layer;

[0027] (2) For the first N - The type gallium nitride layer is far from the drain N + Ion implantation is performed on one side of the gallium nitride layer to form an ion-implanted P-type layer. + Type-shaped trap region;

[0028] (3) Formation of P + After the N-shaped well region, the second N-type well region is then sequentially processed. - Gallium nitride (GaN) layer, P-type GaN substrate and source N + Growth of gallium nitride layers;

[0029] (4) Along the thickness direction, corresponding to P + The location of the type-shaped well region is used for the second N-type well. - Gallium nitride (GaN) layer, P-type GaN substrate and source N + The slotted arrangement of the combined structure of gallium nitride layers forms a trench structure;

[0030] (5) At the source N + At the gallium nitride layer and drain N + The source, drain, and gate are fabricated at the gallium nitride layer and the trench structure, respectively, to obtain the MOSFET device structure.

[0031] Preferably, in step (1), a buffer layer is provided on one side surface of the substrate, and the epitaxial growth of gallium nitride is performed on the surface of the buffer layer.

[0032] Preferably, in step (2), the first N - The gallium nitride (GaN) layer is protected by a mask during ion implantation. After mask removal, an annealing protective layer is prepared at the ion implantation site, followed by annealing. After annealing, the protective layer is removed to form the P-type layer. + Type-shaped trap region.

[0033] Preferably, in step (4), the source N... + The gallium nitride layer is protected by a mask and then subjected to a trenching process.

[0034] Preferably, in step (5), after the source, drain and gate are all prepared, a passivation layer is prepared on all exposed gallium nitride layer surfaces of the device.

[0035] Preferably, in step (5), the source N... + The first etching process is performed on the p-type gallium nitride layer to expose the surface of the p-type gallium nitride substrate, and the first N-type gallium nitride layer is then etched. - Type-2 gallium nitride layer, second N - Gallium nitride (GaN) layer, P-type GaN substrate and source N + The gallium nitride layer undergoes a second etching process to expose the drain N-type electrode. + The surface of the gallium nitride layer.

[0036] Preferably, the source electrode is fabricated on the exposed P-type gallium nitride substrate surface, the gate dielectric layer is deposited first in the trench structure, and then the gate electrode is fabricated on the exposed drain N-type substrate surface. + The drain electrode is fabricated on the surface of the gallium nitride layer.

[0037] The numerical range described in this invention includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this invention will not exhaustively list all the specific point values ​​included in the range.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] (1) In the MOSFET device structure provided by the present invention, P + The type-N well region is located in the first N - In the type gallium nitride layer, a second N-type layer is then introduced. - A type of gallium nitride layer can maintain P + The trap region effectively shields the electric field at the bottom of the trench while providing an effective N-type conduction channel for the device, thus balancing high withstand voltage with normal conduction characteristics and improving the overall performance and reliability of the device.

[0040] (2) The preparation method provided by the present invention, in the formation of ion-implanted P + After the N-shaped well region, another layer of the second N-type well is then formed. - The fabrication of a type-3 gallium nitride layer, through the introduction of this film structure, can maintain p-type... + The trap effectively shields the electric field at the bottom of the trench while providing an effective N-type conduction channel for the device, thus balancing high withstand voltage with normal conduction characteristics and improving the overall performance and reliability of the device. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a MOSFET device structure provided in one embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of step (1) of the fabrication process in the fabrication method of the MOSFET device structure provided in one embodiment of the present invention.

[0043] Figure 3 , Figure 4 and Figure 5 These are schematic diagrams of step (2) of the fabrication process in the fabrication method of the MOSFET device structure provided in one embodiment of the present invention.

[0044] Figure 6 This is a schematic diagram of step (3) of the fabrication process in the fabrication method of the MOSFET device structure provided in one embodiment of the present invention.

[0045] Figure 7 This is a schematic diagram of step (4) of the fabrication process in the fabrication method of the MOSFET device structure provided in one embodiment of the present invention.

[0046] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 This is a schematic diagram of step (5) of the fabrication process in the fabrication method of the MOSFET device structure provided in one embodiment of the present invention.

[0047] Wherein, 1-substrate layer, 2-buffer layer, 3-drain N + Type 4 gallium nitride layer, 4-first N - Gallium nitride layer, 5-P + Type-2 trap region, 6-second N - 7-P type gallium nitride layer, 8-P type gallium nitride substrate, 8-source N + Gallium nitride layer, 9-trench structure, 10-drain, 11-source, 12-gate, 13-gate dielectric layer, 14-passivation layer. Detailed Implementation

[0048] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0049] The "range" disclosed in this invention can be defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific range. This type of range definition can include or exclude endpoints; any endpoint can be independently included or excluded, and they can be arbitrarily combined, meaning any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60~120 and 80~110 are listed for specific parameters, it is understood that ranges of 60~110 and 80~120 are also expected. Furthermore, if minimum range values ​​1 and 2 are listed, and maximum range values ​​3, 4, and 5 are also listed, then the following ranges are all expected: 1~3, 1~4, 1~5, 2~3, 2~4, and 2~5. In this invention, unless otherwise stated, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0~5" indicates that all real numbers between "0" and "5" have been listed in this article; "0~5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is described as an integer ≥2, it is equivalent to listing integers such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc. For instance, when a parameter is described as an integer selected from "2~10", it is equivalent to listing the integers 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0050] In this invention, "a combination of at least two" refers to a quantity greater than or equal to two, unless otherwise specified. For example, "any combination of one or at least two" means one or more or more items. It can be understood that when referring to "a combination of at least two," it refers to any suitable combination of multiple items, that is, a combination of "at least two" items carried out in a manner that does not conflict with and enables the implementation of this invention.

[0051] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0052] The term "embodiment" as used in this invention means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment or implementation of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0053] Those skilled in the art will understand that the order in which the steps are written in the methods of the various embodiments does not imply a strict execution order. The detailed execution order of each step should be determined by its function and possible internal logic. Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, but are preferably performed sequentially. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the method may also include step (c), meaning that step (c) can be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0054] In this invention, open-ended technical features or solutions described using terms such as "comprising" do not exclude additional members beyond those listed unless otherwise specified. They can be considered as providing both closed-ended features or solutions comprised of the listed members and open-ended features or solutions that include additional members beyond the listed members. For example, A includes a1, a2, and a3. Unless otherwise specified, it may also include other members or exclude additional members. This can be considered as providing both technical features or solutions where "A is composed of a1, a2, and a3" or "A is selected from a1, a2, and a3," and technical features or solutions where "A includes not only a1, a2, and a3, but also other members."

[0055] In this invention, unless otherwise specified, the features or solutions corresponding to "and / or" include any one of two or more of the related listed items, as well as any and all combinations of the related listed items. These arbitrary and all combinations include any two related listed items, any more related listed items, or a combination of all related listed items. For example, "A and / or B" represents a group consisting of A, B, and "a combination of A and B". "Containing A and / or B" can mean "containing A, containing B, and containing A and B", or "containing A, containing B, or containing A and B", and can be appropriately understood according to the context.

[0056] In this invention, the terms "first aspect," "second aspect," "third aspect," "fourth aspect," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first," "second," "third," "fourth," etc., serve only as a non-exhaustive enumeration and should be understood not to constitute a closed limitation on the quantity.

[0057] In this invention, "optional" means that something is optional, that is, it refers to either "with" or "without". If there are multiple "optional" options in a technical solution, unless otherwise specified, and there are no contradictions or mutual constraints, then each "optional" option is independent.

[0058] In this invention, "room temperature" generally refers to 4℃~35℃, and can refer to 20℃±5℃. In some embodiments of this invention, room temperature refers to 20℃~30℃.

[0059] In one implementation, such as Figure 1 As shown, the present invention provides a MOSFET device structure, which, from bottom to top, includes a substrate layer 1, a drain layer N, and so on. + Type 3 gallium nitride layer, first N - Type 4 gallium nitride layer, second N - Gallium nitride layer 6, gallium nitride substrate 7, and source N + Type 8 gallium nitride layer,

[0060] The second N - Gallium nitride layer 6, gallium nitride substrate 7, and source N + The combined structure of the type gallium nitride layer 8 has a trench structure 9 disposed along the thickness direction, and at the position corresponding to the trench structure 9, the first N - Gallium nitride layer 4 near the second N - The type gallium nitride layer 6 has ion-implanted P-type gallium nitride on one side. + Type 5 trap region;

[0061] The MOSFET device structure further includes a source 11, a drain 10, and a gate 12, wherein the source 11 is located at source N. + At the gallium nitride layer 8, the drain 10 is located at the drain N. + The gate 11 is located at the trench structure 9, at the gallium nitride layer 3.

[0062] It should be noted that the first N in this invention - Type GaN layer and second N - The gallium nitride layer is a two-layer stacked film structure, not a monolithic structure.

[0063] In existing technical solutions, directly in the first N - A p-type gallium nitride substrate and a source N-type gallium nitride layer are disposed on the surface of the p-type gallium nitride layer. + Type-P gallium nitride layer, i.e. + The p-type well region is in direct contact with the p-type gallium nitride substrate, which leads to the p-type well being directly in contact with the substrate. +The strong depletion effect in the well region makes it difficult for the device to form a continuous electron enrichment layer, cutting off the carrier transport path from the source region to the drift region, making it difficult for the device to conduct normally.

[0064] This invention uses P + The trap region is set in the first N - Within the gallium nitride layer, a second N-type ... - The type of gallium nitride layer decouples the trench bottom electric field modulation function from the conduction channel formation function. Specifically, the second N... - Gallium nitride layers can effectively isolate P + The strong depletion effect of the trap region on the channel formation region should be avoided. + When the well region is in direct contact with the P-type gallium nitride substrate, it interrupts the electron transport path from the source region to the drift region, thus facilitating the formation of a continuous electron-rich layer under gate bias and ensuring normal device conduction. Simultaneously, the P-type well region located at the bottom of the well... + The trap region can still effectively shield the electric field at the bottom of the trench, in conjunction with the second N - The gallium nitride layer forms a smoother longitudinal potential distribution, reduces the local electric field concentration at the bottom corner of the trench, reduces the electric field stress of the gate dielectric, and improves the device's breakdown voltage and gate reliability, thus balancing high breakdown voltage and normal conduction characteristics, and improving the overall performance and reliability of the device.

[0065] In some embodiments, the substrate layer 1 and the drain N + A buffer layer 2 is also provided between the gallium nitride layers 3.

[0066] In this invention, in order to improve the lattice matching parameters between the substrate layer and the gallium nitride layer, a buffer layer is provided between the two. The buffer layer acts as an intermediate bridge, absorbing the stress caused by lattice mismatch and reducing dislocation defects through gradient gradation or low-temperature nucleation layer; it can also isolate impurities in the substrate from diffusing into the active region of the device.

[0067] It is understood that the present invention does not limit the specific material and thickness of the buffer layer. Without violating the overall technical concept of the present invention, any conventional material that can be used as a buffer layer and the corresponding thickness range are applicable to the present invention.

[0068] Optionally, the buffer layer can be a single-layer structure or a multi-layer composite structure.

[0069] Optionally, the material of the buffer layer includes at least one of AlN, CaN, or AlCaN. The above materials can be used as a single layer material or as a gradient layer composite material. Those skilled in the art can make adaptive selections and adjustments according to actual needs, and the material of the buffer layer is an undoped material.

[0070] Optionally, the thickness of the buffer layer is 10nm~100μm, such as 10nm, 50nm, 100nm, 500nm, 1μm, 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm or 100μm.

[0071] In some embodiments, the substrate layer 1 includes a sapphire substrate and / or a gallium nitride substrate.

[0072] In some embodiments, the present invention does not specifically limit the thickness of the substrate layer; conventional substrate parameters applicable to gallium nitride-based MOSFET device structures are also applicable to the present invention.

[0073] For example, the thickness of the substrate layer is 100μm to 1500μm, such as 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, 1100μm, 1200μm, 1300μm, 1400μm or 1500μm.

[0074] In some embodiments, the drain 10 is located at the drain N. + The surface of the gallium nitride layer 3 away from the substrate layer 1.

[0075] In some implementations, the first N - The thickness of the gallium nitride layer 4 is ≥5μm, such as 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 25μm or 30μm, etc.

[0076] In some implementations, the first N - The doping concentration of the type gallium nitride layer 4 is greater than that of the second N-type layer. - The doping concentration of the gallium nitride layer 6.

[0077] It is understood that the N-type gallium nitride layer in this invention can be doped with silicon.

[0078] And regulating the first N - Type gallium nitride layer and the second N - The doping concentrations of the gallium nitride layers are different, and the second N-type layer... - The lower doping concentration of the gallium nitride layer can improve the breakdown voltage of the device without affecting or only slightly affecting the conduction characteristics.

[0079] Example, but not limitation, the first N - The doping concentration of the gallium nitride layer 4 can be 6 × 10⁻⁶. 15 cm -3 ~10×10 15 cm -3 For example, 6×10 15 cm -3 7×10 15 cm -3 8×10 15 cm -3 9×10 15 cm -3 Or 10×10 15 cm -3 wait.

[0080] Furthermore, the second N - The doping concentration of the type gallium nitride layer 6 is higher than that of the first N-type layer. - The doping concentration of the gallium nitride layer 4 is low, at 0.5 × 10⁻⁶. 15 cm -3 ~3.5×10 15 cm -3 .

[0081] In some implementations, the P + The depth of the well region 5 is 300nm~600nm, such as 300nm, 350nm, 400nm, 450nm, 500nm, 550nm or 600nm.

[0082] It is understood that P in this invention + The depth of the trap region is P. + The thickness of this trap region structure is also the actual implantation depth of ion implantation.

[0083] In the MOSFET device structure of the present invention, the P + The depth of the well region affects the effectiveness of electric field shielding and the resistance of the junction field-effect transistor. A depth range of 300nm to 600nm can ensure effective shielding of the electric field without significantly increasing the resistance of the junction field-effect transistor.

[0084] In some implementations, the second N - The thickness of the gallium nitride layer 6 is 300nm~600nm, such as 300nm, 350nm, 400nm, 450nm, 500nm, 550nm or 600nm.

[0085] In this invention, the second N -By controlling the thickness of the gallium nitride (GaN) layer to 300nm~600nm, it is more conducive to achieving effective N-type conduction, and further enhances the performance of P-type conduction. + The electric field shielding effect of the trap region significantly improves the overall performance and reliability of the device.

[0086] In some embodiments, the groove structure 9 has a groove width perpendicular to the thickness direction that is smaller than the corresponding P. + The width of the trap region 5.

[0087] In order to further improve P + The electric field shielding effect of the trap region on the trench structure allows the trench width perpendicular to the thickness direction to be smaller than the corresponding P. + The width of the P+ type well region is important; however, controlling this width can lead to a significant strong depletion effect in the P+ type well region, making it difficult for the device to form a continuous electron-rich layer, cutting off the carrier transport path from the source region to the drift region, and causing the device to fail to conduct properly. Therefore, the second N in this invention... - The introduction of the gallium nitride layer effectively solved the above problems.

[0088] In some implementations, the P + Type 5 trap region includes P ions implanted with Mg ions. + Type-shaped trap region.

[0089] In this invention, P formed by Mg ion implantation is used. + The trap region can better achieve a uniform distribution of the electric field and improve the effect of electric field shielding.

[0090] In some implementations, the source N + The gallium nitride layer 8 has a through-hole disposed along the thickness direction, and the source electrode 11 is located at the through-hole and extends to the source electrode N. + The surface of the type 8 gallium nitride layer.

[0091] In some embodiments, a gate dielectric layer 13 is further disposed between the gate 12 and the trench structure 9.

[0092] In some embodiments, the MOSFET device structure further includes a passivation layer 14 that covers the surface of all exposed gallium nitride layers.

[0093] The passivation layer in this invention can ensure electrical isolation between the gate and the source and drain metals, prevent short circuits, and also serve as a stress buffer layer to reduce the risk of mechanical failure of the device during temperature cycling or power cycling.

[0094] It should be noted that, apart from the above-mentioned feature limitations, the MOSFET device structure provided by this invention does not specifically limit other details such as film thickness and structural material. Under the premise of not violating the overall technical concept of this invention, conventional technical solution details applicable to MOSFET device structures are also applicable to this invention.

[0095] Example, but not limitation, of the drain N + The thickness of the gallium nitride layer is 1000nm~2000nm, such as 1000nm, 1100nm, 1200nm, 1300nm, 1400nm, 1500nm, 1600nm, 1700nm, 1800nm, 1900nm or 2000nm, etc.

[0096] For example, but not limitingly, the thickness of the p-type gallium nitride substrate is 300nm to 500nm, such as 300nm, 350nm, 400nm, 450nm or 500nm.

[0097] Example, but not limitation, of the source N + The thickness of the gallium nitride layer is 150nm~250nm, such as 150nm, 200nm or 250nm.

[0098] For example, but not limitingly, the material of the gate dielectric layer includes aluminum oxide (Al2O3) and / or silicon dioxide (SiO2), and the coverage thickness of the gate dielectric layer is 50nm to 150nm, such as 150nm, 200nm or 250nm.

[0099] For example, but not in a limiting sense, the material of the gate includes at least one of Ti, Al, Ni or Au.

[0100] For example, but not in a limiting sense, the materials of the source and the drain are each independently selected from metallic materials, including but not limited to at least one of Ti, Al, Ni or Au.

[0101] In one implementation, such as Figures 2 to 13 As shown, the present invention provides a method for fabricating a MOSFET device structure as described in the above embodiments, the method comprising the following steps:

[0102] (1) such as Figure 2 As shown, gallium nitride epitaxial growth is performed on one side of the substrate to form sequentially stacked drain N-type electrodes. + Type 3 gallium nitride layer and first N - Type 4 gallium nitride layer;

[0103] (2) For the first N - Type 4 gallium nitride layer is located away from the drain N.+ Ion implantation is performed on one side of the gallium nitride layer 3 to form an ion-implanted P-type layer. + Type 5 trap region;

[0104] (3) such as Figure 6 As shown, P is formed + After the N-shaped well region, the second N-type well region is then sequentially processed. - Gallium nitride layer 6, gallium nitride substrate 7, and source N + Growth of type 8 gallium nitride layer ( Figure 6 );

[0105] (4) Along the thickness direction, corresponding to P + At position 5 of the trap region, perform the second N... - Gallium nitride layer 6, gallium nitride substrate 7, and source N + The slotted arrangement of the combined structure of the gallium nitride layer 8 forms a trench structure 9;

[0106] (5) At the source N + Three gallium nitride layers and N-type drain electrode + The source 11, drain 10, and gate 12 are fabricated at 8 locations of the gallium nitride layer and 9 locations of the trench structure, respectively, to obtain the MOSFET device structure.

[0107] The preparation method provided by this invention involves forming ion-implanted P + After the N-shaped well region, another layer of the second N-type well is then formed. - The fabrication of a type-3 gallium nitride layer, through the introduction of this film structure, can maintain p-type... + The trap effectively shields the electric field at the bottom of the trench while providing an effective N-type conduction channel for the device, thus balancing high withstand voltage with normal conduction characteristics and improving the overall performance and reliability of the device.

[0108] It is understood that in the preparation method provided by the present invention, the corresponding film structure and electrode structure, etc., can be prepared by deposition method, and can be supplemented by masking method and etching method. That is, the present invention does not impose additional limitations on the specific preparation method. Preparation methods known to those skilled in the art within a reasonable scope without violating the overall technical concept of the present invention are applicable to the present invention.

[0109] In some embodiments, in step (1), a buffer layer 2 is provided on one side surface of the substrate, and the gallium nitride epitaxial growth is performed on the surface of the buffer layer 2.

[0110] In some implementations, such as Figure 3 , Figure 4 and Figure 5 As shown, in step (2), for the first N - The type 4 gallium nitride layer is protected by a mask. Figure 3Ion implantation was performed, and after removing the mask, an annealing protective layer was prepared at the ion implantation site. Figure 4 Then, annealing is performed. After annealing, the protective layer is removed to form P. + Type 5 trap region (i.e.) Figure 5 ).

[0111] In the preparation method of the present invention, after determining the corresponding well depth, the specific details of ion implantation can be adaptively selected and adjusted according to actual needs.

[0112] For example, but not limitingly, the ion implanted is a Mg ion, and the ion implantation can be performed in a single operation or in multiple stages. The energy of each implantation during the ion implantation process is independently between 45 keV and 500 keV, for example, 45 keV, 50 keV, 80 keV, 100 keV, 130 keV, 150 keV, 180 keV, 200 keV, 230 keV, 250 keV, 280 keV, 300 keV, 330 keV, 350 keV, 380 keV, 400 keV, 430 keV, 450 keV, 480 keV, or 500 keV, etc. The dose of each ion implantation is independently 5 × 10⁻⁶. 13 cm -2 ~5×10 14 cm -2 For example, 5×10 13 cm -2 6×10 13 cm -2 7×10 13 cm -2 8×10 13 cm -2 9×10 13 cm -2 1×10 14 cm -2 2×10 14 cm -2 3×10 14 cm -2 4×10 14 cm -2 Or 5×10 14 cm -2 wait.

[0113] For example, but not limitingly, the mask in step (2) includes a SiO2 mask.

[0114] For example, but not limitingly, the annealing protective layer includes an aluminum nitride (AlN) layer.

[0115] For example, but not limitingly, the annealing temperature is 1200℃~1400℃, such as 1200℃, 1300℃ or 1400℃, and the annealing time is 45min~90min, such as 45min, 50min, 60min, 70min, 80min or 90min.

[0116] In some implementations, in step (4), such as Figure 7 As shown, for source N + The type 8 gallium nitride layer is protected by a mask and undergoes a trenching process.

[0117] In some implementations, such as Figure 13 As shown, in step (5), after the source 11, drain 10 and gate 12 are all prepared, a passivation layer 14 is prepared on all exposed gallium nitride layer surfaces of the device.

[0118] In some embodiments, the passivation layer 14 includes a silicon dioxide passivation layer.

[0119] In some implementations, in step (5), such as Figure 8 and Figure 9 As shown, for source N + The first etching process is performed on the p-type gallium nitride layer 8 to expose the surface of the p-type gallium nitride substrate layer 7, and the first N-type gallium nitride layer 8 is then etched. - Type 4 gallium nitride layer, second N - Gallium nitride layer 6, gallium nitride substrate 7, and source N + The gallium nitride layer 8 undergoes a second etching process to expose the drain N. + The surface of type 6 gallium nitride layer.

[0120] In some implementations, such as Figure 10 , Figure 11 and Figure 12 As shown, the source 11 is fabricated on the exposed P-type gallium nitride substrate 7. The gate dielectric layer 13 is first deposited in the trench structure 5, followed by the fabrication of the gate 12. The exposed drain N... + Drain electrode 10 is fabricated on the surface of gallium nitride layer 3.

[0121] It should be noted that the specific preparation details of the above-mentioned structures in the preparation method provided by the present invention, and the formation process of the structures can be prepared by deposition method. The deposition parameters can be selected and adjusted according to different materials and thickness values. The present invention will not elaborate further.

[0122] Example 1

[0123] This embodiment provides a MOSFET device structure, which, based on the device structure provided in the above embodiment, specifically includes:

[0124] The MOSFET device structure, from bottom to top, includes a substrate layer 1, a buffer layer 2, and a drain N. + Type 3 gallium nitride layer (1000nm), first N - Gallium nitride layer 4 (6000 nm, doping concentration 8 × 10⁻⁶) 15 cm -3 ), the second N - Type 6 gallium nitride layer (doping concentration of 5×10⁶) 15 cm -3 ), P-type gallium nitride substrate 7 (400nm) and source N + Gallium nitride layer 8 (200nm);

[0125] The second N - The thickness of the gallium nitride layer 6 is 450 nm;

[0126] The second N - Gallium nitride layer 6, gallium nitride substrate 7, and source N + The combined structure of the type gallium nitride layer 8 has a trench structure 9 disposed along the thickness direction, and at the position corresponding to the trench structure 9, the first N - Gallium nitride layer 4 near the second N - The type gallium nitride layer 6 has magnesium ion implanted P on one side. + Type 5 trap region, P + The depth of the trap region 5 is 400 nm; the trench structure 9 has a trench width perpendicular to the thickness direction that is smaller than the corresponding P. + The width of trap region 5;

[0127] The MOSFET device structure further includes a source 11, a drain 10, and a gate 12, wherein the drain 10 is located at the drain N. + The surface of the gallium nitride layer 3 away from the substrate layer 1; the source N + The gallium nitride layer 8 has a through-hole disposed along the thickness direction, and the source electrode 11 is located at the through-hole and extends to the source electrode N. + The gate 11 is located on the surface of the gallium nitride layer 8, and a gate dielectric layer 13 is disposed between the gate 12 and the trench structure 9.

[0128] The fabrication method of the MOSFET device structure is as follows, based on the fabrication method provided in the above embodiments:

[0129] S1. First, a buffer layer is deposited on the substrate surface, and then gallium nitride is epitaxially grown on the surface of the buffer layer to form a drain N-type electrode layered sequentially. + Type 3 gallium nitride layer and first N - Type 4 gallium nitride layer;

[0130] S2, for the first N - The gallium nitride layer 4 was protected by a mask and then subjected to ion implantation. The implantation conditions were 50 keV (5 × 10⁻⁶) for each subsequent implantation. 13 cm -2 ), 150keV (1.5×10 14 cm -2 ) and 250keV (2.5×10 14 cm -2 After removing the mask, an annealing protective layer was prepared at the ion implantation site, followed by annealing at 1000℃ for 30 min. After annealing, the protective layer was removed to form P. + Type 5 trap region, forming ion implanted P + Type 5 trap region;

[0131] S3, forming P + After the N-shaped well region, the second N-type well region is then sequentially processed. - Gallium nitride layer 6, gallium nitride substrate 7, and source N + Growth of type 8 gallium nitride layer;

[0132] S4, for source N + The type 8 gallium nitride layer is protected by a mask, corresponding to P + At position 5 of the trap region, perform the second N... - Gallium nitride layer 6, gallium nitride substrate 7, and source N + The slotted arrangement of the combined structure of the gallium nitride layer 8 forms a trench structure 9;

[0133] S5, for source N + The first etching process is performed on the p-type gallium nitride layer 8 to expose the surface of the p-type gallium nitride substrate layer 7, and the first N-type gallium nitride layer 8 is then etched. - Type 4 gallium nitride layer, second N - Gallium nitride layer 6, gallium nitride substrate 7, and source N + The gallium nitride layer 8 undergoes a second etching process to expose the drain N. + The surface of the gallium nitride layer 6;

[0134] S6. First, deposit the gate dielectric layer 13 in the trench structure 5, and then prepare the gate 12.

[0135] S7. The source electrode 11 is fabricated on the exposed surface of the p-type gallium nitride substrate 7;

[0136] S8, the exposed drain N + Drain electrode 10 is fabricated on the surface of gallium nitride layer 3;

[0137] After S9, source 11, drain 10 and gate 12 are fabricated, a passivation layer 14 is fabricated on all exposed gallium nitride layers of the device, and an opening process is performed to expose all electrode structures, thus obtaining the MOSFET device structure.

[0138] Example 2

[0139] The difference between this embodiment and Embodiment 1 is that in this embodiment, the second N... - The thickness of the gallium nitride layer 6 is 300 nm.

[0140] All other conditions remain the same as in Example 1.

[0141] Example 3

[0142] The difference between this embodiment and Embodiment 1 is that in this embodiment, the second N... - The thickness of the gallium nitride layer 6 is 600 nm.

[0143] All other conditions remain the same as in Example 1.

[0144] Example 4

[0145] The difference between this embodiment and Embodiment 1 is that in this embodiment, P... + The depth of the trap region 5 is 300 nm.

[0146] All other conditions remain the same as in Example 1.

[0147] Example 5

[0148] The difference between this embodiment and Embodiment 1 is that in this embodiment, P... + The depth of the well region 5 is 600 nm.

[0149] All other conditions remain the same as in Example 1.

[0150] Example 6

[0151] The difference between this embodiment and Embodiment 1 is that in this embodiment, the second N... - The thickness of the gallium nitride layer 6 is 200 nm.

[0152] All other conditions remain the same as in Example 1.

[0153] Example 7

[0154] The difference between this embodiment and Embodiment 1 is that in this embodiment, P... + The depth of the trap region 5 is 200 nm.

[0155] All other conditions remain the same as in Example 1.

[0156] Example 8

[0157] The difference between this embodiment and Embodiment 1 is that in this embodiment, P... + The depth of the trap region 5 is 700 nm.

[0158] All other conditions remain the same as in Example 1.

[0159] Example 9

[0160] The difference between this embodiment and Embodiment 1 is that in this embodiment, the groove width of the groove structure 9 perpendicular to the thickness direction is equal to the corresponding P. + Width of type 5 trap region

[0161] All other conditions remain the same as in Example 1.

[0162] Comparative Example 1

[0163] The difference between this comparative example and Example 1 is that this comparative example does not contain the second N. - Type 6 gallium nitride layer, i.e., in the preparation method, after obtaining P + After the well region 5, the p-type gallium nitride substrate 7 and the source N are directly constructed. + Epitaxial growth of type 8 gallium nitride layer.

[0164] All other conditions remain the same as in Example 1.

[0165] Comparative Example 2

[0166] The difference between this comparative example and Example 9 is that this comparative example does not contain the second N. - Type 6 gallium nitride layer, i.e., in the preparation method, after obtaining P + After the well region 5, the p-type gallium nitride substrate 7 and the source N are directly constructed. + Epitaxial growth of type 8 gallium nitride layer.

[0167] All other conditions remain the same as in Example 9.

[0168] A comparison of Examples 1, 2-4, and 6 reveals that the second N - By controlling the thickness of the gallium nitride (GaN) layer to 300nm~600nm, it is more conducive to achieving effective N-type conduction, and further enhances the performance of P-type conduction. + The electric field shielding effect of the trap region, the second N - If the thickness of the gallium nitride layer is too thin, the on-resistance will increase due to the current crowding effect.

[0169] A comparison of Examples 1, 4-5, and 7-8 shows that the depth of the well region affects the performance of the bottom electric field, which in turn affects the on-resistance and breakdown voltage; while a depth range of 300nm to 600nm can ensure effective shielding of the electric field without significantly increasing the resistance of the junction field-effect transistor.

[0170] A comparison of Examples 1 and 9 shows that, in order to further improve P + The electric field shielding effect of the trap region on the trench structure allows the trench width perpendicular to the thickness direction to be smaller than the corresponding P. + The width of the trap region; although it can improve the electric field shielding effect, it works in conjunction with the second N in this invention. - The introduction of the gallium nitride layer effectively avoids the problem of the device failing to conduct properly.

[0171] A comparison of Example 1 and Comparative Example 1, and Example 9 and Comparative Example 2, shows that without setting a second N... - While the field strength at the bottom of the trench can be improved with a type of gallium nitride layer, the on-resistance will increase significantly, reaching infinity, making it difficult to achieve conduction.

[0172] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A MOSFET device structure, characterized in that, The MOSFET device structure, from bottom to top, includes a substrate layer, a drain N-type electrode, and a bottom-to-top layer. + Type gallium nitride layer, first N - Type-2 gallium nitride layer, second N - Gallium nitride (GaN) layer, P-type GaN substrate and source N + Gallium nitride layer, The second N - Gallium nitride (GaN) layer, P-type GaN substrate and source N + The combined structure of the type gallium nitride layer has a trench structure arranged along the thickness direction, and at the position corresponding to the trench structure, the first N - near the second N-type gallium nitride layer - One side of the type gallium nitride layer has ion-implanted P + Type-shaped trap region; The MOSFET device structure further includes a source, a drain, and a gate, with the source located at source N. + At the gallium nitride layer, the drain is located at the drain N. + At the gallium nitride layer, the gate is located at the trench structure.

2. The MOSFET device structure according to claim 1, characterized in that, The substrate and the drain N + A buffer layer is also provided between the gallium nitride layers; Preferably, the substrate layer comprises a sapphire substrate and / or a gallium nitride substrate; Preferably, the drain is located at the drain N. + The surface of the gallium nitride layer on the side away from the substrate layer.

3. The MOSFET device structure according to claim 1, characterized in that, The first N - The thickness of the gallium nitride layer is ≥5μm; Preferably, the P + The depth of the trap region is 300nm~600nm.

4. The MOSFET device structure according to claim 1 or 3, characterized in that, The second N - The thickness of the gallium nitride layer is 300nm~600nm; Preferably, the first N - The doping concentration of the type gallium nitride layer is greater than that of the second N-type layer. - Doping concentration of the gallium nitride layer.

5. The MOSFET device structure according to claim 1, characterized in that, The groove structure has a groove width perpendicular to the thickness direction that is smaller than the corresponding P. + Width of the trap region; Preferably, the P + The trap region includes P-type pits implanted with Mg ions. + Type-shaped trap region.

6. The MOSFET device structure according to claim 1, characterized in that, The source N + The gallium nitride layer has a through-hole disposed along its thickness direction, and the source electrode is located at the through-hole and extends to the source N. + The surface of the gallium nitride layer; Preferably, a gate dielectric layer is further disposed between the gate and the trench structure; Preferably, the MOSFET device structure further includes a passivation layer that covers the surface of all exposed gallium nitride layers.

7. A method for fabricating a MOSFET device structure as described in any one of claims 1-6, characterized in that, The preparation method includes the following steps: (1) Gallium nitride epitaxial growth is performed on one side of the substrate to form a drain N-type electrode that is stacked sequentially. + Type GaN layer and first N - Gallium nitride layer; (2) For the first N - The type gallium nitride layer is far from the drain N + Ion implantation is performed on one side of the gallium nitride layer to form an ion-implanted P-type layer. + Type-shaped trap region; (3) Formation of P + After the N-shaped well region, the second N-type well region is then sequentially processed. - Gallium nitride (GaN) layer, P-type GaN substrate and source N + Growth of gallium nitride layers; (4) Along the thickness direction, corresponding to P + The location of the type-shaped well region is used for the second N-type well. - Gallium nitride (GaN) layer, P-type GaN substrate and source N + The slotted arrangement of the combined structure of gallium nitride layers forms a trench structure; (5) At the source N + At the gallium nitride layer and drain N + The source, drain, and gate are fabricated at the gallium nitride layer and the trench structure, respectively, to obtain the MOSFET device structure.

8. The preparation method according to claim 7, characterized in that, In step (1), a buffer layer is provided on one side surface of the substrate, and the epitaxial growth of gallium nitride is performed on the surface of the buffer layer; Preferably, in step (2), the first N - The gallium nitride (GaN) layer is protected by a mask during ion implantation. After mask removal, an annealing protective layer is prepared at the ion implantation site, followed by annealing. After annealing, the protective layer is removed to form the P-type layer. + Type-shaped trap region; Preferably, in step (4), the source N... + The gallium nitride layer is protected by a mask and then subjected to a trenching process; Preferably, in step (5), after the source, drain and gate are all prepared, a passivation layer is prepared on all exposed gallium nitride layer surfaces of the device.

9. The preparation method according to claim 7 or 8, characterized in that, In step (5), the source N + The first etching process is performed on the p-type gallium nitride layer to expose the surface of the p-type gallium nitride substrate, and the first N-type gallium nitride layer is then etched. - Type-2 gallium nitride layer, second N - Gallium nitride (GaN) layer, P-type GaN substrate and source N + The gallium nitride layer undergoes a second etching process to expose the drain N-type electrode. + The surface of the gallium nitride layer.

10. The preparation method according to claim 9, characterized in that, The source electrode is fabricated on the exposed P-type gallium nitride substrate surface. A gate dielectric layer is first deposited in the trench structure, followed by gate fabrication. The exposed drain electrode is then... + The drain electrode is fabricated on the surface of the gallium nitride layer.

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