A dual-wavelength silicon-based pin photoelectric sensor with ultra-low dark current and high responsivity

Abstract

The application relates to a dual-wavelength silicon-based PIN photoelectric sensor with ultralow dark current and high responsivity, which comprises a silicon substrate, a central P + anode region, high resistance / intrinsic silicon absorption region, bottom N + cathode region, junction termination extension region JTE, guard ring GRL, surface passivation layer and electrode structure. Through accurate regulation of the junction edge electric field, the application effectively suppresses the leakage current and early breakdown phenomenon caused by the high edge electric field in the plane PIN structure, realizes sub-nanoampere dark current output, and simultaneously, through synergistic optimization of the intrinsic region thickness and the doping distribution, the sensor obtains higher light responsivity at two typical wavelengths of 660 nm and 940 nm, and meets the requirements of short-wave shallow absorption and long-wave deep absorption.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic sensor technology, and specifically relates to a dual-wavelength silicon-based PIN optoelectronic sensor with ultra-low dark current and high responsivity. Background Technology

[0002] Silicon-based PIN (Positive-Intrinsic-Negative) photoelectric sensors are widely used in industrial inspection, machine vision, and optical measurement due to their mature technology, low cost, and high reliability. However, traditional planar PIN photoelectric sensors still face the following prominent problems in practical applications:

[0003] On the one hand, as device size increases or reverse bias increases, the junction edge of the planar PIN junction is prone to forming a local high electric field region due to the geometric curvature effect, which leads to avalanche or tunneling effects at the junction edge, thereby causing additional dark current and premature breakdown, which severely limits the application of the device under low noise and high bias conditions.

[0004] On the other hand, the absorption depth of silicon varies significantly at different wavelengths. At 660 nm, light is mainly absorbed at the surface, making it susceptible to surface recombination losses. At 940 nm, however, silicon has a lower absorption coefficient, requiring a thicker intrinsic region for effective absorption. However, simply increasing the thickness of the intrinsic region significantly increases the device's total depletion voltage, accompanied by an increase in dark current, creating a trade-off between responsivity and noise performance.

[0005] Therefore, how to achieve efficient response to dual wavelengths of 660 nm and 940 nm while suppressing dark current has become a key technical challenge in the design of silicon-based PIN photoelectric sensors. Summary of the Invention

[0006] This invention addresses the technical shortcomings of existing silicon-based PIN photoelectric sensors in low-noise and multi-wavelength detection applications, aiming to provide a dual-wavelength silicon-based PIN photoelectric sensor with ultra-low dark current and high responsivity.

[0007] This invention provides a dual-wavelength silicon-based PIN photoelectric sensor with ultra-low dark current and high responsivity, comprising a silicon substrate and a central PIN photoelectric sensor. + Anode region, high-resistivity / intrinsic silicon absorption region, bottom N + Cathode region, junction termination extension (JTE), guard ring layer (GRL), surface passivation layer, and electrode structure;

[0008] The central P +The anode region is formed in the middle of the upper surface of the silicon substrate;

[0009] The bottom N + The cathode region is formed at the bottom of the silicon substrate;

[0010] The high-resistivity / intrinsic silicon absorption region is located in the central P. + Anode region and the bottom N + Between the cathode regions, the central P + Anode region, high-resistivity / intrinsic silicon absorption region and bottom N + The cathode region forms a vertical PIN photojunction in the thickness direction;

[0011] The junction termination extension region (JTE) is formed on the upper surface or near the surface of the silicon substrate and is located at the central P. + Laterally outside the outer edge of the anode region;

[0012] The retaining ring GRL is formed on the upper surface or near the surface region of the silicon substrate and is located laterally outside the junction termination extension region JTE.

[0013] The central P + The anode region, junction termination extension region (JTE), and retaining ring (GRL) are arranged sequentially from the inside to the outside in the transverse direction;

[0014] The surface passivation layer covers the upper surface of the silicon substrate, and the electrode structure includes a central P + The anode electrode, which is electrically connected to the anode region, and the bottom N + The cathode electrode electrically connected to the cathode region and the retaining ring electrode corresponding to the retaining ring GRL.

[0015] Preferably, the thickness of the high-resistivity / intrinsic silicon absorption region is set to 10 μm~50 μm, more preferably 10 μm~30 μm, to balance fast carrier collection at 660 nm wavelength and deep light absorption at 940 nm wavelength.

[0016] Preferably, the junction termination extension region (JTE) is a low-dose shallow junction extension region with a lateral length of 0.5 μm to 5 μm, a junction depth of 0.2 μm to 1 μm, and a peak bulk concentration of 5 × 10⁻⁶ after annealing. 14 cm -3 ~ 5×10 16 cm -3 .

[0017] Preferably, the junction termination extension region (JTE) adopts a single-region or multi-region JTE structure, and its doping concentration gradually decreases radially.

[0018] Preferably, the retaining ring GRL is a floating retaining ring or a bias retaining ring, and the doping concentration is lower than that of the central P.+ Anode area and bottom N + The doping concentration in the cathode region is at least one order of magnitude higher.

[0019] Preferably, the lateral width of the retaining ring GRL is 0.5 μm to 3 μm, the junction depth is 0.2 μm to 1.2 μm, and the peak volume concentration after annealing is 1×10⁻⁶. 15 cm -3 ~5×10 17 cm -3 The peak concentration of the guard ring GRL is lower than that of the central P. + The peak volume concentration in the anode region is at least one order of magnitude higher.

[0020] Preferably, the central P + The peak bulk concentration in the anode region is 1×10 18 cm -3 ~1×10 20 cm -3 The junction depth is 0.2 μm to 1 μm.

[0021] Preferably, the surface passivation layer is a SiO2 layer with a thickness of 0.02 μm to 0.3 μm.

[0022] The electric field distribution formed by the retaining ring and the junction termination extension region works in synergy with the electric field distribution of the high-resistivity / intrinsic silicon absorption region in the central PIN main junction region to improve the responsivity at 940 nm wavelength without significantly increasing the operating voltage.

[0023] Preferably, the photoelectric sensor adopts a central P + Anode region, JTE region, retaining ring GRL, high resistivity / intrinsic silicon absorption region, bottom N + The combined structure of the cathode region and the SiO2 surface passivation layer. Simulation results show a dark current of approximately 0.7 nA under a reverse bias of approximately -10 V. This dark current level represents the electrical effect of the above structural combination and is not intended to limit the structure of any individual product.

[0024] Preferably, the central P + The anode region, JTE region, and retainer ring GRL can be formed through ion implantation, thermal diffusion, and annealing. The above processes are merely preferred preparation methods for forming the corresponding doped regions; the product structure of this invention is determined by the conductivity type, spatial location, lateral dimensions, junction depth, and peak volume concentration after annealing of each doped region. Through the aforementioned central P... + The synergistic design of the anode region, retaining ring, and junction termination extension region can effectively suppress the generation of local high electric fields at the junction edge, significantly reduce leakage current caused by edge effects, and delay breakdown, thereby suppressing dark current at the structural level.

[0025] Preferably, the photoelectric sensor is suitable for dual-wavelength identification, weak light detection, or low-noise photoelectric measurement applications.

[0026] This invention improves the absorption and carrier collection efficiency at 940 nm wavelength without significantly increasing the reverse working voltage by coordinating the thickness design of the high-resistivity / intrinsic silicon absorption region with the overall electric field distribution formed by the retaining ring and the junction termination extension region. At the same time, it maintains the high response characteristics at 660 nm wavelength, thereby achieving a simultaneous improvement in dual-wavelength response performance.

[0027] Beneficial effects

[0028] (1) The present invention effectively weakens the local high electric field generated by the curvature effect at the edge of the planar PIN junction through the integrated electric field control structure of the central PIN main junction region, guard ring and junction termination extension, significantly suppresses the edge leakage current and delays the occurrence of premature breakdown, thereby achieving ultra-low dark current output under reverse bias conditions.

[0029] (2) By optimizing the thickness of the high-resistivity / intrinsic silicon absorption region and the overall electric field distribution of the device, the present invention enables photogenerated carriers to be efficiently collected at different absorption depths, achieving high response characteristics of the device at dual wavelengths of 660 nm and 940 nm. This avoids the contradiction that traditional structures have good short-wavelength response but insufficient long-wavelength response, or that thickening the intrinsic region to improve the long-wavelength response leads to a significant increase in dark current and operating voltage.

[0030] (3) While improving near-infrared response capability, this invention can ensure effective depletion of the high-resistivity / intrinsic silicon absorption region without relying on a significant increase in the thickness of the high-resistivity / intrinsic silicon absorption region, thus enabling the device to maintain stable operation at a lower operating voltage. This structure is compatible with standard silicon processes, has good fabrication repeatability, and possesses good industrialization feasibility. It is suitable for optoelectronic detection applications with strict requirements for low noise and high sensitivity. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the photoelectric sensor of the present invention, showing the relative positions of the silicon substrate, the central PIN main junction region, the retaining ring, and the junction termination extension region.

[0032] Figure 2 The image shows the dark current results of the photoelectric sensor in Example 1.

[0033] Figure 3 The image shows the relative spectral response curve of the photoelectric sensor in Example 1. Detailed Implementation

[0034] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0035] Example 1

[0036] This embodiment provides a dual-wavelength silicon-based PIN photoelectric sensor with ultra-low dark current and high responsivity, as shown in the schematic diagram below. Figure 1 As shown. This embodiment uses a vertical silicon-based PIN structure. A central P-type pin is formed in the middle of the upper surface of the device. + Anode region, N is formed at the bottom + Cathode region, central P + Anode region and N + The area between the cathode regions is a high-resistivity / intrinsic silicon absorption region.

[0037] Central P + The anode region has a lateral width of approximately 6 μm, a junction depth of 0.4 μm to 0.8 μm, and a peak bulk concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 Bottom N + The cathode region thickness ranges from 0.3 μm to 0.6 μm, and the peak volume concentration is 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0038] In the central P + JTE regions are formed on the outer edges of the left and right sides of the anode region. The JTE region is a low-dose P-type shallow nodule extension region, with a lateral length of 0.5 μm to 5 μm, preferably 1 μm to 2 μm; a nodule depth of 0.2 μm to 1 μm, preferably 0.4 μm to 0.8 μm; and an equivalent injection dose of 5 × 10⁻⁶. 11 cm -2 ~5×10 12 cm -2 Preferably 8×10 11 cm -2 ~2×10 12 cm -2 The peak volume concentration after annealing was 5 × 10⁻⁶. 14 cm -3 ~5×10 16 cm -3 .

[0039] Guard rings are formed on the outer lateral sides of the JTE region. The lateral width of each guard ring is 0.5 μm to 3 μm, preferably 1 μm to 2 μm; the junction depth of the guard ring is 0.2 μm to 1.2 μm, preferably 0.5 μm to 0.8 μm; and the peak concentration of the guard ring is 1 × 10⁻⁶. 15 cm -3 ~5×10 17 cm -3 .

[0040] The doping level in the JTE region is lower than that in the central P region. + The doping concentrations of the anode region, JTE region, and retaining ring together satisfy the following relationship: Central P + The peak concentration in the anode region is at least two orders of magnitude higher than that in the JTE region, and the peak concentration in the retaining ring is higher than or close to the peak concentration in the JTE region but lower than that in the central P region. + The anode region is at least one order of magnitude larger.

[0041] Under reverse bias, the central P + The depletion layer at the edge of the anode region first extends into the JTE region, which provides lightly doped space charge to reduce the peak electric field at the main junction edge. As the reverse bias increases, the depletion region further extends into the retainer ring region, where the retainer ring shares the lateral voltage and suppresses premature breakdown at the device edge. Thus, the central P... + The anode region, JTE region, and retaining ring constitute a continuous transverse electric field transition structure.

[0042] The specific implementation process is as follows:

[0043] (1) Substrate selection and pretreatment

[0044] A high-resistivity single-crystal silicon substrate was selected as the device substrate. The substrate resistivity was on the order of 1 kΩ·cm, the thickness was 500~700 μm, and the crystal orientation was <100> or <111>. The high-resistivity silicon substrate is beneficial for reducing bulk recombination current and minimizing background dark current. Before fabrication of the photoelectric sensor, the silicon substrate was sequentially cleaned using standard RCA (Radio Corporation of America) process, including SC-1 (Standard Clean 1, the first step of standard cleaning solution) and SC-2 (Standard Clean 2, the second step of standard cleaning solution) to remove surface organic contaminants and metal ions. Subsequently, a diluted hydrofluoric acid solution was used to etch the silicon surface for a short time to remove the native oxide layer. Finally, the substrate was thoroughly rinsed with deionized water and dried with nitrogen to ensure a clean substrate surface and suppress dark current caused by surface defects from the source.

[0045] (2) Oxide layer growth and graphical definition

[0046] After cleaning, a thermally grown silicon dioxide layer with a thickness of 100–300 nm is grown on the surface of the silicon substrate at 900–1000 °C using dry or wet oxidation processes. This layer serves as a doping mask and surface passivation layer. The thermally grown oxide layer effectively reduces the silicon / oxide interface state density, providing a foundation for achieving low dark current. Subsequently, the oxide layer is patterned using photolithography, creating corresponding windows in the central PIN main junction region, the retaining ring, and the junction termination extension region. The oxide layer in the window areas is removed using wet buffered hydrofluoric acid etching or plasma etching to expose the silicon substrate, providing conditions for selective doping in different regions.

[0047] (3) Formation of the central PIN main junction region

[0048] In the central PIN main junction region, after defining the doping window through photolithography, P is formed using boron diffusion or ion implantation processes. + Type-heavy doped region. Preferably, BBr3 can be used as the boron source, diffusion can be carried out at 900-950℃, and subsequent annealing can drive the diffusion of boron atoms to the designed depth and fully activate them; or high-energy ion implantation can be used, with an implantation dose of 10. 15 ~10 16 cm -2 Subsequently, the lattice was restored and the doping was activated through a rapid thermal annealing process. The resulting P + The P-terminus of the central PIN main junction region is formed by the region and the silicon substrate. This main junction serves as the primary photosensitive area of ​​the device, used to generate photogenerated carriers and complete photoelectric conversion at wavelengths of 660 nm and 940 nm. Preferably, the N-terminus is prepared by phosphorus diffusion or ion implantation. Phosphorus diffusion is performed using a POCl3 source in a tube furnace at 800-950℃. The diffusion temperature (800-950℃), diffusion duration, and surface doping concentration are adjusted according to the design to obtain the required contact resistance and junction depth. Alternatively, high-energy ion implantation is used, with an implantation dose of 10. 15 ~10 16 cm -2 Subsequently, annealing / oxidation removes the PSG (Phosphosilicate Glass) and RTA (Rapid Thermal Annealing) is performed for activation. The resulting N-region can interact with P... + It is compatible with the process and facilitates the formation of shallow, highly doped contact regions.

[0049] (4) Preparation of retaining ring (GRL)

[0050] One or more retainer rings are radially arranged around the central PIN main junction region. These retainer rings are formed around the main junction through multiple photolithography and selective doping processes. Preferably, the retainer rings employ a low-doped homojunction structure, i.e., a ring-shaped region with the same conductivity type as the main junction but a significantly lower doping concentration than the main junction region, is formed around the central main junction. Under reverse bias, the retainer ring region can be preferentially depleted, thereby sharing the electric field at the main junction edge, suppressing local high electric field peaks caused by junction curvature effects, and reducing edge leakage current. After the retainer rings are doped, a high-temperature annealing process is used to drive and activate the doping to form a stable junction structure.

[0051] (5) Formation of the terminal extension (JTE) region

[0052] A junction termination extension region is further formed on the outer side of the retaining ring. This region is lightly doped by using a separate photolithography window or by controlling the mask coverage during diffusion. The JTE region is formed by low-dose ion implantation and annealing. The equivalent implantation dose of the JTE region is 5 × 10⁻⁶. 11 cm -2 ~5×10 12 cm -2 The annealed junction depth was 0.2 μm to 1 μm, and the peak bulk concentration was 5 × 10⁻⁶. 14 cm -3 ~5×10 16 cm -3 The peak bulk concentration in the central P⁺ anode region was 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The peak concentration of the retaining ring is 1×10⁻⁶. 15 cm -3 ~5×10 17 cm -3 Therefore, the peak bulk concentration after annealing in the JTE region is lower than that in the central P region. + The anode region has a concentration at least two orders of magnitude lower than or close to the peak bulk concentration of the retainer ring. The JTE region forms a wide depletion region under reverse bias, causing the junction edge electric field to gradually decay radially, further preventing electric field concentration at the device edge, thereby increasing the device breakdown voltage and further suppressing dark current. After JTE doping, annealing is also performed to ensure doping uniformity and junction stability.

[0053] (6) Co-design of high-resistivity / intrinsic silicon absorption region thickness and dual-wavelength response Based on the above structure, by rationally designing the thickness of the high-resistivity / intrinsic silicon absorption region in the central PIN main junction region, it is made to be in a fully or nearly fully depleted state under normal operating bias. The thickness of the high-resistivity / intrinsic silicon absorption region is set within a range that accommodates both shallow absorption at 660 nm wavelength and deep absorption at 940 nm wavelength, so that photogenerated carriers generated at different absorption depths can be effectively collected under the action of an electric field. By controlling the overall electric field distribution through the retaining ring and JTE structure, the near-infrared band responsivity is improved without significantly increasing the reverse working voltage. At the same time, the problems of dark current and significant increase in working voltage introduced by simply thickening the high-resistivity / intrinsic silicon absorption region are avoided. The synergistic optimization of high response and low dark current at both structural and electric field levels is achieved. More specific design suggestions and trade-offs are given from the aspects of optical absorption and depletion voltage of silicon materials. Under high-resistivity substrates, the reverse voltage required for complete or near-complete depletion of the high-resistivity / intrinsic silicon absorption region with a thickness of 10-50 μm is acceptable. Therefore, in this embodiment, the thickness of the high-resistivity / intrinsic silicon absorption region is preferably 10-50 μm.

[0054] (7) Metal electrode preparation and annealing

[0055] After doping each functional region, photolithography residue is removed, and metal electrodes are deposited via vacuum evaporation or magnetron sputtering. Aluminum is preferably used as the electrode material to react with P. + The anode metal in the contact area can be aluminum or a titanium / aluminum composite metal structure, while the cathode can be aluminum. After forming the electrode pattern through photolithography and etching processes, it is annealed at approximately 400°C in a hydrogen-nitrogen mixed atmosphere to form an ohmic contact with low contact resistance and reduce metal / silicon interface defects, thereby further suppressing contact-related dark current.

[0056] (8) Surface passivation and packaging testing

[0057] A silicon oxide, silicon nitride, or Al2O3 passivation layer is deposited on the surface of the photoelectric sensor to reduce the surface recombination rate and interface state density. After passivation, contact windows are opened, and a final cleaning process is performed. Subsequently, the wafer is diced, packaged, and wire-bonded. Finally, the packaged device undergoes electrical and optical testing. The test results show that the fabricated silicon-based PIN photoelectric sensor exhibits extremely low dark current under reverse bias conditions, and also demonstrates high photoresponsivity at wavelengths of 660 nm and 940 nm, verifying the effectiveness of the technical solution of this invention. The results are as follows... Figure 2 , 3 As shown.

[0058] Depend on Figure 2As can be seen, under reverse bias conditions, the dark current of the dual-wavelength silicon-based PIN photoelectric sensor of this invention remains at the nanoampere level, with a dark current of only about 0.7 nA at an operating voltage of approximately -10 V. Furthermore, the current change is gradual within the main operating range of -10 V to -2 V, without any significant premature breakdown or abnormal surges. This indicates that the electric field distribution at the junction edge of the device is effectively controlled, and carrier recombination and tunneling leakage are significantly suppressed. This result demonstrates that the synergistic design of the central PIN main junction region, the low-doped homotype extended junction guard ring (JTE), and the multiple guard ring structure effectively weakens the local high electric field at the junction edge, significantly reducing the additional leakage current caused by edge avalanche effects and field-induced tunneling, thereby achieving ultra-low dark current characteristics. Therefore, the experimental results verify that the technical solution of this invention in terms of structural design and electric field control can maintain a stable and ultra-low dark current operating state even under higher reverse bias voltages, proving that the technical solution of this invention has significant effects and practical feasibility in improving the low-noise performance of the device. Compared to conventional planar PIN photodiodes, which typically exhibit dark current levels in the range of several nanoamps to tens of nanoamps under the same bias conditions, the dark current of the device of this invention is reduced to approximately 0.7 nA, demonstrating that its edge termination structure has a significant advantage in suppressing leakage current.

[0059] Figure 3 The relative spectral response characteristics of the photoelectric sensor of the present invention are demonstrated. Figure 3 The vertical axis represents the normalized relative response, a dimensionless data point used to characterize the relative response trend of the device at different wavelengths. The relative response gradually increases with increasing wavelength, peaking at approximately 940 nm with a peak value of about 0.958, and then gradually decreases in the longer wavelength region. This test result demonstrates that by rationally designing the thickness and electric field distribution structure of the high-resistivity / intrinsic silicon absorption region in the central PIN main junction region, photogenerated carriers generated at different absorption depths can be effectively collected, thereby achieving high photoelectric conversion efficiency. Therefore, the device structure proposed in this invention exhibits high responsivity characteristics in the near-infrared band, verifying the effectiveness of the technical solution in improving the response performance of photoelectric sensors.

Claims

1. A dual-wavelength silicon-based PIN photoelectric sensor with ultra-low dark current and high responsivity, characterized in that, Including silicon substrate, central P + Anode region, high-resistivity / intrinsic silicon absorption region, bottom N + Cathode region, junction termination extension region (JTE), retaining ring (GRL), surface passivation layer, and electrode structure; The central P + The anode region is formed in the middle of the upper surface of the silicon substrate; The bottom N + The cathode region is formed at the bottom of the silicon substrate; The high-resistivity / intrinsic silicon absorption region is located in the central P. + Anode region and the bottom N + Between the cathode regions, the central P + Anode region, high-resistivity / intrinsic silicon absorption region and bottom N + The cathode region forms a vertical PIN photojunction in the thickness direction; The junction termination extension region (JTE) is formed on the upper surface or near the surface of the silicon substrate and is located at the central P. + Laterally outside the outer edge of the anode region; The retaining ring GRL is formed on the upper surface or near the surface region of the silicon substrate and is located laterally outside the junction termination extension region JTE. The central P + The anode region, junction termination extension region (JTE), and retaining ring (GRL) are arranged sequentially from the inside to the outside in the transverse direction; The surface passivation layer covers the upper surface of the silicon substrate, and the electrode structure includes a central P + The anode electrode, which is electrically connected to the anode region, and the bottom N + The cathode electrode electrically connected to the cathode region and the retaining ring electrode corresponding to the retaining ring GRL.

2. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The thickness of the high-resistivity / intrinsic silicon absorption region is 10 μm to 50 μm.

3. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The junction termination extension region (JTE) is a low-dose shallow junction extension region with a lateral length of 0.5 μm to 5 μm and a junction depth of 0.2 μm to 1 μm. The peak bulk concentration after annealing is 5 × 10⁻⁶. 14 cm -3 ~ 5×10 16 cm -3 .

4. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The junction termination extension region (JTE) adopts a single-region or multi-region JTE structure, and its doping concentration gradually decreases radially.

5. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The retaining ring GRL is a floating retaining ring or a bias retaining ring, with a doping concentration lower than that of the central P. + Anode area and bottom N + The doping concentration in the cathode region is at least one order of magnitude higher.

6. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The retaining ring GRL has a lateral width of 0.5 μm to 3 μm, a junction depth of 0.2 μm to 1.2 μm, and a peak bulk concentration of 1×10⁻⁶ after annealing. 15 cm -3 ~5×10 17 cm -3 The peak concentration of the guard ring GRL is lower than that of the central P. + The peak volume concentration in the anode region is at least one order of magnitude higher.

7. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The central P + The peak bulk concentration in the anode region is 1×10 18 cm -3 ~1×10 20 cm -3 The junction depth is 0.2 μm to 1 μm.

8. The dual-wavelength silicon-based PIN photoelectric sensor according to claim 1, characterized in that, The surface passivation layer is a SiO2 layer with a thickness of 0.02 μm to 0.3 μm.

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