Power semiconductor device

Abstract

Power semiconductor devices are provided. In one example, a semiconductor device includes a wide bandgap epitaxial layer. The wide bandgap epitaxial layer includes silicon carbide. The wide bandgap epitaxial layer has a first surface and an opposing second surface. The semiconductor device includes a first contact on the first surface of the wide bandgap epitaxial layer. The second surface is not in direct or indirect contact with a silicon carbide substrate.

Description

[0001] Priority requirements

[0002] This application is based on and claims priority to U.S. Patent Application No. 18 / 537,435, filed December 12, 2023. This application claims priority and benefit to the entire contents of the referenced application, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to semiconductor devices, such as wide-bandgap semiconductor devices. Background Technology

[0004] Power semiconductor devices are used to carry large currents and withstand high voltages. A wide variety of power semiconductor devices are known in the art, including, for example, transistors, diodes, thyristors, power modules, discrete power semiconductor packages, and other devices. For example, an example semiconductor device may be a transistor device, such as a metal-oxide-semiconductor field-effect transistor (“MOSFET”), a bipolar junction transistor (“BJT”), an insulated-gate bipolar transistor (“IGBT”), a gate turn-off transistor (“GTO”), a junction field-effect transistor (“JFET”), a high electron mobility transistor (“HEMT”), and other devices. An example semiconductor device may be a diode, such as a Schottky diode or other devices. An example semiconductor device may be a power module, which may include one or more power devices and other circuit components, and may be used to dynamically switch large amounts of power, for example, through various components such as motors, inverters, generators, etc. These semiconductor devices may be manufactured from wide-bandgap semiconductor materials, such as silicon carbide (“SiC”) and / or gallium nitride (“GaN”) based semiconductor materials. Summary of the Invention

[0005] Various aspects and advantages of embodiments of this disclosure will be set forth in part in the description which follows, or may be learned from the description or by practice of the embodiments.

[0006] One example aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a wide bandgap epitaxial layer. The wide bandgap epitaxial layer includes silicon carbide. The wide bandgap epitaxial layer has a first surface and an opposing second surface. The semiconductor device includes a first contact on the first surface of the wide bandgap epitaxial layer. The second surface does not directly or indirectly contact a silicon carbide substrate.

[0007] Another example aspect of this disclosure relates to a semiconductor device package. The semiconductor device package includes a wide bandgap epitaxial layer. The wide bandgap epitaxial layer has a first surface and an opposing second surface. The semiconductor device package includes a first contact on the first surface of the wide bandgap epitaxial layer. The first surface of the wide bandgap epitaxial layer is mounted on a substrate in a flip-chip configuration. The second surface of the wide bandgap epitaxial layer provides at least a portion of a heat dissipation path configured to dissipate heat from the wide bandgap epitaxial layer. The heat dissipation path does not include a semiconductor substrate.

[0008] Another example aspect of this disclosure relates to a lateral silicon carbide-based transistor device. The transistor device includes a silicon carbide epitaxial layer having a first surface and an opposing second surface. The transistor device includes a drain contact, a source contact, and a gate contact on the first surface of the silicon carbide epitaxial layer. The second surface of the silicon carbide epitaxial layer does not contact a silicon carbide substrate.

[0009] Another example aspect of this disclosure relates to a method. The method includes forming a wide bandgap epitaxial layer on a substrate. The wide bandgap epitaxial layer has a first surface and an opposite second surface. The second surface is on the substrate. The method includes forming contacts on the first surface of the wide bandgap epitaxial layer. The method includes placing the first surface of the wide bandgap epitaxial layer on a pedestal. The method includes removing the substrate from the second surface of the wide bandgap epitaxial layer.

[0010] These and other features, aspects, and advantages of the various embodiments will become more readily understood with reference to the following description and the appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the relevant principles. Attached Figure Description

[0011] This specification provides a detailed discussion of the embodiments for those skilled in the art, with reference to the accompanying drawings, wherein: Figure 1 An overview of exemplary methods according to exemplary embodiments of the present disclosure is provided; Figure 2 An overview of exemplary methods according to exemplary embodiments of the present disclosure is provided; Figure 3 A cross-sectional view of an exemplary lateral power semiconductor device according to an exemplary embodiment of the present disclosure is depicted; Figure 4 A cross-sectional view of an exemplary lateral power semiconductor device according to an exemplary embodiment of the present disclosure is depicted; Figure 5 A plan view depicting a contact layout on an exemplary lateral power semiconductor device according to an exemplary embodiment of the present disclosure; Figure 6A plan view depicting a contact layout on an exemplary lateral power semiconductor device according to an exemplary embodiment of the present disclosure; Figure 7 A plan view depicting a contact layout on an exemplary lateral power semiconductor device according to an exemplary embodiment of the present disclosure; Figure 8 An overview of exemplary methods according to exemplary embodiments of the present disclosure is provided; Figure 9 A cross-sectional view of an exemplary lateral semiconductor device according to an exemplary embodiment of the present disclosure is depicted; Figure 10 An overview of exemplary methods according to exemplary embodiments of the present disclosure is provided; Figure 11 A cross-sectional view of an exemplary vertical power semiconductor device according to an exemplary embodiment of the present disclosure is depicted; and Figure 12 A cross-sectional view of an exemplary vertical power semiconductor device according to an example embodiment of the present disclosure is depicted. Detailed Implementation

[0012] Reference will now be made in detail to embodiments, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation and not by way of limitation of this disclosure. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments without departing from the scope or spirit of this disclosure. For example, a feature shown or described as part of one embodiment may be used with another embodiment to produce yet another embodiment. Therefore, aspects of this disclosure are intended to cover such modifications and variations.

[0013] Power semiconductor devices are typically fabricated from wide-bandgap semiconductor materials, such as silicon carbide or group III nitride-based semiconductor materials (e.g., gallium nitride). In this document, a wide-bandgap semiconductor material refers to a semiconductor material having a bandgap width greater than 1.40 eV. Aspects of this disclosure are discussed with reference to silicon carbide-based semiconductor layers as wide-bandgap semiconductor structures. Those skilled in the art will understand using the disclosure provided herein that power semiconductor devices according to exemplary embodiments of this disclosure can be used with any semiconductor material, such as other wide-bandgap semiconductor materials, without departing from the scope of this disclosure. Exemplary wide-bandgap semiconductor materials include silicon carbide (e.g., α-silicon carbide with a bandgap of 2.996 eV at room temperature) and group III nitrides (e.g., gallium nitride with a bandgap of 3.36 eV at room temperature).

[0014] Power semiconductor devices can have lateral or vertical structures. In devices with a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals of a power MOSFET device) are on the same main surface (e.g., the top or bottom surface) of the semiconductor layer. In contrast, in power semiconductor devices with a vertical structure, at least one terminal is disposed on each main surface of the semiconductor structure. For example, in a vertical MOSFET device, the source may be on the top surface of the semiconductor structure, and the drain may be on the bottom surface, or vice versa.

[0015] Power semiconductor devices are typically fabricated by performing manufacturing processes on semiconductor wafers. A semiconductor wafer may include one or more epitaxial layers formed on a substrate. As used herein, an "epitaxy layer" is a single-crystal semiconductor layer grown on top of a substrate using a process called epitaxial growth or epitaxy. Epitaxial layers can be deposited atom-by-atom and can adopt the crystal structure of the underlying substrate. Epitaxial layers can have a thickness ranging from, for example, about 0.2 micrometers to about 200 micrometers.

[0016] A “substrate” refers to a solid semiconductor material on which an epitaxial layer is formed. The substrate can be a homogeneous material, such as silicon carbide and / or sapphire, and can provide mechanical support for the formation of the epitaxial layer. In many examples, the substrate can serve as a semiconductor wafer setting on which various other layers and structures are formed. The substrate can have a thickness ranging from about 0.5 micrometers to about 1000 micrometers or greater.

[0017] Power semiconductor devices (e.g., MOSFETs, JFETs, Schottky diodes, HEMTs) can be fabricated on silicon carbide (e.g., 4H polytype) semiconductor wafers, where a single-crystal silicon carbide wafer serves as the substrate for the power semiconductor device. Even after the back side is ground to the final wafer thickness, a significant portion of the silicon carbide substrate (e.g., a single-crystal silicon carbide substrate) may still be retained as part of the power semiconductor device. Many power semiconductor devices are vertical power devices and can conduct current through the substrate. Therefore, in some cases, the silicon carbide substrate may add significant series resistance to the power semiconductor device and may increase conduction losses in the end-application circuitry of the power semiconductor device.

[0018] Various aspects of this disclosure relate to power semiconductor devices that reduce and / or eliminate silicon carbide substrates in power semiconductor devices. More specifically, one or more power semiconductor devices can be fabricated in a wide bandgap epitaxial layer disposed on a substrate (e.g., a semiconductor wafer). The substrate can be, for example, a silicon carbide substrate (e.g., 4H single-crystal silicon carbide) or other substrates, such as a sapphire substrate or a silicon substrate. The semiconductor wafer can undergo, for example, wafer-level processing to mount one or more semiconductor dies to a substrate. The semiconductor die can include one or more semiconductor devices fabricated in a wide bandgap epitaxial layer. In some examples, the semiconductor wafer can be “flipped” and mounted on a substrate structure such that each of a plurality of semiconductor dies on the semiconductor wafer is mounted to one of a plurality of substrates (e.g., lead frames, clip structures, power substrates, DBC substrates, AMB substrates, etc.).

[0019] According to exemplary embodiments of the present disclosure, the back side (including the substrate) of a semiconductor wafer can be removed from an epitaxial wide bandgap semiconductor structure. An example removal process may include inducing a cleavage facet in the wide bandgap epitaxial layer and removing a first substrate from the wide bandgap epitaxial layer along the cleavage facet. Inducing a cleavage facet may include emitting one or more laser beams into the wide bandgap epitaxial layer. Example techniques for inducing cleavage facets using one or more laser beams are disclosed in U.S. Patent Nos. 10,576,585 and 10,562,130, which are incorporated herein by reference. Other suitable techniques may be used to induce cleavage facets without departing from the scope of the present disclosure, such as implanting one or more materials into the wide bandgap epitaxial layer.

[0020] Other suitable removal processes may be used without departing from the scope of this disclosure. For example, chemical mechanical polishing (CMP), grinding, and other processes may be used to remove the substrate from an epitaxial wide-bandgap semiconductor structure. In some embodiments, etching may be used to remove the substrate.

[0021] Semiconductor wafers can undergo further wafer-level processing and be monomerized to form individual semiconductor device packages. Individual semiconductor device packages may include one or more semiconductor dies mounted on a substrate in a flip-chip configuration. Individual semiconductor device packages may not include a silicon carbide substrate. For example, a wide bandgap epitaxial layer may not be in direct or indirect contact with the silicon carbide substrate. In this way, a silicon carbide substrate may be absent from the heat dissipation path configured to dissipate heat from the wide bandgap epitaxial layer.

[0022] For purposes of illustration and discussion, aspects of this disclosure are discussed in conjunction with wafer-level processing. Those skilled in the art will understand using the disclosure provided herein that wafer-level processing is not essential. For example, individual semiconductor dies (after being singulated or diced from a wafer) can be flipped and mounted to a substrate in a flip-chip configuration. The back side of the semiconductor die can undergo a removal process to remove the substrate from the wide bandgap epitaxial layer.

[0023] Examples of this disclosure can be used to provide lateral power semiconductor devices and / or vertical power semiconductor devices. In some examples, a lateral silicon carbide-based transistor device may include an epitaxial silicon carbide layer having a first surface and an opposing second surface. The transistor device may include drain contacts, source contacts, and gate contacts on the first surface of the epitaxial silicon carbide layer, such that the transistor device is a lateral device. The second surface of the epitaxial silicon carbide layer may not be in contact with a silicon carbide substrate. In some examples, the second surface of the silicon carbide epitaxial layer provides at least a portion of a heat dissipation path for heat dissipation from the silicon carbide epitaxial layer. The heat dissipation path does not include the silicon carbide substrate.

[0024] In some examples, the silicon carbide epitaxial layer is on a sapphire substrate. In some examples, the silicon carbide epitaxial layer is on a silicon substrate. In some examples, there is no semiconductor substrate.

[0025] In some examples, the silicon carbide epitaxial layer is mounted in a flip-chip configuration within a semiconductor device package. The insulating material of the semiconductor package (e.g., epoxy molding compound) can be directly applied to the second surface of the silicon carbide epitaxial layer. An underfill material can be applied to the silicon carbide epitaxial layer to increase the creepage distance between the source and drain contacts. An underfill material can also be applied to the gate contacts. The underfill material can be an organic material, such as a composite epoxy resin.

[0026] In some examples, the lateral transistor device is a MOSFET. The silicon carbide epitaxial layer may include a drift region having a first conductivity type. At least a portion of the drift region is between a source contact and a drain contact. The silicon carbide epitaxial layer may include a well region of a second conductivity type. The well region may be between the drift region and the source contact. In some examples, the silicon carbide epitaxial layer includes a source region of a first conductivity type immediately adjacent to the source contact and a drain region of a first conductivity type immediately adjacent to the drain contact. In some examples, the source contact and drain contact are each ohmic contacts with the silicon carbide epitaxial layer. In some examples, the transistor device includes a gate dielectric between a gate contact and the epitaxial silicon carbide layer.

[0027] Source contacts, drain contacts, and gate contacts can be arranged in various patterns on a first surface of the epitaxial silicon carbide layer. For example, in some examples, the drain contacts at least partially interlock with the source contacts. In some examples, the drain contacts include a plurality of intersecting drain buses forming a grid. The source contacts include a plurality of source contacts within the space of the grid. The gate contacts include a plurality of gate contacts. Each gate contact at least partially surrounds one of the plurality of source contacts.

[0028] Various aspects of this disclosure may also include vertical power semiconductor devices. For example, the semiconductor device has a first contact on a first surface of a wide bandgap epitaxial layer. The semiconductor device has a second contact on a second surface of the wide bandgap epitaxial layer, such that the semiconductor device is a vertical power semiconductor device. In some examples, there is no silicon carbide substrate between the wide bandgap epitaxial layer and the second contact. For example, there may be a sapphire substrate or a silicon substrate between the wide bandgap epitaxial layer and the second contact. In some examples, there is no substrate between the wide bandgap epitaxial layer and the second contact.

[0029] The aspects of this disclosure provide numerous technical effects and benefits. For example, aspects of this disclosure can provide power semiconductor devices without a bulk silicon carbide substrate. This can reduce bulk resistivity (e.g., in vertical power devices) and improve heat dissipation performance by providing a heat dissipation path that does not include a silicon carbide substrate. In some cases, such as on the surface of a wide bandgap semiconductor structure, various contact patterns can be implemented to provide enhanced flexibility in semiconductor device packaging. More specifically, contacts can be arranged in different patterns as needed to facilitate connections with the base and other structures in the semiconductor device package.

[0030] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that the terms “comprise,” “comprising,” “include,” and / or “including,” when used herein, specify the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be construed as having an idealized or overly formal meaning unless expressly defined herein.

[0033] It will be understood that when an element, such as a layer, structure, region, or substrate, is referred to as being "on" or extending "on" another element, it can be directly on or directly extending onto the other element, or there may be an intermediate element, and it may be only partially on the other element. Conversely, when an element is referred to as being "directly on" or "directly extending" onto "another element," there is no intermediate element, and it may be partially directly on the other element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0034] As used herein, the first and second structures "at least partially overlap" or "overlap" if an axis perpendicular to the main surface of the first structure passes through both the first and second structures. The "peripheral portion" of a structure includes the structural region located closer to the geometric center of the surface of the structure relative to its surface. The "central portion" of a structure includes the structural region located closer to the geometric center of the surface of the structure relative to its periphery. "Substantially perpendicular" means within 15 degrees of perpendicularity. "Substantially parallel" means within 15 degrees of parallelism.

[0035] Relative terms (such as "below" or "above," or "upper" or "lower," or "horizontal," "lateral," or "vertical") may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It will be understood that these terms are intended to cover different orientations of the device other than those depicted in the figures.

[0036] Embodiments of this disclosure are described herein with reference to cross-sectional illustrations, which are schematic diagrams of idealized embodiments (and intermediate structures) of the invention. For clarity, the thicknesses of the layers and regions in the figures may be exaggerated. Furthermore, variations relative to the shapes shown in the figures are expected, attributable to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be construed as limited to the specific shapes of the regions shown herein, but will include shape deviations attributable to, for example, manufacturing. Similarly, it will be understood that dimensional variations will be expected based on standard deviations during the manufacturing process. As used herein, “about” or “approximately” includes values ​​within 10% of the nominal value.

[0037] The same reference numerals always refer to the same elements. Therefore, other figures can be used to describe the same or similar numbers, even if they are neither mentioned nor described in the corresponding figures. Furthermore, other figures can be used to describe elements not indicated by reference numerals.

[0038] Some embodiments of the invention are described with reference to semiconductor layers and / or regions characterized by having a conductivity type (such as n-type or p-type), where conductivity type refers to the majority carrier concentration in the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. A material may be designated using "+" or "-" (e.g., N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively large ("+") or small ("-") majority carrier concentration compared to another layer or region. However, this designation does not imply the presence of a specific majority or minority carrier concentration in the layer or region.

[0039] Typical embodiments have been disclosed in the accompanying drawings and description, and although specific terminology has been used, it is used only in a general and descriptive sense and not for the purpose of limiting the scope set forth in the following claims.

[0040] Figure 1 An overview of an example method 100 according to an example implementation of the present disclosure is provided. Figure 1The description is intended to represent structures for identification and description, and not to represent the structures to physical scale. Method 100 includes operations shown in a specific order for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that various steps or operations of any method provided in this disclosure may be adjusted, rearranged, omitted, included, and / or modified in various ways, without departing from the scope of this disclosure.

[0041] At 110, the method may include forming a wide bandgap epitaxial layer 102 on a substrate 104. In some examples, the substrate 104 may be a silicon carbide substrate (e.g., 4H single-crystal silicon carbide), a sapphire substrate, or a silicon substrate. Other suitable substrates may be used as substrate 104 without departing from the scope of this disclosure. The substrate 104 may be in the form of a semiconductor wafer 105. In some examples, the substrate 104 has a thickness in the range of about 100 μm to about 1000 μm.

[0042] The wide bandgap epitaxial layer 102 can be formed by epitaxial growth. In some embodiments, the wide bandgap epitaxial layer 102 may be a silicon carbide epitaxial layer. In some embodiments, the wide bandgap epitaxial layer 102 may be a group III nitride epitaxial layer. The wide bandgap epitaxial layer 102 can be formed using any suitable epitaxial growth process, such as mixed vapor phase epitaxy (HVPE), metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), or other suitable growth processes. The wide bandgap epitaxial layer 102 may have a thickness in the range of about 0.2 μm to about 200 μm, such as about 0.5 μm to about 100 μm, such as about 0.5 μm to about 20 μm.

[0043] In some examples, substrate 104 may include a buffer layer 106. The buffer layer may be an epitaxial layer. Buffer layer 106 may be formed by epitaxial growth on substrate 104. Buffer layer 106 may be used to mitigate lattice mismatch between, for example, substrate 104 (e.g., a sapphire substrate) and wide-bandgap epitaxial layer 102. In some embodiments, buffer layer 106 may be a group III nitride, such as aluminum nitride.

[0044] Method 100 at 120 may include fabricating one or more semiconductor device structures (e.g., transistor structures, Schottky diode structures, etc.) at least partially in the wide bandgap epitaxial layer 102. More specifically, one or more semiconductor device structures (e.g., MOSFETs, Schottky diodes, HEMTs) may be fabricated in the wide bandgap epitaxial layer.

[0045] For illustrative and discussion purposes, fabricating one or more semiconductor device structures may include forming one or more doped regions 112 in a wide bandgap epitaxial layer 102. The one or more doped regions 112 may include regions of a first conductivity type (e.g., n-type) and may include regions of a second conductivity type (e.g., p-type). In some embodiments, the one or more doped regions may be formed, for example, by dopant implantation. In some embodiments, the one or more doped regions may be formed, for example, as part of the epitaxial growth of the wide bandgap epitaxial layer 102.

[0046] Fabricating one or more semiconductor device structures may include forming one or more contacts 114 (e.g., metal contacts) on a wide bandgap epitaxial layer 102. For example, patterned contacts 114 may be formed on the wide bandgap epitaxial layer 102 using polysilicon and / or metal deposition techniques. In some embodiments, contacts 114 may include source contacts, drain contacts, and gate contacts on the surface of the wide bandgap epitaxial layer 102. Contacts 114 may include, for example, solder bumps, contact pads, or other interconnect structures on the wide bandgap epitaxial layer 102.

[0047] Fabricating one or more semiconductor device structures may include other fabrication steps, such as deposition, etching, and metallization. For illustrative and discussion purposes, the description of the fabrication process is provided below. Figure 1 The discussion has been simplified. Those skilled in the art will understand using the disclosure provided herein that any suitable fabrication process can be used to form a semiconductor device structure in the wide bandgap epitaxial layer 102 without departing from the scope of this disclosure.

[0048] refer to Figure 1 Method 100 at 130 may include “flipping” the semiconductor wafer 105 and attaching the semiconductor wafer 105 to the substrate 122. The substrate 122 may include, for example, a lead frame, a heat sink, a clip structure, a DBC substrate, or other suitable substrate. Contacts 114 may be attached to a metal structure 124 on the substrate (e.g., a pad) to provide thermal and / or electrical connections to the contacts 114. In some embodiments, die attachment material may be used to attach the wafer 105 to the substrate 122.

[0049] refer to Figure 1At 140, method 100 may include removing substrate 104 (e.g., a sapphire substrate) from wide bandgap epitaxial layer 102. An example removal process may include inducing a cleavage plane 132 in wide bandgap epitaxial layer 102 and removing substrate 104 from wide bandgap epitaxial layer 102 along cleavage plane 132. Inducing cleavage plane 132 may include emitting one or more laser beams 134 into wide bandgap epitaxial layer 102 to induce a damaged region along cleavage plane 132. Other suitable techniques may be used to induce cleavage plane 132 without departing from the scope of this disclosure, such as implanting one or more materials into wide bandgap epitaxial layer 102.

[0050] Once the substrate 104 has been removed from the wide bandgap epitaxial layer 102, method 100 produces an assembly 145 at 150, which has a (substrate-free) semiconductor die including the wide bandgap epitaxial layer 102 attached to the base 122. The assembly 145 may be monomerized or diced and processed to form a separate semiconductor device package comprising one or more semiconductor dies.

[0051] For example, at 160, method 100 may include providing an insulating material 155 on a wide bandgap epitaxial layer 102 and a substrate 122 to form a power semiconductor device package 150. The insulating material 155 may be an epoxy molding compound. Method 100 may also include providing an underfill material 157 on contacts 114. The underfill material 157 may be, for example, a composite material composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. The underfill material 157 may increase the creepage distance between the source and gate contacts of, for example, the power semiconductor package 150. The power semiconductor device package 150 may be a discrete power semiconductor package. However, in some embodiments, the power semiconductor device package may be, for example, a power module.

[0052] Figure 2 An overview of an example method 200 according to an example implementation of this disclosure is provided. Figure 2 The description is intended to represent structures for identification and description, and not to represent the structures to physical scale. Method 200 includes operations shown in a specific order for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that various steps or operations of any method provided in this disclosure may be adjusted, rearranged, omitted, included, and / or modified in various ways, without departing from the scope of this disclosure.

[0053] Figure 2 Method 200 is similar Figure 1Method 100. More specifically, at 210, the method may include forming a wide bandgap epitaxial layer 202 on a substrate 204. In some examples, the substrate 204 may be a silicon carbide substrate (e.g., 4H single-crystal silicon carbide), a sapphire substrate, or a silicon substrate. Other suitable substrates may be used as substrate 204 without departing from the scope of this disclosure. The substrate 204 may be in the form of a semiconductor wafer 205. In some examples, the substrate 204 has a thickness in the range of about 100 μm to about 1000 μm.

[0054] The wide bandgap epitaxial layer 202 can be formed by epitaxial growth. In some embodiments, the wide bandgap epitaxial layer 202 can be a silicon carbide epitaxial layer. In some embodiments, the wide bandgap epitaxial layer 202 can be a group III nitride. The wide bandgap epitaxial layer 202 can be formed using any suitable epitaxial growth process, such as mixed vapor phase epitaxy (HVPE), metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), or other suitable growth processes. The wide bandgap epitaxial layer 202 can have a thickness in the range of about 0.2 μm to about 200 μm, such as about 0.5 μm to about 100 μm, such as about 0.5 μm to about 20 μm.

[0055] In some examples, substrate 204 may include a buffer layer 206. The buffer layer may be an epitaxial layer. Buffer layer 206 may be formed by epitaxial growth on substrate 204. Buffer layer 206 may be used to mitigate lattice mismatch between, for example, the first substrate 204 (e.g., a sapphire substrate) and the wide bandgap epitaxial layer 202. In some embodiments, buffer layer 206 may be a group III nitride, such as aluminum nitride.

[0056] Method 200 may include fabricating one or more semiconductor device structures (e.g., transistor structures, Schottky diode structures, etc.) at least partially in a wide bandgap epitaxial layer 202 at location 220. More specifically, one or more semiconductor device structures (e.g., MOSFETs, Schottky diodes, HEMTs) may be fabricated in the wide bandgap epitaxial layer 202.

[0057] For illustrative and discussion purposes, fabricating one or more semiconductor device structures may include forming one or more doped regions 212 in a wide bandgap epitaxial layer 202. The one or more doped regions may include regions of a first conductivity type (e.g., n-type) and may include regions of a second conductivity type (e.g., p-type). In some embodiments, the one or more doped regions may be formed, for example, by dopant implantation. In some embodiments, the one or more doped regions may be formed, for example, as part of the epitaxial growth of the wide bandgap epitaxial layer 202.

[0058] Fabricating one or more semiconductor device structures may include forming one or more contacts 214 (e.g., metal contacts) on a wide bandgap epitaxial layer 202. For example, patterned contacts 214 may be formed on the wide bandgap epitaxial layer 202 using polysilicon and / or metal deposition techniques. In some embodiments, contacts 214 may include source contacts, drain contacts, and gate contacts on the surface of the wide bandgap epitaxial layer 202. Contacts 214 may include, for example, solder bumps, contact pads, or other interconnect structures on the wide bandgap epitaxial layer 202.

[0059] Fabricating one or more semiconductor device structures may include other fabrication steps, such as deposition, etching, and metallization. For illustrative and discussion purposes, the description of the fabrication process is provided below. Figure 2 The discussion has been simplified. Those skilled in the art will understand using the disclosure provided herein that any suitable fabrication process can be used to form a semiconductor device structure in the wide bandgap epitaxial layer 202 without departing from the scope of this disclosure.

[0060] refer to Figure 2 Method 200 may include “flipping” the semiconductor wafer 205 at 230 and attaching the semiconductor wafer 205 to a base 222. The base 222 may include, for example, a lead frame, a heat sink, a clip structure, a DBC substrate, or other suitable base. Contacts 214 may be attached to a metal structure 224 (e.g., a pad) on the base to provide thermal and / or electrical connections to the contacts 214. In some embodiments, die attachment material may be used to attach the wafer 205 to the base 222.

[0061] refer to Figure 2 Method 200 may include removing substrate 204 (e.g., sapphire substrate) from wide bandgap epitaxial layer 202 at 240. The removal process at 240 is performed by backside processing tool 264. Backside processing tool 264 may perform process 262 (such as CMP process or polishing process) to remove the backside of wafer 205 (including part or all of substrate 204).

[0062] Once the substrate 204 has been removed from the wide bandgap epitaxial layer 202, method 200 produces an assembly 245 at 250, which has a (substrate-free) semiconductor die including the wide bandgap epitaxial layer 202 attached to a base 222. The assembly 245 may be monomerized or diced and processed to form a separate semiconductor device package comprising one or more semiconductor dies.

[0063] For example, at 260, method 200 may include providing an insulating material 255 on a wide bandgap epitaxial layer 202 and a substrate 222 to form a power semiconductor device package 250. The insulating material 255 may be an epoxy molding compound. Method 200 may also include providing an underfill material 257 on contacts 214. The underfill material 257 may be, for example, a composite material composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. The underfill material 257 may increase the creepage distance between the source and gate contacts of, for example, the power semiconductor package 250. The power semiconductor device package 250 may be a discrete power semiconductor package. However, in some embodiments, the power semiconductor device package may be, for example, a power module.

[0064] Figure 3 An example semiconductor device package 150 (such as using) according to an example embodiment of the present disclosure is depicted. Figure 1 This is a cross-sectional view of a portion of a semiconductor device package manufactured using a method described above. The semiconductor device package 150 includes a wide bandgap epitaxial layer 102. The wide bandgap epitaxial layer 102 may include one or more semiconductor devices, such as MOSFETs, diodes, HEMTs, etc. In some embodiments, the wide bandgap epitaxial layer 102 may be silicon carbide. In some embodiments, the wide bandgap epitaxial layer 102 may be a group III nitride.

[0065] A wide bandgap epitaxial layer 102 may be attached to a base 122. The base 122 may be a lead frame, power substrate, DBC substrate, AMB substrate, clip structure, or other suitable base. The base 122 may include contact portions (e.g., metal pads) 124.1 and 124.2. Contacts (e.g., metal contacts) 114.1 and 114.2 on the wide bandgap epitaxial layer 102 may be attached or coupled to contact portions 124.1 and 124.2, respectively (e.g., using die attachment material). Contacts 114.1 and 114.2 may include solder bumps or other suitable attachment structures. Contact portions 124.1 and 124.2 may include conductive pads (e.g., copper pads). In some examples, contact 114.1 may be a source contact, and contact 114.2 may be a drain contact. The wide bandgap epitaxial layer 102 may also include a gate contact (not shown). In this manner, the wide bandgap epitaxial layer 102 includes one or more lateral power semiconductor devices. The semiconductor device package 150 may include an underfill material 157. The underfill material 157 may be between contacts 114.1 and 114.2. The underfill material 157 may be, for example, a composite material composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. In some examples, the underfill material 157 may also be between contact portions 124.1 and 124.2 on the base 122. The underfill material 157 may provide creepage distance between contacts 114.1 and 114.2. In other words, the underfill material 157 may act as an insulating material between contacts 114.1 and 114.2 to prevent leakage or breakdown between contacts 114.1 and 114.2. The underfill material 157 may be applied before or after contacts 114.1 and 114.2 are attached to contact portions 124.1 and 124.2.

[0066] The semiconductor device package 150 includes an insulating material 155 on a wide bandgap epitaxial layer 102. The insulating material 155 may be an epoxy molding compound. The insulating material 155 may form the housing of the semiconductor device package 150. The insulating material 155 may directly contact the wide bandgap epitaxial layer 102.

[0067] The wide bandgap epitaxial layer 102 does not directly or indirectly contact the silicon carbide substrate. Arrow 170 depicts the heat conduction path for transferring heat from the wide bandgap epitaxial layer 102. As shown, the heat conduction path indicated by arrow 170 does not include the silicon carbide substrate. In fact, the heat conduction path indicated by arrow 170 does not include the semiconductor substrate.

[0068] Figure 4A cross-sectional view of an example lateral transistor device 300 according to an exemplary embodiment of the present disclosure is depicted. This device can be fabricated, at least in part, based on a wide bandgap epitaxial layer 302 without a silicon carbide substrate. The wide bandgap epitaxial layer 302 can be similar to any wide bandgap epitaxial layer described herein. The wide bandgap epitaxial layer 302 can have a thickness ranging from about 0.2 μm to about 200 μm, such as about 0.5 μm to about 100 μm, such as about 0.5 μm to about 20 μm.

[0069] The lateral transistor device 300 may include a wide bandgap epitaxial layer 302 (e.g., an epitaxial silicon carbide layer) having a first surface 302A and an opposing second surface 302B. The lateral transistor device 300 may include source contacts 312, drain contacts 314, and gate contacts 318 on the first surface 302A of the wide bandgap epitaxial layer 302, such that the transistor device 300 is a lateral device. The second surface 302B of the epitaxial silicon carbide layer may not be in contact with a silicon carbide substrate. In some examples, the epitaxial silicon carbide layer is on a sapphire substrate (not shown). In some examples, the epitaxial silicon carbide layer is on a silicon substrate (not shown). In some examples, no semiconductor substrate is present.

[0070] In some examples, the lateral transistor device 300 is a MOSFET. The wide bandgap epitaxial layer 302 may include a drift region 313 having a first conductivity type (e.g., n-type). The drift region 313 may be an n-region. At least a portion of the drift region 313 is located in the wide bandgap epitaxial layer 302 (e.g., a silicon carbide epitaxial layer) between the source contact 312 and the drain contact 314. The wide bandgap epitaxial layer 302 may include a well region 310 of a second conductivity type (e.g., p-type). The well region 310 may be a p+ region. The well region 310 may be located in the epitaxial wide bandgap semiconductor structure 302 between the drift region 313 and the source contact 312.

[0071] In some examples, the wide bandgap epitaxial layer 302 includes a source region 306 of a first conductivity type (e.g., n-type). The source region 306 may be an n+ region. The source region 306 may be immediately adjacent to the source contact 312 within the wide bandgap epitaxial layer 302. In some examples, the wide bandgap epitaxial layer 302 includes a drain region 304 of a first conductivity type (e.g., n-type). The drain region 304 may be an n+ region. The drain region 304 may be immediately adjacent to the drain contact 314 within the wide bandgap epitaxial layer 302.

[0072] In some examples, source contact 312 and drain contact 314 are each ohmic contacts with the wide bandgap epitaxial layer 302. For example, source contact 312 and drain contact 314 may each comprise a nickel-based conductive layer, such as Ni and / or NiSi. Other suitable metals capable of forming ohmic contacts with the wide bandgap epitaxial layer 302 may be used without departing from the scope of this disclosure.

[0073] In some examples, the gate contact 318 may be on a first surface 302A of the wide bandgap epitaxial layer 302. In some embodiments, the gate contact 318 may be a multilayer gate contact 318. The multilayer gate contact 318 may include, for example, one or more polysilicon layers, one or more metal layers, one or more inter-metal dielectric (IMD) layers, etc. The transistor device 300 includes a gate dielectric 316 between the gate contact 318 and the wide bandgap epitaxial layer 302. The gate dielectric 316 may be, for example, an oxide, such as silicon dioxide.

[0074] Due to the lateral nature of the transistor device 300, the source contact 312, drain contact 314, and gate contact 318 can be arranged in various patterns on the first surface 302A of the wide bandgap epitaxial layer 302. Figures 5 to 7 An example contact pattern on surface 302A of wide bandgap semiconductor layer 302 is depicted.

[0075] An underfill material 357 may be present between the source contact 312 and the drain contact 314. The underfill material 357 may be a composite material, for example, composed of a polymer (e.g., an epoxy polymer) and fillers and / or additional components. The underfill material 357 may provide a creepage distance between the source contact 312 and the drain contact 314. In other words, the underfill material 357 may act as an insulating material between the source contact 312 and the drain contact 314 to prevent leakage or breakdown between them.

[0076] In the above description, it is assumed that transistor device 300 is an n-type power MOSFET. However, those skilled in the art will understand using the disclosure provided herein that various aspects of this disclosure may be implemented in p-type power MOSFETs or other semiconductor devices (e.g., IGBTs, Schottky diodes, etc.) without departing from the scope of this disclosure.

[0077] For example, Figure 5 Example source contact 312, drain contact 314, and gate contact 318 are depicted on surface 302A of wide bandgap semiconductor layer 302. Gate pad 320 may be an electrical connection to gate contact 318. Gate contact 318 is located between source contact 312 and drain contact 314. Source contact 312 and drain contact 314 interlock with each other. For example, each of source contact 312 and drain contact 314 has a comb pattern. The fingers of the comb pattern of source contact 312 interlock with the fingers of the comb pattern of drain contact 314.

[0078] Figure 6Example source contact 312, drain contact 314, and gate contact 318 are depicted on surface 302A of a wide bandgap semiconductor layer 302. Gate pad 320 can be an electrical connection to gate contact 318. Gate contact 318 is located between source contact 312 and drain contact 314. Figure 5 Similarly, the source contact 312 and the drain contact 314 intersect each other in a cross-finger pattern. For example, each of the source contact 312 and the drain contact 314 has a comb-like pattern. The fingers of the comb-like pattern of the source contact 312 are triangular in shape. The fingers of the comb-like pattern of the drain contact 314 are triangular in shape. The fingers of the comb-like pattern of the source contact 312 intersect with the fingers of the comb-like pattern of the drain contact 314 in a cross-finger pattern.

[0079] Figure 7 Example source contacts 312, drain contacts 314, and gate contacts 318 are depicted on surface 302A of a wide bandgap semiconductor layer 302. Drain contacts 314 may include a plurality of intersecting drain buses 314.1, 314.2, ..., 314.n forming a grid pattern. Source contacts 312 may include a plurality of source contacts 312 that may be located within spaces 315 formed in the grid pattern. Gate contacts 318 may include a plurality of gate contacts 318, wherein gate pads 320 provide electrical connections for the gate contacts 318. Each gate contact 318 at least partially surrounds one of the plurality of source contacts 312 within the spaces 315 in the grid pattern formed by the drain contacts 314.

[0080] Figures 5 to 7 Example patterns depicting source contact 312, drain contact 314, and gate contact 318 are provided for illustrative and discussion purposes. Other patterns may be used without departing from the scope of this disclosure.

[0081] In some examples, the method according to exemplary aspects of this disclosure may not include removing the substrate from the epitaxial wide bandgap layer. The substrate may be retained. The substrate may not include silicon carbide. For example, the substrate may be a sapphire substrate or a silicon substrate.

[0082] For example, Figure 8 An overview of an example method 400 according to an example implementation of this disclosure is provided. Figure 8 The purpose of this disclosure is to represent structures for identification and description, rather than to represent the structures to physical scale. Method 400 includes operations shown in a specific order for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that various steps or operations of any method provided in this disclosure may be adjusted, rearranged, omitted, included, and / or modified in various ways, without departing from the scope of this disclosure.

[0083] Method 400 is similar to Figure 1 Method 100. However, at 410, method 400 may include forming a wide bandgap epitaxial layer 402 on a substrate 404. Substrate 404 does not include silicon carbide. In some examples, substrate 404 may be a sapphire substrate or a silicon substrate. Substrate 404 may be in the form of a semiconductor wafer 405. In some examples, substrate 404 has a thickness in the range of about 100 μm to about 1000 μm.

[0084] The wide bandgap epitaxial layer 402 can be formed by epitaxial growth. In some embodiments, the wide bandgap epitaxial layer 402 may be a silicon carbide epitaxial layer. In some embodiments, the wide bandgap epitaxial layer 402 may be a group III nitride. The wide bandgap epitaxial layer 402 can be formed using any suitable epitaxial growth process, such as mixed vapor phase epitaxy (HVPE), metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), or other suitable growth processes. The wide bandgap epitaxial layer 402 may have a thickness in the range of about 0.2 μm to about 200 μm, such as about 0.5 μm to about 100 μm, such as about 0.5 μm to about 20 μm.

[0085] In some examples, substrate 404 may include a buffer layer 406. The buffer layer may be an epitaxial layer. Buffer layer 406 may be formed by epitaxial growth on substrate 404. Buffer layer 406 may be used to mitigate lattice mismatch between, for example, a first substrate 404 (e.g., a sapphire substrate) and a wide-bandgap epitaxial layer 402. In some embodiments, buffer layer 406 may be a group III nitride, such as aluminum nitride.

[0086] Method 400 may include fabricating one or more semiconductor device structures (e.g., transistor structures, Schottky diode structures, etc.) at least partially in a wide bandgap epitaxial layer 402 at 420. More specifically, one or more semiconductor device structures (e.g., MOSFETs, Schottky diodes, HEMTs) may be fabricated in the wide bandgap epitaxial layer.

[0087] For illustrative and discussion purposes, fabricating one or more semiconductor device structures may include forming one or more doped regions 412 in a wide bandgap epitaxial region. The one or more doped regions may include regions of a first conductivity type (e.g., n-type) and may include regions of a second conductivity type (e.g., p-type). In some embodiments, the one or more doped regions may be formed, for example, by dopant implantation. In some embodiments, the one or more doped regions may be formed, for example, as part of the epitaxial growth of the wide bandgap epitaxial layer 402.

[0088] Fabricating one or more semiconductor device structures may include forming one or more contacts 414 (e.g., metal contacts) on a wide bandgap epitaxial layer 402. For example, patterned contacts 414 may be formed on the wide bandgap epitaxial layer 402 using polysilicon and / or metal deposition techniques. In some embodiments, contacts 414 may include source contacts, drain contacts, and gate contacts on the surface of the wide bandgap epitaxial layer 402. Contacts 414 may include, for example, solder bumps, contact pads, or other interconnect structures on the wide bandgap epitaxial layer 402.

[0089] Fabricating one or more semiconductor device structures may include other fabrication steps, such as deposition, etching, and metallization. For illustrative and discussion purposes, the description of the fabrication process is provided below. Figure 8 The discussion has been simplified. Those skilled in the art will understand using the disclosure provided herein that any suitable fabrication process can be used to form a semiconductor device structure in the wide bandgap epitaxial layer 102 without departing from the scope of this disclosure.

[0090] refer to Figure 8 Method 400 at 430 may include "flipping" semiconductor wafer 405 and attaching semiconductor wafer 405 to base 422. Base 422 may include, for example, a lead frame, heat sink, clip structure, DBC substrate, or other suitable base. Contact 414 may be attached to a metal structure 424 on the base (e.g., a pad) to provide thermal and / or electrical connections to contact 414. In some embodiments, die attachment material may be used to attach wafer 405 to base 422.

[0091] Figure 8 The method does not involve removing the substrate from the wide bandgap epitaxial layer 402. Instead, method 400 proceeds directly to 460, where method 400 may include depositing an insulating material 455 on the wide bandgap epitaxial layer 402 and the substrate 422 to form a power semiconductor device package 450. The insulating material 455 may be an epoxy molding compound. Method 400 may also include depositing an underfill material 457 on the contacts 414. The underfill material 457 may be, for example, a composite material composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. The underfill material 457 may increase the creepage distance between the source and gate contacts of, for example, the power semiconductor package 450. The power semiconductor device package 450 may be a discrete power semiconductor package. However, in some embodiments, the power semiconductor device package may be, for example, a power module.

[0092] Figure 9A cross-sectional view of a portion of an example semiconductor device package 450 according to an exemplary embodiment of the present disclosure is depicted. The semiconductor device package 450 includes a wide bandgap epitaxial layer 402. The wide bandgap epitaxial layer 402 may include one or more semiconductor devices, such as MOSFETs, diodes, HEMTs, etc. In some embodiments, the wide bandgap epitaxial layer 402 may be silicon carbide. In some embodiments, the wide bandgap epitaxial layer 402 may be a group III nitride.

[0093] A wide bandgap epitaxial layer 402 may be attached to a substrate 422. The substrate 422 may be a lead frame, power substrate, DBC substrate, AMB substrate, clip structure, or other suitable substrate. The substrate 422 may include contact portions (e.g., metal pads) 424.1 and 424.2. Contacts (e.g., metal contacts) 414.1 and 414.2 on the wide bandgap epitaxial layer 402 may be attached or coupled to contact portions 424.1 and 424.2, respectively (e.g., using die attachment material). In some examples, contact 414.1 may be a source contact, and contact 414.2 may be a drain contact. The wide bandgap epitaxial layer 402 may also include a gate contact (not shown). In this manner, the wide bandgap epitaxial layer 402 includes one or more lateral power semiconductor devices.

[0094] The semiconductor device package 450 may include an underfill material 457. The underfill material 457 may be between contacts 414.1 and 414.2 (to provide creepage distance). In some examples, the underfill material 457 may also be between contact portions 424.1 and 424.2 on the base 422.

[0095] The semiconductor device package 450 includes an insulating material 455 on a wide bandgap epitaxial layer 402. The insulating material 455 may be an epoxy molding compound. The insulating material 455 may form the housing of the semiconductor device package 450. The insulating material 455 may be directly on the substrate 404.

[0096] The wide bandgap epitaxial layer 402 does not directly or indirectly contact the silicon carbide substrate. Arrow 470 depicts a heat conduction path for transferring heat from the wide bandgap epitaxial layer 402. As shown, the heat conduction path indicated by arrow 470 does not include the silicon carbide substrate. Instead, the heat conduction path indicated by arrow 470 passes through the substrate 404, which does not include silicon carbide. The heat conduction path indicated by arrow 470 may pass through the substrate 404, which is either a sapphire substrate or a silicon substrate.

[0097] The methods described in the exemplary embodiments of this disclosure can also be used to manufacture vertical power semiconductor devices. Figure 10 An overview of an example method 500 according to an example implementation of this disclosure is provided. Figure 10The purpose of this disclosure is to represent structures for identification and description, rather than to represent the structures to physical scale. Method 500 includes operations shown in a specific order for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that various steps or operations of any method provided in this disclosure may be adjusted, rearranged, omitted, included, and / or modified in various ways without departing from the scope of this disclosure.

[0098] At 510, the method may include forming a wide bandgap epitaxial layer 502 on a substrate 504. In some examples, the substrate 504 may be a silicon carbide substrate (e.g., 4H single-crystal silicon carbide), a sapphire substrate, or a silicon substrate. Other suitable substrates may be used as substrate 504 without departing from the scope of this disclosure. The substrate 504 may be in the form of a semiconductor wafer 505. In some examples, the substrate 504 has a thickness in the range of about 100 μm to about 1000 μm.

[0099] The wide bandgap epitaxial layer 502 can be formed by epitaxial growth. In some embodiments, the wide bandgap epitaxial layer 502 can be a silicon carbide epitaxial layer. In some embodiments, the wide bandgap epitaxial layer 502 can be a group III nitride. The wide bandgap epitaxial layer 502 can be formed using any suitable epitaxial growth process, such as mixed vapor phase epitaxy (HVPE), metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), or other suitable growth processes. The wide bandgap epitaxial layer 502 can have a thickness in the range of about 0.2 μm to about 200 μm, such as about 0.5 μm to about 100 μm, such as about 0.5 μm to about 20 μm.

[0100] In some examples, substrate 504 may include a buffer layer 506. The buffer layer may be an epitaxial layer. Buffer layer 506 may be formed by epitaxial growth on substrate 504. Buffer layer 506 may be used to mitigate, for example, lattice mismatch between substrate 504 (e.g., a sapphire substrate) and wide-bandgap epitaxial layer 502. In some embodiments, buffer layer 506 may be a group III nitride, such as aluminum nitride.

[0101] Method 500 at 520 may include fabricating one or more semiconductor device structures (e.g., transistor structures, Schottky diode structures, etc.) at least partially in a wide bandgap epitaxial layer 502. More specifically, one or more semiconductor device structures (e.g., MOSFETs, Schottky diodes, HEMTs) may be fabricated in the wide bandgap epitaxial layer.

[0102] For illustrative and discussion purposes, fabricating one or more semiconductor device structures may include forming one or more doped regions 512 in a wide bandgap epitaxial region. The one or more doped regions may include regions of a first conductivity type (e.g., n-type) and may include regions of a second conductivity type (e.g., p-type). In some embodiments, the one or more doped regions may be formed, for example, by dopant implantation. In some embodiments, the one or more doped regions may be formed, for example, as part of the epitaxial growth of a wide bandgap epitaxial layer 502.

[0103] Fabricating one or more semiconductor device structures may include forming one or more contacts 514 (e.g., metal contacts) on a wide bandgap epitaxial layer 502. For example, patterned contacts 514 may be formed on the wide bandgap epitaxial layer using polysilicon and / or metal deposition techniques. In some embodiments, contacts 514 may include source contacts, drain contacts, and gate contacts on the surface of the wide bandgap epitaxial layer 502. Contacts 514 may include, for example, solder bumps, contact pads, or other interconnect structures on the wide bandgap epitaxial layer 502.

[0104] Fabricating one or more semiconductor device structures may include other fabrication steps, such as deposition, etching, and metallization. For illustrative and discussion purposes, the description of the fabrication process is provided below. Figure 10 The discussion has been simplified. Those skilled in the art will understand using the disclosure provided herein that any suitable fabrication process can be used to form a semiconductor device structure in the wide bandgap epitaxial layer 502 without departing from the scope of this disclosure.

[0105] refer to Figure 10 Method 500 at 530 may include "flipping" semiconductor wafer 505 and attaching semiconductor wafer 505 to base 522. Base 522 may include, for example, a lead frame, heat sink, clip structure, DBC substrate, or other suitable base. Contact 514 may be attached to a metal structure 524 (e.g., a pad) on the base to provide thermal and / or electrical connections to contact 514. In some embodiments, die attachment material may be used to attach wafer 505 to base 522.

[0106] refer to Figure 10At 540, method 500 may include removing substrate 504 (e.g., a sapphire substrate) from wide bandgap epitaxial layer 502. An example removal process may include inducing a cleavage facet 532 in wide bandgap epitaxial layer 502 and removing the first substrate 504 from wide bandgap epitaxial layer 502 along the cleavage facet 532. Inducing the cleavage facet 532 may include emitting one or more laser beams 534 into wide bandgap epitaxial layer 502 to induce a damaged region along the cleavage facet 532. Other suitable techniques may be used to induce the cleavage facet 532 without departing from the scope of this disclosure, such as implanting one or more materials into wide bandgap epitaxial layer 502. In some embodiments, the removal process at 530 may be implemented using a backside processing tool. The backside processing tool may implement processes (such as CMP processes or polishing processes) to remove the backside of wafer 505, including part or all of substrate 504. In some implementations, an etching process can be used to remove the back side of wafer 505 (including part or all of substrate 504).

[0107] Once the substrate 504 is removed from the wide bandgap epitaxial layer 502, method 500 produces an assembly 545 at 550, which has a (substrate-free) semiconductor die including the wide bandgap epitaxial layer 502 attached to a base 522. Back contacts 553 (e.g., a metal layer) can be formed on the wide bandgap epitaxial layer 502. The back contacts 553 can be formed using any suitable metallization process, such as metal deposition, sputtering, etc. The assembly 545 can be monomerized or diced and processed to form a separate semiconductor device package comprising one or more semiconductor dies.

[0108] For example, at 560, method 500 may include providing an insulating material 555 on a wide bandgap epitaxial layer 502 and a base 522 to form a power semiconductor device package 550. The insulating material 555 may be an epoxy molding compound. Method 500 may also include providing an underfill material 557 on contacts 514. The underfill material 557 may be, for example, a composite material composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. The underfill material 557 may increase the creepage distance between the source and gate contacts of, for example, the power semiconductor package 550. The power semiconductor device package 550 may be a discrete power semiconductor package. However, in some embodiments, the power semiconductor device package may be, for example, a power module.

[0109] Figure 11A cross-sectional view of a portion of an example semiconductor device package 550 according to an exemplary embodiment of the present disclosure is depicted. The semiconductor device package 550 includes a wide bandgap epitaxial layer 502. The wide bandgap epitaxial layer 502 may include one or more semiconductor devices, such as MOSFETs, diodes, HEMTs, etc. In some embodiments, the wide bandgap epitaxial layer 502 may be silicon carbide. In some embodiments, the wide bandgap epitaxial layer 502 may be a group III nitride.

[0110] A wide bandgap epitaxial layer 502 may be attached to a base 522. The base 522 may be a lead frame, a DBC substrate, a clip structure, or other suitable base. The base 522 may include contact portions (e.g., metal pads) 524.1 and 524.2. Contacts (e.g., metal contacts) 514.1 and 514.2 on the wide bandgap epitaxial layer 502 may be attached or coupled to contact portions 524.1 and 524.2, respectively (e.g., using die attachment material). In some examples, contact 514.1 may be a source contact, and contact 514.2 may be a drain contact. The wide bandgap epitaxial layer 502 may also include a gate contact (not shown). In this manner, the wide bandgap epitaxial layer 502 includes one or more lateral power semiconductor devices.

[0111] Semiconductor device package 550 may include underfill material 557. Underfill material 557 may be between contacts 514.1 and 514.2. Underfill material 557 may be a composite material, for example, composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. In some examples, underfill material 557 may also be between contact portions 524.1 and 524.2 on a base 522. Underfill material 557 may provide creepage distance between contacts 514.1 and 514.2. In other words, underfill material 557 may act as an insulating material between contacts 514.1 and 514.2 to prevent leakage or breakdown between contacts 514.1 and 514.2. Underfill material 557 may be applied before or after contacts 514.1 and 514.2 are attached to contact portions 524.1 and 524.2.

[0112] The semiconductor device package 550 includes an insulating material 555 on a wide bandgap epitaxial layer 502. The insulating material 555 may be an epoxy molding compound. The insulating material 555 may form the housing of the semiconductor device package 550. The insulating material 555 may be directly on the back contact 553.

[0113] The wide bandgap epitaxial layer 502 does not directly or indirectly contact the silicon carbide substrate. Arrow 570 depicts the thermal path for transferring heat from the wide bandgap epitaxial layer 502. As shown, the thermal path indicated by arrow 570 does not include the silicon carbide substrate. Instead, the thermal path indicated by arrow 570 passes through the back contact 553.

[0114] Figure 12 A cross-sectional view of an example vertical transistor device 600 according to an exemplary embodiment of the present disclosure is depicted. This device can be fabricated, at least in part, based on a wide bandgap epitaxial layer 602 without a silicon carbide substrate. The wide bandgap epitaxial layer 602 can be similar to any wide bandgap epitaxial layer described herein. The wide bandgap epitaxial layer 602 can have a thickness ranging from about 0.2 μm to about 200 μm, such as about 0.5 μm to about 100 μm, such as about 0.5 μm to about 20 μm.

[0115] The wide bandgap epitaxial layer 602 (e.g., an epitaxial silicon carbide layer) may have a first surface 602A and an opposing second surface 602B. The vertical transistor device 600 may include a source contact 612 on the first surface 602A. The vertical transistor device 600 may include a drain contact 614 on the second surface 602B. The vertical transistor device 600 may include a gate contact 618 on the first surface 602A of the wide bandgap epitaxial layer 602, such that the transistor device 600 is a vertical device.

[0116] The second surface 602B of the silicon carbide epitaxial layer may not be in contact with the silicon carbide substrate. In some examples, the silicon carbide epitaxial layer is on a sapphire substrate (not shown). In some examples, the silicon carbide epitaxial layer is on a silicon substrate (not shown). In some examples, there is no semiconductor substrate.

[0117] In some examples, the vertical transistor device 600 is a MOSFET. The wide bandgap epitaxial layer 602 may include a drift region 613 having a first conductivity type (e.g., n-type). The drift region 613 may be an n-type region. At least a portion of the drift region 613 lies within the wide bandgap epitaxial layer 602 (e.g., an epitaxial silicon carbide layer) between the source contacts 612 and below the gate contact 618. The wide bandgap epitaxial layer 602 may include a deep well region 610 of a second conductivity type (e.g., p-type) below each source contact 612.

[0118] The wide bandgap epitaxial layer 602 may include a base region 605 and a source region 606 beneath the source contact 612. The base region 605 may be of a second conductivity type. In some examples, the base region 605 is a p+ region. The source region 606 may be of a first conductivity type (e.g., n-type). The source region 606 may be an n+ region. The source region 606 may be immediately adjacent to the source contact 612 within the wide bandgap epitaxial layer 602.

[0119] In some examples, the source contact 612 and the drain contact 614 are each ohmic contacts with the wide bandgap epitaxial layer 602. For example, the source contact 612 and the drain contact 614 may each comprise a nickel-based conductive layer, such as Ni and / or NiSi. Other suitable metals capable of forming ohmic contacts with the wide bandgap epitaxial layer 602 may be used without departing from the scope of this disclosure.

[0120] In some examples, the gate contact 618 may be on a first surface 602A of the wide bandgap epitaxial layer 602. In some embodiments, the gate contact 618 may be a multilayer gate contact 618. The multilayer gate contact 618 may include, for example, one or more polysilicon layers, one or more metal layers, one or more inter-metal dielectric (IMD) layers, etc. The transistor device 600 includes a gate dielectric 616 between the gate contact 618 and the wide bandgap epitaxial layer 602. The gate dielectric 616 may be, for example, an oxide, such as silicon dioxide.

[0121] The underfill material 657 may be present between the source contacts 612 and on the gate contact 618. The underfill material 657 may be a composite material, for example, composed of a polymer (e.g., an epoxy polymer) with fillers and / or additional components. The underfill material 657 may be an insulator between the different source contacts 612 and between the source contacts 612 and the gate contact 618.

[0122] In the above description, it is assumed that transistor device 600 is an n-type power MOSFET. However, those skilled in the art will understand using the disclosure provided herein that various aspects of this disclosure may be implemented in p-type power MOSFETs or other semiconductor devices (e.g., IGBTs, Schottky diodes, etc.) without departing from the scope of this disclosure.

[0123] Examples of this disclosure are set forth below. Any of the following features or examples may be used in combination with any implementation or feature provided in this disclosure.

[0124] One example aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a wide bandgap epitaxial layer. The wide bandgap epitaxial layer includes silicon carbide. The wide bandgap epitaxial layer has a first surface and an opposing second surface. The semiconductor device includes a first contact on the first surface of the wide bandgap epitaxial layer. The second surface does not directly or indirectly contact a silicon carbide substrate.

[0125] In some embodiments, the semiconductor device includes a second contact on a second surface of a wide bandgap epitaxial layer, such that the semiconductor device is a vertical power semiconductor device.

[0126] In some implementations, there is no silicon carbide substrate between the wide bandgap epitaxial layer and the second contact.

[0127] In some implementations, there is no semiconductor substrate between the wide bandgap epitaxial layer and the second contact.

[0128] In some embodiments, the semiconductor device includes a second contact on a first surface of a wide bandgap epitaxial layer, such that the semiconductor device is a lateral power semiconductor device.

[0129] In some implementations, the wide bandgap epitaxial layer is on a sapphire substrate.

[0130] In some implementations, the wide bandgap epitaxial layer is on a silicon substrate.

[0131] In some implementations, the wide bandgap epitaxial layer does not contact any semiconductor substrate.

[0132] In some embodiments, the semiconductor device includes a gate contact located between a first contact and a second contact on a first surface of a wide bandgap epitaxial layer.

[0133] In some embodiments, the semiconductor device includes an underfill material located between a first contact and a second contact on at least a portion of a wide bandgap epitaxial layer.

[0134] In some implementations, the wide bandgap epitaxial layer is mounted in a flip-chip configuration within a semiconductor device package.

[0135] In some implementations, the wide bandgap epitaxial layer directly contacts the insulating material of the semiconductor device package.

[0136] In some implementations, the wide bandgap epitaxial layer includes one or more doped regions.

[0137] In some embodiments, the wide bandgap epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

[0138] In some embodiments, the second surface provides at least a portion of a heat dissipation path for dissipating heat from the wide bandgap epitaxial layer, wherein the heat dissipation path does not include the silicon carbide substrate.

[0139] In some implementations, the semiconductor device includes a Schottky diode or a MOSFET.

[0140] Another example aspect of this disclosure relates to a semiconductor device package. The semiconductor device package includes a wide bandgap epitaxial layer. The wide bandgap epitaxial layer has a first surface and an opposing second surface. The semiconductor device package includes a first contact on the first surface of the wide bandgap epitaxial layer. The first surface of the wide bandgap epitaxial layer is mounted on a substrate in a flip-chip configuration. The second surface of the wide bandgap epitaxial layer provides at least a portion of a heat dissipation path configured to dissipate heat from the wide bandgap epitaxial layer. The heat dissipation path does not include a semiconductor substrate.

[0141] In some embodiments, the semiconductor device package includes a second contact on a second surface of a wide bandgap epitaxial layer, such that the semiconductor device is a vertical power semiconductor device.

[0142] In some implementations, there is no semiconductor substrate between the wide bandgap epitaxial layer and the second contact.

[0143] In some embodiments, the semiconductor device package includes a second contact on a first surface of a wide bandgap epitaxial layer, such that the semiconductor device is a lateral power semiconductor device.

[0144] In some implementations, the wide bandgap epitaxial layer does not contact any semiconductor substrate.

[0145] In some embodiments, the semiconductor device includes a gate contact located between a first contact and a second contact on a first surface of a wide bandgap epitaxial layer.

[0146] In some embodiments, the semiconductor device includes an underfill material located between a first contact and a second contact on at least a portion of a wide bandgap epitaxial layer.

[0147] In some implementations, the wide bandgap epitaxial layer includes one or more doped regions.

[0148] In some embodiments, the wide bandgap epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

[0149] In some implementations, the wide bandgap epitaxial layer includes a silicon carbide epitaxial layer.

[0150] In some implementations, the wide bandgap epitaxial layer includes a group III nitride epitaxial layer.

[0151] In some embodiments, the second surface provides at least a portion of a heat dissipation path for dissipating heat from the wide bandgap epitaxial layer, wherein the heat dissipation path does not include the silicon carbide substrate.

[0152] In some implementations, the base includes a lead frame, a clip structure, or a direct bonded copper (DBC) base.

[0153] In some implementations, the insulating material of the semiconductor package is directly on the second surface of the wide bandgap epitaxial layer.

[0154] In some implementations, the insulating material is epoxy molding compound.

[0155] In some implementations, the semiconductor device package includes a Schottky diode or a MOSFET.

[0156] Another exemplary aspect of this disclosure relates to a lateral silicon carbide-based transistor device. The transistor device includes a silicon carbide epitaxial layer having a first surface and an opposite second surface. The transistor device includes a drain contact, a source contact, and a gate contact on the first surface of the silicon carbide epitaxial layer. The second surface of the silicon carbide epitaxial layer does not contact a silicon carbide substrate.

[0157] In some implementations, the silicon carbide epitaxial layer is on a sapphire substrate.

[0158] In some embodiments, the silicon carbide epitaxial layer is on a silicon substrate.

[0159] In some implementations, a semiconductor substrate is not present.

[0160] In some implementations, the transistor device includes an underfill material on an epitaxial silicon carbide layer to increase the creepage distance between the source and drain contacts.

[0161] In some implementations, the underfill material is on the gate contacts.

[0162] In some embodiments, the silicon carbide epitaxial layer includes a drift region having a first conductivity type, wherein at least a portion of the drift region is between a source contact and a drain contact.

[0163] In some embodiments, the silicon carbide epitaxial layer includes a well region of a second conductivity type, the well region being located between the drift region and the source contact.

[0164] In some embodiments, the silicon carbide epitaxial layer includes a source region of a first conductivity type adjacent to the source contact and a drain region of a first conductivity type adjacent to the drain contact.

[0165] In some implementations, the source and drain contacts are each ohmic contacts of the silicon carbide epitaxial layer.

[0166] In some embodiments, the transistor device includes a gate dielectric between a gate contact and an epitaxial silicon carbide layer.

[0167] In some embodiments, the second surface provides at least a portion of a heat dissipation path for dissipating heat from the silicon carbide epitaxial layer, wherein the heat dissipation path does not include the silicon carbide substrate.

[0168] In some embodiments, the silicon carbide epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

[0169] In some implementations, the silicon carbide epitaxial layer is mounted in a flip-chip configuration within a semiconductor device package.

[0170] In some implementations, the insulating material of the semiconductor package is directly on the second surface of the silicon carbide epitaxial layer.

[0171] In some implementations, the drain contact interlocks at least partially with the source contact in a finger-like manner.

[0172] In some embodiments, the drain contacts include a plurality of intersecting drain buses forming a grid, wherein the source contacts include a plurality of source contacts within the space of the grid, and wherein the gate contacts include a plurality of gate contacts, each gate contact at least partially surrounding one of the plurality of source contacts.

[0173] Another example aspect of this disclosure relates to a method. The method includes forming a wide bandgap epitaxial layer on a substrate. The wide bandgap epitaxial layer has a first surface and an opposing second surface. The second surface is on the substrate. The method includes forming contacts on the first surface of the wide bandgap epitaxial layer. The method includes placing the first surface of the wide bandgap epitaxial layer on a pedestal. The method includes removing the substrate from the second surface of the wide bandgap epitaxial layer.

[0174] In some embodiments, the substrate includes a sapphire substrate.

[0175] In some embodiments, the substrate includes a silicon carbide substrate.

[0176] In some embodiments, removing the substrate from the second surface includes: forming a cleavage plane in a wide bandgap epitaxial layer; and removing the substrate along the cleavage plane.

[0177] In some implementations, forming the cleavage surface includes emitting one or more laser beams into a wide bandgap epitaxial layer.

[0178] In some implementations, forming cleavage surfaces includes injecting one or more materials into a wide bandgap epitaxial layer.

[0179] In some implementations, substrate removal includes grinding, etching, or chemical mechanical polishing (CMP) processes.

[0180] In some implementations, the wide bandgap epitaxial layer includes one or more doped regions.

[0181] In some embodiments, the wide bandgap epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

[0182] In some embodiments, the substrate has a thickness ranging from about 100 μm to about 1000 μm.

[0183] In some implementations, the wide bandgap epitaxial layer includes a silicon carbide epitaxial layer.

[0184] In some implementations, the wide bandgap epitaxial layer includes a group III nitride epitaxial layer.

[0185] While the subject matter has been described in detail with respect to specific exemplary embodiments of the invention, it should be understood that those skilled in the art, upon gaining an understanding of the foregoing, can readily generate changes, modifications, and equivalents of these embodiments. Therefore, the scope of this disclosure is by way of example rather than limitation, and this disclosure does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter, as will be readily understood by those skilled in the art.

Claims

1. A semiconductor device, comprising: A wide bandgap epitaxial layer comprising silicon carbide, the wide bandgap epitaxial layer having a first surface and an opposing second surface; The first contact point is located on the first surface of the wide bandgap epitaxial layer; and The second surface is not in direct or indirect contact with the silicon carbide substrate.

2. The semiconductor device according to claim 1, wherein, The semiconductor device includes a second contact on the second surface of the wide bandgap epitaxial layer, such that the semiconductor device is a vertical power semiconductor device.

3. The semiconductor device according to claim 2, wherein, There is no silicon carbide substrate between the wide bandgap epitaxial layer and the second contact.

4. The semiconductor device according to claim 2, wherein, There is no semiconductor substrate between the wide bandgap epitaxial layer and the second contact.

5. The semiconductor device according to claim 1, wherein, The semiconductor device includes a second contact on the first surface of the wide bandgap epitaxial layer, such that the semiconductor device is a lateral power semiconductor device.

6. The semiconductor device according to claim 5, wherein, The wide bandgap epitaxial layer is on a sapphire substrate.

7. The semiconductor device according to claim 5, wherein, The wide bandgap epitaxial layer is on a silicon substrate.

8. The semiconductor device according to claim 5, wherein, The wide bandgap epitaxial layer does not contact any semiconductor substrate.

9. The semiconductor device of claim 5, further comprising a gate contact located between the first contact and the second contact on the first surface of the wide bandgap epitaxial layer.

10. The semiconductor device of claim 5, further comprising an underfill material located on at least a portion of the wide bandgap epitaxial layer between the first contact and the second contact.

11. The semiconductor device according to claim 1, wherein, The wide bandgap epitaxial layer is mounted in a flip-chip configuration within a semiconductor device package.

12. The semiconductor device according to claim 11, wherein, The wide bandgap epitaxial layer is in direct contact with the insulating material of the semiconductor device package.

13. The semiconductor device according to claim 1, wherein, The wide bandgap epitaxial layer includes one or more doped regions.

14. The semiconductor device according to claim 1, wherein, The wide bandgap epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

15. The semiconductor device according to claim 1, wherein, The second surface provides at least a portion of a heat dissipation path for dissipating heat from the wide bandgap epitaxial layer, wherein the heat dissipation path does not include the silicon carbide substrate.

16. The semiconductor device according to claim 1, wherein, The semiconductor device includes a Schottky diode or a MOSFET.

17. A semiconductor device package, comprising: A wide bandgap epitaxial layer having a first surface and an opposing second surface; The first contact point is located on the first surface of the wide bandgap epitaxial layer; and The first surface of the wide bandgap epitaxial layer is mounted on a substrate in a flip-chip configuration; and The second surface of the wide bandgap epitaxial layer provides at least a portion of a heat dissipation path configured to dissipate heat from the wide bandgap epitaxial layer, wherein the heat dissipation path does not include a semiconductor substrate.

18. The semiconductor device package of claim 17, wherein, The semiconductor device package includes a second contact on the second surface of the wide bandgap epitaxial layer, such that the semiconductor device is a vertical power semiconductor device.

19. The semiconductor device package of claim 18, wherein, There is no semiconductor substrate between the wide bandgap epitaxial layer and the second contact.

20. The semiconductor device package of claim 17, wherein, The semiconductor device package includes a second contact on the first surface of the wide bandgap epitaxial layer, such that the semiconductor device is a lateral power semiconductor device.

21. The semiconductor device package of claim 20, wherein, The wide bandgap epitaxial layer does not contact any semiconductor substrate.

22. The semiconductor device package of claim 20, further comprising a gate contact located between the first contact and the second contact on the first surface of the wide bandgap epitaxial layer.

23. The semiconductor device package of claim 20, further comprising an underfill material located on at least a portion of the wide bandgap epitaxial layer between the first contact and the second contact.

24. The semiconductor device package of claim 17, wherein, The wide bandgap epitaxial layer includes one or more doped regions.

25. The semiconductor device package according to claim 17, wherein, The wide bandgap epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

26. The semiconductor device package of claim 17, wherein, The wide bandgap epitaxial layer includes a silicon carbide epitaxial layer.

27. The semiconductor device package of claim 17, wherein, The wide bandgap epitaxial layer includes a group III nitride epitaxial layer.

28. The semiconductor device package according to claim 17, wherein, The second surface provides at least a portion of a heat dissipation path for dissipating heat from the wide bandgap epitaxial layer, wherein the heat dissipation path does not include the silicon carbide substrate.

29. The semiconductor device package according to claim 17, wherein, The base includes a lead frame, a clip structure, or a direct bonded copper (DBC) base.

30. The semiconductor device package according to claim 17, wherein, The insulating material of the semiconductor package is directly on the second surface of the wide bandgap epitaxial layer.

31. The semiconductor device package according to claim 30, wherein, The insulating material is epoxy resin molding compound.

32. The semiconductor device package according to claim 17, wherein, The semiconductor device package includes a Schottky diode or a MOSFET.

33. A lateral silicon carbide-based transistor device, comprising: A silicon carbide epitaxial layer having a first surface and an opposing second surface; The drain contact, source contact, and gate contact are on the first surface of the silicon carbide epitaxial layer; and The second surface of the silicon carbide epitaxial layer does not contact the silicon carbide substrate.

34. The lateral silicon carbide-based transistor device according to claim 33, wherein, The silicon carbide epitaxial layer is on a sapphire substrate.

35. The lateral silicon carbide-based transistor device according to claim 33, wherein, The silicon carbide epitaxial layer is on a silicon substrate.

36. The lateral silicon carbide-based transistor device according to claim 33, wherein, There is no semiconductor substrate.

37. The lateral silicon carbide-based transistor device of claim 33 further includes an underfill material on the silicon carbide epitaxial layer to increase the creepage distance between the source contact and the drain contact.

38. The lateral silicon carbide-based transistor device according to claim 37, wherein, The underfill material is on the gate contact.

39. The lateral silicon carbide-based transistor device according to claim 38, wherein, The silicon carbide epitaxial layer includes a drift region having a first conductivity type, wherein at least a portion of the drift region is between the source contact and the drain contact.

40. The lateral silicon carbide-based transistor device according to claim 39, wherein, The silicon carbide epitaxial layer includes a well region of a second conductivity type, the well region being located between the drift region and the source contact.

41. The lateral silicon carbide-based transistor device according to claim 40, wherein, The silicon carbide epitaxial layer includes a source region of the first conductivity type adjacent to the source contact and a drain region of the first conductivity type adjacent to the drain contact.

42. The lateral silicon carbide-based transistor device according to claim 33, wherein, The source contact and the drain contact are each ohmic contacts of the silicon carbide epitaxial layer.

43. The lateral silicon carbide-based transistor device of claim 33 further includes a gate dielectric between the gate contact and the silicon carbide epitaxial layer.

44. The lateral silicon carbide-based transistor device according to claim 33, wherein, The second surface provides at least a portion of a heat dissipation path for dissipating heat from the silicon carbide epitaxial layer, wherein the heat dissipation path does not include the silicon carbide substrate.

45. The lateral silicon carbide-based transistor device according to claim 33, wherein, The silicon carbide epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

46. ​​The lateral silicon carbide-based transistor device according to claim 33, wherein, The silicon carbide epitaxial layer is mounted in a flip-chip configuration within a semiconductor device package.

47. The lateral silicon carbide-based transistor device according to claim 33, wherein, The insulating material of the semiconductor package is directly on the second surface of the silicon carbide epitaxial layer.

48. The lateral silicon carbide-based transistor device according to claim 33, wherein, The drain contact at least partially intersects the source contact in a finger-like manner.

49. The lateral silicon carbide-based transistor device according to claim 33, wherein, The drain contacts include a plurality of intersecting drain buses forming a grid, wherein the source contacts include a plurality of source contacts within the space of the grid, and wherein the gate contacts include a plurality of gate contacts, each gate contact at least partially surrounding one of the plurality of source contacts.

50. A method comprising: A wide bandgap epitaxial layer is disposed on a substrate, the wide bandgap epitaxial layer having a first surface and an opposing second surface, the second surface being on the substrate; A contact is provided on the first surface of the wide bandgap epitaxial layer; The first surface of the wide bandgap epitaxial layer is placed on the base; as well as The substrate is removed from the second surface of the wide bandgap epitaxial layer.

51. The method according to claim 50, wherein, The substrate includes a sapphire substrate.

52. The method according to claim 50, wherein, The substrate includes a silicon carbide substrate.

53. The method according to claim 50, wherein, Removing the substrate from the second surface includes: Cleavage surfaces are formed in the wide bandgap epitaxial layer; and The substrate is removed along the cleavage plane.

54. The method according to claim 53, wherein, Forming the cleavage surface involves emitting one or more laser beams into the wide bandgap epitaxial layer.

55. The method according to claim 53, wherein, Forming cleavage surfaces involves injecting one or more materials into the wide bandgap epitaxial layer.

56. The method of claim 50, wherein, Removing the substrate includes a grinding process, an etching process, or a chemical mechanical polishing (CMP) process.

57. The method of claim 50, wherein, The wide bandgap epitaxial layer includes one or more doped regions.

58. The method according to claim 50, wherein, The wide bandgap epitaxial layer has a thickness ranging from about 0.2 μm to about 200 μm.

59. The method according to claim 50, wherein, The substrate has a thickness ranging from about 100 μm to about 1000 μm.

60. The method of claim 50, wherein, The wide bandgap epitaxial layer includes a silicon carbide epitaxial layer.

61. The method according to claim 50, wherein, The wide bandgap epitaxial layer includes a group III nitride epitaxial layer.

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