Memory allocation method and device, electronic equipment, chip, circuit, medium

Abstract

The disclosure provides a memory allocation method and device, electronic equipment, chip, circuit and medium. The method is applied to a device including a display engine. The display engine includes a plurality of target processing modules and a shared memory pool commonly used by the plurality of target processing modules. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirement range of the plurality of target processing modules. The method includes: obtaining the current actual memory requirement of the plurality of target processing modules; and allocating storage units to the plurality of target processing modules according to the current actual memory requirement of the plurality of target processing modules and the capacity of the single storage unit. According to the embodiment of the disclosure, the memory hardware area can be saved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a memory allocation method and apparatus, electronic device, chip, circuit, and medium. Background Technology

[0002] In a display engine, each processing module typically operates independently, with its output data directly serving downstream modules. For a single processing module, the data processing flow is generally as follows: intermediate data is written to Static Random-Access Memory (SRAM); subsequently, this data is retrieved again to perform calculations. In related technologies, hardware devices typically allocate private SRAM to each processing module to effectively ensure data independence. However, this approach significantly increases hardware area. Summary of the Invention

[0003] This disclosure provides a memory allocation method and apparatus, electronic device, chip, circuit, and medium.

[0004] In a first aspect, this disclosure provides a memory allocation method applied to a device including a display engine, the display engine including multiple target processing modules and a shared memory pool for use by the multiple target processing modules, the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool being determined based on the memory requirements of the multiple target processing modules, the method comprising: obtaining the current actual memory requirements of the multiple target processing modules; and allocating storage units to the multiple target processing modules based on the current actual memory requirements of the multiple target processing modules and the capacity of the single storage unit.

[0005] In some possible implementations, for each target processing module, the memory requirement range of the target processing module is determined based on the type of the target processing module. The memory requirement range includes a first threshold and a second threshold. The first threshold is the minimum memory capacity required for the corresponding target processing module to run, and the second threshold is the maximum memory capacity required for the corresponding target processing module to run. The total capacity of the shared memory pool is determined based on the sum of the second thresholds of each target processing module. The capacity of a single storage unit is determined based on the proportional relationship between the first thresholds of each target processing module.

[0006] In some possible implementations, when the target processing module is a direct memory access module for the image layer, the memory requirement range of the target processing module is determined according to the compression format of the target processing module.

[0007] In some possible implementations, when the compression format of the target processing module is tile-based rearrangement, the memory requirement range of the target processing module is determined based on the image cropping size, resolution, and incomplete transactions of the AXI protocol; when the compression format of the target processing module is linear layout, the memory requirement range of the target processing module is determined based on one or more of the image data format, burst length of the AXI protocol, incomplete transactions of the AXI protocol, and the size of data bytes transmitted in a single session.

[0008] In some possible implementations, where the target processing module is an image scaling preprocessing module, the memory requirements of the target processing module are determined based on the maximum resolution width and data format size supported by the display engine.

[0009] In some possible implementations, when the target processing module is a write-back module or a post-direct memory access module, the memory requirement range of the target processing module is determined based on the capacity of the cached pixels.

[0010] In some possible implementations, allocating storage units to the multiple target processing modules based on their current actual memory requirements and the capacity of a single storage unit includes: determining the memory allocation priority of the multiple target processing modules based on one or more of their timing dependencies, real-time characteristics, and data flow order; allocating storage units to each target processing module sequentially in descending order of priority, wherein, for any target processing module, the number of storage units to be allocated to the target processing module is determined based on its current actual memory requirements and the capacity of a single storage unit, and the number of storage units is allocated from the remaining storage units in the shared memory pool for the exclusive use of the target processing module.

[0011] In some possible implementations, the method further includes: when a corresponding number of storage units have been allocated to each target processing module, determining the remaining storage units allocated in the shared memory pool as shared memory resources for the multiple target processing modules to be shared by the multiple target processing modules.

[0012] In some possible implementations, the method further includes: re-acquiring the actual memory requirements of the plurality of target processing modules in response to an adjustment of one or more of the type, compression format, and associated parameters of the target processing modules; and allocating storage units to the plurality of target processing modules based on the re-acquired actual memory requirements and the capacity of the individual storage units.

[0013] Secondly, this disclosure provides a memory allocation apparatus applied to a device including a display engine, the display engine including multiple target processing modules and a shared memory pool for use by the multiple target processing modules, the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool being determined according to the memory requirements of the multiple target processing modules, the apparatus including: a first acquisition module, used to acquire the current actual memory requirements of the multiple target processing modules; and a first allocation module, used to allocate a corresponding number of storage units to the multiple target processing modules according to the current actual memory requirements of the multiple target processing modules and the capacity of the single storage unit.

[0014] Thirdly, this disclosure provides an electronic device comprising: at least one display engine, each display engine including a plurality of target processing modules and a shared memory pool for common use by the plurality of target processing modules, the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool being determined according to the memory requirements of the plurality of target processing modules; a memory communicatively connected to the at least one display engine; wherein the memory stores one or more computer programs executable by the at least one display engine, the one or more computer programs being executed by the at least one display engine to enable the at least one display engine to perform the memory allocation method described above.

[0015] Fourthly, this disclosure provides a chip including at least one display engine, each display engine including multiple target processing modules and a shared memory pool for use by the multiple target processing modules, wherein the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules, and the chip is used to implement the above-described memory allocation method.

[0016] Fifthly, this disclosure provides a circuit including multiple target processing modules and a shared memory pool for use by the multiple target processing modules. The multiple target processing modules are connected to the shared memory pool. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules. The circuit is used to implement the memory allocation method described above.

[0017] Sixthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described memory allocation method.

[0018] In the embodiments provided in this disclosure, the total capacity of the shared memory pool in the display engine and the capacity of a single storage unit in the shared memory pool are determined based on the memory requirements of each target processing module in the display engine. The display engine can allocate storage units to these target processing modules according to their current actual memory requirements and the capacity of a single storage unit in the shared memory pool. On the one hand, multiple target processing modules sharing the shared memory pool can reduce hardware area; on the other hand, by determining the total capacity of the shared memory pool and the capacity of a single storage unit based on the memory requirements of multiple target processing modules, a reasonable number of storage units can be dynamically allocated to each target processing module according to its actual memory requirements, thereby effectively reducing hardware area while meeting the usage requirements of each target processing module.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a flowchart of a memory allocation method provided in an embodiment of the present disclosure.

[0022] Figure 2 An exemplary block diagram of a display engine provided in an embodiment of this disclosure.

[0023] Figure 3 This is a schematic diagram illustrating the memory capacity requirements of the DMA module provided in an embodiment of this disclosure.

[0024] Figure 4 This is a schematic diagram illustrating the maximum memory capacity of the memory pool provided in an embodiment of this disclosure.

[0025] Figure 5 This is a schematic diagram illustrating the allocation of storage units provided in an embodiment of this disclosure.

[0026] Figure 6 This is a block diagram of a memory allocation device provided in an embodiment of the present disclosure.

[0027] Figure 7 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0029] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0030] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0032] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0033] In the hardware implementation of related technologies, the maximum SRAM capacity used by each processing module of each display layer in the display engine needs to be calculated, and a private SRAM of corresponding capacity needs to be allocated to each processing module. This method of allocating private SRAM to each processing module significantly increases the area required by the hardware. This situation is particularly prominent in chips with multiple display engines.

[0034] According to the memory allocation method of this disclosure, the total capacity of the shared memory pool in the display engine and the capacity of a single storage unit in the shared memory pool are determined based on the memory requirement range of each target processing module in the display engine. The display engine can allocate storage units to these target processing modules based on their current actual memory requirements and the capacity of a single storage unit in the shared memory pool. On the one hand, multiple target processing modules sharing the shared memory pool can reduce hardware area; on the other hand, by determining the total capacity of the shared memory pool and the capacity of a single storage unit based on the memory requirement range of multiple target processing modules, a reasonable number of storage units can be dynamically allocated to each target processing module according to its actual memory requirements, thereby effectively reducing hardware area while meeting the usage requirements of each target processing module.

[0035] The memory method according to embodiments of this disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, wearable device, etc. The method can be implemented by a processor calling computer-readable program instructions stored in memory. Alternatively, the method can be executed by a server.

[0036] The memory allocation method provided in this disclosure can be applied to a device including a display engine, which may be a processing unit, a chip, an electronic device, etc. The display engine includes multiple target processing modules and a shared memory pool for use by the multiple target processing modules. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules.

[0037] The runtime scenario can be used to indicate the application requirements and / or functional configuration of the display engine. Based on the runtime scenario, it can be determined which processing modules in the display engine require memory sharing, what type of these processing modules are, and / or the specific content of the parameters used by these processing modules. This disclosure does not limit the runtime scenario.

[0038] A target processing module can represent a processing module within the display engine that is capable of memory sharing. Multiple target processing modules are determined from among multiple processing modules based on the display engine's operating scenario. It should be understood that the display engine includes multiple processing modules. These processing modules can be enabled or disabled depending on the operating mode. For enabled processing modules, they may have various memory capacity requirements, or they may maintain a single memory capacity requirement; for disabled processing modules, no memory space needs to be allocated.

[0039] In one possible implementation, the processing modules currently in operation can be determined first, and then the processing modules with multiple memory capacity requirements can be selected as target processing modules. Since the target processing modules have multiple memory capacity requirements, allocating dedicated memory to them might waste memory space. Therefore, in this embodiment, a shared memory pool can be set up for the target processing modules to improve memory resource utilization and reduce hardware area.

[0040] After the target processing modules are determined, the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool can be determined based on the memory requirements of each target processing module.

[0041] A shared memory pool is a memory space shared by multiple target processing modules. Since each target processing module has various memory capacity requirements, allocating dedicated memory space according to the maximum independent requirement of each module would result in a large amount of idle memory, increasing the hardware area and power consumption of the storage space. Therefore, embodiments of this disclosure construct a shared memory pool based on the memory requirement range of each target processing module. The memory requirement range of any target processing module covers its various memory capacity requirements; for example, the minimum memory capacity requirement of the target processing module can be used as the lower limit of its memory requirement range, and the maximum memory capacity requirement of the target processing module can be used as the upper limit of its memory requirement range.

[0042] In one example, the total capacity of the shared memory pool can be determined based on the upper limit of the content demand of each target processing module during concurrent operation, ensuring that the memory capacity requirements of all target processing modules can be met during peak scenarios.

[0043] A shared memory pool can be divided into multiple storage units. In this embodiment of the disclosure, a storage unit can represent the smallest allocation granularity of the shared memory pool, and the storage capacity of each storage unit is the same.

[0044] In one example, the capacity of a single storage unit can be determined based on the minimum scheduling granularity and data bit width of each target processing module, ensuring that the actual memory requirements of any target processing module can be adapted to an integer number of storage units. This avoids fragmentation of the shared memory pool and increased addressing complexity, while also conforming to the hardware's cell array design rules.

[0045] In one possible implementation, the runtime scenario can be used to indicate application requirements and / or functional configurations of the display engine, such as image resolution, number of layers, data compression format, and processing module enable status. The target processing module is a processing module within the display engine whose memory requirements dynamically fluctuate and which can reuse resources. Processing modules with fixed underlying operation and that do not require dynamic adjustment are not considered target processing modules.

[0046] First, the enable signals of each processing module in the running scenario are read to filter out the processing modules that are in the enabled state. Then, the processing modules that are fixed in the underlying operation and the processing modules that do not need to be dynamically adjusted are removed. Finally, the target processing modules that participate in memory sharing are determined.

[0047] In one example, in a 4K multi-image-layer display scenario, the image layer direct memory access module, image scaling preprocessing module, and write-back module can be identified as the target processing modules. The cursor layer's direct memory access module has only one plane and a fixed input format, so its memory capacity requirement is constant. Therefore, it can be set to have a private memory space, without needing to be identified as a target processing module for memory sharing.

[0048] This embodiment of the disclosure, by accurately selecting target processing modules, can ensure that dynamic demand modules are included in the shared memory pool to save hardware resources, while also ensuring the operational stability of other modules and avoiding memory scheduling from affecting basic functions.

[0049] Figure 1 A flowchart illustrating a memory allocation method provided in an embodiment of this disclosure. (Refer to...) Figure 1 The method includes steps S11 and S12.

[0050] In step S11, the current actual memory requirements of the plurality of target processing modules are obtained.

[0051] In step S12, storage units are allocated to the multiple target processing modules based on their current actual memory requirements and the capacity of a single storage unit.

[0052] For each target processing module, the number of storage units allocated to the target processing module can be determined based on the current actual memory requirements of the target processing module and the capacity of a single storage unit, and a corresponding number of storage units can be allocated to the target processing module.

[0053] It should be understood that if a target processing module has a high current actual memory requirement, a larger number of storage units will be allocated to it; if a target processing module has a low current actual memory requirement, a smaller number of storage units will be allocated to it.

[0054] In one possible implementation, the current actual memory requirements of multiple target processing modules can be obtained at preset time intervals, and then storage units can be dynamically allocated to the multiple target processing modules periodically.

[0055] In one possible implementation, storage units can be reallocated to multiple target processing modules when the actual memory requirements of one or more target processing modules change.

[0056] According to the memory allocation method of this disclosure, the total capacity of the shared memory pool in the display engine and the capacity of a single storage unit in the shared memory pool are determined based on the memory requirement range of each target processing module in the display engine. The display engine can allocate storage units to these target processing modules based on their current actual memory requirements and the capacity of a single storage unit in the shared memory pool. On the one hand, multiple target processing modules sharing the shared memory pool can reduce hardware area; on the other hand, by determining the total capacity of the shared memory pool and the capacity of a single storage unit based on the memory requirement range of multiple target processing modules, a reasonable number of storage units can be dynamically allocated to each target processing module according to its actual memory requirements, thereby effectively reducing hardware area while meeting the usage requirements of each target processing module.

[0057] In some embodiments, for each target processing module, the memory requirement range of the target processing module is determined based on the type of the target processing module. The memory requirement range includes a first threshold and a second threshold. The first threshold is the minimum memory capacity required for the corresponding target processing module to run, and the second threshold is the maximum memory capacity required for the corresponding target processing module to run. The total capacity of the shared memory pool is determined based on the sum of the second thresholds of each target processing module. The capacity of the individual storage unit is determined based on the proportional relationship between the first thresholds of each target processing module.

[0058] The first threshold represents the lower limit of the memory requirement range needed for the operation of the corresponding target processing module, and the second threshold represents the upper limit of the memory requirement range needed for the operation of the corresponding target processing module. Different types of target processing modules may have different memory requirement ranges. In this embodiment, the memory requirement range can be determined based on the type of the target processing module.

[0059] In one example, the type of target processing module includes, but is not limited to, a direct memory access module for the image layer, an image scaling preprocessing module, a write-back module, and a post-direct memory access module. This disclosure does not limit the type of target processing module. The method for determining the memory requirement range based on the type of the target processing module will be described in detail later and will not be repeated here.

[0060] After determining the first and second thresholds for each target processing module, the second thresholds of each module can be summed to obtain the total capacity of the shared memory pool. This ensures that even when all target processing modules are simultaneously at peak load, the shared memory pool can still meet their needs, preventing memory shortages. In another example, the second thresholds of each module can be summed first, then multiplied by a coefficient less than 1 to obtain the total capacity of the shared memory pool. This further improves memory resource utilization and reduces hardware area.

[0061] After determining the first and second thresholds for each target module, the capacity of a single storage unit can be determined based on the proportional relationship between the first thresholds of each target processing module.

[0062] In one example, the minimum value among the first thresholds of each target processing module can be determined as the capacity of a single storage unit. This reduces memory allocation fragmentation and simplifies hardware addressing logic.

[0063] In another example, the greatest common divisor of the first thresholds of each target processing module can be used to determine the capacity of a single storage unit. This can effectively reduce storage space waste and improve storage resource utilization.

[0064] The method for determining the memory requirement range of the target processing module (including the first threshold and the second threshold) is explained below.

[0065] In some embodiments, when the target processing module is a direct memory access module for image layers, the memory requirement range of the target processing module is determined according to the compression format of the target processing module.

[0066] The compression format for direct memory access modules (DMIs) is divided into two types: tile rearrangement and linear layout. A DMI selects one of these two compression formats at startup.

[0067] In one possible implementation, when the compression format of the target processing module is tile-based rearrangement, the memory requirement range of the target processing module is determined based on the image cropping size, resolution, and unfinished transactions of the Advanced eXtensible Interface (AXI) protocol; when the compression format of the target processing module is linear layout, the memory requirement range of the target processing module is determined based on one or more of the image data format, burst length of the AXI protocol, unfinished transactions of the AXI protocol, and the size of data bytes transmitted in a single session.

[0068] Among them, tile-based rearrangement refers to the arrangement format in which a complete image is divided into several fixed-size tile units, and data is cached and transmitted block by block; linear layout refers to the conventional storage format in which image data is arranged continuously in rows and columns of pixels.

[0069] AXI protocol refers to the high-speed on-chip bus transmission protocol, which is used to realize data interaction between modules. An incomplete transaction in the AXI protocol refers to a data transmission request that has not been completed during the bus transmission process. The burst length in the AXI protocol refers to the number of data cycles (i.e., the number of data transmissions) transmitted continuously in a single bus transmission.

[0070] Image data format refers to the storage specifications corresponding to pixel bit depth and number of color channels; single transmission data byte size refers to the total amount of data transmitted in a single round of bus interaction.

[0071] For example, for a tile-based image layer DMA module, the image cropping tile size at 4K resolution is 64×64. Combined with the corresponding number of incomplete transactions, the lower and upper limits of the module's memory requirements can be determined. For a linearly laid-out image layer DMA module, using the RGB color format and setting the AXI burst length to 16, combined with the corresponding incomplete transactions and the size of bytes transferred per transaction, the corresponding memory requirement range for this module can be calculated.

[0072] In some embodiments, when the target processing module is an image scaling preprocessing module, the memory requirement range of the target processing module is determined based on the maximum resolution width and data format size supported by the display engine.

[0073] The image scaling preprocessing module refers to the image processing module that enlarges, reduces, and adapts the size of the input image; the maximum resolution width refers to the maximum number of pixels horizontally that the display engine can support; and the data format size refers to the number of bytes of storage corresponding to a single pixel. For example, the display engine supports 8K ultra-high-definition display with a maximum resolution width of 7680 pixels, coupled with a 32-bit color data format, and the cache memory range required for this scaling module is calculated accordingly.

[0074] In some embodiments, when the target processing module is a write-back module or a post-direct memory access module, the content requirement range of the target processing module is determined based on the capacity of the cache pixels, which determines the memory requirement range of the target processing module.

[0075] The write-back module is a functional module that caches the processed image data and sends it back to the memory; the post-direct memory access module is a direct memory access module that performs data transfer and storage after image processing. The write-back module and the post-direct memory access module will not start simultaneously, so they can share a storage space and are allocated the same storage units.

[0076] The cached pixel capacity refers to the maximum number of processed pixels that the module can temporarily store. For example, a write-back module can cache the pixels of one frame of image at a resolution of 1080P at a time. The corresponding pixel capacity is the basis for calculating the memory requirement of this module, thereby defining the corresponding memory requirement range.

[0077] As some implementation methods of the embodiments of this disclosure, memory requirement ranges are calculated for different types of target processing modules, so that the memory requirement ranges are more in line with the actual business logic and ensure the rationality of subsequent memory allocation.

[0078] The following describes the memory allocation process in actual operation.

[0079] In some embodiments, the allocation of storage units to the plurality of target processing modules in step S12 based on the current actual memory requirements of the plurality of target processing modules and the capacity of the single storage unit may include steps S121 and S122.

[0080] In step S121, the memory allocation priority of the multiple target processing modules is determined based on one or more of the timing dependency, real-time performance, and data flow order of the multiple target processing modules.

[0081] Multiple target processing modules may have temporal dependencies. For example, target processing module B can only begin execution after target processing module A has finished executing. In this case, there is a temporal dependency between target processing module A and target processing module B. A higher priority can be assigned to the dependent target processing module. That is, the priority of target processing module A is higher than the priority of target processing module B.

[0082] Multiple target processing modules may have different real-time requirements. For example, target processing module A requires fast response or cannot lag, so target processing module A has a higher priority. This ensures that core business logic is allocated memory first, providing the necessary conditions for its execution.

[0083] There may be data flow relationships between multiple target processing modules. For example, if the output data of target processing module A is used as the input data of target processing module B, then the priority of target processing module A should be higher than that of target processing module B.

[0084] In one example, the direct memory access module of the image layer has a higher priority than the image scaling preprocessing module, which ensures that image data is read and transmitted normally.

[0085] As some implementations of the embodiments of this disclosure, by setting the module memory allocation priority, the core business is guaranteed to obtain memory resources first, thereby ensuring the data processing timing and business smoothness of the display engine.

[0086] In step S122, storage units are allocated to each target processing module in descending order of priority. For any target processing module, the number of storage units to be allocated to the target processing module is determined based on the current actual memory requirements of the target processing module and the capacity of the single storage unit. The number of storage units is then allocated from the remaining storage units in the shared memory pool for the exclusive use of the target processing module.

[0087] First, for each target processing module, the number of storage units required is calculated based on its current actual memory requirements and the capacity of a single storage unit. In one example, the current actual memory requirement can be divided by the capacity of a single storage unit, and the result can be rounded up to obtain the number of storage units required for the target processing module. Then, the corresponding number of storage units are allocated to each target processing module according to priority. In one example, consecutive storage units can be allocated to the same target processing module.

[0088] In one example, multiple target processing modules include Module 1, Module 2, and Module 3, with priority from highest to lowest as follows: Module 1, Module 2, and Module 3. Module 1 corresponds to 3 storage units, Module 2 corresponds to 1 storage unit, and Module 3 corresponds to 2 storage units. The total number of storage units in the shared memory pool is 5. In this case, Module 1 can be allocated 3 consecutive storage units from the 8 storage units in the shared memory pool for its exclusive use. Then, Module 2 can be allocated 1 storage unit from the remaining 5 storage units for its exclusive use. Finally, Module 3 can be allocated 2 consecutive storage units from the remaining 4 storage units for its exclusive use.

[0089] As some implementations of the embodiments of this disclosure, storage units are allocated based on priority order to prioritize the memory needs of core services, improve the rationality of memory scheduling, and ensure that each processing module works in an orderly manner.

[0090] In some embodiments, the memory allocation method provided in this disclosure further includes S13.

[0091] In step S13, after allocating a corresponding number of storage units to each target processing module, the remaining storage units allocated in the shared memory pool are determined as shared memory resources for the multiple target processing modules to be shared by the multiple target processing modules.

[0092] Since the total capacity of the shared memory pool is determined based on the upper limit of the memory requirements of each target processing module, the actual memory capacity required by each target processing module during operation may be lower than its upper limit. Therefore, after allocating dedicated storage units for each target processing module (i.e., after completing step S12), some unallocated storage units may remain. These remaining free storage units can then be used as shared resources for all target processing modules to improve their efficiency, cope with unexpected situations, and further enhance memory resource utilization.

[0093] In one example, multiple target processing modules include Module 1, Module 2, and Module 3, in descending order of priority. Module 1 has 3 storage units, Module 2 has 1 storage unit, and Module 3 has 2 storage units. The shared memory pool contains a total of 5 storage units. After allocating 3 storage units to Module 1, 1 storage unit to Module 2, and 2 storage units to Module 3, 2 storage units remain in the shared memory pool. These 2 storage units can be shared by Module 1, Module 2, and Module 3. Specifically, the 3 storage units allocated to Module 1 are dedicated to Module 1, the 1 storage unit allocated to Module 2 is dedicated to Module 2, the 2 storage units allocated to Module 3 are dedicated to Module 3, and the remaining 2 storage units are shared by Module 1, Module 2, and Module 3.

[0094] As some implementations of the embodiments of this disclosure, the shared memory pool is maximized by sharing the remaining storage units, avoiding resource idleness and waste, and further reducing hardware memory overhead.

[0095] In some embodiments, when the operating scenario of the display engine changes, the total capacity of the shared memory pool and the capacity of individual storage units of the plurality of target processing modules are adjusted accordingly.

[0096] When the display engine's operating scenario changes, such as from the first scenario to the second, the enable status and memory requirements of the target processing modules included in the display engine may change. In this case, the total capacity of the shared memory pool and the capacity of the storage units within the shared memory pool can be redefined to adapt to the new operating scenario. The methods for determining the total capacity of the shared pool and the methods for determining individual storage units have been explained previously and will not be repeated here.

[0097] As some implementation methods of the embodiments of this disclosure, they are adapted to various operating scenarios, realize dynamic reconstruction of memory resources, maintain high memory utilization under different operating conditions, and effectively reduce hardware implementation overhead.

[0098] In some embodiments, the memory allocation method provided in this disclosure may further include steps S14 and S15.

[0099] In step S14, in response to the adjustment of one or more of the type, compression format and associated parameters of the target processing module, the actual memory requirements of the plurality of target processing modules are re-acquired.

[0100] In step S15, storage units are allocated to the plurality of target processing modules based on the actual memory requirements to be reacquired and the capacity of the single storage unit.

[0101] If one or more of the target processing module's type, compression format, and associated parameters are adjusted, the actual memory requirements of the target processing module may change, therefore it is necessary to obtain the actual memory requirements. These associated parameters include, but are not limited to, the image size after cropping and its resolution. One or more of the AXI protocol's incomplete transactions and image data formats are also considered; these will not be elaborated upon here. Step S15 can refer to step S12, and will not be repeated here.

[0102] In one example, a user can modify one or more of the target processing module's type, compression format, and associated parameters by sending configuration information.

[0103] As some implementation methods of the embodiments of this disclosure, dynamically obtaining the actual memory requirements of the target processing module can realize the dynamic allocation of storage units, which is more reasonable and efficient.

[0104] It should be understood that a display engine includes multiple processing modules, which can be divided into multiple groups, each group using a shared memory pool. Each shared memory pool is allocated and shared within a group. In this embodiment of the disclosure, by setting one or more shared memory pools in the display engine, hardware area is significantly saved.

[0105] The memory allocation method according to embodiments of this disclosure will now be described in detail.

[0106] Figure 2 This is an exemplary block diagram of a display engine provided in an embodiment of this disclosure. (Refer to...) Figure 2 The DisplayEngine comprises two parts: preprocessing (de_pre) and postprocessing (de_post). The preprocessing part includes multiple image layers and a cursor layer. Each image layer contains a Direct Memory Access (DMA) module, an image scaling preprocessing (pre_scaler) module, etc.; the cursor layer contains a DMA module, etc. The postprocessing part includes write-back or post-DMA modules, etc.

[0107] The direct memory access module may include one or more data planes. (See reference...) Figure 2The DMA module of the image layer includes three data planes, namely data plane 10, data plane 11 and data plane 12; the DMA module of the cursor layer includes one data plane, namely data plane 20.

[0108] Reference Figure 2 The display engine also includes a memory pool, which includes at least a first storage space for storing data related to the DMA module, a second storage space for storing data related to the pre_scaler module, and a third storage space for storing write-back data from the write-back / post_dma module.

[0109] Reference Figure 2 The display engine also includes a graphics overlay module, which overlays the processing results of multiple image layers and cursor layers in the preprocessing part and sends them to the write-back or post-direct memory access module.

[0110] It should be understood that the embodiments disclosed herein do not limit the number and type of processing modules (such as DMA modules, pre_scaler modules, etc.) included in the display engine, nor do they limit the internal structure of the processing modules (such as the number of data planes included in the DMA module).

[0111] The following is based on Figure 2 Taking the display engine shown as an example, the memory allocation method provided in this embodiment will be explained. For ease of understanding, the memory capacity requirements of each processing module in the display engine will be explained first.

[0112] For DMA modules, their memory capacity requirements can be determined based on one or more of the following: compression mode, image cropping size, and data format. DMA mode has two compression formats: twiddle and linear layout.

[0113] When the compression format is in twiddle mode, linear mode is off. At this time, based on the image's cropped size, resolution, and outstanding AXI protocol transactions, the DMA module may have three memory capacity requirements (also known as SRAM capacity): 256KB, 512KB, and 1024KB.

[0114] When the compression format is in linear mode, twiddle mode is disabled. At this point, the possible memory capacity requirements of the DMA module (32KB, 96KB, 128KB, 768KB, 1024KB) can be determined based on the data format, the burst length of the AXI protocol, the number of incomplete transactions in the AXI protocol, and the data size (data bytes).

[0115] Figure 3 This diagram illustrates the memory capacity requirements of a DMA module according to an embodiment of this disclosure. (Refer to...) Figure 3 The memory requirements of a DMA module vary depending on the data format. For example, a DMA module can use four data formats: one data plane with Alpha Red Green Blue (ARGB); two data planes with a 4:2:0 ratio of luminance to chromaticity (YUV420); three data planes with a 4:2:2 ratio of luminance to chromaticity (YUV422); and three data planes with a 4:4:4 ratio of luminance to chromaticity (YUV444). In the ARGB format with one data plane: one data plane is used, with data plane 10 (Plane0) used and data planes 11 (Plane1) and 12 (Plane2) not used. The minimum and maximum memory requirements for Plane0 are 32KB and 1024KB, respectively. In 2-plane format, YUV420: Two data planes are used, Plane0 and Plane1 are used, Plane2 is not used. The minimum and maximum memory requirements for Plane0 are 64KB and 512KB, respectively, and the minimum and maximum memory requirements for Plane1 are 32KB and 256KB, respectively. In 3-plane format, YUV422: Three data planes are used, i.e., Planes0 through Plane2 are all used. The minimum and maximum memory requirements for Plane0 are 64KB and 512KB, respectively, the minimum and maximum memory requirements for Plane1 are 32KB and 256KB, respectively, and the minimum and maximum memory requirements for Plane2 are 32KB and 256KB, respectively. In 3plane format, YUV444: three data planes are used, namely Plane0 to Plane2. The minimum and maximum memory requirements for Plane0 are 32KB and 256KB, respectively. The minimum and maximum memory requirements for Plane1 are 32KB and 256KB, respectively. The minimum and maximum memory requirements for Plane2 are 32KB and 256KB, respectively.

[0116] It should be noted that ARGB and YUV in the above text refer to pixel storage specifications. Y represents luminance, U represents the blue differential chromaticity component, and V represents the red differential chromaticity component. YUV444 and YUV420 represent sampling rules. YUV444 means that each Y is paired with one U and one Y, with no color compression and no image quality loss, but it uses a large amount of memory; YUV420 means that four Ys are paired with a U+V pair, with significant data compression and less memory usage; YUV422 means that two Ys are paired with a U+V pair, and its memory usage is between that of YUV444 and YUV420.

[0117] For a single image layer, based on the two modes of the DMA module, the maximum memory capacity requirement of the DMA module can be determined to be 1024KB.

[0118] For the pre_scaler module, the memory requirement varies depending on the maximum resolution width supported by the display engine and the data format size, with two possibilities: 128KB and 256KB. Therefore, the maximum memory requirement for the pre_scaler module is 1024KB.

[0119] In one example, the display engine supports a maximum resolution of 8K, or 7680×4320; the maximum bit width of the data format is 256 bits, and the depth is either 1024 or 2048 depending on the resolution. When the resolution width is less than 4096, the memory requirement is 256×1024 (i.e., 128KB); when the resolution width is greater than or equal to 4096, the memory requirement is 256×2048 (i.e., 256KB).

[0120] The `write_back / post_dma` module represents either the write-back module or the post-direct memory access (post_dma) module. Since these two modules are not enabled simultaneously, they can use the same memory space and can be considered as a single module. Depending on the size of the cached pixels, there are several memory capacity requirements: 32KB, 64KB, 96KB, and 128KB. A 32KB memory unit can cache 8K pixels. Therefore, the maximum memory capacity requirement for the `write_back / post_dma` module is 128KB.

[0121] In related technologies, a private memory space is allocated for each processing module. To meet the needs of each processing module, the design is based on the maximum memory capacity requirement of each module.

[0122] Figure 4This is a schematic diagram illustrating the maximum memory capacity of the memory pool provided in an embodiment of this disclosure. (Refer to...) Figure 4 As mentioned earlier, the maximum static random access memory (SRAM) capacity of the direct memory access module (i.e., the maximum memory capacity requirement) is 1024KB, the maximum SRAM capacity of the image scaling preprocessing module is 256KB, and the maximum SRAM capacity of the write-back or post-DMA module is 128KB. The SRAM dimensions (width × height) are 256 × 1024, and the SRAM size (i.e., the capacity of a single memory cell) is 32KB. Therefore, the maximum number of SRAM units required by the DMA module is 32, the maximum number of SRAM units required by the pre_scaler module is 8, and the maximum number of SRAM units required by the write_back / post_DMA module is 4. For a single-layer image display engine (i.e., containing one DMA module, one pre_scaler module, and one write_back / post_DMA module), the total maximum SRAM capacity is 1.408MB.

[0123] In this embodiment of the disclosure, a shared memory pool is designed for the target processing module, which can improve memory resource utilization and thus reduce hardware area.

[0124] For the DMA module, in Linear compression mode, the supported number of memory units (mem_num) for plane0 are 1, 2, 4, 8, 12, 16, 20, 28, and 32; for plane1 and plane2, the supported mem_num values ​​are 1, 2, 4, and 8. For the YUV444 3-plane format, the minimum possible numbers for plane0, plane1, and plane2 are 1, 1, and 1, respectively, and the maximum possible numbers are 8, 8, and 8, respectively. In Twiddle compression mode, the supported mem_num values ​​are 8, 16, or 32.

[0125] For the pre_scaler module, depending on the maximum resolution width and data format size, the supported mem_num configuration options are 0, 4, and 8.

[0126] Based on actual usage, a display engine with three image layers is designed, comprising three DMA modules and two pre-scaler modules. The three DMA modules include one 8K twiddle format (512KB) DMA module and two 8K linear YUV444 3plane format (128KB×2) DMA modules; and two 8K format pre-scaler modules (256KB×2). Therefore, this embodiment designs a 1.28MB (512KB + 128KB×2 + 256KB×2) shared memory pool, which can be divided into 40 (16 + 8 + 16) 32KB storage units for the above modules to share. When the maximum memory requirement is met, the number of storage units corresponding to the 8K twiddle format DMA modules is set to 16, the number of storage units corresponding to the 8K YUV444 3plane format DMA modules is set to 8, and the number of storage units corresponding to the 8K format pre-scaler modules is set to 16. This makes full use of the entire shared memory pool.

[0127] It should be noted that 8K refers to a resolution of 7680×4320. In the example above, three DMA modules are enabled, two pre_scaler modules are enabled, and the write_back / post_dma modules are disabled. This setting is based on the maximum resolution and actual usage. Furthermore, because the DMA module in the cursor layer has only one data plane, a fixed input format, and internally uses a private SRAM that is mandatory and has a size of 32KB, the DMA module in the cursor layer does not need to use memory resources from the shared memory pool.

[0128] If the maximum SRAM capacity of each processing module is superimposed, the memory capacity required for a single display layer is 1.408M. However, in this embodiment, the total capacity of the shared memory pool designed under multiple (specifically 3) image layers is 1.28MB, which reduces the capacity requirement and thus effectively saves hardware area.

[0129] In this embodiment, the memory requirements of each target processing module are first determined, and then a shared memory pool is designed based on the memory requirements of each target module. The smallest SRAM usage unit (i.e., storage unit) within the shared memory pool is then defined. Compared to a private SRAM mode, this embodiment designs one or more shared memory pools within the display engine and dynamically adjusts the usage of specific SRAM (i.e., storage units) through software-based configuration. This saves hardware area for a single display engine, and is even more significant in chips with multiple display engines.

[0130] Furthermore, SRAM usage can be dynamically adjusted through software configuration, offering greater flexibility. When users modify parameters such as compression mode or resolution, a new configuration (i.e., the number of reassigned storage units) can be issued via software, and storage units will then be reallocated to each target processing module. During allocation, units are allocated sequentially in descending order of priority.

[0131] Figure 5 This is a schematic diagram illustrating the allocation of storage units according to an embodiment of this disclosure. For example... Figure 5 As shown, the target processing modules, from highest to lowest priority, are the direct memory access module, the image scaling preprocessing module, and the write-back or post-direct memory access module, with allocated storage units of N1, N2, and N3 respectively. (Refer to...) Figure 5 The shared memory pool contains 40 storage units. First, storage units 0 to N1-1 are allocated to the direct memory access module. Then, storage units N1 to N1+N2-1 are allocated to the image scaling preprocessing module, and so on. It should be understood that if N1+N2+N3=40, there are no remaining storage units; if N1+N2+N3<40, there are remaining storage units.

[0132] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0133] In addition, this disclosure also provides memory allocation apparatus, electronic devices, chips, circuits, and computer-readable storage media, all of which can be used to implement any of the memory allocation methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding descriptions in the method section and will not be repeated here.

[0134] Figure 6 This is a block diagram of a memory allocation device provided in an embodiment of the present disclosure.

[0135] Reference Figure 6 This disclosure provides a memory allocation device applied to a device including a display engine. The display engine includes multiple target processing modules and a shared memory pool for use by the multiple target processing modules. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules. The memory allocation device 60 includes a first acquisition module 61 and a first allocation module 62.

[0136] The first acquisition module 61 is used to acquire the current actual memory requirements of the plurality of target processing modules.

[0137] The first allocation module 62 is used to allocate storage units to the multiple target processing modules according to the current actual memory requirements of the multiple target processing modules and the capacity of the single storage unit.

[0138] In some possible implementations, for each target processing module, the memory requirement range of the target processing module is determined based on the type of the target processing module. The memory requirement range includes a first threshold and a second threshold. The first threshold is the minimum memory capacity required for the corresponding target processing module to run, and the second threshold is the maximum memory capacity required for the corresponding target processing module to run. The total capacity of the shared memory pool is determined based on the sum of the second thresholds of each target processing module. The capacity of a single storage unit is determined based on the proportional relationship between the first thresholds of each target processing module.

[0139] In some possible implementations, when the target processing module is a direct memory access module for the image layer, the memory requirement range of the target processing module is determined according to the compression format of the target processing module.

[0140] In some possible implementations, when the compression format of the target processing module is tile-based rearrangement, the memory requirement range of the target processing module is determined based on the image cropping size, resolution, and incomplete transactions of the AXI protocol; when the compression format of the target processing module is linear layout, the memory requirement range of the target processing module is determined based on one or more of the image data format, burst length of the AXI protocol, incomplete transactions of the AXI protocol, and the size of data bytes transmitted in a single session.

[0141] In some possible implementations, where the target processing module is an image scaling preprocessing module, the memory requirements of the target processing module are determined based on the maximum resolution width and data format size supported by the display engine.

[0142] In some possible implementations, when the target processing module is a write-back module or a post-direct memory access module, the memory requirement range of the target processing module is determined based on the capacity of the cached pixels.

[0143] In some possible implementations, the allocation module is further configured to determine the memory allocation priority of the plurality of target processing modules based on one or more of the timing dependency, real-time performance, and data flow order of the plurality of target processing modules; and to allocate storage units to each target processing module in descending order of priority. Specifically, for any target processing module, the number of storage units allocated to the target processing module is determined based on the current actual memory requirements of the target processing module and the capacity of the single storage unit, and the number of storage units is allocated from the remaining storage units in the shared memory pool for the exclusive use of the target processing module.

[0144] In some possible implementations, the apparatus further includes a determining module.

[0145] The determination module is used to determine the remaining storage units allocated in the shared memory pool as shared memory resources for the multiple target processing modules, provided that a corresponding number of storage units have been allocated to each target processing module.

[0146] In some possible implementations, the device further includes: a second acquisition module and a second allocation module.

[0147] The second acquisition module is used to reacquire the actual memory requirements of the plurality of target processing modules in response to an adjustment of one or more of the type, compression format and associated parameters of the target processing module.

[0148] The second allocation module is used to allocate storage units to the multiple target processing modules based on the actual memory requirements after reacquisition and the capacity of the single storage unit.

[0149] Figure 7 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0150] Reference Figure 7 This disclosure provides an electronic device, which includes: at least one processor 701; at least one memory 702; and one or more I / O interfaces 703 connected between the processor 701 and the memory 702; wherein the memory 702 stores one or more computer programs that can be executed by at least one processor 701, and the one or more computer programs are executed by at least one processor 701 to enable at least one processor 701 to perform the memory allocation method described above.

[0151] This disclosure also provides a chip including at least one display engine, each display engine including multiple target processing modules and a shared memory pool for use by the multiple target processing modules, wherein the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules, and the chip is used to implement the above-described memory allocation method.

[0152] This disclosure also provides a circuit including multiple target processing modules and a shared memory pool for use by the multiple target processing modules. The multiple target processing modules are connected to the shared memory pool. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules. The circuit is used to implement the memory allocation method described above.

[0153] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the memory allocation method described above. The computer-readable storage medium may be volatile or non-volatile.

[0154] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes the memory allocation method described above.

[0155] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0156] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0157] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0158] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0159] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0160] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0161] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0162] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0163] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0164] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A memory allocation method, characterized in that, Applied to a device including a display engine, the display engine comprising multiple target processing modules and a shared memory pool for use by the multiple target processing modules, the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool being determined based on the memory requirements of the multiple target processing modules, the method comprising: Obtain the current actual memory requirements of the multiple target processing modules; Storage units are allocated to the multiple target processing modules based on their current actual memory requirements and the capacity of each individual storage unit.

2. The method according to claim 1, characterized in that, For each target processing module, the memory requirement range of the target processing module is determined based on the type of the target processing module. The memory requirement range includes a first threshold and a second threshold. The first threshold is the minimum memory capacity required for the target processing module to run, and the second threshold is the maximum memory capacity required for the target processing module to run. The total capacity of the shared memory pool is determined based on the sum of the second thresholds of each target processing module; The capacity of a single storage unit is determined based on the proportional relationship between the first thresholds of each target processing module.

3. The method according to claim 2, characterized in that, When the target processing module is a direct memory access module for the image layer, the memory requirement range of the target processing module is determined according to the compression format of the target processing module.

4. The method according to claim 3, characterized in that, When the compression format of the target processing module is tile-based rearrangement, the memory requirement range of the target processing module is determined based on the image cropping size, resolution, and unfinished transactions of the Advanced Extensible Interface (AXI) protocol. When the compression format of the target processing module is linear layout, the memory requirement range of the target processing module is determined based on one or more of the following: image data format, burst length of the AXI protocol, incomplete transactions of the AXI protocol, and the size of data bytes transmitted in a single transaction.

5. The method according to claim 2, characterized in that, When the target processing module is an image scaling preprocessing module, the memory requirement range of the target processing module is determined based on the maximum resolution width and data format size supported by the display engine.

6. The method according to claim 2, characterized in that, When the target processing module is a write-back module or a post-direct memory access module, the memory requirement range of the target processing module is determined based on the capacity of the cache pixels.

7. The method according to claim 1, characterized in that, The step of allocating storage units to the multiple target processing modules based on their current actual memory requirements and the capacity of a single storage unit includes: The memory allocation priority of the multiple target processing modules is determined based on one or more of the time-series dependency, real-time performance, and data flow order of the multiple target processing modules. Storage units are allocated to each target processing module in descending order of priority. For any target processing module, the number of storage units to be allocated to the target processing module is determined based on the current actual memory requirements of the target processing module and the capacity of the single storage unit. The remaining storage units in the shared memory pool are then allocated to the target processing module for exclusive use.

8. The method according to claim 7, characterized in that, The method further includes: With a corresponding number of storage units already allocated to each target processing module, the remaining storage units allocated in the shared memory pool are determined as shared memory resources for the multiple target processing modules to be shared by the multiple target processing modules.

9. The method according to claim 2, characterized in that, The method further includes: In response to an adjustment of one or more of the type, compression format, and associated parameters of the target processing module, the actual memory requirements of the plurality of target processing modules are re-acquired. Storage units are allocated to the multiple target processing modules based on the actual memory requirements to be reacquired and the capacity of the individual storage units.

10. A memory allocation device, characterized in that, An apparatus applicable to a device including a display engine, the display engine comprising multiple target processing modules and a shared memory pool for use by the multiple target processing modules, the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool being determined based on the memory requirements of the multiple target processing modules, the apparatus comprising: The first acquisition module is used to acquire the current actual memory requirements of the plurality of target processing modules; The first allocation module is used to allocate a corresponding number of storage units to the multiple target processing modules based on their current actual memory requirements and the capacity of the individual storage units.

11. An electronic device, characterized in that, include: At least one display engine, each of the display engines including a plurality of target processing modules and a shared memory pool for use by the plurality of target processing modules, wherein the total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the plurality of target processing modules; A memory communicatively connected to the at least one display engine; wherein, The memory stores one or more computer programs that can be executed by the at least one display engine, and the one or more computer programs are executed by the at least one display engine to enable the at least one display engine to perform the memory allocation method as described in any one of claims 1-9.

12. A chip, characterized in that, The chip includes at least one display engine, each of which includes multiple target processing modules and a shared memory pool for use by the multiple target processing modules. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules. The chip is used to implement the memory allocation method of any one of claims 1-9.

13. A circuit, characterized in that, The circuit includes multiple target processing modules and a shared memory pool for use by the multiple target processing modules. The multiple target processing modules are connected to the shared memory pool. The total capacity of the shared memory pool and the capacity of a single storage unit in the shared memory pool are determined according to the memory requirements of the multiple target processing modules. The circuit is used to implement the memory allocation method according to any one of claims 1-9.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory allocation method as described in any one of claims 1-9.

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