Calibration circuit and method for capacitance offset in SAR ADC circuits

Abstract

The application discloses a calibration circuit for capacitance unbalance of a SAR ADC circuit, which comprises a capacitance array and a resistance array. N‑1 The capacitance array is composed of N calibration capacitances, a supplementary capacitance and a connecting capacitance connected in parallel, the capacitance value of the first calibration capacitance is a reference capacitance value, the capacitance value of the Nth calibration capacitance is 2 N‑1 times the reference capacitance value, the upper plate of each capacitance is connected with an input end of an external comparator, the lower plate of the supplementary capacitance and each calibration capacitance is grounded or connected with a power supply; the resistance array is composed of two or two N‑2 identical resistances connected in series, one end of the resistance array is connected with the power supply, and the other end is grounded; a first group of switches is arranged at the end of each resistance close to the power supply, and the other end of each first group of switches is selectively connected with the lower plate of the connecting capacitance; N is a natural number greater than 1. Meanwhile, the application also discloses a calibration method for capacitance unbalance of a SAR ADC circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a calibration circuit and method for capacitance offset in SAR ADC circuits. Background Technology

[0002] The core of a SAR ADC circuit relies on charge redistribution capacitors to achieve analog-to-digital conversion. However, due to limitations in semiconductor manufacturing processes, on-chip binary weighted capacitor arrays cannot achieve ideal matching. Capacitor mismatch directly causes weight deviation in the ADC circuit, deteriorating its integral and differential linearity, and significantly limiting its resolution and linearity. While increasing the capacitor area can improve matching, this leads to increased chip area, higher power consumption, and reduced conversion rate, making it difficult to meet the design requirements of medium-to-high speed, low power consumption, and high precision ADCs. Therefore, calibration techniques for capacitor mismatch have become crucial for optimizing SAR ADC performance. Currently, commonly used calibration methods include digital calibration and analog calibration.

[0003] The core advantage of analog calibration lies in its high compatibility with the native operating mechanism of SAR ADCs. It directly handles capacitance mismatch errors within the analog charge and voltage domains, eliminating the need to convert errors into digital signals for computation and compensation. This avoids the additional quantization noise introduced by digital quantization and the nonlinear interference introduced by digital algorithms, perfectly matching the core operating logic of SAR ADC charge redistribution. The linearity and accuracy of the compensation process are superior. Furthermore, analog calibration relies heavily on basic analog components such as capacitors and resistors, resulting in extremely low static power consumption. Pure capacitor-based analog calibration, for example, consumes almost no static power, aligning with the low-power design requirements of SAR ADCs. At the timing level, analog calibration can seamlessly integrate with the ADC sampling and conversion cycles without interrupting signal acquisition or adding additional digital logic overhead. It has virtually no negative impact on the sampling rate of high-speed SARs (5-20 MSPS), and its analog domain response is more immediate, eliminating the need to wait for digital algorithm convergence. It can quickly adapt to mismatch correction requirements under variations in process technology, voltage, and temperature (PVT). Therefore, analog calibration is more widely used.

[0004] In analog calibration methods, the core advantages of secondary resistor array calibration circuits compared to secondary capacitor array calibration circuits lie in their compensation range, area, and adjustment flexibility. Secondary resistor arrays can achieve wide-range voltage threshold fine-tuning through voltage divider logic, covering a larger capacitor mismatch error range. Coarse and fine adjustments are more convenient, unaffected by the superposition of secondary capacitor charges, resulting in stronger compensation elasticity. In terms of area, the resistance per unit area of ​​high-resistivity polysilicon resistors is much higher than that of capacitors. Under the same accuracy requirements, the chip area occupied by resistor strings is smaller. Even with interdigitated and common-centroid layouts to ensure resistor matching, the overall area is still more advantageous. The circuit structure is also simpler, requiring only a voltage divider network and isolation buffers to complete the core functions, eliminating the need for complex capacitor charge balance control and high-precision layout design, reducing the implementation difficulty and debugging cost of analog circuits. Furthermore, the adjustment logic of secondary resistor arrays is more flexible, allowing direct digital control to change the voltage division ratio without the parasitic capacitance interference from additional analog switch arrays. In low-speed, power-insensitive high-precision SAR ADC circuits, mismatch compensation can be achieved with a lighter circuit, adapting to the design requirements of specific scenarios.

[0005] Therefore, it is necessary to provide a calibration circuit and method for capacitance offset in SAR ADC circuits that utilizes a resistor array to calibrate capacitance offset, thereby overcoming the aforementioned deficiencies. Summary of the Invention

[0006] The purpose of this invention is to provide a calibration circuit and method for capacitance mismatch in SAR ADC circuits. The calibration circuit and method for capacitance mismatch in SAR ADC circuits of this invention can cover a larger capacitance mismatch error range, and the implementation of coarse and fine adjustment is more convenient. It occupies less chip area and improves the chip integration.

[0007] To achieve the above objectives, the present invention provides a calibration circuit for capacitance offset in a SAR ADC circuit, comprising a capacitor array and a resistor array. The capacitor array consists of N calibration capacitors, supplementary capacitors, and connecting capacitors connected in parallel. The capacitance values ​​of the supplementary capacitors and connecting capacitors are both reference capacitance values. The capacitance value of the first calibration capacitor is the reference capacitance value, and the capacitance value of the Nth calibration capacitor is 2. N-1 The reference capacitance value is doubled, and the upper plate of each capacitor is connected to an input terminal of an external comparator. The lower plates of the supplementary capacitor and each calibration capacitor can be selectively grounded or connected to the power supply voltage; the resistor array consists of 2... N-1 or 2 N-2The resistor array is composed of identical resistor groups connected in series. One end of the resistor array is connected to the power supply voltage, and the other end is grounded. A first set of switches is provided at the end of each resistor near the power supply voltage. The other end of each first set of switches can be selectively connected to the lower plate of the capacitor. A second set of switches is provided at the end of each resistor group near the power supply voltage. The other end of the second set of switches can be selectively connected to the lower plate of the supplementary capacitor. N is a natural number greater than 1.

[0008] Preferably, each resistor group is formed by connecting at least two identical resistors in series. Preferably, each resistor group is formed by connecting two identical resistors in series; when N is odd, the number of resistors in the resistor array is 2N, the number of switches in the first group is 2N, and the number of resistor groups is 2N-1; when N is even, the number of resistors in the resistor array is 2. N-1 The first group of switches has 2. N-1 The number of resistor groups is 2 N-2 .

[0009] Preferably, the calibration circuit for capacitor offset in the SAR ADC circuit further includes a third set of switches, wherein the lower plates of the supplementary capacitor and each calibration capacitor can be selectively grounded or connected to the power supply voltage via each of the third set of switches.

[0010] Preferably, the calibration circuit for capacitor offset in the SAR ADC circuit further includes a fourth switch and a fifth switch, wherein the connecting capacitor is selectively connected to the other end of each of the first group of switches via the fourth switch; one end of the fifth switch is connected to an input terminal of an external comparator, and the other end is connected to the lower plate of the connecting capacitor.

[0011] Preferably, when calibrating the calibration capacitors, the calibration should start with the calibration capacitor with the largest capacitance value and proceed sequentially, with the calibration capacitor having the reference capacitance value being the last to be calibrated.

[0012] Meanwhile, the present invention also provides a calibration method for capacitance offset in SAR ADC circuits, which includes the following steps: a. The lower plate of the highest-position calibration capacitor is connected to the power supply voltage, and the lower plates of the other calibration capacitors are grounded. A first group switch is closed, and the voltage of the lower plate of the connected capacitor is half of the power supply voltage. b. The lower plate of the highest-order calibration capacitor is grounded, and the lower plates of the other calibration capacitors are connected to the power supply voltage. The offset value of the current highest-order calibration capacitor is confirmed by an external comparator. c. Based on the offset value of the current highest-order calibration capacitor, through 2 N or 2 N-1 The bit code turns each of the first group switches on / off to calibrate the offset of the current highest bit calibration capacitor; d. Keep the lower plate of the highest-order calibration capacitor grounded, and repeat step ac to calibrate the misalignment of the other calibration capacitors from high to low until all calibration capacitors are calibrated.

[0013] Better location, 2 N-1 or 2 N-2 The bit code controls the opening / closing of each of the first group of switches. Specifically, a bit code of 1 indicates that the switch is closed, and a bit code of 0 indicates that the switch is open.

[0014] Preferably, when one of the first group switches is closed so that the voltage of the lower plate of the connected capacitor is half of the power supply voltage, the closure of the first group switch is defined as a half-amplitude switch; when the offset value of the current highest bit calibration capacitor is greater than 0, while keeping the half-amplitude switch closed, and with the half-amplitude switch as the center, each of the other first group switches near the ground direction is closed in sequence, and each of the other first group switches near the power supply voltage direction remains open.

[0015] Preferably, when the offset value of the current calibration capacitor is less than 0, while keeping the half-amplitude switch closed, and with the half-amplitude switch as the center, the other first group switches closer to the power supply voltage direction are closed in sequence, while the other first group switches closer to the ground direction remain open.

[0016] Compared with the prior art, the calibration circuit and method for capacitance mismatch in SAR ADC circuits of the present invention can cover a larger range of capacitance mismatch errors. By calibrating from high to low capacitance values ​​of the calibration capacitors, coarse and fine adjustments are made more convenient. Coarse or fine adjustments can be flexibly selected according to specific circumstances, which speeds up the calibration process and improves efficiency. Moreover, since no capacitors are used in the calibration structure (excluding the calibration capacitors themselves), the chip area occupied by the entire circuit is greatly reduced, improving the chip integration.

[0017] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the calibration circuit for capacitor offset in a SAR ADC circuit according to the present invention.

[0019] Figure 2 This is a schematic diagram of one embodiment of the calibration circuit for capacitor offset in a SAR ADC circuit according to the present invention.

[0020] Figure 3 for Figure 2 The diagram shows a dynamic calibration structure of the calibration circuit.

[0021] Figure 4 This is a flowchart of the calibration method for capacitance offset in a SAR ADC circuit according to the present invention. Detailed Implementation

[0022] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides a calibration circuit and method for capacitance misalignment in SAR ADC circuits. The calibration circuit and method for capacitance misalignment in SAR ADC circuits of the present invention can cover a larger capacitance misalignment error range, and the implementation of coarse and fine adjustments is more convenient, occupying less chip area and improving chip integration.

[0023] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the calibration circuit for capacitance offset in a SAR ADC circuit according to the present invention. As shown in the figure, the calibration circuit for capacitance offset in a SAR ADC circuit includes a capacitor array and a resistor array. The capacitor array consists of N calibration capacitors (C11, C12...C1N) connected in parallel, a supplementary capacitor C2, and a connecting capacitor C3. The capacitance values ​​of the supplementary capacitor C2 and the connecting capacitor C3 are both reference capacitance values ​​C0, and the specific reference capacitance value can be set according to the actual situation. The capacitance value of the first calibration capacitor C11 is the reference capacitance value C0, and the capacitance value of the Nth calibration capacitor C1N is 2... N-1 Double the reference capacitance value, which is 2 N-1 C0. The upper plate of each capacitor is connected to an input terminal (POS terminal) of an external comparator (not shown), meaning the voltage of each capacitor's upper plate is input to one input terminal of the comparator for comparison. The lower plates of the supplementary capacitor C2 and each calibration capacitor C11, C12...C1N can be selectively grounded or connected to the power supply voltage AVD to adjust the voltage of each capacitor's lower plate. The resistor array consists of 2... N -1 or 2 N-2 The resistor array is constructed by connecting identical resistor groups in series; one end of the resistor array is connected to the power supply voltage AVD, and the other end is grounded. In this invention, each resistor group is formed by connecting at least two identical resistors in series. Obviously, the more resistors in each resistor group, the higher the calibration accuracy; however, the corresponding cost and layout area also increase significantly. In practical applications, the number of resistors in each resistor group can be flexibly selected according to specific circumstances. Specifically, for example... Figure 1 As shown, in this invention, each resistor group is formed by connecting two identical resistors in series as an example, that is, the resistor array has a total of 2 N or 2 N-1 Several resistors are connected in series, and the resistors R1, R2...R(2 N) or R (2 N-1 All are exactly the same in each resistor R1, R2...R(2 N (or R (2) N-1 A first set of switches S11, S12...S1 (2) is set at the end near the power supply voltage AVD. N (or S1 (2) N-1 Each of the first group of switches S11, S12...S1 (2 N (or S1 (2) N-1 The other end of either of the two terminals can be selectively connected to the lower plate of capacitor C3, for a total of 2 terminals. N or 2 N-1 Each of the first group of switches is connected to a resistor at the end closest to the power supply voltage; thus, by opening / closing each of the first group of switches S11, S12...S1(2 N (or S1 (2) N-1 This allows different numbers of resistors to be connected to the lower plate of the connecting capacitor C3, thereby changing the voltage value of the lower plate of the connecting capacitor C3, and thus changing the voltage difference between the upper and lower plates of the connecting capacitor C3, ultimately changing the voltage value input to the comparator. A second set of switches S21, S22...S2(2) is provided at the end of each resistor group closest to the power supply voltage AVD. N-1 (or S1 (2) N-2 The second set of switches S21, S22...S2(2) N-1 (or S1 (2) N-2 The other end of the resistor array can be selectively connected to the lower plate of the supplementary capacitor C2 to provide a corresponding voltage value to the lower plate of the supplementary capacitor C2; N is a natural number greater than 1. In this invention, when N is an odd number, the number of resistors in the resistor array is 2. N The number of switches in the first group is 2. N The number of resistor groups is 2 N-1 When N is an even number, the number of resistors in the resistor array is 2. N-1 The number of switches in the first group is 2. N-1 The number of resistor groups is 2 N-2 The specific value of N is determined by the number of bits in the SAR ADC circuit. For example, when the number of bits in the SAR ADC circuit is 5, then N is 3, which means 3 capacitors plus 2 resistors, and the number of resistor groups is 2. 3-1 That is, there are 4 groups, and the number of resistors is 2. 3 That is, there are 8; the number of switches in the other groups can also be obtained accordingly, which will not be elaborated here.

[0024] The calibration circuit for capacitor offset in the SAR ADC circuit of the present invention further includes a third set of switches S31a, S31b, S32a, S32b...S3 (2N a, S3 (2) N )b (or S3 (2) N-1 a, S3 (2) N-1 (b) The lower plates of the supplementary capacitor C2 and each calibration capacitor C11, C12...C1N can be selectively grounded or connected to the power supply voltage AVD by switching the third set of switches on / off; thereby changing the voltage value of the lower plates of the charging capacitor C2 and each calibration capacitor C11, C12...C1N, and thus changing the voltage difference between the upper and lower plates of the charging capacitor C2 and each calibration capacitor C11, C12...C1N, thereby changing the final voltage value input to the comparator.

[0025] The calibration circuit for capacitor offset in a SAR ADC circuit of the present invention further includes a fourth switch S4 and a fifth switch S5. The connecting capacitor C3 can be selectively connected to the first group of switches S11, S12...S1 (2) via the fourth switch S4. N (or S1 (2) N-1 The other end (node ​​U1) of the fifth switch S5 is connected; one end of the fifth switch S5 is connected to one input terminal of the external comparator, and the other end is connected to the lower plate of the connecting capacitor C3. During the formal conversion of the SAR ADC circuit, during the sampling period, the fifth switch S5 is closed and the fourth switch S4 is open, so that all resistors are not connected to the circuit, that is, all circuit structures for calibrating the calibration capacitor do not affect the normal sampling process.

[0026] Please refer to the references. Figure 2 , Figure 2 This is a schematic diagram of one embodiment of the capacitor offset calibration circuit for a SAR ADC circuit according to the present invention. Figure 2 As shown, this SAR ADC circuit is a 5-bit SAR ADC. In this calibration circuit, the capacitor array is 3 bits (C11, C12, C13), and the resistor array is 2 bits. Theoretically, the 2-bit resistor string should have 4 resistors (4 resistor groups, 2...). 2 =4), such as Figure 2 As shown, eight resistors R1, R2, R3, R4, R5, R6, R7, and R8 are set. These eight resistors form a resistor group of two, that is, four resistor groups. In this invention, the four resistors (groups) are specifically implemented using eight resistors, thereby enabling calibration to a value of 0.5 LSB during capacitor calibration, significantly improving calibration accuracy.

[0027] Please refer to the references. Figure 3 ,describe Figure 2 The calibration process of the calibration circuit shown is described. Figure 3To clearly and concisely illustrate the calibration process of the calibration circuit, unnecessary switches have been simplified and directly connected as wires, and the calibration of one calibration capacitor is performed in three stages; specifically: In the first stage, the lower plate of the largest calibration capacitor C13 (the highest-order capacitor) is connected to the power supply voltage AVD, and the lower plates of the other calibration capacitors C11 and C12 are grounded. The switch S15 of the first set of switches is closed. At this time, the lower plate of the capacitor C3 is connected to the common-mode voltage VCM (1 / 2AVD), while the other input of the comparator is always connected to the common-mode voltage VCM.

[0028] In the second stage, the lower plate of calibration capacitor C13 is switched to ground, and the lower plates of the remaining calibration capacitors C11 and C12 are all switched to be connected to the power supply voltage AVD. At this time, switch S15 of the first group of switches connected to the lower plate of capacitor C3 remains closed. If calibration capacitor C13 is misaligned, such as the actual capacitance value of calibration capacitor C13 being 4C0 + Cd1 (Cd1 being the misalignment capacitance value), and the sum of the capacitance values ​​of the remaining calibration capacitors (including the capacitance value of supplementary capacitor C2) being 4C0 + Cd2 (Cd2 being the misalignment capacitance value), then when the second stage is switched, the voltage at the POS terminal (connected to the upper plate of capacitor C3) will deviate from the voltage of the first stage, at which point the subsequent comparator starts to work.

[0029] In the third stage, the voltage of the lower plate of the capacitor C3 is adjusted by controlling the switches of the first group of switches S11-S18 through an 8-bit digital code. After the comparison is completed, the 8-bit digital code is recorded. This digital code contains the offset capacitance values ​​Cd1 and Cd2.

[0030] Repeat stages one through three, calibrating capacitors C12 and C11 sequentially, with the difference that the lower plate of each calibrated capacitor remains grounded throughout. Finally, store the offset value of each calibration capacitor using an 8-bit digital code, which is then eliminated during the actual comparison to complete the calibration of each capacitor.

[0031] In the calibration process of calibration capacitors C11, C12, and C13 described above, calibration is performed sequentially starting with the calibration capacitor with the largest capacitance value, and ending with the calibration capacitor whose capacitance value is the reference value. For example, calibration starts with calibration capacitor C13 with a capacitance value of 4C0, and ends with calibration capacitor C11 with a capacitance value of C0. Because the capacitance values ​​of the higher-order calibration capacitors are much larger than those of the other calibration capacitors, the misalignment of the higher-order calibration capacitors has a much greater impact on the entire circuit. Therefore, in this invention, calibration is performed in descending order of capacitance, achieving coarse-to-fine calibration. By performing calibration on each of the calibration capacitors C11, C12, and C13 sequentially, the entire capacitor array can be calibrated with high precision, avoiding repeated calibration and improving calibration efficiency. Moreover, in some applications where high precision is not required, it may only be necessary to calibrate the misalignment of a few higher-order calibration capacitors, thereby speeding up the calibration process and improving efficiency.

[0032] Please refer to the references. Figure 4 This invention describes a calibration method for capacitor offset in SAR ADC circuits, wherein the calibration method utilizes... Figures 1-3 The calibration circuit shown is used for this purpose. Specifically, the calibration method includes the following steps: Step S001. The lower plate of the highest-order calibration capacitor is connected to the power supply voltage, while the lower plates of the other calibration capacitors are grounded. One of the first group switches is closed, and the voltage across the lower plate of the connected capacitor is half of the power supply voltage. In this step, except for the lower plate of the highest-order calibration capacitor which is connected to the power supply voltage, the lower plates of the other calibration capacitors are grounded, ensuring that only the highest-order calibration capacitor is connected to the circuit. This facilitates calibration of the highest-order calibration capacitor and ensures that the calibration process is not affected by the other calibration capacitors. The closing of one of the first group switches... Figure 3 When switch S15 is closed, one of the middle resistors in the entire resistor array is connected to the circuit and to the lower plate of the connecting capacitor. Since the entire resistor array is connected in series, with one end connected to the power supply voltage and the other end grounded, the voltage value of the middle resistor is half of the power supply voltage (common-mode voltage). The voltage of the middle resistor is input to one input terminal of the comparator through the connecting capacitor, while the other input terminal of the comparator is fixed to receive the common-mode voltage, theoretically ensuring that the voltages at the two input terminals of the comparator are the same.

[0033] Step S002. The lower plate of the highest-order calibration capacitor is grounded, and the lower plates of the other calibration capacitors are connected to the power supply voltage. The offset value of the current highest-order calibration capacitor is confirmed by an external comparator. In this step, if the current highest-order calibration capacitor being calibrated (such as...) Figure 3The calibration capacitor C13 shown is misaligned. For example, if the actual capacitance value of calibration capacitor C13 is 4C0 + Cd1 (Cd1 is the misalignment capacitance value), and the sum of the capacitance values ​​of the other calibration capacitors (including the capacitance value of supplementary capacitor C2) is 4C0 + Cd2 (Cd2 is the misalignment capacitance value), then when the grounding / power supply voltage of the lower plate of each capacitor is switched, the voltage at the POS terminal (connected to the upper plate of capacitor C3) will be different from the voltage before the switch. At this time, the comparator starts to work. The difference between the two voltages before and after the switch can be obtained through the comparator, thereby obtaining the misalignment value of the highest bit capacitor.

[0034] Step S003. Based on the offset value of the current highest bit calibration capacitor, through 2 N or 2 N-1 The bit code turns each of the first group of switches on / off to calibrate the offset of the current highest bit calibration capacitor; in this step, when N is odd, the number of resistors in the resistor array is 2. N The number of switches in the first group is 2. N When N is an even number, the number of resistors in the resistor array is 2. N-1 The number of switches in the first group is 2. N-1 The specific value of N is determined by the number of bits in the SAR ADC circuit, for example, such as Figure 2 As shown, when the SAR ADC circuit has 5 bits, then N is 3, which means 3 capacitor bits plus 2 resistor bits, and the number of resistors is 2. 3 That is, there are 8; that is, according to the number of digits corresponding to the number of resistors, the control of each first group of switches is achieved through digital codes to calibrate the current calibration capacitor. Specifically, the calibration process is as follows: a corresponding digital code of 1 indicates the current switch is closed, and a corresponding digital code of 0 indicates the current switch is open. Each digital code controls the opening / closing of one first group of switches. In this invention, closing one switch in the first group (such as switch S15) makes the voltage of the lower plate of the connected capacitor half of the power supply voltage; this closed switch (such as switch S15) is defined as a half-amplitude switch. When the offset value of the current calibration capacitor is greater than 0, while keeping the half-amplitude switch closed, and with the half-amplitude switch as the center, the other first group switches closer to the ground direction are closed sequentially, and the others closer to the ground direction are closed sequentially. The first set of switches closest to the power supply voltage remains open. When the offset value of the current calibration capacitor is less than 0, while keeping the half-amplitude switch closed, and with the half-amplitude switch as the center, the other first set of switches closest to the power supply voltage are closed in sequence, while the other first set of switches closest to the ground remain open. That is, with the half-amplitude switch as the center, the first set of switches are closed in sequence to both sides according to the positive or negative sign of the offset value of the current calibration capacitor, until the switch closest to the power supply voltage or ground is closed, and the digital code in this process is recorded. The formed digital code contains the offset capacitor values ​​Cd1 and Cd2 information.

[0035] Step S004. Keep the lower plate of the highest-order calibration capacitor grounded, and repeat step ac to calibrate the offset of other calibration capacitors from high to low until all calibration capacitors are calibrated. In this step, keep the lower plate of the calibrated capacitor grounded at all times; that is, do not connect the calibrated capacitor to the circuit to avoid affecting the calibration process of other calibration capacitors. Based on this, repeat steps S001-S003 to complete the calibration of all remaining calibration capacitors. It should be noted that before each repetition, the lower plate of the calibrated capacitor should be kept grounded and no further switching should be performed. Finally, use 2 N or 2 N-1 The bit code stores the offset value of each calibration capacitor, which can be eliminated during the actual comparison to complete the calibration of each calibration capacitor.

[0036] In summary, the calibration circuit and method for capacitor mismatch in SAR ADC circuits of the present invention can cover a wider range of capacitor mismatch errors. By calibrating from high to low capacitance values, coarse and fine adjustments are made more convenient. Coarse or fine adjustments can be flexibly selected according to specific circumstances, which speeds up the calibration process and improves efficiency. Moreover, since no capacitors are used in the calibration structure (excluding the calibration capacitors themselves), the chip area occupied by the entire circuit is significantly reduced, improving the chip integration.

[0037] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.

Claims

1. A calibration circuit for capacitance offset in a SAR ADC circuit, characterized in that, The system includes a capacitor array and a resistor array. The capacitor array consists of N calibration capacitors, supplementary capacitors, and connecting capacitors connected in parallel. The capacitance values ​​of the supplementary capacitors and connecting capacitors are both reference capacitance values. The capacitance value of the first calibration capacitor is the reference capacitance value, and the capacitance value of the Nth calibration capacitor is 2. N-1 The reference capacitance value is doubled, and the upper plate of each capacitor is connected to an input terminal of an external comparator. The lower plates of the supplementary capacitor and each calibration capacitor can be selectively grounded or connected to the power supply voltage; the resistor array consists of 2... N-1 or 2 N-2 The resistor array is composed of identical resistor groups connected in series. One end of the resistor array is connected to the power supply voltage, and the other end is grounded. A first set of switches is provided at the end of each resistor near the power supply voltage. The other end of each first set of switches can be selectively connected to the lower plate of the capacitor. A second set of switches is provided at the end of each resistor group near the power supply voltage. The other end of the second set of switches can be selectively connected to the lower plate of the supplementary capacitor. N is a natural number greater than 1.

2. The calibration circuit for capacitor offset in a SAR ADC circuit as described in claim 1, characterized in that, Each resistor group is formed by connecting at least two identical resistors in series.

3. The calibration circuit for capacitor offset in a SAR ADC circuit as described in claim 2, characterized in that, Each resistor group is formed by two identical resistors connected in series; when N is an odd number, the number of resistors in the resistor array is 2. N The first group of switches has 2. N The number of resistor groups is 2 N-1 When N is an even number, the number of resistors in the resistor array is 2. N-1 The first group of switches has 2. N-1 The number of resistor groups is 2 N-2 .

4. The calibration circuit for capacitor offset in a SAR ADC circuit as described in claim 2, characterized in that, It also includes a third set of switches, through which the lower plates of the supplementary capacitor and each calibration capacitor can be selectively grounded or connected to the power supply voltage via each of the third set of switches.

5. The calibration circuit for capacitor offset in a SAR ADC circuit as described in claim 2, characterized in that, It also includes a fourth switch and a fifth switch. The connecting capacitor can be selectively connected to the other end of each of the first group of switches via the fourth switch. One end of the fifth switch is connected to an input terminal of an external comparator, and the other end is connected to the lower plate of the connecting capacitor.

6. The calibration circuit for capacitor offset in a SAR ADC circuit as described in claim 2, characterized in that, When calibrating the calibration capacitors, start with the calibration capacitor with the largest capacitance value and calibrate sequentially, ending with the calibration capacitor whose capacitance value is the reference capacitance value.

7. A calibration method using the calibration circuit for capacitor offset of a SAR ADC circuit according to any one of claims 1-6, characterized in that, Includes the following steps: a. The lower plate of the highest-position calibration capacitor is connected to the power supply voltage, and the lower plates of the other calibration capacitors are grounded. A first group switch is closed, and the voltage of the lower plate of the connected capacitor is half of the power supply voltage. b. The lower plate of the highest-order calibration capacitor is grounded, and the lower plates of the other calibration capacitors are connected to the power supply voltage. The offset value of the current highest-order calibration capacitor is confirmed by an external comparator. c. Based on the offset value of the current highest-order calibration capacitor, through 2 N or 2 N-1 The bit code turns each of the first group switches on / off to calibrate the offset of the current highest bit calibration capacitor; d. Keep the lower plate of the highest-order calibration capacitor grounded, and repeat step ac to calibrate the misalignment of the other calibration capacitors from high to low until all calibration capacitors are calibrated.

8. The calibration method for capacitance offset in a SAR ADC circuit as described in claim 7, characterized in that, 2 N-1 or 2 N -2 The bit code controls the opening / closing of each of the first group of switches. Specifically, a bit code of 1 indicates that the switch is closed, and a bit code of 0 indicates that the switch is open.

9. The calibration method for capacitance offset in a SAR ADC circuit as described in claim 7, characterized in that, When one of the first group switches is closed so that the voltage of the lower plate of the connected capacitor is half of the power supply voltage, the closure of the first group switch is defined as a half-amplitude switch. When the offset value of the current highest bit calibration capacitor is greater than 0, while keeping the half-amplitude switch closed, and with the half-amplitude switch as the center, each of the other first group switches near the ground direction is closed in sequence, and each of the other first group switches near the power supply voltage direction remains open.

10. The calibration method for capacitance offset in a SAR ADC circuit as described in claim 9, characterized in that, When the offset value of the current calibration capacitor is less than 0, while keeping the half-amplitude switch closed, and with the half-amplitude switch as the center, the other first group switches closer to the power supply voltage direction are closed in sequence, while the other first group switches closer to the ground direction remain open.

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