3D Integrated SCB-VO2 Current Protection Device Based on TSV Interconnect and Its Fabrication Method

Abstract

The application discloses a kind of 3D integrated SCB-VO2 current protection devices based on TSV interconnection and preparation method thereof.For the problem that existing SCB-NTC protection scheme is large in size and difficult to be compatible, the application proposes a three-dimensional heterogeneous integration architecture of front SCB and back VO2 film.The core process includes: depositing polysilicon on the front surface of the silicon substrate and etching SCB bridge area;etching TSV blind hole and electroplating copper filling, after CMP planarization, thinning from the back surface to expose TSV structure;making interdigital electrode with line width / pitch of about 20 μm on the back surface, and using 3D printing technology to directly write VO2 ink, and after step heating and curing, a thermosensitive layer is formed.The application solves the thermal budget conflict between the front high-temperature process and the back VO2 low-temperature preparation by using a specific process sequence of "blind hole first and then thinning", and uses TSV to realize the parallel connection of SCB and VO2, with miniaturization and high reliability.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor bridge current protection, specifically to a 3D integrated SCB-VO2 current protection device based on TSV interconnect and its fabrication method. Background Technology

[0002] The semiconductor bridge (SCB) is a core component of a miniature electronic ignition device, widely used in fields requiring precise and reliable ignition, such as civil blasting, airbags, and spacecraft separation devices. With increasingly complex and harsh electromagnetic environments, energy can be transferred from the pins and converted into heat, adversely affecting the safety and reliability of pyrotechnic devices. Therefore, many devices have requirements for safe current; under current flow, the temperature of the semiconductor bridge must not rise to the upper temperature limit required by the device within 5 minutes.

[0003] Traditional thermal protection solutions primarily employ a parallel connection of a negative temperature coefficient (NTC) thermistor and a semiconductor current bridge (SCB). This approach leverages the characteristic that the resistance of an NTC decreases with increasing temperature, achieving temperature control through dynamic current shunting. However, as devices trend towards miniaturization and integration, this solution reveals significant limitations: firstly, NTC resistors are mostly made of bulk ceramic materials, making them difficult to integrate with semiconductor processes; secondly, their large size severely restricts the miniaturization and integration of devices. Therefore, there is an urgent need in the field for a novel current protection method that can combine rapid triggering with a semiconductor bridge while overcoming process compatibility challenges.

[0004] Vanadium dioxide (VO2) is a metal-insulator transition (MIT) material with a reversible phase transition temperature of 68°C. Its resistance changes by 2-5 orders of magnitude from its insulating state at room temperature to its metallic state at high temperatures. This significant resistance difference acts as an effective current protection switch for the SCB (Silicon Carbide) chip. At low temperatures, the higher resistance results in less current shunting, not affecting normal combustion. At high temperatures, the lower resistance opens the shunt switch, diverting heat from the SCB and protecting the chip from accidental combustion. It has unique application prospects in the field of current protection for thin-film energy exchange chips. However, planar integration of vanadium dioxide and SCB results in a large area, high process difficulty, and poor protection performance. Optimizing the SCB-VO2 integration process and improving its performance are the main issues restricting its effective application. Summary of the Invention

[0005] This invention aims to address the shortcomings of existing technologies by proposing a 3D integrated semiconductor bridge-vanadium dioxide composite current protection structure and manufacturing method based on TSV interconnects, thereby achieving an integrated SCB current protection scheme. Building upon the successful development of SCB preparation, M-phase VO2 powder preparation, and VO2 ink by our research group, the planar integration of VO2 is improved to 3D integration. The SCB is fabricated on the front (upper surface) of a silicon substrate, and interdigitated electrodes are fabricated on the back. Interconnection is achieved through TSV technology. Advanced 3D printing technology is used to fabricate a vanadium dioxide thin film on the interdigitated electrodes on the back (lower surface), solving the problems of miniaturization difficulties, high manufacturing complexity, and poor protection performance in existing SCB-VO2 planar integrated devices.

[0006] This invention achieves three-dimensional integration of SCB and vanadium dioxide structures based on TSV technology: the front-side SCB device and the back-side interdigitated electrodes are coated with vanadium dioxide structures, and the front and back structures are electrically interconnected through a TSV structure. The front structure includes: depositing a silicon dioxide insulating layer on the front side of a silicon substrate, depositing polycrystalline silicon on top, and then etching the SCB bridge region to fabricate metal electrodes; the back structure includes: depositing a copper seed layer on the back side of the silicon substrate, then electroplating a copper layer, etching out interdigitated electrodes, and using 3D printing technology to fabricate vanadium dioxide ink on the interdigitated electrodes to form a thermistor device; the TSV structure includes etching TSV vias penetrating the substrate and filling the vias with copper to achieve electrical interconnection between the upper and lower surfaces of the chip. In the SCB-VO2 3D integrated device proposed in this invention, the heat generated by the SCB is conducted to the VO2 thin film through the substrate, inducing an insulating-metal phase transition, resulting in a sharp drop in resistance. The TSV vias connect the SCB in parallel, shunting the current on the SCB and reducing heat accumulation on the SCB, thereby achieving current protection.

[0007] The specific technical solution is as follows: A method for fabricating a 3D integrated SCB-VO2 current protection device based on TSV interconnect includes the following steps: Fabrication of front-side SCB structure: A silicon dioxide insulating layer and a polycrystalline silicon thin film are sequentially deposited on the front side of a silicon substrate, and the polycrystalline silicon thin film is patterned and etched to form a semiconductor bridge structure; TSV vertical interconnect construction: TSV blind holes are etched on the silicon substrate, an insulating layer is deposited on the inner wall of the TSV blind holes and then filled with copper metal. Chemical mechanical polishing is performed to remove excess metal on the front side of the silicon substrate, leaving metal electrodes as electrodes in the semiconductor bridge structure to form conductive paths. Backside thinning and electrode fabrication: Thinning is performed on the backside of the silicon substrate until the TSV blind via becomes a TSV through-hole to expose the copper metal inside the TSV through-hole. Then, a metal layer is deposited and patterned on the backside to form an interdigitated electrode structure. The width of a single finger of the interdigitated electrode is 15-25 μm, and the spacing between adjacent fingers is 15-25 μm. Preparation of VO2 film on the back side: VO2 ink is directly written onto the interdigitated electrodes using 3D printing to form a VO2 film, and then subjected to step heating curing treatment.

[0008] Preferably, the polycrystalline silicon thin film has a thickness of 2 μm and its sheet resistance is adjusted to 3 Ω by in-situ doping or ion implantation.

[0009] Preferably, the diameter of the TSV via is 100 μm and the depth is 400 μm; the step of filling with copper metal specifically includes copper electroplating.

[0010] Preferably, in the step of directly writing VO2 ink onto the interdigitated electrodes using 3D printing, a nozzle with a diameter of 100 μm is used and a driving voltage of 60V is applied, resulting in a VO2 deposition thickness of 15-25 μm.

[0011] Preferably, the stepped heating curing process specifically involves heating at 80-90°C for 2-5 minutes, then heating at 100-110°C for 2-5 minutes, and finally heating at 120°C for 6 minutes, followed by cooling to room temperature.

[0012] Preferably, the preparation method further includes the following steps: the semiconductor bridge structure includes an electrode region, a protective film is attached to the electrode region, and the remaining regions are passivated by CVD deposition of silicon dioxide and silicon nitride, wherein the thickness of silicon dioxide is about 500 nm and the thickness of silicon nitride is about 300 nm.

[0013] The 3D integrated SCB-VO2 current protection device based on TSV interconnect provided by this invention includes: A silicon substrate with a silicon dioxide layer deposited on the front side, and semiconductor bridge structures and back side structures respectively disposed on the front and back sides of the silicon substrate; The semiconductor bridge structure includes a semiconductor bridge and a front metal electrode connected to the semiconductor bridge; The back structure includes interdigitated electrodes and a vanadium dioxide thin film layer that is 3D printed onto the interdigitated electrodes; The silicon substrate further includes a vertical interconnect structure that extends through the silicon substrate, the vertical interconnect structure connecting the front metal electrode and the interdigitated electrode, such that the semiconductor bridge and the back structure form a parallel loop.

[0014] Preferably, the thickness of the vanadium dioxide thin film layer is 15-25 μm, the width of a single finger of the interdigitated electrode is 15-25 μm, and the distance between adjacent fingers is 15-25 μm.

[0015] Preferably, the diameter of the through-hole in the vertical interconnect structure is 80-120μm, the depth is 350-450μm, the interior is filled with copper, and the inner wall of the through-hole is provided with a silicon dioxide insulating layer; the dimensions of the semiconductor bridge are 350-400μm in length, 90-110μm in width, and 1.5-2.5μm in thickness.

[0016] The application method of the 3D integrated SCB-VO2 current protection device based on TSV interconnect includes the following steps: When the semiconductor bridge heats up due to abnormal current, the heat is conducted through the silicon substrate to the vanadium dioxide thin film layer on the back side. When the temperature on the back reaches the phase transition temperature of VO2, VO2 changes from an insulating state to a metallic state. Combined with the setting of the single finger width and the spacing between adjacent fingers of the interdigitated electrodes, the resistance of the back structure drops sharply to no more than 4.3Ω. By utilizing the TSV interconnect structure, the current on the semiconductor bridge is shunted to the back structure connected in parallel with the semiconductor bridge, limiting the temperature rise of the semiconductor bridge and preventing device damage.

[0017] The beneficial effects of this invention are as follows: Firstly, in the SCB-VO2 planar integration technology, magnetron sputtering is used to deposit VO2 on the front side of the substrate, etching a serpentine pattern to increase the aspect ratio and reduce the resistance after the phase transition. However, the film thickness prepared by magnetron sputtering is limited. In our group's continuous attempts, the resistance after the VO2 phase transition could only be reduced to 15Ω, while the SCB resistance was 1Ω, indicating poor shunting effect of VO2 on SCB after the phase transition. Further increasing the aspect ratio to reduce resistance requires a larger surface area, which is detrimental to chip miniaturization. Further increasing the thickness will lead to warping, peeling, and other phenomena, making the process extremely difficult.

[0018] In 3D integration technology, fabricating VO2 on the back side of the substrate can effectively utilize space. The design of interdigitated electrodes with a high aspect ratio can serve as the carrier for 3D printing VO2 thermistors, making it easier to fabricate thicker VO2 films. This solves the challenges of magnetron sputtering and is more conducive to chip miniaturization. Through preparation and testing by our research group, the SCB protection device fabricated by the improved method can achieve a VO2 resistance of 4.3Ω after the temperature rises to the VO2 phase transition, demonstrating good current protection performance.

[0019] In terms of fabrication process, the workflow of "prioritizing front-side processing, followed by copper filling of TSV blind vias, then back-side thinning, post-printing, and low-temperature annealing" forms a tightly integrated whole that achieves excellent protection and high yield. If thinning is performed before fabricating the front-side SCB, the fragile bridge region is easily damaged; if high-temperature VO2 phase-change annealing is used on the back side, the delicate structure of the front-side SCB will be burned away. This invention solves the problems of thermal budget conflicts and mechanical damage in three-dimensional heterogeneous integration through this specific sequence of steps. Attached Figure Description

[0020] Figure 1 This is a comparison diagram showing the differences between the traditional method and the present invention in phase change resistors.

[0021] Figure 2 This is a schematic diagram of the overall structure of the device of the present invention.

[0022] Figure 3 The graph shows a comparison of SCB temperature changes. When the current is 1A, the temperature change of the SCB in the product of this invention over time is compared with that of the product without VO2 protection. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] like Figure 2 The present invention provides a 3D integrated SCB-VO2 current protection device based on TSV interconnect, comprising: A silicon substrate with a silicon dioxide layer deposited on the front side, and semiconductor bridge structures and back side structures respectively disposed on the front and back sides of the silicon substrate; The semiconductor bridge structure includes a semiconductor bridge and a front metal electrode connected to the semiconductor bridge; The back structure includes interdigitated electrodes and a vanadium dioxide thin film layer that is 3D printed onto the interdigitated electrodes; The silicon substrate further includes a vertical interconnect structure that extends through the silicon substrate, the vertical interconnect structure connecting the front metal electrode and the interdigitated electrode, such that the semiconductor bridge and the back structure form a parallel loop.

[0025] The 3D integrated SCB-VO2 current protection device based on TSV interconnect provided by this invention includes the following steps in its fabrication method: 1. Wafer Preparation In one specific embodiment, a silicon substrate is provided as a device substrate, wherein the silicon substrate is a single-crystal silicon wafer with a crystal orientation of [missing information]. <100> The substrate, with a thickness of 725 μm, is used to fabricate SCB-VO2 current protection devices with varying areas, including 1×1 mm, 1×1.5 mm, 1×2 mm, and 1.5×2 mm. Before the process begins, the silicon substrate is sequentially cleaned with organic solvents, rinsed with deionized water, and dried to remove surface organic contaminants and particles.

[0026] 2. Front-side polycrystalline silicon thin film deposition A silicon dioxide layer with a thickness of 0.5-1 μm is prepared on the surface of the silicon substrate using chemical vapor deposition (CVD), followed by a polycrystalline silicon thin film with a thickness of 2 μm.

[0027] The polycrystalline silicon thin film can be doped in situ or by subsequent ion implantation to adjust its resistance value so that the sheet resistance is 3Ω.

[0028] 3. Front-side semiconductor bridge patterning Photoresist is spin-coated onto the surface of the polycrystalline silicon thin film, and a semiconductor bridge pattern is formed using a photolithography process. Subsequently, the polycrystalline silicon thin film is etched using a dry etching process to form a semiconductor bridge structure.

[0029] In one specific embodiment, the semiconductor bridge structure has dimensions of 380μm×100μm×2μm.

[0030] After etching is complete, the photoresist is removed and the area is cleaned.

[0031] 4. TSV vias and copper filler The TSV blind via is formed using a deep reactive ion etching (DRIE) process. In one specific embodiment, the TSV diameter is 100 μm and the TSV depth is 400 μm.

[0032] A silicon dioxide insulating layer is deposited on the inner wall of the TSV hole to isolate the TSV metal from the silicon substrate.

[0033] After the insulating layer is completed, a metal seed layer is deposited in the TSV hole and then filled with copper metal through an electroplating process to form a conductive TSV structure.

[0034] The reason why this invention chooses the "blind hole first, then thinning" process instead of the "through hole first" process is as follows: The VO2 used in this invention is a 3D printing ink with a maximum curing temperature of only 130°C. However, front-side SCB processes (such as polysilicon deposition and annealing) typically require temperatures above 600°C. If vias are pre-drilled and connected to the back side, heat will be rapidly conducted to the back side via the copper TSV once the front-side high-temperature process is performed. If the back side already has a VO2 film, heat above 130°C can cause a VO2 phase transition or even failure; if the back side has exposed copper electrodes, high-temperature oxidation can also lead to poor contact. The process proposed in this invention allows for high-temperature processing on the front side and low-temperature processing on the back side last, without interference between the two processes.

[0035] The initial thickness of the silicon substrate is 725 μm, while the diameter of the TSV is only 100 μm. If through-holes are etched from the beginning, the wafer will become as fragile as a "sieve" during subsequent CMP and electroplating processes. The CMP process generates enormous mechanical pressure and vacuum suction forces, which can easily cause the wafer to break; the fluid impact during electroplating can also cause wafer warping. This invention provides a "blind via first, then thinning" method that preserves the integrity of the substrate, enabling it to withstand the mechanical stress of all subsequent front-side processes (deposition, photolithography, etching, CMP), and significantly improving production yield.

[0036] The front-side SCB is a polycrystalline silicon structure, and metal electrodes will be added later. If vias are used from the beginning, chemical reagents (such as etching solutions and cleaning agents) used in the front-side process may flow out from the back side or remain, contaminating the equipment. If the back side is already exposed, high-temperature steps in the subsequent front-side process (such as polycrystalline silicon annealing) may affect the cleanliness or structure of the back side. The "blind via first" method ensures that the front-side process is carried out in a closed environment, completely isolating interference from the back side and ensuring the cleanliness and electrical performance of the SCB bridge area.

[0037] This invention employs electroplating to fill copper in TSVs. In through-holes, the plating solution flows in from both sides simultaneously, making it difficult to control the filling rate at the bottom and easily leading to voids in the center, resulting in poor conductivity or breakage. The "blind via" of this invention has only one opening, allowing copper ions to grow uniformly from the bottom up during electroplating, making it easier to achieve void-free filling and ensuring the conductivity reliability of the TSV.

[0038] After filling, excess metal on the front side can be removed by CMP process to leave the metal electrode with an electrode size of 200×700μm×35μm.

[0039] 5. Rear interdigitated electrodes After completing the TSV structure, the back side is thinned to expose the TSV structure, a silicon dioxide insulating layer and a copper seed layer are deposited, and a 10μm thick copper layer is electroplated.

[0040] The metal electrode layer is patterned using photolithography, and excess metal is removed by a lift-off method to form an interdigitated electrode structure. In one specific embodiment, the width of a single finger electrode is 20 μm, and the spacing between adjacent finger electrodes is 20 μm. This high precision allows the vanadium dioxide film to have a larger aspect ratio after being formed on the surface of the interdigitated electrode, thereby reducing the resistance value of the thermistor after the vanadium dioxide phase transition.

[0041] 6. Vanadium dioxide thin film on the back side The prepared VO2 ink was loaded into the reservoir of the 3D printing system. Using a nozzle with a diameter of 100 μm and a driving voltage of 60 V, the ink was uniformly printed between and on the surface of the interdigital electrode combs, with a total thickness of approximately 20 μm.

[0042] The printed ink is heated at 80-90℃, 100-110℃, and 120-130℃ for 2-5 minutes, 2-5 minutes, and 3-6 minutes respectively to cure the ink, and then cooled to room temperature.

[0043] Existing technologies typically employ vacuum evaporation or magnetron sputtering to prepare VO2 thin films. These processes are not only costly and require high-temperature annealing, but also difficult to perform directly on the back side of wafers with fine structure on the front side (SCB). This invention creatively introduces "VO2 ink direct writing technology" into MEMS micro / nano fabrication lines, perfectly circumventing the problem of existing fine SCB structures on the front side. This "additive manufacturing + specific ink formulation" process route is not a simple replacement that those skilled in the art would easily conceive of.

[0044] 7. Device surface passivation A film is attached to the front electrode area, and CVD SiO2 / SiNx is used to passivate the other areas. The SiO2 thickness is about 500nm and the SiNx thickness is about 300nm.

[0045] The above steps are used to prepare an integrated SCB-VO2 current protection device. The vanadium dioxide thermistor in this device can effectively shunt the current on the SCB and play a role in current protection. Specific Implementation

[0046] 1. Wafer Preparation In one specific embodiment, a silicon substrate is provided as a device substrate, wherein the silicon substrate is a single-crystal silicon wafer with a crystal orientation of [missing information]. <100> The substrate, with a thickness of 725 μm, is used to fabricate a 1×1.5 mm SCB-VO2 current protection device. Before the process begins, the silicon substrate is sequentially cleaned with organic solvents, rinsed with deionized water, and dried to remove surface organic contaminants and particles.

[0047] 2. Front-side polycrystalline silicon thin film deposition A 0.5 μm thick silicon dioxide layer is prepared on the surface of the silicon substrate using chemical vapor deposition (CVD), followed by a 2 μm thick polycrystalline silicon film.

[0048] The polycrystalline silicon thin film can be doped in situ or by subsequent ion implantation to adjust its resistance value so that the sheet resistance is 3Ω.

[0049] 3. Front-side semiconductor bridge patterning Photoresist is spin-coated onto the surface of the polycrystalline silicon thin film, and a semiconductor bridge pattern is formed using a photolithography process. Subsequently, the polycrystalline silicon thin film is etched using a dry etching process to form a semiconductor bridge structure.

[0050] In one specific embodiment, the semiconductor bridge structure has dimensions of 380μm×100μm×2μm.

[0051] After etching is complete, the photoresist is removed and the area is cleaned.

[0052] 4. TSV vias and copper filler The TSV blind via is formed using a deep reactive ion etching (DRIE) process. In one specific embodiment, the TSV diameter is 100 μm and the TSV depth is 400 μm.

[0053] A silicon dioxide insulating layer is deposited on the inner wall of the TSV hole to isolate the TSV metal from the silicon substrate.

[0054] After the insulating layer is completed, a metal seed layer is deposited in the TSV hole and then filled with copper metal through an electroplating process to form a conductive TSV structure.

[0055] After filling, excess metal on the front side can be removed by CMP process to leave the metal electrode with an electrode size of 200×700μm×35μm.

[0056] 5. Rear interdigitated electrodes After completing the TSV structure, the back side is thinned to expose the TSV structure, a silicon dioxide insulating layer and a copper seed layer are deposited, and a 10μm thick copper layer is electroplated.

[0057] The metal electrode layer is patterned using photolithography, and excess metal is removed by a lift-off method to form an interdigitated electrode structure. In one specific embodiment, the width of a single finger electrode is 20 μm, and the spacing between adjacent finger electrodes is 20 μm. This high precision allows the vanadium dioxide film to have a larger aspect ratio after being formed on the surface of the interdigitated electrode, thereby reducing the resistance value of the thermistor after the vanadium dioxide phase transition.

[0058] 6. Vanadium dioxide thin film on the back side The prepared VO2 ink was loaded into the reservoir of the 3D printing system. Using a nozzle with a diameter of 100 μm and a driving voltage of 60 V, the ink was uniformly printed between and on the surface of the interdigital electrode combs, with a total thickness of approximately 20 μm.

[0059] The printed ink was heated at 80℃, 100℃, and 120℃ for 5 minutes, 5 minutes, and 6 minutes respectively to solidify the ink, and then cooled to room temperature.

[0060] 7. Device surface passivation A film is attached to the front electrode area, and CVD SiO2 / SiNx is used to passivate the other areas. The SiO2 thickness is about 500nm and the SiNx thickness is about 300nm.

[0061] like Figure 1 The top figure shows the resistance change of the product obtained by traditional methods, such as magnetron sputtering to fabricate VO2 on the front side of a substrate and etching a serpentine shape to increase the aspect ratio, before and after the phase transition. The bottom figure shows the product obtained by the present invention. In both figures, the horizontal axis represents time, in seconds. As can be seen from the figures, the SCB protection device prepared by the improved method achieves a VO2 resistance of 4.3Ω after the temperature rises to the VO2 phase transition, demonstrating good current protection performance.

[0062] like Figure 3 When a constant current of 1A is applied, the temperature of the unprotected SCB device gradually increases with the increase of the current application time, and it is damaged after the SCB temperature rises to 360℃ in about 175s. With vanadium dioxide protection, when a current of 1A is applied, the SCB temperature can eventually be kept constant at 105℃, indicating that the structure has a good current protection effect.

Claims

1. A method for fabricating a 3D integrated SCB-VO2 current protection device based on TSV interconnect, characterized in that, Includes the following steps: Fabrication of front-side SCB structure: A silicon dioxide insulating layer and a polycrystalline silicon thin film are sequentially deposited on the front side of a silicon substrate, and the polycrystalline silicon thin film is patterned and etched to form a semiconductor bridge structure; TSV vertical interconnect construction: TSV blind holes are etched on the silicon substrate, an insulating layer is deposited on the inner wall of the TSV blind holes and then filled with copper metal. Chemical mechanical polishing is performed to remove excess metal on the front side of the silicon substrate, leaving metal electrodes as electrodes in the semiconductor bridge structure to form conductive paths. Backside thinning and electrode fabrication: Thinning is performed on the backside of the silicon substrate until the TSV blind via becomes a TSV through-hole to expose the copper metal inside the TSV through-hole. Then, a metal layer is deposited and patterned on the backside to form an interdigitated electrode structure. The width of a single finger of the interdigitated electrode is 15-25 μm, and the spacing between adjacent fingers is 15-25 μm. Preparation of VO2 film on the back side: VO2 ink is directly written onto the interdigitated electrodes using 3D printing to form a VO2 film, and then subjected to step heating curing treatment.

2. The preparation method according to claim 1, characterized in that, The polycrystalline silicon thin film has a thickness of 2 μm and its sheet resistance is adjusted to 3 Ω by in-situ doping or ion implantation.

3. The preparation method according to claim 1, characterized in that, The TSV via has a diameter of 100 μm and a depth of 400 μm; the step of filling with copper metal specifically includes copper electroplating.

4. The preparation method according to claim 1, characterized in that, In the step of directly writing VO2 ink onto the interdigital electrodes using 3D printing, a nozzle with a diameter of 100μm is used, and a driving voltage of 60V is applied to deposit VO2 ink with a thickness of 15-25μm.

5. The preparation method according to claim 1, characterized in that, The specific steps of the stepped heat curing process are as follows: Heat at 80-90℃ for 2-5 minutes, then at 100-110℃ for 2-5 minutes, and finally at 120℃ for 6 minutes, then cool to room temperature.

6. The preparation method according to claim 1, characterized in that, It also includes the following steps: The semiconductor bridge structure includes an electrode region, which is protected by a film. The remaining regions are passivated by CVD deposition of silicon dioxide and silicon nitride, wherein the thickness of silicon dioxide is approximately 500 nm and the thickness of silicon nitride is approximately 300 nm.

7. A 3D integrated SCB-VO2 current protection device based on TSV interconnect, characterized in that, include: A silicon substrate with a silicon dioxide layer deposited on the front side, and semiconductor bridge structures and back side structures respectively disposed on the front and back sides of the silicon substrate; The semiconductor bridge structure includes a semiconductor bridge and a front metal electrode connected to the semiconductor bridge; The back structure includes interdigitated electrodes and a vanadium dioxide thin film layer that is 3D printed onto the interdigitated electrodes; The silicon substrate further includes a vertical interconnect structure that extends through the silicon substrate, the vertical interconnect structure connecting the front metal electrode and the interdigitated electrode, such that the semiconductor bridge and the back structure form a parallel loop.

8. The 3D integrated SCB-VO2 current protection device according to claim 7, characterized in that, The thickness of the vanadium dioxide thin film is 15-25 μm, the width of a single finger of the interdigitated electrode is 15-25 μm, and the distance between adjacent fingers is 15-25 μm.

9. The 3D integrated SCB-VO2 current protection device according to claim 8, characterized in that, The through-hole of the vertical interconnect structure has a diameter of 80-120μm and a depth of 350-450μm, is filled with copper, and has a silicon dioxide insulating layer on the inner wall of the through-hole; the semiconductor bridge has a length of 350-400μm, a width of 90-110μm, and a thickness of 1.5-2.5μm.

10. The application of the 3D integrated SCB-VO2 current protection device based on TSV interconnect according to claim 8, characterized in that, Includes the following steps: When the semiconductor bridge heats up due to abnormal current, the heat is conducted through the silicon substrate to the vanadium dioxide thin film layer on the back side. When the temperature on the back reaches the phase transition temperature of VO2, VO2 changes from an insulating state to a metallic state. Combined with the setting of the single finger width and the spacing between adjacent fingers of the interdigitated electrodes, the resistance of the back structure drops sharply to no more than 4.3Ω. By utilizing the TSV interconnect structure, the current on the semiconductor bridge is shunted to the back structure connected in parallel with the semiconductor bridge, limiting the temperature rise of the semiconductor bridge and preventing device damage.

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